MipsRegisterInfo.td revision 193323
1193323Sed//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Declarations that describe the MIPS register file 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed// We have banks of 32 registers each. 15193323Sedclass MipsReg<string n> : Register<n> { 16193323Sed field bits<5> Num; 17193323Sed let Namespace = "Mips"; 18193323Sed} 19193323Sed 20193323Sed// Mips CPU Registers 21193323Sedclass MipsGPRReg<bits<5> num, string n> : MipsReg<n> { 22193323Sed let Num = num; 23193323Sed} 24193323Sed 25193323Sed// Mips 32-bit FPU Registers 26193323Sedclass FPR<bits<5> num, string n> : MipsReg<n> { 27193323Sed let Num = num; 28193323Sed} 29193323Sed 30193323Sed// Mips 64-bit (aliased) FPU Registers 31193323Sedclass AFPR<bits<5> num, string n, list<Register> aliases> : MipsReg<n> { 32193323Sed let Num = num; 33193323Sed let Aliases = aliases; 34193323Sed} 35193323Sed 36193323Sed//===----------------------------------------------------------------------===// 37193323Sed// Registers 38193323Sed//===----------------------------------------------------------------------===// 39193323Sed 40193323Sedlet Namespace = "Mips" in { 41193323Sed 42193323Sed // General Purpose Registers 43193323Sed def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>; 44193323Sed def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; 45193323Sed def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 46193323Sed def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 47193323Sed def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>; 48193323Sed def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 49193323Sed def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 50193323Sed def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 51193323Sed def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 52193323Sed def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 53193323Sed def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 54193323Sed def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 55193323Sed def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 56193323Sed def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 57193323Sed def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 58193323Sed def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 59193323Sed def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 60193323Sed def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 61193323Sed def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 62193323Sed def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 63193323Sed def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 64193323Sed def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 65193323Sed def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 66193323Sed def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 67193323Sed def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 68193323Sed def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 69193323Sed def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 70193323Sed def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 71193323Sed def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>; 72193323Sed def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>; 73193323Sed def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>; 74193323Sed def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>; 75193323Sed 76193323Sed /// Mips Single point precision FPU Registers 77193323Sed def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>; 78193323Sed def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>; 79193323Sed def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>; 80193323Sed def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>; 81193323Sed def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>; 82193323Sed def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>; 83193323Sed def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>; 84193323Sed def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>; 85193323Sed def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>; 86193323Sed def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>; 87193323Sed def F10 : FPR<10, "F10">, DwarfRegNum<[42]>; 88193323Sed def F11 : FPR<11, "F11">, DwarfRegNum<[43]>; 89193323Sed def F12 : FPR<12, "F12">, DwarfRegNum<[44]>; 90193323Sed def F13 : FPR<13, "F13">, DwarfRegNum<[45]>; 91193323Sed def F14 : FPR<14, "F14">, DwarfRegNum<[46]>; 92193323Sed def F15 : FPR<15, "F15">, DwarfRegNum<[47]>; 93193323Sed def F16 : FPR<16, "F16">, DwarfRegNum<[48]>; 94193323Sed def F17 : FPR<17, "F17">, DwarfRegNum<[49]>; 95193323Sed def F18 : FPR<18, "F18">, DwarfRegNum<[50]>; 96193323Sed def F19 : FPR<19, "F19">, DwarfRegNum<[51]>; 97193323Sed def F20 : FPR<20, "F20">, DwarfRegNum<[52]>; 98193323Sed def F21 : FPR<21, "F21">, DwarfRegNum<[53]>; 99193323Sed def F22 : FPR<22, "F22">, DwarfRegNum<[54]>; 100193323Sed def F23 : FPR<23, "F23">, DwarfRegNum<[55]>; 101193323Sed def F24 : FPR<24, "F24">, DwarfRegNum<[56]>; 102193323Sed def F25 : FPR<25, "F25">, DwarfRegNum<[57]>; 103193323Sed def F26 : FPR<26, "F26">, DwarfRegNum<[58]>; 104193323Sed def F27 : FPR<27, "F27">, DwarfRegNum<[59]>; 105193323Sed def F28 : FPR<28, "F28">, DwarfRegNum<[60]>; 106193323Sed def F29 : FPR<29, "F29">, DwarfRegNum<[61]>; 107193323Sed def F30 : FPR<30, "F30">, DwarfRegNum<[62]>; 108193323Sed def F31 : FPR<31, "F31">, DwarfRegNum<[63]>; 109193323Sed 110193323Sed /// Mips Double point precision FPU Registers (aliased 111193323Sed /// with the single precision to hold 64 bit values) 112193323Sed def D0 : AFPR< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>; 113193323Sed def D1 : AFPR< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>; 114193323Sed def D2 : AFPR< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>; 115193323Sed def D3 : AFPR< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>; 116193323Sed def D4 : AFPR< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>; 117193323Sed def D5 : AFPR<10, "F10", [F10, F11]>, DwarfRegNum<[42]>; 118193323Sed def D6 : AFPR<12, "F12", [F12, F13]>, DwarfRegNum<[44]>; 119193323Sed def D7 : AFPR<14, "F14", [F14, F15]>, DwarfRegNum<[46]>; 120193323Sed def D8 : AFPR<16, "F16", [F16, F17]>, DwarfRegNum<[48]>; 121193323Sed def D9 : AFPR<18, "F18", [F18, F19]>, DwarfRegNum<[50]>; 122193323Sed def D10 : AFPR<20, "F20", [F20, F21]>, DwarfRegNum<[52]>; 123193323Sed def D11 : AFPR<22, "F22", [F22, F23]>, DwarfRegNum<[54]>; 124193323Sed def D12 : AFPR<24, "F24", [F24, F25]>, DwarfRegNum<[56]>; 125193323Sed def D13 : AFPR<26, "F26", [F26, F27]>, DwarfRegNum<[58]>; 126193323Sed def D14 : AFPR<28, "F28", [F28, F29]>, DwarfRegNum<[60]>; 127193323Sed def D15 : AFPR<30, "F30", [F30, F31]>, DwarfRegNum<[62]>; 128193323Sed 129193323Sed // Hi/Lo registers 130193323Sed def HI : Register<"hi">, DwarfRegNum<[64]>; 131193323Sed def LO : Register<"lo">, DwarfRegNum<[65]>; 132193323Sed 133193323Sed // Status flags register 134193323Sed def FCR31 : Register<"31">; 135193323Sed} 136193323Sed 137193323Sed//===----------------------------------------------------------------------===// 138193323Sed// Register Classes 139193323Sed//===----------------------------------------------------------------------===// 140193323Sed 141193323Seddef CPURegs : RegisterClass<"Mips", [i32], 32, 142193323Sed // Return Values and Arguments 143193323Sed [V0, V1, A0, A1, A2, A3, 144193323Sed // Not preserved across procedure calls 145193323Sed T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, 146193323Sed // Callee save 147193323Sed S0, S1, S2, S3, S4, S5, S6, S7, 148193323Sed // Reserved 149193323Sed ZERO, AT, K0, K1, GP, SP, FP, RA]> 150193323Sed{ 151193323Sed let MethodProtos = [{ 152193323Sed iterator allocation_order_end(const MachineFunction &MF) const; 153193323Sed }]; 154193323Sed let MethodBodies = [{ 155193323Sed CPURegsClass::iterator 156193323Sed CPURegsClass::allocation_order_end(const MachineFunction &MF) const { 157193323Sed // The last 8 registers on the list above are reserved 158193323Sed return end()-8; 159193323Sed } 160193323Sed }]; 161193323Sed} 162193323Sed 163193323Sed// 64bit fp: 164193323Sed// * FGR64 - 32 64-bit registers 165193323Sed// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 166193323Sed// 167193323Sed// 32bit fp: 168193323Sed// * FGR32 - 16 32-bit even registers 169193323Sed// * FGR32 - 32 32-bit registers (single float only mode) 170193323Seddef FGR32 : RegisterClass<"Mips", [f32], 32, 171193323Sed // Return Values and Arguments 172193323Sed [F0, F1, F2, F3, F12, F13, F14, F15, 173193323Sed // Not preserved across procedure calls 174193323Sed F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19, 175193323Sed // Callee save 176193323Sed F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, 177193323Sed // Reserved 178193323Sed F31]> 179193323Sed{ 180193323Sed let MethodProtos = [{ 181193323Sed iterator allocation_order_begin(const MachineFunction &MF) const; 182193323Sed iterator allocation_order_end(const MachineFunction &MF) const; 183193323Sed }]; 184193323Sed let MethodBodies = [{ 185193323Sed 186193323Sed static const unsigned MIPS_FGR32[] = { 187193323Sed Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13, 188193323Sed Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7, 189193323Sed Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17, 190193323Sed Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, 191193323Sed Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, 192193323Sed Mips::F30 193193323Sed }; 194193323Sed 195193323Sed static const unsigned MIPS_SVR4_FGR32[] = { 196193323Sed Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4, 197193323Sed Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18, 198193323Sed Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 199193323Sed }; 200193323Sed 201193323Sed FGR32Class::iterator 202193323Sed FGR32Class::allocation_order_begin(const MachineFunction &MF) const { 203193323Sed const TargetMachine &TM = MF.getTarget(); 204193323Sed const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>(); 205193323Sed 206193323Sed if (Subtarget.isSingleFloat()) 207193323Sed return MIPS_FGR32; 208193323Sed else 209193323Sed return MIPS_SVR4_FGR32; 210193323Sed } 211193323Sed 212193323Sed FGR32Class::iterator 213193323Sed FGR32Class::allocation_order_end(const MachineFunction &MF) const { 214193323Sed const TargetMachine &TM = MF.getTarget(); 215193323Sed const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>(); 216193323Sed 217193323Sed if (Subtarget.isSingleFloat()) 218193323Sed return MIPS_FGR32 + (sizeof(MIPS_FGR32) / sizeof(unsigned)); 219193323Sed else 220193323Sed return MIPS_SVR4_FGR32 + (sizeof(MIPS_SVR4_FGR32) / sizeof(unsigned)); 221193323Sed } 222193323Sed }]; 223193323Sed} 224193323Sed 225193323Seddef AFGR64 : RegisterClass<"Mips", [f64], 64, 226193323Sed // Return Values and Arguments 227193323Sed [D0, D1, D6, D7, 228193323Sed // Not preserved across procedure calls 229193323Sed D2, D3, D4, D5, D8, D9, 230193323Sed // Callee save 231193323Sed D10, D11, D12, D13, D14, 232193323Sed // Reserved 233193323Sed D15]> 234193323Sed{ 235193323Sed let MethodProtos = [{ 236193323Sed iterator allocation_order_end(const MachineFunction &MF) const; 237193323Sed }]; 238193323Sed let MethodBodies = [{ 239193323Sed AFGR64Class::iterator 240193323Sed AFGR64Class::allocation_order_end(const MachineFunction &MF) const { 241193323Sed // The last register on the list above is reserved 242193323Sed return end()-1; 243193323Sed } 244193323Sed }]; 245193323Sed} 246193323Sed 247193323Sed// Condition Register for floating point operations 248193323Seddef CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>; 249193323Sed 250193323Sed// Hi/Lo Registers 251193323Seddef HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>; 252193323Sed 253