1234353Sdim//===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===// 2234353Sdim// 3234353Sdim// The LLVM Compiler Infrastructure 4234353Sdim// 5234353Sdim// This file is distributed under the University of Illinois Open Source 6234353Sdim// License. See LICENSE.TXT for details. 7234353Sdim// 8234353Sdim//===----------------------------------------------------------------------===// 9234353Sdim// 10234353Sdim// This file implements the MipsAsmBackend and MipsELFObjectWriter classes. 11234353Sdim// 12234353Sdim//===----------------------------------------------------------------------===// 13234353Sdim// 14234353Sdim 15234353Sdim#include "MipsFixupKinds.h" 16226584Sdim#include "MCTargetDesc/MipsMCTargetDesc.h" 17234353Sdim#include "llvm/MC/MCAsmBackend.h" 18226584Sdim#include "llvm/MC/MCAssembler.h" 19226584Sdim#include "llvm/MC/MCDirectives.h" 20226584Sdim#include "llvm/MC/MCELFObjectWriter.h" 21234353Sdim#include "llvm/MC/MCFixupKindInfo.h" 22226584Sdim#include "llvm/MC/MCObjectWriter.h" 23226584Sdim#include "llvm/MC/MCSubtargetInfo.h" 24226584Sdim#include "llvm/Support/ErrorHandling.h" 25226584Sdim#include "llvm/Support/raw_ostream.h" 26234353Sdim 27226584Sdimusing namespace llvm; 28226584Sdim 29234353Sdim// Prepare value for the target space for it 30234353Sdimstatic unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 31234353Sdim 32234353Sdim // Add/subtract and shift 33234353Sdim switch (Kind) { 34234353Sdim default: 35234353Sdim return 0; 36234353Sdim case FK_GPRel_4: 37234353Sdim case FK_Data_4: 38239462Sdim case FK_Data_8: 39234353Sdim case Mips::fixup_Mips_LO16: 40249423Sdim case Mips::fixup_Mips_GPREL16: 41239462Sdim case Mips::fixup_Mips_GPOFF_HI: 42239462Sdim case Mips::fixup_Mips_GPOFF_LO: 43239462Sdim case Mips::fixup_Mips_GOT_PAGE: 44239462Sdim case Mips::fixup_Mips_GOT_OFST: 45239462Sdim case Mips::fixup_Mips_GOT_DISP: 46244628Sdim case Mips::fixup_Mips_GOT_LO16: 47244628Sdim case Mips::fixup_Mips_CALL_LO16: 48234353Sdim break; 49234353Sdim case Mips::fixup_Mips_PC16: 50234353Sdim // So far we are only using this type for branches. 51234353Sdim // For branches we start 1 instruction after the branch 52234353Sdim // so the displacement will be one instruction size less. 53234353Sdim Value -= 4; 54234353Sdim // The displacement is then divided by 4 to give us an 18 bit 55234353Sdim // address range. 56234353Sdim Value >>= 2; 57234353Sdim break; 58234353Sdim case Mips::fixup_Mips_26: 59234353Sdim // So far we are only using this type for jumps. 60234353Sdim // The displacement is then divided by 4 to give us an 28 bit 61234353Sdim // address range. 62234353Sdim Value >>= 2; 63234353Sdim break; 64234353Sdim case Mips::fixup_Mips_HI16: 65234353Sdim case Mips::fixup_Mips_GOT_Local: 66244628Sdim case Mips::fixup_Mips_GOT_HI16: 67244628Sdim case Mips::fixup_Mips_CALL_HI16: 68239462Sdim // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 69234353Sdim Value = ((Value + 0x8000) >> 16) & 0xffff; 70234353Sdim break; 71239462Sdim case Mips::fixup_Mips_HIGHER: 72239462Sdim // Get the 3rd 16-bits. 73239462Sdim Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 74239462Sdim break; 75239462Sdim case Mips::fixup_Mips_HIGHEST: 76239462Sdim // Get the 4th 16-bits. 77239462Sdim Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 78239462Sdim break; 79234353Sdim } 80234353Sdim 81234353Sdim return Value; 82234353Sdim} 83234353Sdim 84226584Sdimnamespace { 85234353Sdimclass MipsAsmBackend : public MCAsmBackend { 86234353Sdim Triple::OSType OSType; 87234353Sdim bool IsLittle; // Big or little endian 88234353Sdim bool Is64Bit; // 32 or 64 bit words 89226584Sdim 90226584Sdimpublic: 91234353Sdim MipsAsmBackend(const Target &T, Triple::OSType _OSType, 92234353Sdim bool _isLittle, bool _is64Bit) 93234353Sdim :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {} 94226584Sdim 95234353Sdim MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 96239462Sdim return createMipsELFObjectWriter(OS, 97239462Sdim MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 98226584Sdim } 99226584Sdim 100243830Sdim /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 101226584Sdim /// data fragment, at the offset specified by the fixup and following the 102226584Sdim /// fixup kind as appropriate. 103234353Sdim void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 104226584Sdim uint64_t Value) const { 105234353Sdim MCFixupKind Kind = Fixup.getKind(); 106234353Sdim Value = adjustFixupValue((unsigned)Kind, Value); 107234353Sdim 108234982Sdim if (!Value) 109234353Sdim return; // Doesn't change encoding. 110234353Sdim 111234353Sdim // Where do we start in the object 112234353Sdim unsigned Offset = Fixup.getOffset(); 113234353Sdim // Number of bytes we need to fixup 114234353Sdim unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 115234353Sdim // Used to point to big endian bytes 116234353Sdim unsigned FullSize; 117234353Sdim 118234353Sdim switch ((unsigned)Kind) { 119234353Sdim case Mips::fixup_Mips_16: 120234353Sdim FullSize = 2; 121234353Sdim break; 122234353Sdim case Mips::fixup_Mips_64: 123234353Sdim FullSize = 8; 124234353Sdim break; 125234353Sdim default: 126234353Sdim FullSize = 4; 127234353Sdim break; 128234353Sdim } 129234353Sdim 130234353Sdim // Grab current value, if any, from bits. 131234353Sdim uint64_t CurVal = 0; 132234353Sdim 133234353Sdim for (unsigned i = 0; i != NumBytes; ++i) { 134234353Sdim unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 135234353Sdim CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 136234353Sdim } 137234353Sdim 138239462Sdim uint64_t Mask = ((uint64_t)(-1) >> 139239462Sdim (64 - getFixupKindInfo(Kind).TargetSize)); 140234982Sdim CurVal |= Value & Mask; 141234353Sdim 142234353Sdim // Write out the fixed up bytes back to the code/data bits. 143234353Sdim for (unsigned i = 0; i != NumBytes; ++i) { 144234353Sdim unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 145234353Sdim Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 146234353Sdim } 147226584Sdim } 148226584Sdim 149234353Sdim unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } 150234353Sdim 151234353Sdim const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 152234353Sdim const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { 153234353Sdim // This table *must* be in same the order of fixup_* kinds in 154234353Sdim // MipsFixupKinds.h. 155234353Sdim // 156234353Sdim // name offset bits flags 157234353Sdim { "fixup_Mips_16", 0, 16, 0 }, 158234353Sdim { "fixup_Mips_32", 0, 32, 0 }, 159234353Sdim { "fixup_Mips_REL32", 0, 32, 0 }, 160234353Sdim { "fixup_Mips_26", 0, 26, 0 }, 161234353Sdim { "fixup_Mips_HI16", 0, 16, 0 }, 162234353Sdim { "fixup_Mips_LO16", 0, 16, 0 }, 163234353Sdim { "fixup_Mips_GPREL16", 0, 16, 0 }, 164234353Sdim { "fixup_Mips_LITERAL", 0, 16, 0 }, 165234353Sdim { "fixup_Mips_GOT_Global", 0, 16, 0 }, 166234353Sdim { "fixup_Mips_GOT_Local", 0, 16, 0 }, 167234353Sdim { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 168234353Sdim { "fixup_Mips_CALL16", 0, 16, 0 }, 169234353Sdim { "fixup_Mips_GPREL32", 0, 32, 0 }, 170234353Sdim { "fixup_Mips_SHIFT5", 6, 5, 0 }, 171234353Sdim { "fixup_Mips_SHIFT6", 6, 5, 0 }, 172234353Sdim { "fixup_Mips_64", 0, 64, 0 }, 173234353Sdim { "fixup_Mips_TLSGD", 0, 16, 0 }, 174234353Sdim { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 175234353Sdim { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 176234353Sdim { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 177234353Sdim { "fixup_Mips_TLSLDM", 0, 16, 0 }, 178234353Sdim { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 179234353Sdim { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 180239462Sdim { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 181239462Sdim { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 182239462Sdim { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 183239462Sdim { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 184239462Sdim { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 185239462Sdim { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 186239462Sdim { "fixup_Mips_HIGHER", 0, 16, 0 }, 187244628Sdim { "fixup_Mips_HIGHEST", 0, 16, 0 }, 188244628Sdim { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 189244628Sdim { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 190244628Sdim { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 191244628Sdim { "fixup_Mips_CALL_LO16", 0, 16, 0 } 192234353Sdim }; 193234353Sdim 194234353Sdim if (Kind < FirstTargetFixupKind) 195234353Sdim return MCAsmBackend::getFixupKindInfo(Kind); 196234353Sdim 197234353Sdim assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 198234353Sdim "Invalid kind!"); 199234353Sdim return Infos[Kind - FirstTargetFixupKind]; 200234353Sdim } 201234353Sdim 202226584Sdim /// @name Target Relaxation Interfaces 203226584Sdim /// @{ 204226584Sdim 205226584Sdim /// MayNeedRelaxation - Check whether the given instruction may need 206226584Sdim /// relaxation. 207226584Sdim /// 208226584Sdim /// \param Inst - The instruction to test. 209234353Sdim bool mayNeedRelaxation(const MCInst &Inst) const { 210226584Sdim return false; 211226584Sdim } 212226584Sdim 213234353Sdim /// fixupNeedsRelaxation - Target specific predicate for whether a given 214234353Sdim /// fixup requires the associated instruction to be relaxed. 215234353Sdim bool fixupNeedsRelaxation(const MCFixup &Fixup, 216234353Sdim uint64_t Value, 217249423Sdim const MCRelaxableFragment *DF, 218234353Sdim const MCAsmLayout &Layout) const { 219234353Sdim // FIXME. 220234353Sdim assert(0 && "RelaxInstruction() unimplemented"); 221234353Sdim return false; 222234353Sdim } 223234353Sdim 224234353Sdim /// RelaxInstruction - Relax the instruction in the given fragment 225234353Sdim /// to the next wider instruction. 226226584Sdim /// 227234353Sdim /// \param Inst - The instruction to relax, which may be the same 228234353Sdim /// as the output. 229243830Sdim /// \param [out] Res On return, the relaxed instruction. 230234353Sdim void relaxInstruction(const MCInst &Inst, MCInst &Res) const { 231226584Sdim } 232234353Sdim 233226584Sdim /// @} 234226584Sdim 235234353Sdim /// WriteNopData - Write an (optimal) nop sequence of Count bytes 236234353Sdim /// to the given output. If the target cannot generate such a sequence, 237234353Sdim /// it should return an error. 238226584Sdim /// 239226584Sdim /// \return - True on success. 240234353Sdim bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 241239462Sdim // Check for a less than instruction size number of bytes 242239462Sdim // FIXME: 16 bit instructions are not handled yet here. 243239462Sdim // We shouldn't be using a hard coded number for instruction size. 244239462Sdim if (Count % 4) return false; 245239462Sdim 246239462Sdim uint64_t NumNops = Count / 4; 247239462Sdim for (uint64_t i = 0; i != NumNops; ++i) 248239462Sdim OW->Write32(0); 249234353Sdim return true; 250226584Sdim } 251234353Sdim}; // class MipsAsmBackend 252226584Sdim 253234353Sdim} // namespace 254226584Sdim 255234353Sdim// MCAsmBackend 256241430SdimMCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT, 257241430Sdim StringRef CPU) { 258234353Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 259234353Sdim /*IsLittle*/true, /*Is64Bit*/false); 260234353Sdim} 261226584Sdim 262241430SdimMCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT, 263241430Sdim StringRef CPU) { 264234353Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 265234353Sdim /*IsLittle*/false, /*Is64Bit*/false); 266234353Sdim} 267226584Sdim 268241430SdimMCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT, 269241430Sdim StringRef CPU) { 270234353Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 271234353Sdim /*IsLittle*/true, /*Is64Bit*/true); 272234353Sdim} 273226584Sdim 274241430SdimMCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT, 275241430Sdim StringRef CPU) { 276234353Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 277234353Sdim /*IsLittle*/false, /*Is64Bit*/true); 278226584Sdim} 279226584Sdim 280