MBlazeSchedule5.td revision 259065
167754Smsmith//===-- MBlazeSchedule5.td - MBlaze Scheduling Definitions -*- tablegen -*-===// 267754Smsmith// 367754Smsmith// The LLVM Compiler Infrastructure 477424Smsmith// 567754Smsmith// This file is distributed under the University of Illinois Open Source 667754Smsmith// License. See LICENSE.TXT for details. 767754Smsmith// 8217365Sjkim//===----------------------------------------------------------------------===// 9217365Sjkim 1070243Smsmith//===----------------------------------------------------------------------===// 1167754Smsmith// MBlaze instruction itineraries for the five stage pipeline. 12217365Sjkim//===----------------------------------------------------------------------===// 13217365Sjkimdef MBlazePipe5Itineraries : ProcessorItineraries< 14217365Sjkim [IF,ID,EX,MA,WB], [], [ 15217365Sjkim 16217365Sjkim // ALU instruction with one destination register and either two register 17217365Sjkim // source operands or one register source operand and one immediate operand. 18217365Sjkim // The instruction takes one cycle to execute in each of the stages. The 19217365Sjkim // two source operands are read during the decode stage and the result is 20217365Sjkim // ready after the execute stage. 21217365Sjkim InstrItinData< IIC_ALU, 22217365Sjkim [ InstrStage<1,[IF]> // one cycle in fetch stage 23217365Sjkim , InstrStage<1,[ID]> // one cycle in decode stage 24217365Sjkim , InstrStage<1,[EX]> // one cycle in execute stage 25217365Sjkim , InstrStage<1,[MA]> // one cycle in memory access stage 2667754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 27217365Sjkim [ 2 // result ready after two cycles 28217365Sjkim , 1 // first operand read after one cycle 29217365Sjkim , 1 ]>, // second operand read after one cycle 3067754Smsmith 31217365Sjkim // ALU multiply instruction with one destination register and either two 32217365Sjkim // register source operands or one register source operand and one immediate 33217365Sjkim // operand. The instruction takes one cycle to execute in each of the 34217365Sjkim // pipeline stages. The two source operands are read during the decode stage 35217365Sjkim // and the result is ready after the execute stage. 36217365Sjkim InstrItinData< IIC_ALUm, 37217365Sjkim [ InstrStage<1,[IF]> // one cycle in fetch stage 38217365Sjkim , InstrStage<1,[ID]> // one cycle in decode stage 39217365Sjkim , InstrStage<1,[EX]> // one cycle in execute stage 40217365Sjkim , InstrStage<1,[MA]> // one cycle in memory access stage 41217365Sjkim , InstrStage<1,[WB]>], // one cycle in write back stage 42217365Sjkim [ 2 // result ready after two cycles 43217365Sjkim , 1 // first operand read after one cycle 4467754Smsmith , 1 ]>, // second operand read after one cycle 4577424Smsmith 4667754Smsmith // ALU divide instruction with one destination register two register source 47193341Sjkim // operands. The instruction takes one cycle to execute in each the pipeline 48193341Sjkim // stages except the memory access stage, which takes 31 cycles. The two 49193341Sjkim // source operands are read during the decode stage and the result is ready 50193341Sjkim // after the memory access stage. 51193341Sjkim InstrItinData< IIC_ALUd, 52193341Sjkim [ InstrStage<1,[IF]> // one cycle in fetch stage 5367754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 5467754Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 5577424Smsmith , InstrStage<31,[MA]> // 31 cycles in memory access stage 5691116Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 5767754Smsmith [ 33 // result ready after 33 cycles 58151937Sjkim , 1 // first operand read after one cycle 5967754Smsmith , 1 ]>, // second operand read after one cycle 60151937Sjkim 61151937Sjkim // Shift instruction with one destination register and either two register 62151937Sjkim // source operands or one register source operand and one immediate operand. 63151937Sjkim // The instruction takes one cycle to execute in each of the pipeline stages. 64151937Sjkim // The two source operands are read during the decode stage and the result is 65151937Sjkim // ready after the memory access stage. 6667754Smsmith InstrItinData< IIC_SHT, 6767754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 6877424Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 6967754Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 7067754Smsmith , InstrStage<1,[MA]> // one cycle in memory access stage 7177424Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 7267754Smsmith [ 3 // result ready after three cycles 7377424Smsmith , 1 // first operand read after one cycle 7467754Smsmith , 1 ]>, // second operand read after one cycle 7567754Smsmith 7667754Smsmith // Branch instruction with one source operand register. The instruction takes 7771867Smsmith // one cycle to execute in each of the pipeline stages. The source operand is 7867754Smsmith // read during the decode stage. 7967754Smsmith InstrItinData< IIC_BR, 8067754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 8167754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 8277424Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 8367754Smsmith , InstrStage<1,[MA]> // one cycle in memory access stage 8467754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 8567754Smsmith [ 1 ]>, // first operand read after one cycle 8677424Smsmith 8767754Smsmith // Conditional branch instruction with two source operand registers. The 8867754Smsmith // instruction takes one cycle to execute in each of the pipeline stages. The 89167802Sjkim // two source operands are read during the decode stage. 9067754Smsmith InstrItinData< IIC_BRc, 9167754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 9267754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 9367754Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 94167802Sjkim , InstrStage<1,[MA]> // one cycle in memory access stage 9567754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 9667754Smsmith [ 1 // first operand read after one cycle 9767754Smsmith , 1 ]>, // second operand read after one cycle 9867754Smsmith 9967754Smsmith // Branch and link instruction with one destination register and one source 10067754Smsmith // operand register. The instruction takes one cycle to execute in each of 10167754Smsmith // the pipeline stages. The source operand is read during the decode stage 10267754Smsmith // and the destination register is ready after the writeback stage. 10399679Siwasaki InstrItinData< IIC_BRl, 10467754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 10577424Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 10667754Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 10767754Smsmith , InstrStage<1,[MA]> // one cycle in memory access stage 10867754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 10967754Smsmith [ 4 // result ready after four cycles 110151937Sjkim , 1 ]>, // first operand read after one cycle 111151937Sjkim 112151937Sjkim // Cache control instruction with two source operand registers. The 113167802Sjkim // instruction takes one cycle to execute in each of the pipeline stages 114151937Sjkim // except the memory access stage, which takes two cycles. The source 115151937Sjkim // operands are read during the decode stage. 11667754Smsmith InstrItinData< IIC_WDC, 11767754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 11867754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 11977424Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 12067754Smsmith , InstrStage<2,[MA]> // two cycles in memory access stage 12167754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 12291116Smsmith [ 1 // first operand read after one cycle 12367754Smsmith , 1 ]>, // second operand read after one cycle 12499679Siwasaki 12599679Siwasaki // Floating point instruction with one destination register and two source 12677424Smsmith // operand registers. The instruction takes one cycle to execute in each of 12777424Smsmith // the pipeline stages except the memory access stage, which takes two 12877424Smsmith // cycles. The source operands are read during the decode stage and the 12977424Smsmith // results are ready after the writeback stage. 13077424Smsmith InstrItinData< IIC_FPU, 13167754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 13267754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 13399146Siwasaki , InstrStage<1,[EX]> // one cycle in execute stage 13477424Smsmith , InstrStage<2,[MA]> // two cycles in memory access stage 13567754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 13667754Smsmith [ 5 // result ready after five cycles 13767754Smsmith , 1 // first operand read after one cycle 13867754Smsmith , 1 ]>, // second operand read after one cycle 13967754Smsmith 14077424Smsmith // Floating point divide instruction with one destination register and two 14167754Smsmith // source operand registers. The instruction takes one cycle to execute in 142151937Sjkim // each of the pipeline stages except the memory access stage, which takes 26 14377424Smsmith // cycles. The source operands are read during the decode stage and the 14467754Smsmith // results are ready after the writeback stage. 14567754Smsmith InstrItinData< IIC_FPUd, 14667754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 147151937Sjkim , InstrStage<1,[ID]> // one cycle in decode stage 14867754Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 14967754Smsmith , InstrStage<26,[MA]> // 26 cycles in memory access stage 15067754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 15167754Smsmith [ 29 // result ready after 29 cycles 152151937Sjkim , 1 // first operand read after one cycle 15377424Smsmith , 1 ]>, // second operand read after one cycle 15467754Smsmith 15567754Smsmith // Convert floating point to integer instruction with one destination 15667754Smsmith // register and one source operand register. The instruction takes one cycle 15777424Smsmith // to execute in each of the pipeline stages except the memory access stage, 15867754Smsmith // which takes three cycles. The source operands are read during the decode 159167802Sjkim // stage and the results are ready after the writeback stage. 160193267Sjkim InstrItinData< IIC_FPUi, 16167754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 16267754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 163167802Sjkim , InstrStage<1,[EX]> // one cycle in execute stage 16467754Smsmith , InstrStage<3,[MA]> // three cycles in memory access stage 16567754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 16667754Smsmith [ 6 // result ready after six cycles 16767754Smsmith , 1 ]>, // first operand read after one cycle 16867754Smsmith 16967754Smsmith // Convert integer to floating point instruction with one destination 170193267Sjkim // register and one source operand register. The instruction takes one cycle 17167754Smsmith // to execute in each of the pipeline stages except the memory access stage, 172107325Siwasaki // which takes two cycles. The source operands are read during the decode 17367754Smsmith // stage and the results are ready after the writeback stage. 174193267Sjkim InstrItinData< IIC_FPUf, 17567754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 176193267Sjkim , InstrStage<1,[ID]> // one cycle in decode stage 17767754Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 178193267Sjkim , InstrStage<2,[MA]> // two cycles in memory access stage 179193267Sjkim , InstrStage<1,[WB]>], // one cycle in write back stage 18067754Smsmith [ 5 // result ready after five cycles 18167754Smsmith , 1 ]>, // first operand read after one cycle 18267754Smsmith 18367754Smsmith // Floating point square root instruction with one destination register and 18467754Smsmith // one source operand register. The instruction takes one cycle to execute in 185193267Sjkim // each of the pipeline stages except the memory access stage, which takes 25 186193267Sjkim // cycles. The source operands are read during the decode stage and the 18767754Smsmith // results are ready after the writeback stage. 18867754Smsmith InstrItinData< IIC_FPUs, 18967754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 19067754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 19167754Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 192129684Snjl , InstrStage<25,[MA]> // 25 cycles in memory access stage 193193267Sjkim , InstrStage<1,[WB]>], // one cycle in write back stage 194129684Snjl [ 28 // result ready after 28 cycles 19567754Smsmith , 1 ]>, // first operand read after one cycle 19667754Smsmith 197129684Snjl // Floating point comparison instruction with one destination register and 19867754Smsmith // two source operand registers. The instruction takes one cycle to execute 19977424Smsmith // in each of the pipeline stages. The source operands are read during the 20067754Smsmith // decode stage and the results are ready after the execute stage. 20167754Smsmith InstrItinData< IIC_FPUc, 20267754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 20367754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 204193267Sjkim , InstrStage<1,[EX]> // one cycle in execute stage 20567754Smsmith , InstrStage<1,[MA]> // one cycle in memory access stage 20667754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 20767754Smsmith [ 2 // result ready after two cycles 20867754Smsmith , 1 // first operand read after one cycle 20967754Smsmith , 1 ]>, // second operand read after one cycle 210193267Sjkim 21167754Smsmith // FSL get instruction with one register or immediate source operand and one 21267754Smsmith // destination register. The instruction takes one cycle to execute in each 21367754Smsmith // of the pipeline stages. The one source operand is read during the decode 21467754Smsmith // stage and the result is ready after the execute stage. 21599679Siwasaki InstrItinData< IIC_FSLg, 216193267Sjkim [ InstrStage<1,[IF]> // one cycle in fetch stage 217193267Sjkim , InstrStage<1,[ID]> // one cycle in decode stage 218193267Sjkim , InstrStage<1,[EX]> // one cycle in execute stage 219193267Sjkim , InstrStage<1,[MA]> // one cycle in memory access stage 220193267Sjkim , InstrStage<1,[WB]>], // one cycle in write back stage 221193267Sjkim [ 2 // result ready after two cycles 222193267Sjkim , 1 ]>, // first operand read after one cycle 223193267Sjkim 224193267Sjkim // FSL put instruction with either two register source operands or one 225193267Sjkim // register source operand and one immediate operand. There is no result 22667754Smsmith // produced by the instruction. The instruction takes one cycle to execute in 22767754Smsmith // each of the pipeline stages. The two source operands are read during the 22867754Smsmith // decode stage. 22967754Smsmith InstrItinData< IIC_FSLp, 230193267Sjkim [ InstrStage<1,[IF]> // one cycle in fetch stage 23167754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 23267754Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 23367754Smsmith , InstrStage<1,[MA]> // one cycle in memory access stage 23477424Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 23577424Smsmith [ 1 // first operand read after one cycle 23667754Smsmith , 1 ]>, // second operand read after one cycle 23767754Smsmith 23867754Smsmith // Memory store instruction with either three register source operands or two 23967754Smsmith // register source operands and one immediate operand. There is no result 24067754Smsmith // produced by the instruction. The instruction takes one cycle to execute in 241193267Sjkim // each of the pipeline stages. All of the source operands are read during 24277424Smsmith // the decode stage. 24367754Smsmith InstrItinData< IIC_MEMs, 244167802Sjkim [ InstrStage<1,[IF]> // one cycle in fetch stage 245193267Sjkim , InstrStage<1,[ID]> // one cycle in decode stage 24677424Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 24767754Smsmith , InstrStage<1,[MA]> // one cycle in memory access stage 24867754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 24967754Smsmith [ 1 // first operand read after one cycle 25067754Smsmith , 1 // second operand read after one cycle 25199679Siwasaki , 1 ]>, // third operand read after one cycle 25267754Smsmith 25399679Siwasaki // Memory load instruction with one destination register and either two 25477424Smsmith // register source operands or one register source operand and one immediate 25567754Smsmith // operand. The instruction takes one cycle to execute in each of the 256167802Sjkim // pipeline stages. All of the source operands are read during the decode 257204773Sjkim // stage and the result is ready after the writeback stage. 25867754Smsmith InstrItinData< IIC_MEMl, 25967754Smsmith [ InstrStage<1,[IF]> // one cycle in fetch stage 26067754Smsmith , InstrStage<1,[ID]> // one cycle in decode stage 26167754Smsmith , InstrStage<1,[EX]> // one cycle in execute stage 26267754Smsmith , InstrStage<1,[MA]> // one cycle in memory access stage 26367754Smsmith , InstrStage<1,[WB]>], // one cycle in write back stage 26467754Smsmith [ 4 // result ready after four cycles 265193267Sjkim , 1 // second operand read after one cycle 266193267Sjkim , 1 ]> // third operand read after one cycle 267193267Sjkim]>; 26867754Smsmith