MBlazeSchedule5.td revision 221337
158234Skato//===- MBlazeSchedule5.td - MBlaze Scheduling Definitions --*- tablegen -*-===// 258234Skato// 358234Skato// The LLVM Compiler Infrastructure 458234Skato// 558234Skato// This file is distributed under the University of Illinois Open Source 658234Skato// License. See LICENSE.TXT for details. 758234Skato// 858234Skato//===----------------------------------------------------------------------===// 958234Skato 1058234Skato//===----------------------------------------------------------------------===// 1158234Skato// MBlaze instruction itineraries for the five stage pipeline. 1258234Skato//===----------------------------------------------------------------------===// 1358234Skatodef MBlazePipe5Itineraries : ProcessorItineraries< 1458234Skato [IF,ID,EX,MA,WB], [], [ 1558234Skato 1658234Skato // ALU instruction with one destination register and either two register 1758234Skato // source operands or one register source operand and one immediate operand. 1858234Skato // The instruction takes one cycle to execute in each of the stages. The 1958234Skato // two source operands are read during the decode stage and the result is 2058234Skato // ready after the execute stage. 2158234Skato InstrItinData< IIC_ALU, 2258234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 2358234Skato , InstrStage<1,[ID]> // one cycle in decode stage 2458234Skato , InstrStage<1,[EX]> // one cycle in execute stage 2558234Skato , InstrStage<1,[MA]> // one cycle in memory access stage 2658234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 27145748Snyan [ 2 // result ready after two cycles 28145748Snyan , 1 // first operand read after one cycle 2958234Skato , 1 ]>, // second operand read after one cycle 30106047Snyan 3158234Skato // ALU multiply instruction with one destination register and either two 32104459Snyan // register source operands or one register source operand and one immediate 33106047Snyan // operand. The instruction takes one cycle to execute in each of the 3458234Skato // pipeline stages. The two source operands are read during the decode stage 35106047Snyan // and the result is ready after the execute stage. 3658234Skato InstrItinData< IIC_ALUm, 3758234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 3858234Skato , InstrStage<1,[ID]> // one cycle in decode stage 3958234Skato , InstrStage<1,[EX]> // one cycle in execute stage 40148062Snyan , InstrStage<1,[MA]> // one cycle in memory access stage 4169793Sobrien , InstrStage<1,[WB]>], // one cycle in write back stage 42106047Snyan [ 2 // result ready after two cycles 43106047Snyan , 1 // first operand read after one cycle 4458234Skato , 1 ]>, // second operand read after one cycle 4558234Skato 4658234Skato // ALU divide instruction with one destination register two register source 4758234Skato // operands. The instruction takes one cycle to execute in each the pipeline 4858234Skato // stages except the memory access stage, which takes 31 cycles. The two 4958234Skato // source operands are read during the decode stage and the result is ready 5058234Skato // after the memory access stage. 5158234Skato InstrItinData< IIC_ALUd, 5258234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 5358234Skato , InstrStage<1,[ID]> // one cycle in decode stage 5458234Skato , InstrStage<1,[EX]> // one cycle in execute stage 5558234Skato , InstrStage<31,[MA]> // 31 cycles in memory access stage 5658234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 5758234Skato [ 33 // result ready after 33 cycles 5858234Skato , 1 // first operand read after one cycle 5958234Skato , 1 ]>, // second operand read after one cycle 6058234Skato 6158234Skato // Shift instruction with one destination register and either two register 6258234Skato // source operands or one register source operand and one immediate operand. 6358234Skato // The instruction takes one cycle to execute in each of the pipeline stages. 6458234Skato // The two source operands are read during the decode stage and the result is 6558234Skato // ready after the memory access stage. 6658234Skato InstrItinData< IIC_SHT, 6758234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 6858234Skato , InstrStage<1,[ID]> // one cycle in decode stage 6958234Skato , InstrStage<1,[EX]> // one cycle in execute stage 70106047Snyan , InstrStage<1,[MA]> // one cycle in memory access stage 7158234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 72106047Snyan [ 3 // result ready after three cycles 7358234Skato , 1 // first operand read after one cycle 74106047Snyan , 1 ]>, // second operand read after one cycle 7558234Skato 76106047Snyan // Branch instruction with one source operand register. The instruction takes 7758234Skato // one cycle to execute in each of the pipeline stages. The source operand is 7858234Skato // read during the decode stage. 7958234Skato InstrItinData< IIC_BR, 80108650Snyan [ InstrStage<1,[IF]> // one cycle in fetch stage 8158234Skato , InstrStage<1,[ID]> // one cycle in decode stage 8258234Skato , InstrStage<1,[EX]> // one cycle in execute stage 8358234Skato , InstrStage<1,[MA]> // one cycle in memory access stage 84106047Snyan , InstrStage<1,[WB]>], // one cycle in write back stage 85148062Snyan [ 1 ]>, // first operand read after one cycle 86106047Snyan 8758234Skato // Conditional branch instruction with two source operand registers. The 8858234Skato // instruction takes one cycle to execute in each of the pipeline stages. The 89106047Snyan // two source operands are read during the decode stage. 90106047Snyan InstrItinData< IIC_BRc, 91106047Snyan [ InstrStage<1,[IF]> // one cycle in fetch stage 92106047Snyan , InstrStage<1,[ID]> // one cycle in decode stage 9358234Skato , InstrStage<1,[EX]> // one cycle in execute stage 9458234Skato , InstrStage<1,[MA]> // one cycle in memory access stage 9558234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 9658234Skato [ 1 // first operand read after one cycle 9758234Skato , 1 ]>, // second operand read after one cycle 9858234Skato 9958234Skato // Branch and link instruction with one destination register and one source 10058234Skato // operand register. The instruction takes one cycle to execute in each of 10158234Skato // the pipeline stages. The source operand is read during the decode stage 10258234Skato // and the destination register is ready after the writeback stage. 10358234Skato InstrItinData< IIC_BRl, 10458234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 10558234Skato , InstrStage<1,[ID]> // one cycle in decode stage 10658234Skato , InstrStage<1,[EX]> // one cycle in execute stage 10758234Skato , InstrStage<1,[MA]> // one cycle in memory access stage 10858234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 10958234Skato [ 4 // result ready after four cycles 110106047Snyan , 1 ]>, // first operand read after one cycle 11158234Skato 11258234Skato // Cache control instruction with two source operand registers. The 11358234Skato // instruction takes one cycle to execute in each of the pipeline stages 114106047Snyan // except the memory access stage, which takes two cycles. The source 11558234Skato // operands are read during the decode stage. 116106047Snyan InstrItinData< IIC_WDC, 117106047Snyan [ InstrStage<1,[IF]> // one cycle in fetch stage 118106047Snyan , InstrStage<1,[ID]> // one cycle in decode stage 11958234Skato , InstrStage<1,[EX]> // one cycle in execute stage 12058234Skato , InstrStage<2,[MA]> // two cycles in memory access stage 12158234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 12258234Skato [ 1 // first operand read after one cycle 12358234Skato , 1 ]>, // second operand read after one cycle 12458234Skato 12558234Skato // Floating point instruction with one destination register and two source 126102231Strhodes // operand registers. The instruction takes one cycle to execute in each of 127102231Strhodes // the pipeline stages except the memory access stage, which takes two 12858234Skato // cycles. The source operands are read during the decode stage and the 12958234Skato // results are ready after the writeback stage. 13058234Skato InstrItinData< IIC_FPU, 13158234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 132102231Strhodes , InstrStage<1,[ID]> // one cycle in decode stage 13358234Skato , InstrStage<1,[EX]> // one cycle in execute stage 13458234Skato , InstrStage<2,[MA]> // two cycles in memory access stage 13558234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 13658234Skato [ 5 // result ready after five cycles 13758234Skato , 1 // first operand read after one cycle 13858234Skato , 1 ]>, // second operand read after one cycle 13958234Skato 14058234Skato // Floating point divide instruction with one destination register and two 14158234Skato // source operand registers. The instruction takes one cycle to execute in 14258234Skato // each of the pipeline stages except the memory access stage, which takes 26 14358234Skato // cycles. The source operands are read during the decode stage and the 14458234Skato // results are ready after the writeback stage. 14558234Skato InstrItinData< IIC_FPUd, 14658234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 14758234Skato , InstrStage<1,[ID]> // one cycle in decode stage 14858234Skato , InstrStage<1,[EX]> // one cycle in execute stage 14958234Skato , InstrStage<26,[MA]> // 26 cycles in memory access stage 15058234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 15158234Skato [ 29 // result ready after 29 cycles 15258234Skato , 1 // first operand read after one cycle 15358234Skato , 1 ]>, // second operand read after one cycle 15458234Skato 15558234Skato // Convert floating point to integer instruction with one destination 156106047Snyan // register and one source operand register. The instruction takes one cycle 15758234Skato // to execute in each of the pipeline stages except the memory access stage, 158106047Snyan // which takes three cycles. The source operands are read during the decode 159106047Snyan // stage and the results are ready after the writeback stage. 160106047Snyan InstrItinData< IIC_FPUi, 161145765Snyan [ InstrStage<1,[IF]> // one cycle in fetch stage 162106047Snyan , InstrStage<1,[ID]> // one cycle in decode stage 16358234Skato , InstrStage<1,[EX]> // one cycle in execute stage 164148062Snyan , InstrStage<3,[MA]> // three cycles in memory access stage 165106047Snyan , InstrStage<1,[WB]>], // one cycle in write back stage 166106047Snyan [ 6 // result ready after six cycles 167106047Snyan , 1 ]>, // first operand read after one cycle 168106047Snyan 169106047Snyan // Convert integer to floating point instruction with one destination 170106047Snyan // register and one source operand register. The instruction takes one cycle 17158234Skato // to execute in each of the pipeline stages except the memory access stage, 172145765Snyan // which takes two cycles. The source operands are read during the decode 17358234Skato // stage and the results are ready after the writeback stage. 17458234Skato InstrItinData< IIC_FPUf, 17558234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 17658234Skato , InstrStage<1,[ID]> // one cycle in decode stage 177106047Snyan , InstrStage<1,[EX]> // one cycle in execute stage 17858234Skato , InstrStage<2,[MA]> // two cycles in memory access stage 179106047Snyan , InstrStage<1,[WB]>], // one cycle in write back stage 180108650Snyan [ 5 // result ready after five cycles 18158234Skato , 1 ]>, // first operand read after one cycle 182106047Snyan 18358234Skato // Floating point square root instruction with one destination register and 18458234Skato // one source operand register. The instruction takes one cycle to execute in 18558234Skato // each of the pipeline stages except the memory access stage, which takes 25 18658234Skato // cycles. The source operands are read during the decode stage and the 18758234Skato // results are ready after the writeback stage. 18858234Skato InstrItinData< IIC_FPUs, 18958234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 19058234Skato , InstrStage<1,[ID]> // one cycle in decode stage 19158234Skato , InstrStage<1,[EX]> // one cycle in execute stage 19258234Skato , InstrStage<25,[MA]> // 25 cycles in memory access stage 19358234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 19458234Skato [ 28 // result ready after 28 cycles 19558234Skato , 1 ]>, // first operand read after one cycle 19658234Skato 19758234Skato // Floating point comparison instruction with one destination register and 19858234Skato // two source operand registers. The instruction takes one cycle to execute 19958234Skato // in each of the pipeline stages. The source operands are read during the 20058234Skato // decode stage and the results are ready after the execute stage. 20158234Skato InstrItinData< IIC_FPUc, 20258234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 20358234Skato , InstrStage<1,[ID]> // one cycle in decode stage 20458234Skato , InstrStage<1,[EX]> // one cycle in execute stage 20558234Skato , InstrStage<1,[MA]> // one cycle in memory access stage 20658234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 20758234Skato [ 2 // result ready after two cycles 20858234Skato , 1 // first operand read after one cycle 20958234Skato , 1 ]>, // second operand read after one cycle 21058234Skato 21158234Skato // FSL get instruction with one register or immediate source operand and one 21258234Skato // destination register. The instruction takes one cycle to execute in each 21358234Skato // of the pipeline stages. The one source operand is read during the decode 21458234Skato // stage and the result is ready after the execute stage. 21558234Skato InstrItinData< IIC_FSLg, 21658234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 21758234Skato , InstrStage<1,[ID]> // one cycle in decode stage 21858234Skato , InstrStage<1,[EX]> // one cycle in execute stage 21958234Skato , InstrStage<1,[MA]> // one cycle in memory access stage 22058234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 22158234Skato [ 2 // result ready after two cycles 22258234Skato , 1 ]>, // first operand read after one cycle 22358234Skato 22458234Skato // FSL put instruction with either two register source operands or one 22558234Skato // register source operand and one immediate operand. There is no result 22658234Skato // produced by the instruction. The instruction takes one cycle to execute in 22758234Skato // each of the pipeline stages. The two source operands are read during the 228106047Snyan // decode stage. 229106047Snyan InstrItinData< IIC_FSLp, 230106047Snyan [ InstrStage<1,[IF]> // one cycle in fetch stage 231106047Snyan , InstrStage<1,[ID]> // one cycle in decode stage 232106047Snyan , InstrStage<1,[EX]> // one cycle in execute stage 23358234Skato , InstrStage<1,[MA]> // one cycle in memory access stage 234136887Snyan , InstrStage<1,[WB]>], // one cycle in write back stage 235106047Snyan [ 1 // first operand read after one cycle 236106047Snyan , 1 ]>, // second operand read after one cycle 237106047Snyan 238106047Snyan // Memory store instruction with either three register source operands or two 239106047Snyan // register source operands and one immediate operand. There is no result 240106047Snyan // produced by the instruction. The instruction takes one cycle to execute in 241106047Snyan // each of the pipeline stages. All of the source operands are read during 24258234Skato // the decode stage. 24358234Skato InstrItinData< IIC_MEMs, 244106047Snyan [ InstrStage<1,[IF]> // one cycle in fetch stage 245106047Snyan , InstrStage<1,[ID]> // one cycle in decode stage 24658234Skato , InstrStage<1,[EX]> // one cycle in execute stage 247106047Snyan , InstrStage<1,[MA]> // one cycle in memory access stage 24858234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 24958234Skato [ 1 // first operand read after one cycle 25058234Skato , 1 // second operand read after one cycle 25158234Skato , 1 ]>, // third operand read after one cycle 25258234Skato 25358234Skato // Memory load instruction with one destination register and either two 254108650Snyan // register source operands or one register source operand and one immediate 25558234Skato // operand. The instruction takes one cycle to execute in each of the 25658234Skato // pipeline stages. All of the source operands are read during the decode 257145765Snyan // stage and the result is ready after the writeback stage. 25858234Skato InstrItinData< IIC_MEMl, 25958234Skato [ InstrStage<1,[IF]> // one cycle in fetch stage 26058234Skato , InstrStage<1,[ID]> // one cycle in decode stage 26158234Skato , InstrStage<1,[EX]> // one cycle in execute stage 26258234Skato , InstrStage<1,[MA]> // one cycle in memory access stage 26358234Skato , InstrStage<1,[WB]>], // one cycle in write back stage 26458234Skato [ 4 // result ready after four cycles 26558234Skato , 1 // second operand read after one cycle 26658234Skato , 1 ]> // third operand read after one cycle 267106047Snyan]>; 26858234Skato