HexagonISelLowering.cpp revision 249423
1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Hexagon uses to lower LLVM code 11// into a selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "HexagonISelLowering.h" 16#include "HexagonMachineFunctionInfo.h" 17#include "HexagonSubtarget.h" 18#include "HexagonTargetMachine.h" 19#include "HexagonTargetObjectFile.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineJumpTableInfo.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/SelectionDAGISel.h" 27#include "llvm/CodeGen/ValueTypes.h" 28#include "llvm/IR/CallingConv.h" 29#include "llvm/IR/DerivedTypes.h" 30#include "llvm/IR/Function.h" 31#include "llvm/IR/GlobalAlias.h" 32#include "llvm/IR/GlobalVariable.h" 33#include "llvm/IR/InlineAsm.h" 34#include "llvm/IR/Intrinsics.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/raw_ostream.h" 39 40using namespace llvm; 41 42const unsigned Hexagon_MAX_RET_SIZE = 64; 43 44static cl::opt<bool> 45EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, 46 cl::desc("Control jump table emission on Hexagon target")); 47 48int NumNamedVarArgParams = -1; 49 50// Implement calling convention for Hexagon. 51static bool 52CC_Hexagon(unsigned ValNo, MVT ValVT, 53 MVT LocVT, CCValAssign::LocInfo LocInfo, 54 ISD::ArgFlagsTy ArgFlags, CCState &State); 55 56static bool 57CC_Hexagon32(unsigned ValNo, MVT ValVT, 58 MVT LocVT, CCValAssign::LocInfo LocInfo, 59 ISD::ArgFlagsTy ArgFlags, CCState &State); 60 61static bool 62CC_Hexagon64(unsigned ValNo, MVT ValVT, 63 MVT LocVT, CCValAssign::LocInfo LocInfo, 64 ISD::ArgFlagsTy ArgFlags, CCState &State); 65 66static bool 67RetCC_Hexagon(unsigned ValNo, MVT ValVT, 68 MVT LocVT, CCValAssign::LocInfo LocInfo, 69 ISD::ArgFlagsTy ArgFlags, CCState &State); 70 71static bool 72RetCC_Hexagon32(unsigned ValNo, MVT ValVT, 73 MVT LocVT, CCValAssign::LocInfo LocInfo, 74 ISD::ArgFlagsTy ArgFlags, CCState &State); 75 76static bool 77RetCC_Hexagon64(unsigned ValNo, MVT ValVT, 78 MVT LocVT, CCValAssign::LocInfo LocInfo, 79 ISD::ArgFlagsTy ArgFlags, CCState &State); 80 81static bool 82CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT, 83 MVT LocVT, CCValAssign::LocInfo LocInfo, 84 ISD::ArgFlagsTy ArgFlags, CCState &State) { 85 86 // NumNamedVarArgParams can not be zero for a VarArg function. 87 assert ( (NumNamedVarArgParams > 0) && 88 "NumNamedVarArgParams is not bigger than zero."); 89 90 if ( (int)ValNo < NumNamedVarArgParams ) { 91 // Deal with named arguments. 92 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State); 93 } 94 95 // Deal with un-named arguments. 96 unsigned ofst; 97 if (ArgFlags.isByVal()) { 98 // If pass-by-value, the size allocated on stack is decided 99 // by ArgFlags.getByValSize(), not by the size of LocVT. 100 assert ((ArgFlags.getByValSize() > 8) && 101 "ByValSize must be bigger than 8 bytes"); 102 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4); 103 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 104 return false; 105 } 106 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { 107 LocVT = MVT::i32; 108 ValVT = MVT::i32; 109 if (ArgFlags.isSExt()) 110 LocInfo = CCValAssign::SExt; 111 else if (ArgFlags.isZExt()) 112 LocInfo = CCValAssign::ZExt; 113 else 114 LocInfo = CCValAssign::AExt; 115 } 116 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 117 ofst = State.AllocateStack(4, 4); 118 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 119 return false; 120 } 121 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 122 ofst = State.AllocateStack(8, 8); 123 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 124 return false; 125 } 126 llvm_unreachable(0); 127} 128 129 130static bool 131CC_Hexagon (unsigned ValNo, MVT ValVT, 132 MVT LocVT, CCValAssign::LocInfo LocInfo, 133 ISD::ArgFlagsTy ArgFlags, CCState &State) { 134 135 if (ArgFlags.isByVal()) { 136 // Passed on stack. 137 assert ((ArgFlags.getByValSize() > 8) && 138 "ByValSize must be bigger than 8 bytes"); 139 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4); 140 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 141 return false; 142 } 143 144 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { 145 LocVT = MVT::i32; 146 ValVT = MVT::i32; 147 if (ArgFlags.isSExt()) 148 LocInfo = CCValAssign::SExt; 149 else if (ArgFlags.isZExt()) 150 LocInfo = CCValAssign::ZExt; 151 else 152 LocInfo = CCValAssign::AExt; 153 } 154 155 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 156 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 157 return false; 158 } 159 160 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 161 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 162 return false; 163 } 164 165 return true; // CC didn't match. 166} 167 168 169static bool CC_Hexagon32(unsigned ValNo, MVT ValVT, 170 MVT LocVT, CCValAssign::LocInfo LocInfo, 171 ISD::ArgFlagsTy ArgFlags, CCState &State) { 172 173 static const uint16_t RegList[] = { 174 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 175 Hexagon::R5 176 }; 177 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 178 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 179 return false; 180 } 181 182 unsigned Offset = State.AllocateStack(4, 4); 183 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 184 return false; 185} 186 187static bool CC_Hexagon64(unsigned ValNo, MVT ValVT, 188 MVT LocVT, CCValAssign::LocInfo LocInfo, 189 ISD::ArgFlagsTy ArgFlags, CCState &State) { 190 191 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 193 return false; 194 } 195 196 static const uint16_t RegList1[] = { 197 Hexagon::D1, Hexagon::D2 198 }; 199 static const uint16_t RegList2[] = { 200 Hexagon::R1, Hexagon::R3 201 }; 202 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) { 203 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 204 return false; 205 } 206 207 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2); 208 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 209 return false; 210} 211 212static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT, 213 MVT LocVT, CCValAssign::LocInfo LocInfo, 214 ISD::ArgFlagsTy ArgFlags, CCState &State) { 215 216 217 if (LocVT == MVT::i1 || 218 LocVT == MVT::i8 || 219 LocVT == MVT::i16) { 220 LocVT = MVT::i32; 221 ValVT = MVT::i32; 222 if (ArgFlags.isSExt()) 223 LocInfo = CCValAssign::SExt; 224 else if (ArgFlags.isZExt()) 225 LocInfo = CCValAssign::ZExt; 226 else 227 LocInfo = CCValAssign::AExt; 228 } 229 230 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 231 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 232 return false; 233 } 234 235 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 236 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 237 return false; 238 } 239 240 return true; // CC didn't match. 241} 242 243static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT, 244 MVT LocVT, CCValAssign::LocInfo LocInfo, 245 ISD::ArgFlagsTy ArgFlags, CCState &State) { 246 247 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 248 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) { 249 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 250 return false; 251 } 252 } 253 254 unsigned Offset = State.AllocateStack(4, 4); 255 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 256 return false; 257} 258 259static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, 260 MVT LocVT, CCValAssign::LocInfo LocInfo, 261 ISD::ArgFlagsTy ArgFlags, CCState &State) { 262 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 263 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 264 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 265 return false; 266 } 267 } 268 269 unsigned Offset = State.AllocateStack(8, 8); 270 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 271 return false; 272} 273 274SDValue 275HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) 276const { 277 return SDValue(); 278} 279 280/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 281/// by "Src" to address "Dst" of size "Size". Alignment information is 282/// specified by the specific parameter attribute. The copy will be passed as 283/// a byval function parameter. Sometimes what we are copying is the end of a 284/// larger object, the part that does not fit in registers. 285static SDValue 286CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 287 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 288 DebugLoc dl) { 289 290 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 291 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 292 /*isVolatile=*/false, /*AlwaysInline=*/false, 293 MachinePointerInfo(), MachinePointerInfo()); 294} 295 296 297// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is 298// passed by value, the function prototype is modified to return void and 299// the value is stored in memory pointed by a pointer passed by caller. 300SDValue 301HexagonTargetLowering::LowerReturn(SDValue Chain, 302 CallingConv::ID CallConv, bool isVarArg, 303 const SmallVectorImpl<ISD::OutputArg> &Outs, 304 const SmallVectorImpl<SDValue> &OutVals, 305 DebugLoc dl, SelectionDAG &DAG) const { 306 307 // CCValAssign - represent the assignment of the return value to locations. 308 SmallVector<CCValAssign, 16> RVLocs; 309 310 // CCState - Info about the registers and stack slot. 311 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 312 getTargetMachine(), RVLocs, *DAG.getContext()); 313 314 // Analyze return values of ISD::RET 315 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon); 316 317 SDValue Flag; 318 SmallVector<SDValue, 4> RetOps(1, Chain); 319 320 // Copy the result values into the output registers. 321 for (unsigned i = 0; i != RVLocs.size(); ++i) { 322 CCValAssign &VA = RVLocs[i]; 323 324 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 325 326 // Guarantee that all emitted copies are stuck together with flags. 327 Flag = Chain.getValue(1); 328 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 329 } 330 331 RetOps[0] = Chain; // Update chain. 332 333 // Add the flag if we have it. 334 if (Flag.getNode()) 335 RetOps.push_back(Flag); 336 337 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, 338 &RetOps[0], RetOps.size()); 339} 340 341 342 343 344/// LowerCallResult - Lower the result values of an ISD::CALL into the 345/// appropriate copies out of appropriate physical registers. This assumes that 346/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 347/// being lowered. Returns a SDNode with the same number of values as the 348/// ISD::CALL. 349SDValue 350HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 351 CallingConv::ID CallConv, bool isVarArg, 352 const 353 SmallVectorImpl<ISD::InputArg> &Ins, 354 DebugLoc dl, SelectionDAG &DAG, 355 SmallVectorImpl<SDValue> &InVals, 356 const SmallVectorImpl<SDValue> &OutVals, 357 SDValue Callee) const { 358 359 // Assign locations to each value returned by this call. 360 SmallVector<CCValAssign, 16> RVLocs; 361 362 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 363 getTargetMachine(), RVLocs, *DAG.getContext()); 364 365 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon); 366 367 // Copy all of the result registers out of their specified physreg. 368 for (unsigned i = 0; i != RVLocs.size(); ++i) { 369 Chain = DAG.getCopyFromReg(Chain, dl, 370 RVLocs[i].getLocReg(), 371 RVLocs[i].getValVT(), InFlag).getValue(1); 372 InFlag = Chain.getValue(2); 373 InVals.push_back(Chain.getValue(0)); 374 } 375 376 return Chain; 377} 378 379/// LowerCall - Functions arguments are copied from virtual regs to 380/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 381SDValue 382HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 383 SmallVectorImpl<SDValue> &InVals) const { 384 SelectionDAG &DAG = CLI.DAG; 385 DebugLoc &dl = CLI.DL; 386 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 387 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 388 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 389 SDValue Chain = CLI.Chain; 390 SDValue Callee = CLI.Callee; 391 bool &isTailCall = CLI.IsTailCall; 392 CallingConv::ID CallConv = CLI.CallConv; 393 bool isVarArg = CLI.IsVarArg; 394 395 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 396 397 // Analyze operands of the call, assigning locations to each operand. 398 SmallVector<CCValAssign, 16> ArgLocs; 399 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 400 getTargetMachine(), ArgLocs, *DAG.getContext()); 401 402 // Check for varargs. 403 NumNamedVarArgParams = -1; 404 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee)) 405 { 406 const Function* CalleeFn = NULL; 407 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32); 408 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal()))) 409 { 410 // If a function has zero args and is a vararg function, that's 411 // disallowed so it must be an undeclared function. Do not assume 412 // varargs if the callee is undefined. 413 if (CalleeFn->isVarArg() && 414 CalleeFn->getFunctionType()->getNumParams() != 0) { 415 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams(); 416 } 417 } 418 } 419 420 if (NumNamedVarArgParams > 0) 421 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg); 422 else 423 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon); 424 425 426 if(isTailCall) { 427 bool StructAttrFlag = 428 DAG.getMachineFunction().getFunction()->hasStructRetAttr(); 429 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 430 isVarArg, IsStructRet, 431 StructAttrFlag, 432 Outs, OutVals, Ins, DAG); 433 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){ 434 CCValAssign &VA = ArgLocs[i]; 435 if (VA.isMemLoc()) { 436 isTailCall = false; 437 break; 438 } 439 } 440 if (isTailCall) { 441 DEBUG(dbgs () << "Eligible for Tail Call\n"); 442 } else { 443 DEBUG(dbgs () << 444 "Argument must be passed on stack. Not eligible for Tail Call\n"); 445 } 446 } 447 // Get a count of how many bytes are to be pushed on the stack. 448 unsigned NumBytes = CCInfo.getNextStackOffset(); 449 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 450 SmallVector<SDValue, 8> MemOpChains; 451 452 SDValue StackPtr = 453 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(), 454 getPointerTy()); 455 456 // Walk the register/memloc assignments, inserting copies/loads. 457 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 458 CCValAssign &VA = ArgLocs[i]; 459 SDValue Arg = OutVals[i]; 460 ISD::ArgFlagsTy Flags = Outs[i].Flags; 461 462 // Promote the value if needed. 463 switch (VA.getLocInfo()) { 464 default: 465 // Loc info must be one of Full, SExt, ZExt, or AExt. 466 llvm_unreachable("Unknown loc info!"); 467 case CCValAssign::Full: 468 break; 469 case CCValAssign::SExt: 470 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 471 break; 472 case CCValAssign::ZExt: 473 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 474 break; 475 case CCValAssign::AExt: 476 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 477 break; 478 } 479 480 if (VA.isMemLoc()) { 481 unsigned LocMemOffset = VA.getLocMemOffset(); 482 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType()); 483 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 484 485 if (Flags.isByVal()) { 486 // The argument is a struct passed by value. According to LLVM, "Arg" 487 // is is pointer. 488 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain, 489 Flags, DAG, dl)); 490 } else { 491 // The argument is not passed by value. "Arg" is a buildin type. It is 492 // not a pointer. 493 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 494 MachinePointerInfo(),false, false, 495 0)); 496 } 497 continue; 498 } 499 500 // Arguments that can be passed on register must be kept at RegsToPass 501 // vector. 502 if (VA.isRegLoc()) { 503 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 504 } 505 } 506 507 // Transform all store nodes into one single node because all store 508 // nodes are independent of each other. 509 if (!MemOpChains.empty()) { 510 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], 511 MemOpChains.size()); 512 } 513 514 if (!isTailCall) 515 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, 516 getPointerTy(), true)); 517 518 // Build a sequence of copy-to-reg nodes chained together with token 519 // chain and flag operands which copy the outgoing args into registers. 520 // The InFlag in necessary since all emitted instructions must be 521 // stuck together. 522 SDValue InFlag; 523 if (!isTailCall) { 524 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 525 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 526 RegsToPass[i].second, InFlag); 527 InFlag = Chain.getValue(1); 528 } 529 } 530 531 // For tail calls lower the arguments to the 'real' stack slot. 532 if (isTailCall) { 533 // Force all the incoming stack arguments to be loaded from the stack 534 // before any new outgoing arguments are stored to the stack, because the 535 // outgoing stack slots may alias the incoming argument stack slots, and 536 // the alias isn't otherwise explicit. This is slightly more conservative 537 // than necessary, because it means that each store effectively depends 538 // on every argument instead of just those arguments it would clobber. 539 // 540 // Do not flag preceding copytoreg stuff together with the following stuff. 541 InFlag = SDValue(); 542 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 543 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 544 RegsToPass[i].second, InFlag); 545 InFlag = Chain.getValue(1); 546 } 547 InFlag =SDValue(); 548 } 549 550 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 551 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 552 // node so that legalize doesn't hack it. 553 if (flag_aligned_memcpy) { 554 const char *MemcpyName = 555 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes"; 556 Callee = 557 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy()); 558 flag_aligned_memcpy = false; 559 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 560 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy()); 561 } else if (ExternalSymbolSDNode *S = 562 dyn_cast<ExternalSymbolSDNode>(Callee)) { 563 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 564 } 565 566 // Returns a chain & a flag for retval copy to use. 567 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 568 SmallVector<SDValue, 8> Ops; 569 Ops.push_back(Chain); 570 Ops.push_back(Callee); 571 572 // Add argument registers to the end of the list so that they are 573 // known live into the call. 574 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 575 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 576 RegsToPass[i].second.getValueType())); 577 } 578 579 if (InFlag.getNode()) { 580 Ops.push_back(InFlag); 581 } 582 583 if (isTailCall) 584 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 585 586 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 587 InFlag = Chain.getValue(1); 588 589 // Create the CALLSEQ_END node. 590 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 591 DAG.getIntPtrConstant(0, true), InFlag); 592 InFlag = Chain.getValue(1); 593 594 // Handle result values, copying them out of physregs into vregs that we 595 // return. 596 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG, 597 InVals, OutVals, Callee); 598} 599 600static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, 601 bool isSEXTLoad, SDValue &Base, 602 SDValue &Offset, bool &isInc, 603 SelectionDAG &DAG) { 604 if (Ptr->getOpcode() != ISD::ADD) 605 return false; 606 607 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 608 isInc = (Ptr->getOpcode() == ISD::ADD); 609 Base = Ptr->getOperand(0); 610 Offset = Ptr->getOperand(1); 611 // Ensure that Offset is a constant. 612 return (isa<ConstantSDNode>(Offset)); 613 } 614 615 return false; 616} 617 618// TODO: Put this function along with the other isS* functions in 619// HexagonISelDAGToDAG.cpp into a common file. Or better still, use the 620// functions defined in HexagonOperands.td. 621static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) { 622 ConstantSDNode *N = cast<ConstantSDNode>(S); 623 624 // immS4 predicate - True if the immediate fits in a 4-bit sign extended. 625 // field. 626 int64_t v = (int64_t)N->getSExtValue(); 627 int64_t m = 0; 628 if (ShiftAmount > 0) { 629 m = v % ShiftAmount; 630 v = v >> ShiftAmount; 631 } 632 return (v <= 7) && (v >= -8) && (m == 0); 633} 634 635/// getPostIndexedAddressParts - returns true by value, base pointer and 636/// offset pointer and addressing mode by reference if this node can be 637/// combined with a load / store to form a post-indexed load / store. 638bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 639 SDValue &Base, 640 SDValue &Offset, 641 ISD::MemIndexedMode &AM, 642 SelectionDAG &DAG) const 643{ 644 EVT VT; 645 SDValue Ptr; 646 bool isSEXTLoad = false; 647 648 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 649 VT = LD->getMemoryVT(); 650 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 651 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 652 VT = ST->getMemoryVT(); 653 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) { 654 return false; 655 } 656 } else { 657 return false; 658 } 659 660 bool isInc = false; 661 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 662 isInc, DAG); 663 // ShiftAmount = number of left-shifted bits in the Hexagon instruction. 664 int ShiftAmount = VT.getSizeInBits() / 16; 665 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) { 666 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 667 return true; 668 } 669 670 return false; 671} 672 673SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, 674 SelectionDAG &DAG) const { 675 SDNode *Node = Op.getNode(); 676 MachineFunction &MF = DAG.getMachineFunction(); 677 HexagonMachineFunctionInfo *FuncInfo = 678 MF.getInfo<HexagonMachineFunctionInfo>(); 679 switch (Node->getOpcode()) { 680 case ISD::INLINEASM: { 681 unsigned NumOps = Node->getNumOperands(); 682 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 683 --NumOps; // Ignore the flag operand. 684 685 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 686 if (FuncInfo->hasClobberLR()) 687 break; 688 unsigned Flags = 689 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 690 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 691 ++i; // Skip the ID value. 692 693 switch (InlineAsm::getKind(Flags)) { 694 default: llvm_unreachable("Bad flags!"); 695 case InlineAsm::Kind_RegDef: 696 case InlineAsm::Kind_RegUse: 697 case InlineAsm::Kind_Imm: 698 case InlineAsm::Kind_Clobber: 699 case InlineAsm::Kind_Mem: { 700 for (; NumVals; --NumVals, ++i) {} 701 break; 702 } 703 case InlineAsm::Kind_RegDefEarlyClobber: { 704 for (; NumVals; --NumVals, ++i) { 705 unsigned Reg = 706 cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 707 708 // Check it to be lr 709 if (Reg == TM.getRegisterInfo()->getRARegister()) { 710 FuncInfo->setHasClobberLR(true); 711 break; 712 } 713 } 714 break; 715 } 716 } 717 } 718 } 719 } // Node->getOpcode 720 return Op; 721} 722 723 724// 725// Taken from the XCore backend. 726// 727SDValue HexagonTargetLowering:: 728LowerBR_JT(SDValue Op, SelectionDAG &DAG) const 729{ 730 SDValue Chain = Op.getOperand(0); 731 SDValue Table = Op.getOperand(1); 732 SDValue Index = Op.getOperand(2); 733 DebugLoc dl = Op.getDebugLoc(); 734 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 735 unsigned JTI = JT->getIndex(); 736 MachineFunction &MF = DAG.getMachineFunction(); 737 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); 738 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); 739 740 // Mark all jump table targets as address taken. 741 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables(); 742 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs; 743 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { 744 MachineBasicBlock *MBB = JTBBs[i]; 745 MBB->setHasAddressTaken(); 746 // This line is needed to set the hasAddressTaken flag on the BasicBlock 747 // object. 748 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock())); 749 } 750 751 SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl, 752 getPointerTy(), TargetJT); 753 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 754 DAG.getConstant(2, MVT::i32)); 755 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase, 756 ShiftIndex); 757 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress, 758 MachinePointerInfo(), false, false, false, 759 0); 760 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget); 761} 762 763 764SDValue 765HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 766 SelectionDAG &DAG) const { 767 SDValue Chain = Op.getOperand(0); 768 SDValue Size = Op.getOperand(1); 769 DebugLoc dl = Op.getDebugLoc(); 770 771 unsigned SPReg = getStackPointerRegisterToSaveRestore(); 772 773 // Get a reference to the stack pointer. 774 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 775 776 // Subtract the dynamic size from the actual stack size to 777 // obtain the new stack size. 778 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 779 780 // 781 // For Hexagon, the outgoing memory arguments area should be on top of the 782 // alloca area on the stack i.e., the outgoing memory arguments should be 783 // at a lower address than the alloca area. Move the alloca area down the 784 // stack by adding back the space reserved for outgoing arguments to SP 785 // here. 786 // 787 // We do not know what the size of the outgoing args is at this point. 788 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the 789 // stack pointer. We patch this instruction with the correct, known 790 // offset in emitPrologue(). 791 // 792 // Use a placeholder immediate (zero) for now. This will be patched up 793 // by emitPrologue(). 794 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl, 795 MVT::i32, 796 Sub, 797 DAG.getConstant(0, MVT::i32)); 798 799 // The Sub result contains the new stack start address, so it 800 // must be placed in the stack pointer register. 801 SDValue CopyChain = DAG.getCopyToReg(Chain, dl, 802 TM.getRegisterInfo()->getStackRegister(), 803 Sub); 804 805 SDValue Ops[2] = { ArgAdjust, CopyChain }; 806 return DAG.getMergeValues(Ops, 2, dl); 807} 808 809SDValue 810HexagonTargetLowering::LowerFormalArguments(SDValue Chain, 811 CallingConv::ID CallConv, 812 bool isVarArg, 813 const 814 SmallVectorImpl<ISD::InputArg> &Ins, 815 DebugLoc dl, SelectionDAG &DAG, 816 SmallVectorImpl<SDValue> &InVals) 817const { 818 819 MachineFunction &MF = DAG.getMachineFunction(); 820 MachineFrameInfo *MFI = MF.getFrameInfo(); 821 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 822 HexagonMachineFunctionInfo *FuncInfo = 823 MF.getInfo<HexagonMachineFunctionInfo>(); 824 825 826 // Assign locations to all of the incoming arguments. 827 SmallVector<CCValAssign, 16> ArgLocs; 828 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 829 getTargetMachine(), ArgLocs, *DAG.getContext()); 830 831 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon); 832 833 // For LLVM, in the case when returning a struct by value (>8byte), 834 // the first argument is a pointer that points to the location on caller's 835 // stack where the return value will be stored. For Hexagon, the location on 836 // caller's stack is passed only when the struct size is smaller than (and 837 // equal to) 8 bytes. If not, no address will be passed into callee and 838 // callee return the result direclty through R0/R1. 839 840 SmallVector<SDValue, 4> MemOps; 841 842 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 843 CCValAssign &VA = ArgLocs[i]; 844 ISD::ArgFlagsTy Flags = Ins[i].Flags; 845 unsigned ObjSize; 846 unsigned StackLocation; 847 int FI; 848 849 if ( (VA.isRegLoc() && !Flags.isByVal()) 850 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) { 851 // Arguments passed in registers 852 // 1. int, long long, ptr args that get allocated in register. 853 // 2. Large struct that gets an register to put its address in. 854 EVT RegVT = VA.getLocVT(); 855 if (RegVT == MVT::i8 || RegVT == MVT::i16 || 856 RegVT == MVT::i32 || RegVT == MVT::f32) { 857 unsigned VReg = 858 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass); 859 RegInfo.addLiveIn(VA.getLocReg(), VReg); 860 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 861 } else if (RegVT == MVT::i64) { 862 unsigned VReg = 863 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass); 864 RegInfo.addLiveIn(VA.getLocReg(), VReg); 865 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 866 } else { 867 assert (0); 868 } 869 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) { 870 assert (0 && "ByValSize must be bigger than 8 bytes"); 871 } else { 872 // Sanity check. 873 assert(VA.isMemLoc()); 874 875 if (Flags.isByVal()) { 876 // If it's a byval parameter, then we need to compute the 877 // "real" size, not the size of the pointer. 878 ObjSize = Flags.getByValSize(); 879 } else { 880 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3; 881 } 882 883 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset(); 884 // Create the frame index object for this incoming parameter... 885 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true); 886 887 // Create the SelectionDAG nodes cordl, responding to a load 888 // from this parameter. 889 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 890 891 if (Flags.isByVal()) { 892 // If it's a pass-by-value aggregate, then do not dereference the stack 893 // location. Instead, we should generate a reference to the stack 894 // location. 895 InVals.push_back(FIN); 896 } else { 897 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 898 MachinePointerInfo(), false, false, 899 false, 0)); 900 } 901 } 902 } 903 904 if (!MemOps.empty()) 905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], 906 MemOps.size()); 907 908 if (isVarArg) { 909 // This will point to the next argument passed via stack. 910 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize, 911 HEXAGON_LRFP_SIZE + 912 CCInfo.getNextStackOffset(), 913 true); 914 FuncInfo->setVarArgsFrameIndex(FrameIndex); 915 } 916 917 return Chain; 918} 919 920SDValue 921HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 922 // VASTART stores the address of the VarArgsFrameIndex slot into the 923 // memory location argument. 924 MachineFunction &MF = DAG.getMachineFunction(); 925 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>(); 926 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32); 927 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 928 return DAG.getStore(Op.getOperand(0), Op.getDebugLoc(), Addr, 929 Op.getOperand(1), MachinePointerInfo(SV), false, 930 false, 0); 931} 932 933SDValue 934HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 935 SDValue LHS = Op.getOperand(0); 936 SDValue RHS = Op.getOperand(1); 937 SDValue CC = Op.getOperand(4); 938 SDValue TrueVal = Op.getOperand(2); 939 SDValue FalseVal = Op.getOperand(3); 940 DebugLoc dl = Op.getDebugLoc(); 941 SDNode* OpNode = Op.getNode(); 942 EVT SVT = OpNode->getValueType(0); 943 944 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC); 945 return DAG.getNode(ISD::SELECT, dl, SVT, Cond, TrueVal, FalseVal); 946} 947 948SDValue 949HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 950 EVT ValTy = Op.getValueType(); 951 952 DebugLoc dl = Op.getDebugLoc(); 953 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 954 SDValue Res; 955 if (CP->isMachineConstantPoolEntry()) 956 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy, 957 CP->getAlignment()); 958 else 959 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy, 960 CP->getAlignment()); 961 return DAG.getNode(HexagonISD::CONST32, dl, ValTy, Res); 962} 963 964SDValue 965HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { 966 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 967 MachineFunction &MF = DAG.getMachineFunction(); 968 MachineFrameInfo *MFI = MF.getFrameInfo(); 969 MFI->setReturnAddressIsTaken(true); 970 971 EVT VT = Op.getValueType(); 972 DebugLoc dl = Op.getDebugLoc(); 973 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 974 if (Depth) { 975 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 976 SDValue Offset = DAG.getConstant(4, MVT::i32); 977 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 978 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 979 MachinePointerInfo(), false, false, false, 0); 980 } 981 982 // Return LR, which contains the return address. Mark it an implicit live-in. 983 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); 984 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 985} 986 987SDValue 988HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 989 const HexagonRegisterInfo *TRI = TM.getRegisterInfo(); 990 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 991 MFI->setFrameAddressIsTaken(true); 992 993 EVT VT = Op.getValueType(); 994 DebugLoc dl = Op.getDebugLoc(); 995 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 996 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 997 TRI->getFrameRegister(), VT); 998 while (Depth--) 999 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 1000 MachinePointerInfo(), 1001 false, false, false, 0); 1002 return FrameAddr; 1003} 1004 1005 1006SDValue HexagonTargetLowering::LowerMEMBARRIER(SDValue Op, 1007 SelectionDAG& DAG) const { 1008 DebugLoc dl = Op.getDebugLoc(); 1009 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0)); 1010} 1011 1012 1013SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1014 SelectionDAG& DAG) const { 1015 DebugLoc dl = Op.getDebugLoc(); 1016 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0)); 1017} 1018 1019 1020SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, 1021 SelectionDAG &DAG) const { 1022 SDValue Result; 1023 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1024 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 1025 DebugLoc dl = Op.getDebugLoc(); 1026 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 1027 1028 const HexagonTargetObjectFile &TLOF = 1029 static_cast<const HexagonTargetObjectFile &>(getObjFileLowering()); 1030 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1031 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result); 1032 } 1033 1034 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result); 1035} 1036 1037SDValue 1038HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 1039 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1040 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32); 1041 DebugLoc dl = Op.getDebugLoc(); 1042 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD); 1043} 1044 1045//===----------------------------------------------------------------------===// 1046// TargetLowering Implementation 1047//===----------------------------------------------------------------------===// 1048 1049HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine 1050 &targetmachine) 1051 : TargetLowering(targetmachine, new HexagonTargetObjectFile()), 1052 TM(targetmachine) { 1053 1054 const HexagonRegisterInfo* QRI = TM.getRegisterInfo(); 1055 1056 // Set up the register classes. 1057 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); 1058 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); 1059 1060 if (QRI->Subtarget.hasV5TOps()) { 1061 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); 1062 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); 1063 } 1064 1065 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); 1066 1067 computeRegisterProperties(); 1068 1069 // Align loop entry 1070 setPrefLoopAlignment(4); 1071 1072 // Limits for inline expansion of memcpy/memmove 1073 MaxStoresPerMemcpy = 6; 1074 MaxStoresPerMemmove = 6; 1075 1076 // 1077 // Library calls for unsupported operations 1078 // 1079 1080 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf"); 1081 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf"); 1082 1083 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti"); 1084 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti"); 1085 1086 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti"); 1087 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti"); 1088 1089 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3"); 1090 setOperationAction(ISD::SDIV, MVT::i32, Expand); 1091 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3"); 1092 setOperationAction(ISD::SREM, MVT::i32, Expand); 1093 1094 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3"); 1095 setOperationAction(ISD::SDIV, MVT::i64, Expand); 1096 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3"); 1097 setOperationAction(ISD::SREM, MVT::i64, Expand); 1098 1099 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3"); 1100 setOperationAction(ISD::UDIV, MVT::i32, Expand); 1101 1102 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3"); 1103 setOperationAction(ISD::UDIV, MVT::i64, Expand); 1104 1105 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3"); 1106 setOperationAction(ISD::UREM, MVT::i32, Expand); 1107 1108 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3"); 1109 setOperationAction(ISD::UREM, MVT::i64, Expand); 1110 1111 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3"); 1112 setOperationAction(ISD::FDIV, MVT::f32, Expand); 1113 1114 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3"); 1115 setOperationAction(ISD::FDIV, MVT::f64, Expand); 1116 1117 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 1118 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 1119 setOperationAction(ISD::FSIN, MVT::f32, Expand); 1120 setOperationAction(ISD::FSIN, MVT::f64, Expand); 1121 1122 if (QRI->Subtarget.hasV5TOps()) { 1123 // Hexagon V5 Support. 1124 setOperationAction(ISD::FADD, MVT::f32, Legal); 1125 setOperationAction(ISD::FADD, MVT::f64, Legal); 1126 setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal); 1127 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal); 1128 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal); 1129 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal); 1130 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal); 1131 1132 setCondCodeAction(ISD::SETOGE, MVT::f32, Legal); 1133 setCondCodeAction(ISD::SETOGE, MVT::f64, Legal); 1134 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal); 1135 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal); 1136 1137 setCondCodeAction(ISD::SETOGT, MVT::f32, Legal); 1138 setCondCodeAction(ISD::SETOGT, MVT::f64, Legal); 1139 setCondCodeAction(ISD::SETUGT, MVT::f32, Legal); 1140 setCondCodeAction(ISD::SETUGT, MVT::f64, Legal); 1141 1142 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal); 1143 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal); 1144 setCondCodeAction(ISD::SETOLT, MVT::f32, Legal); 1145 setCondCodeAction(ISD::SETOLT, MVT::f64, Legal); 1146 1147 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 1148 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); 1149 1150 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); 1151 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); 1152 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); 1153 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); 1154 1155 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); 1156 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); 1157 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); 1158 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); 1159 1160 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); 1161 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); 1162 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); 1163 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); 1164 1165 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); 1166 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); 1167 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); 1168 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); 1169 1170 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal); 1171 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal); 1172 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal); 1173 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal); 1174 1175 setOperationAction(ISD::FABS, MVT::f32, Legal); 1176 setOperationAction(ISD::FABS, MVT::f64, Expand); 1177 1178 setOperationAction(ISD::FNEG, MVT::f32, Legal); 1179 setOperationAction(ISD::FNEG, MVT::f64, Expand); 1180 } else { 1181 1182 // Expand fp<->uint. 1183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); 1184 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 1185 1186 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 1187 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 1188 1189 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf"); 1190 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf"); 1191 1192 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf"); 1193 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf"); 1194 1195 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf"); 1196 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf"); 1197 1198 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf"); 1199 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf"); 1200 1201 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi"); 1202 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi"); 1203 1204 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi"); 1205 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi"); 1206 1207 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi"); 1208 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi"); 1209 1210 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3"); 1211 setOperationAction(ISD::FADD, MVT::f64, Expand); 1212 1213 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3"); 1214 setOperationAction(ISD::FADD, MVT::f32, Expand); 1215 1216 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2"); 1217 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand); 1218 1219 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2"); 1220 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 1221 1222 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2"); 1223 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 1224 1225 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2"); 1226 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 1227 1228 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2"); 1229 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 1230 1231 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2"); 1232 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); 1233 1234 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2"); 1235 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); 1236 1237 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi"); 1238 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); 1239 1240 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi"); 1241 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); 1242 1243 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2"); 1244 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 1245 1246 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2"); 1247 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 1248 1249 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2"); 1250 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand); 1251 1252 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2"); 1253 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); 1254 1255 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3"); 1256 setOperationAction(ISD::FMUL, MVT::f64, Expand); 1257 1258 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3"); 1259 setOperationAction(ISD::MUL, MVT::f32, Expand); 1260 1261 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2"); 1262 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 1263 1264 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2"); 1265 1266 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3"); 1267 setOperationAction(ISD::SUB, MVT::f64, Expand); 1268 1269 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3"); 1270 setOperationAction(ISD::SUB, MVT::f32, Expand); 1271 1272 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2"); 1273 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand); 1274 1275 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2"); 1276 setCondCodeAction(ISD::SETUO, MVT::f64, Expand); 1277 1278 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2"); 1279 setCondCodeAction(ISD::SETO, MVT::f64, Expand); 1280 1281 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2"); 1282 setCondCodeAction(ISD::SETO, MVT::f32, Expand); 1283 1284 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2"); 1285 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); 1286 1287 setOperationAction(ISD::FABS, MVT::f32, Expand); 1288 setOperationAction(ISD::FABS, MVT::f64, Expand); 1289 setOperationAction(ISD::FNEG, MVT::f32, Expand); 1290 setOperationAction(ISD::FNEG, MVT::f64, Expand); 1291 } 1292 1293 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3"); 1294 setOperationAction(ISD::SREM, MVT::i32, Expand); 1295 1296 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 1297 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 1298 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); 1299 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal); 1300 1301 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); 1302 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); 1303 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); 1304 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal); 1305 1306 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 1307 1308 // Turn FP extload into load/fextend. 1309 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 1310 // Hexagon has a i1 sign extending load. 1311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand); 1312 // Turn FP truncstore into trunc + store. 1313 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1314 1315 // Custom legalize GlobalAddress nodes into CONST32. 1316 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 1317 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom); 1318 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 1319 // Truncate action? 1320 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand); 1321 1322 // Hexagon doesn't have sext_inreg, replace them with shl/sra. 1323 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 1324 1325 // Hexagon has no REM or DIVREM operations. 1326 setOperationAction(ISD::UREM, MVT::i32, Expand); 1327 setOperationAction(ISD::SREM, MVT::i32, Expand); 1328 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1329 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1330 setOperationAction(ISD::SREM, MVT::i64, Expand); 1331 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 1332 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 1333 1334 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 1335 1336 // Lower SELECT_CC to SETCC and SELECT. 1337 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1338 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 1339 1340 if (QRI->Subtarget.hasV5TOps()) { 1341 1342 // We need to make the operation type of SELECT node to be Custom, 1343 // such that we don't go into the infinite loop of 1344 // select -> setcc -> select_cc -> select loop. 1345 setOperationAction(ISD::SELECT, MVT::f32, Custom); 1346 setOperationAction(ISD::SELECT, MVT::f64, Custom); 1347 1348 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 1349 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 1350 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 1351 1352 } else { 1353 1354 // Hexagon has no select or setcc: expand to SELECT_CC. 1355 setOperationAction(ISD::SELECT, MVT::f32, Expand); 1356 setOperationAction(ISD::SELECT, MVT::f64, Expand); 1357 1358 // This is a workaround documented in DAGCombiner.cpp:2892 We don't 1359 // support SELECT_CC on every type. 1360 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 1361 1362 } 1363 1364 setOperationAction(ISD::BRIND, MVT::Other, Expand); 1365 if (EmitJumpTables) { 1366 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 1367 } else { 1368 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 1369 } 1370 // Increase jump tables cutover to 5, was 4. 1371 setMinimumJumpTableEntries(5); 1372 1373 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 1374 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 1375 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 1376 setOperationAction(ISD::BR_CC, MVT::i1, Expand); 1377 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 1378 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 1379 1380 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 1381 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 1382 1383 setOperationAction(ISD::FSIN , MVT::f64, Expand); 1384 setOperationAction(ISD::FCOS , MVT::f64, Expand); 1385 setOperationAction(ISD::FREM , MVT::f64, Expand); 1386 setOperationAction(ISD::FSIN , MVT::f32, Expand); 1387 setOperationAction(ISD::FCOS , MVT::f32, Expand); 1388 setOperationAction(ISD::FREM , MVT::f32, Expand); 1389 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 1390 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 1391 1392 // In V4, we have double word add/sub with carry. The problem with 1393 // modelling this instruction is that it produces 2 results - Rdd and Px. 1394 // To model update of Px, we will have to use Defs[p0..p3] which will 1395 // cause any predicate live range to spill. So, we pretend we dont't 1396 // have these instructions. 1397 setOperationAction(ISD::ADDE, MVT::i8, Expand); 1398 setOperationAction(ISD::ADDE, MVT::i16, Expand); 1399 setOperationAction(ISD::ADDE, MVT::i32, Expand); 1400 setOperationAction(ISD::ADDE, MVT::i64, Expand); 1401 setOperationAction(ISD::SUBE, MVT::i8, Expand); 1402 setOperationAction(ISD::SUBE, MVT::i16, Expand); 1403 setOperationAction(ISD::SUBE, MVT::i32, Expand); 1404 setOperationAction(ISD::SUBE, MVT::i64, Expand); 1405 setOperationAction(ISD::ADDC, MVT::i8, Expand); 1406 setOperationAction(ISD::ADDC, MVT::i16, Expand); 1407 setOperationAction(ISD::ADDC, MVT::i32, Expand); 1408 setOperationAction(ISD::ADDC, MVT::i64, Expand); 1409 setOperationAction(ISD::SUBC, MVT::i8, Expand); 1410 setOperationAction(ISD::SUBC, MVT::i16, Expand); 1411 setOperationAction(ISD::SUBC, MVT::i32, Expand); 1412 setOperationAction(ISD::SUBC, MVT::i64, Expand); 1413 1414 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 1415 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 1416 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 1417 setOperationAction(ISD::CTTZ , MVT::i64, Expand); 1418 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 1419 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 1420 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 1421 setOperationAction(ISD::CTLZ , MVT::i64, Expand); 1422 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 1423 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 1424 setOperationAction(ISD::ROTL , MVT::i32, Expand); 1425 setOperationAction(ISD::ROTR , MVT::i32, Expand); 1426 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 1427 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 1428 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 1429 setOperationAction(ISD::FPOW , MVT::f64, Expand); 1430 setOperationAction(ISD::FPOW , MVT::f32, Expand); 1431 1432 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 1433 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 1434 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 1435 1436 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 1437 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 1438 1439 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 1440 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 1441 1442 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 1443 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 1444 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 1445 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 1446 1447 setOperationAction(ISD::EH_RETURN, MVT::Other, Expand); 1448 1449 if (TM.getSubtargetImpl()->isSubtargetV2()) { 1450 setExceptionPointerRegister(Hexagon::R20); 1451 setExceptionSelectorRegister(Hexagon::R21); 1452 } else { 1453 setExceptionPointerRegister(Hexagon::R0); 1454 setExceptionSelectorRegister(Hexagon::R1); 1455 } 1456 1457 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 1458 setOperationAction(ISD::VASTART , MVT::Other, Custom); 1459 1460 // Use the default implementation. 1461 setOperationAction(ISD::VAARG , MVT::Other, Expand); 1462 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1463 setOperationAction(ISD::VAEND , MVT::Other, Expand); 1464 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1465 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1466 1467 1468 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 1469 setOperationAction(ISD::INLINEASM , MVT::Other, Custom); 1470 1471 setMinFunctionAlignment(2); 1472 1473 // Needed for DYNAMIC_STACKALLOC expansion. 1474 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister(); 1475 setStackPointerRegisterToSaveRestore(StackRegister); 1476 setSchedulingPreference(Sched::VLIW); 1477} 1478 1479 1480const char* 1481HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { 1482 switch (Opcode) { 1483 default: return 0; 1484 case HexagonISD::CONST32: return "HexagonISD::CONST32"; 1485 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP"; 1486 case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real"; 1487 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC"; 1488 case HexagonISD::CMPICC: return "HexagonISD::CMPICC"; 1489 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC"; 1490 case HexagonISD::BRICC: return "HexagonISD::BRICC"; 1491 case HexagonISD::BRFCC: return "HexagonISD::BRFCC"; 1492 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC"; 1493 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC"; 1494 case HexagonISD::Hi: return "HexagonISD::Hi"; 1495 case HexagonISD::Lo: return "HexagonISD::Lo"; 1496 case HexagonISD::FTOI: return "HexagonISD::FTOI"; 1497 case HexagonISD::ITOF: return "HexagonISD::ITOF"; 1498 case HexagonISD::CALL: return "HexagonISD::CALL"; 1499 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG"; 1500 case HexagonISD::BR_JT: return "HexagonISD::BR_JT"; 1501 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN"; 1502 } 1503} 1504 1505bool 1506HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 1507 EVT MTy1 = EVT::getEVT(Ty1); 1508 EVT MTy2 = EVT::getEVT(Ty2); 1509 if (!MTy1.isSimple() || !MTy2.isSimple()) { 1510 return false; 1511 } 1512 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32)); 1513} 1514 1515bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 1516 if (!VT1.isSimple() || !VT2.isSimple()) { 1517 return false; 1518 } 1519 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32)); 1520} 1521 1522SDValue 1523HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1524 switch (Op.getOpcode()) { 1525 default: llvm_unreachable("Should not custom lower this!"); 1526 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1527 // Frame & Return address. Currently unimplemented. 1528 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1529 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1530 case ISD::GlobalTLSAddress: 1531 llvm_unreachable("TLS not implemented for Hexagon."); 1532 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 1533 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 1534 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); 1535 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 1536 case ISD::VASTART: return LowerVASTART(Op, DAG); 1537 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1538 1539 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1540 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1541 case ISD::SELECT: return Op; 1542 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1543 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG); 1544 1545 } 1546} 1547 1548 1549 1550//===----------------------------------------------------------------------===// 1551// Hexagon Scheduler Hooks 1552//===----------------------------------------------------------------------===// 1553MachineBasicBlock * 1554HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1555 MachineBasicBlock *BB) 1556const { 1557 switch (MI->getOpcode()) { 1558 case Hexagon::ADJDYNALLOC: { 1559 MachineFunction *MF = BB->getParent(); 1560 HexagonMachineFunctionInfo *FuncInfo = 1561 MF->getInfo<HexagonMachineFunctionInfo>(); 1562 FuncInfo->addAllocaAdjustInst(MI); 1563 return BB; 1564 } 1565 default: llvm_unreachable("Unexpected instr type to insert"); 1566 } // switch 1567} 1568 1569//===----------------------------------------------------------------------===// 1570// Inline Assembly Support 1571//===----------------------------------------------------------------------===// 1572 1573std::pair<unsigned, const TargetRegisterClass*> 1574HexagonTargetLowering::getRegForInlineAsmConstraint(const 1575 std::string &Constraint, 1576 EVT VT) const { 1577 if (Constraint.size() == 1) { 1578 switch (Constraint[0]) { 1579 case 'r': // R0-R31 1580 switch (VT.getSimpleVT().SimpleTy) { 1581 default: 1582 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type"); 1583 case MVT::i32: 1584 case MVT::i16: 1585 case MVT::i8: 1586 case MVT::f32: 1587 return std::make_pair(0U, &Hexagon::IntRegsRegClass); 1588 case MVT::i64: 1589 case MVT::f64: 1590 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass); 1591 } 1592 default: 1593 llvm_unreachable("Unknown asm register class"); 1594 } 1595 } 1596 1597 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1598} 1599 1600/// isFPImmLegal - Returns true if the target can instruction select the 1601/// specified FP immediate natively. If false, the legalizer will 1602/// materialize the FP immediate as a load from a constant pool. 1603bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 1604 const HexagonRegisterInfo* QRI = TM.getRegisterInfo(); 1605 return QRI->Subtarget.hasV5TOps(); 1606} 1607 1608/// isLegalAddressingMode - Return true if the addressing mode represented by 1609/// AM is legal for this target, for a load/store of the specified type. 1610bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1611 Type *Ty) const { 1612 // Allows a signed-extended 11-bit immediate field. 1613 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { 1614 return false; 1615 } 1616 1617 // No global is ever allowed as a base. 1618 if (AM.BaseGV) { 1619 return false; 1620 } 1621 1622 int Scale = AM.Scale; 1623 if (Scale < 0) Scale = -Scale; 1624 switch (Scale) { 1625 case 0: // No scale reg, "r+i", "r", or just "i". 1626 break; 1627 default: // No scaled addressing mode. 1628 return false; 1629 } 1630 return true; 1631} 1632 1633/// isLegalICmpImmediate - Return true if the specified immediate is legal 1634/// icmp immediate, that is the target has icmp instructions which can compare 1635/// a register against the immediate without having to materialize the 1636/// immediate into a register. 1637bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 1638 return Imm >= -512 && Imm <= 511; 1639} 1640 1641/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1642/// for tail call optimization. Targets which want to do tail call 1643/// optimization should implement this function. 1644bool HexagonTargetLowering::IsEligibleForTailCallOptimization( 1645 SDValue Callee, 1646 CallingConv::ID CalleeCC, 1647 bool isVarArg, 1648 bool isCalleeStructRet, 1649 bool isCallerStructRet, 1650 const SmallVectorImpl<ISD::OutputArg> &Outs, 1651 const SmallVectorImpl<SDValue> &OutVals, 1652 const SmallVectorImpl<ISD::InputArg> &Ins, 1653 SelectionDAG& DAG) const { 1654 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1655 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1656 bool CCMatch = CallerCC == CalleeCC; 1657 1658 // *************************************************************************** 1659 // Look for obvious safe cases to perform tail call optimization that do not 1660 // require ABI changes. 1661 // *************************************************************************** 1662 1663 // If this is a tail call via a function pointer, then don't do it! 1664 if (!(dyn_cast<GlobalAddressSDNode>(Callee)) 1665 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) { 1666 return false; 1667 } 1668 1669 // Do not optimize if the calling conventions do not match. 1670 if (!CCMatch) 1671 return false; 1672 1673 // Do not tail call optimize vararg calls. 1674 if (isVarArg) 1675 return false; 1676 1677 // Also avoid tail call optimization if either caller or callee uses struct 1678 // return semantics. 1679 if (isCalleeStructRet || isCallerStructRet) 1680 return false; 1681 1682 // In addition to the cases above, we also disable Tail Call Optimization if 1683 // the calling convention code that at least one outgoing argument needs to 1684 // go on the stack. We cannot check that here because at this point that 1685 // information is not available. 1686 return true; 1687} 1688