ARMScheduleV6.td revision 218893
1198090Srdivacky//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===// 2194612Sed// 3194612Sed// The LLVM Compiler Infrastructure 4194612Sed// 5194612Sed// This file is distributed under the University of Illinois Open Source 6194612Sed// License. See LICENSE.TXT for details. 7194612Sed// 8194612Sed//===----------------------------------------------------------------------===// 9194612Sed// 10194612Sed// This file defines the itinerary class data for the ARM v6 processors. 11194612Sed// 12194612Sed//===----------------------------------------------------------------------===// 13194612Sed 14199511Srdivacky// Model based on ARM1176 15199511Srdivacky// 16207618Srdivacky// Functional Units 17207618Srdivackydef V6_Pipe : FuncUnit; // pipeline 18207618Srdivacky 19210299Sed// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual" 20199511Srdivacky// 21207618Srdivackydef ARMV6Itineraries : ProcessorItineraries< 22218893Sdim [V6_Pipe], [], [ 23199511Srdivacky // 24199511Srdivacky // No operand cycles 25207618Srdivacky InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>, 26199511Srdivacky // 27199511Srdivacky // Binary Instructions that produce a result 28207618Srdivacky InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 29207618Srdivacky InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 30207618Srdivacky InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 31207618Srdivacky InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 32199511Srdivacky // 33218893Sdim // Bitwise Instructions that produce a result 34218893Sdim InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 35218893Sdim InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 36218893Sdim InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 37218893Sdim InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 38218893Sdim // 39199511Srdivacky // Unary Instructions that produce a result 40207618Srdivacky InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 41207618Srdivacky InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 42199511Srdivacky // 43218893Sdim // Zero and sign extension instructions 44218893Sdim InstrItinData<IIC_iEXTr , [InstrStage<1, [V6_Pipe]>], [1, 1]>, 45218893Sdim InstrItinData<IIC_iEXTAr , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 46218893Sdim InstrItinData<IIC_iEXTAsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 47218893Sdim // 48199511Srdivacky // Compare instructions 49207618Srdivacky InstrItinData<IIC_iCMPi , [InstrStage<1, [V6_Pipe]>], [2]>, 50207618Srdivacky InstrItinData<IIC_iCMPr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 51207618Srdivacky InstrItinData<IIC_iCMPsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 52207618Srdivacky InstrItinData<IIC_iCMPsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 53199511Srdivacky // 54218893Sdim // Test instructions 55218893Sdim InstrItinData<IIC_iTSTi , [InstrStage<1, [V6_Pipe]>], [2]>, 56218893Sdim InstrItinData<IIC_iTSTr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 57218893Sdim InstrItinData<IIC_iTSTsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 58218893Sdim InstrItinData<IIC_iTSTsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 59218893Sdim // 60199511Srdivacky // Move instructions, unconditional 61207618Srdivacky InstrItinData<IIC_iMOVi , [InstrStage<1, [V6_Pipe]>], [2]>, 62207618Srdivacky InstrItinData<IIC_iMOVr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 63207618Srdivacky InstrItinData<IIC_iMOVsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 64207618Srdivacky InstrItinData<IIC_iMOVsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 65218893Sdim InstrItinData<IIC_iMOVix2 , [InstrStage<1, [V6_Pipe]>, 66218893Sdim InstrStage<1, [V6_Pipe]>], [2]>, 67218893Sdim InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [V6_Pipe]>, 68218893Sdim InstrStage<1, [V6_Pipe]>, 69218893Sdim InstrStage<1, [V6_Pipe]>], [3]>, 70218893Sdim InstrItinData<IIC_iMOVix2ld , [InstrStage<1, [V6_Pipe]>, 71218893Sdim InstrStage<1, [V6_Pipe]>, 72218893Sdim InstrStage<1, [V6_Pipe]>], [5]>, 73199511Srdivacky // 74199511Srdivacky // Move instructions, conditional 75207618Srdivacky InstrItinData<IIC_iCMOVi , [InstrStage<1, [V6_Pipe]>], [3]>, 76207618Srdivacky InstrItinData<IIC_iCMOVr , [InstrStage<1, [V6_Pipe]>], [3, 2]>, 77207618Srdivacky InstrItinData<IIC_iCMOVsi , [InstrStage<1, [V6_Pipe]>], [3, 1]>, 78207618Srdivacky InstrItinData<IIC_iCMOVsr , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 79218893Sdim InstrItinData<IIC_iCMOVix2 , [InstrStage<1, [V6_Pipe]>, 80218893Sdim InstrStage<1, [V6_Pipe]>], [4]>, 81218893Sdim // 82218893Sdim // MVN instructions 83218893Sdim InstrItinData<IIC_iMVNi , [InstrStage<1, [V6_Pipe]>], [2]>, 84218893Sdim InstrItinData<IIC_iMVNr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 85218893Sdim InstrItinData<IIC_iMVNsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 86218893Sdim InstrItinData<IIC_iMVNsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 87199511Srdivacky 88199511Srdivacky // Integer multiply pipeline 89199511Srdivacky // 90207618Srdivacky InstrItinData<IIC_iMUL16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 91207618Srdivacky InstrItinData<IIC_iMAC16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1, 2]>, 92207618Srdivacky InstrItinData<IIC_iMUL32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1]>, 93207618Srdivacky InstrItinData<IIC_iMAC32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1, 2]>, 94207618Srdivacky InstrItinData<IIC_iMUL64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1]>, 95207618Srdivacky InstrItinData<IIC_iMAC64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1, 2]>, 96199511Srdivacky 97199511Srdivacky // Integer load pipeline 98199511Srdivacky // 99199511Srdivacky // Immediate offset 100218893Sdim InstrItinData<IIC_iLoad_i , [InstrStage<1, [V6_Pipe]>], [4, 1]>, 101218893Sdim InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [V6_Pipe]>], [4, 1]>, 102218893Sdim InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [V6_Pipe]>], [4, 1]>, 103199511Srdivacky // 104199511Srdivacky // Register offset 105218893Sdim InstrItinData<IIC_iLoad_r , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 106218893Sdim InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 107218893Sdim InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 108199511Srdivacky // 109199511Srdivacky // Scaled register offset, issues over 2 cycles 110218893Sdim InstrItinData<IIC_iLoad_si , [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>, 111218893Sdim InstrItinData<IIC_iLoad_bh_si, [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>, 112199511Srdivacky // 113199511Srdivacky // Immediate offset with update 114218893Sdim InstrItinData<IIC_iLoad_iu , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 115218893Sdim InstrItinData<IIC_iLoad_bh_iu, [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 116199511Srdivacky // 117199511Srdivacky // Register offset with update 118218893Sdim InstrItinData<IIC_iLoad_ru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>, 119218893Sdim InstrItinData<IIC_iLoad_bh_ru, [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>, 120218893Sdim InstrItinData<IIC_iLoad_d_ru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>, 121199511Srdivacky // 122199511Srdivacky // Scaled register offset with update, issues over 2 cycles 123218893Sdim InstrItinData<IIC_iLoad_siu, [InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>, 124218893Sdim InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>, 125199511Srdivacky 126199511Srdivacky // 127218893Sdim // Load multiple, def is the 5th operand. 128218893Sdim InstrItinData<IIC_iLoad_m , [InstrStage<3, [V6_Pipe]>], [1, 1, 1, 1, 4]>, 129218893Sdim // 130218893Sdim // Load multiple + update, defs are the 1st and 5th operands. 131218893Sdim InstrItinData<IIC_iLoad_mu , [InstrStage<3, [V6_Pipe]>], [2, 1, 1, 1, 4]>, 132218893Sdim // 133218893Sdim // Load multiple plus branch 134218893Sdim InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [V6_Pipe]>, 135218893Sdim InstrStage<1, [V6_Pipe]>], [1, 2, 1, 1, 4]>, 136199511Srdivacky 137218893Sdim // 138218893Sdim // iLoadi + iALUr for t2LDRpci_pic. 139218893Sdim InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>, 140218893Sdim InstrStage<1, [V6_Pipe]>], [3, 1]>, 141218893Sdim 142218893Sdim // 143218893Sdim // Pop, def is the 3rd operand. 144218893Sdim InstrItinData<IIC_iPop , [InstrStage<3, [V6_Pipe]>], [1, 1, 4]>, 145218893Sdim // 146218893Sdim // Pop + branch, def is the 3rd operand. 147218893Sdim InstrItinData<IIC_iPop_Br, [InstrStage<3, [V6_Pipe]>, 148218893Sdim InstrStage<1, [V6_Pipe]>], [1, 2, 4]>, 149218893Sdim 150199511Srdivacky // Integer store pipeline 151199511Srdivacky // 152199511Srdivacky // Immediate offset 153218893Sdim InstrItinData<IIC_iStore_i , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 154218893Sdim InstrItinData<IIC_iStore_bh_i, [InstrStage<1, [V6_Pipe]>], [2, 1]>, 155218893Sdim InstrItinData<IIC_iStore_d_i , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 156199511Srdivacky // 157199511Srdivacky // Register offset 158218893Sdim InstrItinData<IIC_iStore_r , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>, 159218893Sdim InstrItinData<IIC_iStore_bh_r, [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>, 160218893Sdim InstrItinData<IIC_iStore_d_r , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>, 161199511Srdivacky // 162199511Srdivacky // Scaled register offset, issues over 2 cycles 163218893Sdim InstrItinData<IIC_iStore_si , [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>, 164218893Sdim InstrItinData<IIC_iStore_bh_si, [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>, 165199511Srdivacky // 166199511Srdivacky // Immediate offset with update 167218893Sdim InstrItinData<IIC_iStore_iu , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 168218893Sdim InstrItinData<IIC_iStore_bh_iu, [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 169199511Srdivacky // 170199511Srdivacky // Register offset with update 171218893Sdim InstrItinData<IIC_iStore_ru, [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>, 172218893Sdim InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>, 173218893Sdim InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>, 174199511Srdivacky // 175199511Srdivacky // Scaled register offset with update, issues over 2 cycles 176218893Sdim InstrItinData<IIC_iStore_siu, [InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>, 177218893Sdim InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>, 178199511Srdivacky // 179199511Srdivacky // Store multiple 180218893Sdim InstrItinData<IIC_iStore_m , [InstrStage<3, [V6_Pipe]>]>, 181218893Sdim // 182218893Sdim // Store multiple + update 183218893Sdim InstrItinData<IIC_iStore_mu , [InstrStage<3, [V6_Pipe]>], [2]>, 184199511Srdivacky 185199511Srdivacky // Branch 186199511Srdivacky // 187199511Srdivacky // no delay slots, so the latency of a branch is unimportant 188207618Srdivacky InstrItinData<IIC_Br , [InstrStage<1, [V6_Pipe]>]>, 189199511Srdivacky 190199511Srdivacky // VFP 191199511Srdivacky // Issue through integer pipeline, and execute in NEON unit. We assume 192199511Srdivacky // RunFast mode so that NFP pipeline is used for single-precision when 193199511Srdivacky // possible. 194199511Srdivacky // 195199511Srdivacky // FP Special Register to Integer Register File Move 196207618Srdivacky InstrItinData<IIC_fpSTAT , [InstrStage<1, [V6_Pipe]>], [3]>, 197199511Srdivacky // 198199511Srdivacky // Single-precision FP Unary 199207618Srdivacky InstrItinData<IIC_fpUNA32 , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 200199511Srdivacky // 201199511Srdivacky // Double-precision FP Unary 202207618Srdivacky InstrItinData<IIC_fpUNA64 , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 203199511Srdivacky // 204199511Srdivacky // Single-precision FP Compare 205207618Srdivacky InstrItinData<IIC_fpCMP32 , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 206199511Srdivacky // 207199511Srdivacky // Double-precision FP Compare 208207618Srdivacky InstrItinData<IIC_fpCMP64 , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 209199511Srdivacky // 210199511Srdivacky // Single to Double FP Convert 211207618Srdivacky InstrItinData<IIC_fpCVTSD , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 212199511Srdivacky // 213199511Srdivacky // Double to Single FP Convert 214207618Srdivacky InstrItinData<IIC_fpCVTDS , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 215199511Srdivacky // 216199511Srdivacky // Single-Precision FP to Integer Convert 217207618Srdivacky InstrItinData<IIC_fpCVTSI , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 218199511Srdivacky // 219199511Srdivacky // Double-Precision FP to Integer Convert 220207618Srdivacky InstrItinData<IIC_fpCVTDI , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 221199511Srdivacky // 222199511Srdivacky // Integer to Single-Precision FP Convert 223207618Srdivacky InstrItinData<IIC_fpCVTIS , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 224199511Srdivacky // 225199511Srdivacky // Integer to Double-Precision FP Convert 226207618Srdivacky InstrItinData<IIC_fpCVTID , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 227199511Srdivacky // 228199511Srdivacky // Single-precision FP ALU 229207618Srdivacky InstrItinData<IIC_fpALU32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 230199511Srdivacky // 231199511Srdivacky // Double-precision FP ALU 232207618Srdivacky InstrItinData<IIC_fpALU64 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 233199511Srdivacky // 234199511Srdivacky // Single-precision FP Multiply 235207618Srdivacky InstrItinData<IIC_fpMUL32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 236199511Srdivacky // 237199511Srdivacky // Double-precision FP Multiply 238207618Srdivacky InstrItinData<IIC_fpMUL64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2]>, 239199511Srdivacky // 240199511Srdivacky // Single-precision FP MAC 241207618Srdivacky InstrItinData<IIC_fpMAC32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>, 242199511Srdivacky // 243199511Srdivacky // Double-precision FP MAC 244207618Srdivacky InstrItinData<IIC_fpMAC64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>, 245199511Srdivacky // 246199511Srdivacky // Single-precision FP DIV 247207618Srdivacky InstrItinData<IIC_fpDIV32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>, 248199511Srdivacky // 249199511Srdivacky // Double-precision FP DIV 250207618Srdivacky InstrItinData<IIC_fpDIV64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>, 251199511Srdivacky // 252199511Srdivacky // Single-precision FP SQRT 253207618Srdivacky InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>, 254199511Srdivacky // 255199511Srdivacky // Double-precision FP SQRT 256207618Srdivacky InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>, 257199511Srdivacky // 258218893Sdim // Integer to Single-precision Move 259218893Sdim InstrItinData<IIC_fpMOVIS, [InstrStage<1, [V6_Pipe]>], [10, 1]>, 260218893Sdim // 261218893Sdim // Integer to Double-precision Move 262218893Sdim InstrItinData<IIC_fpMOVID, [InstrStage<1, [V6_Pipe]>], [10, 1, 1]>, 263218893Sdim // 264218893Sdim // Single-precision to Integer Move 265218893Sdim InstrItinData<IIC_fpMOVSI, [InstrStage<1, [V6_Pipe]>], [10, 1]>, 266218893Sdim // 267218893Sdim // Double-precision to Integer Move 268218893Sdim InstrItinData<IIC_fpMOVDI, [InstrStage<1, [V6_Pipe]>], [10, 10, 1]>, 269218893Sdim // 270199511Srdivacky // Single-precision FP Load 271207618Srdivacky InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>, 272199511Srdivacky // 273199511Srdivacky // Double-precision FP Load 274207618Srdivacky InstrItinData<IIC_fpLoad64 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>, 275199511Srdivacky // 276199511Srdivacky // FP Load Multiple 277218893Sdim InstrItinData<IIC_fpLoad_m , [InstrStage<3, [V6_Pipe]>], [2, 1, 1, 5]>, 278199511Srdivacky // 279218893Sdim // FP Load Multiple + update 280218893Sdim InstrItinData<IIC_fpLoad_mu, [InstrStage<3, [V6_Pipe]>], [3, 2, 1, 1, 5]>, 281218893Sdim // 282199511Srdivacky // Single-precision FP Store 283207618Srdivacky InstrItinData<IIC_fpStore32 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 284199511Srdivacky // 285199511Srdivacky // Double-precision FP Store 286199511Srdivacky // use FU_Issue to enforce the 1 load/store per cycle limit 287207618Srdivacky InstrItinData<IIC_fpStore64 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 288199511Srdivacky // 289199511Srdivacky // FP Store Multiple 290218893Sdim InstrItinData<IIC_fpStore_m, [InstrStage<3, [V6_Pipe]>], [2, 2, 2, 2]>, 291218893Sdim // 292218893Sdim // FP Store Multiple + update 293218893Sdim InstrItinData<IIC_fpStore_mu,[InstrStage<3, [V6_Pipe]>], [3, 2, 2, 2, 2]> 294199511Srdivacky]>; 295