ARMScheduleV6.td revision 207618
1198090Srdivacky//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===// 2194612Sed// 3194612Sed// The LLVM Compiler Infrastructure 4194612Sed// 5194612Sed// This file is distributed under the University of Illinois Open Source 6194612Sed// License. See LICENSE.TXT for details. 7194612Sed// 8194612Sed//===----------------------------------------------------------------------===// 9194612Sed// 10194612Sed// This file defines the itinerary class data for the ARM v6 processors. 11194612Sed// 12194612Sed//===----------------------------------------------------------------------===// 13194612Sed 14199511Srdivacky// Model based on ARM1176 15199511Srdivacky// 16207618Srdivacky// Functional Units 17207618Srdivackydef V6_Pipe : FuncUnit; // pipeline 18207618Srdivacky 19199511Srdivacky// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual". 20199511Srdivacky// 21207618Srdivackydef ARMV6Itineraries : ProcessorItineraries< 22207618Srdivacky [V6_Pipe], [ 23199511Srdivacky // 24199511Srdivacky // No operand cycles 25207618Srdivacky InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>, 26199511Srdivacky // 27199511Srdivacky // Binary Instructions that produce a result 28207618Srdivacky InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 29207618Srdivacky InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 30207618Srdivacky InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 31207618Srdivacky InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 32199511Srdivacky // 33199511Srdivacky // Unary Instructions that produce a result 34207618Srdivacky InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 35207618Srdivacky InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 36207618Srdivacky InstrItinData<IIC_iUNAsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 37199511Srdivacky // 38199511Srdivacky // Compare instructions 39207618Srdivacky InstrItinData<IIC_iCMPi , [InstrStage<1, [V6_Pipe]>], [2]>, 40207618Srdivacky InstrItinData<IIC_iCMPr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 41207618Srdivacky InstrItinData<IIC_iCMPsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 42207618Srdivacky InstrItinData<IIC_iCMPsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 43199511Srdivacky // 44199511Srdivacky // Move instructions, unconditional 45207618Srdivacky InstrItinData<IIC_iMOVi , [InstrStage<1, [V6_Pipe]>], [2]>, 46207618Srdivacky InstrItinData<IIC_iMOVr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 47207618Srdivacky InstrItinData<IIC_iMOVsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 48207618Srdivacky InstrItinData<IIC_iMOVsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, 49199511Srdivacky // 50199511Srdivacky // Move instructions, conditional 51207618Srdivacky InstrItinData<IIC_iCMOVi , [InstrStage<1, [V6_Pipe]>], [3]>, 52207618Srdivacky InstrItinData<IIC_iCMOVr , [InstrStage<1, [V6_Pipe]>], [3, 2]>, 53207618Srdivacky InstrItinData<IIC_iCMOVsi , [InstrStage<1, [V6_Pipe]>], [3, 1]>, 54207618Srdivacky InstrItinData<IIC_iCMOVsr , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 55199511Srdivacky 56199511Srdivacky // Integer multiply pipeline 57199511Srdivacky // 58207618Srdivacky InstrItinData<IIC_iMUL16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 59207618Srdivacky InstrItinData<IIC_iMAC16 , [InstrStage<1, [V6_Pipe]>], [4, 1, 1, 2]>, 60207618Srdivacky InstrItinData<IIC_iMUL32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1]>, 61207618Srdivacky InstrItinData<IIC_iMAC32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1, 2]>, 62207618Srdivacky InstrItinData<IIC_iMUL64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1]>, 63207618Srdivacky InstrItinData<IIC_iMAC64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1, 2]>, 64199511Srdivacky 65199511Srdivacky // Integer load pipeline 66199511Srdivacky // 67199511Srdivacky // Immediate offset 68207618Srdivacky InstrItinData<IIC_iLoadi , [InstrStage<1, [V6_Pipe]>], [4, 1]>, 69199511Srdivacky // 70199511Srdivacky // Register offset 71207618Srdivacky InstrItinData<IIC_iLoadr , [InstrStage<1, [V6_Pipe]>], [4, 1, 1]>, 72199511Srdivacky // 73199511Srdivacky // Scaled register offset, issues over 2 cycles 74207618Srdivacky InstrItinData<IIC_iLoadsi , [InstrStage<2, [V6_Pipe]>], [5, 2, 1]>, 75199511Srdivacky // 76199511Srdivacky // Immediate offset with update 77207618Srdivacky InstrItinData<IIC_iLoadiu , [InstrStage<1, [V6_Pipe]>], [4, 2, 1]>, 78199511Srdivacky // 79199511Srdivacky // Register offset with update 80207618Srdivacky InstrItinData<IIC_iLoadru , [InstrStage<1, [V6_Pipe]>], [4, 2, 1, 1]>, 81199511Srdivacky // 82199511Srdivacky // Scaled register offset with update, issues over 2 cycles 83207618Srdivacky InstrItinData<IIC_iLoadsiu , [InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>, 84199511Srdivacky 85199511Srdivacky // 86199511Srdivacky // Load multiple 87207618Srdivacky InstrItinData<IIC_iLoadm , [InstrStage<3, [V6_Pipe]>]>, 88199511Srdivacky 89199511Srdivacky // Integer store pipeline 90199511Srdivacky // 91199511Srdivacky // Immediate offset 92207618Srdivacky InstrItinData<IIC_iStorei , [InstrStage<1, [V6_Pipe]>], [2, 1]>, 93199511Srdivacky // 94199511Srdivacky // Register offset 95207618Srdivacky InstrItinData<IIC_iStorer , [InstrStage<1, [V6_Pipe]>], [2, 1, 1]>, 96199511Srdivacky 97199511Srdivacky // 98199511Srdivacky // Scaled register offset, issues over 2 cycles 99207618Srdivacky InstrItinData<IIC_iStoresi , [InstrStage<2, [V6_Pipe]>], [2, 2, 1]>, 100199511Srdivacky // 101199511Srdivacky // Immediate offset with update 102207618Srdivacky InstrItinData<IIC_iStoreiu , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 103199511Srdivacky // 104199511Srdivacky // Register offset with update 105207618Srdivacky InstrItinData<IIC_iStoreru , [InstrStage<1, [V6_Pipe]>], [2, 2, 1, 1]>, 106199511Srdivacky // 107199511Srdivacky // Scaled register offset with update, issues over 2 cycles 108207618Srdivacky InstrItinData<IIC_iStoresiu, [InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>, 109199511Srdivacky // 110199511Srdivacky // Store multiple 111207618Srdivacky InstrItinData<IIC_iStorem , [InstrStage<3, [V6_Pipe]>]>, 112199511Srdivacky 113199511Srdivacky // Branch 114199511Srdivacky // 115199511Srdivacky // no delay slots, so the latency of a branch is unimportant 116207618Srdivacky InstrItinData<IIC_Br , [InstrStage<1, [V6_Pipe]>]>, 117199511Srdivacky 118199511Srdivacky // VFP 119199511Srdivacky // Issue through integer pipeline, and execute in NEON unit. We assume 120199511Srdivacky // RunFast mode so that NFP pipeline is used for single-precision when 121199511Srdivacky // possible. 122199511Srdivacky // 123199511Srdivacky // FP Special Register to Integer Register File Move 124207618Srdivacky InstrItinData<IIC_fpSTAT , [InstrStage<1, [V6_Pipe]>], [3]>, 125199511Srdivacky // 126199511Srdivacky // Single-precision FP Unary 127207618Srdivacky InstrItinData<IIC_fpUNA32 , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 128199511Srdivacky // 129199511Srdivacky // Double-precision FP Unary 130207618Srdivacky InstrItinData<IIC_fpUNA64 , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 131199511Srdivacky // 132199511Srdivacky // Single-precision FP Compare 133207618Srdivacky InstrItinData<IIC_fpCMP32 , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 134199511Srdivacky // 135199511Srdivacky // Double-precision FP Compare 136207618Srdivacky InstrItinData<IIC_fpCMP64 , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 137199511Srdivacky // 138199511Srdivacky // Single to Double FP Convert 139207618Srdivacky InstrItinData<IIC_fpCVTSD , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 140199511Srdivacky // 141199511Srdivacky // Double to Single FP Convert 142207618Srdivacky InstrItinData<IIC_fpCVTDS , [InstrStage<1, [V6_Pipe]>], [5, 2]>, 143199511Srdivacky // 144199511Srdivacky // Single-Precision FP to Integer Convert 145207618Srdivacky InstrItinData<IIC_fpCVTSI , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 146199511Srdivacky // 147199511Srdivacky // Double-Precision FP to Integer Convert 148207618Srdivacky InstrItinData<IIC_fpCVTDI , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 149199511Srdivacky // 150199511Srdivacky // Integer to Single-Precision FP Convert 151207618Srdivacky InstrItinData<IIC_fpCVTIS , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 152199511Srdivacky // 153199511Srdivacky // Integer to Double-Precision FP Convert 154207618Srdivacky InstrItinData<IIC_fpCVTID , [InstrStage<1, [V6_Pipe]>], [9, 2]>, 155199511Srdivacky // 156199511Srdivacky // Single-precision FP ALU 157207618Srdivacky InstrItinData<IIC_fpALU32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 158199511Srdivacky // 159199511Srdivacky // Double-precision FP ALU 160207618Srdivacky InstrItinData<IIC_fpALU64 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 161199511Srdivacky // 162199511Srdivacky // Single-precision FP Multiply 163207618Srdivacky InstrItinData<IIC_fpMUL32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2]>, 164199511Srdivacky // 165199511Srdivacky // Double-precision FP Multiply 166207618Srdivacky InstrItinData<IIC_fpMUL64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2]>, 167199511Srdivacky // 168199511Srdivacky // Single-precision FP MAC 169207618Srdivacky InstrItinData<IIC_fpMAC32 , [InstrStage<1, [V6_Pipe]>], [9, 2, 2, 2]>, 170199511Srdivacky // 171199511Srdivacky // Double-precision FP MAC 172207618Srdivacky InstrItinData<IIC_fpMAC64 , [InstrStage<2, [V6_Pipe]>], [9, 2, 2, 2]>, 173199511Srdivacky // 174199511Srdivacky // Single-precision FP DIV 175207618Srdivacky InstrItinData<IIC_fpDIV32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>, 176199511Srdivacky // 177199511Srdivacky // Double-precision FP DIV 178207618Srdivacky InstrItinData<IIC_fpDIV64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>, 179199511Srdivacky // 180199511Srdivacky // Single-precision FP SQRT 181207618Srdivacky InstrItinData<IIC_fpSQRT32 , [InstrStage<15, [V6_Pipe]>], [20, 2, 2]>, 182199511Srdivacky // 183199511Srdivacky // Double-precision FP SQRT 184207618Srdivacky InstrItinData<IIC_fpSQRT64 , [InstrStage<29, [V6_Pipe]>], [34, 2, 2]>, 185199511Srdivacky // 186199511Srdivacky // Single-precision FP Load 187207618Srdivacky InstrItinData<IIC_fpLoad32 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>, 188199511Srdivacky // 189199511Srdivacky // Double-precision FP Load 190207618Srdivacky InstrItinData<IIC_fpLoad64 , [InstrStage<1, [V6_Pipe]>], [5, 2, 2]>, 191199511Srdivacky // 192199511Srdivacky // FP Load Multiple 193207618Srdivacky InstrItinData<IIC_fpLoadm , [InstrStage<3, [V6_Pipe]>]>, 194199511Srdivacky // 195199511Srdivacky // Single-precision FP Store 196207618Srdivacky InstrItinData<IIC_fpStore32 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 197199511Srdivacky // 198199511Srdivacky // Double-precision FP Store 199199511Srdivacky // use FU_Issue to enforce the 1 load/store per cycle limit 200207618Srdivacky InstrItinData<IIC_fpStore64 , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 201199511Srdivacky // 202199511Srdivacky // FP Store Multiple 203207618Srdivacky InstrItinData<IIC_fpStorem , [InstrStage<3, [V6_Pipe]>]> 204199511Srdivacky]>; 205