DAGCombiner.cpp revision 226633
1193323Sed//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
2193323Sed//
3193323Sed//                     The LLVM Compiler Infrastructure
4193323Sed//
5193323Sed// This file is distributed under the University of Illinois Open Source
6193323Sed// License. See LICENSE.TXT for details.
7193323Sed//
8193323Sed//===----------------------------------------------------------------------===//
9193323Sed//
10193323Sed// This pass combines dag nodes to form fewer, simpler DAG nodes.  It can be run
11193323Sed// both before and after the DAG is legalized.
12193323Sed//
13193323Sed// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14193323Sed// primarily intended to handle simplification opportunities that are implicit
15193323Sed// in the LLVM IR and exposed by the various codegen lowering phases.
16193323Sed//
17193323Sed//===----------------------------------------------------------------------===//
18193323Sed
19193323Sed#define DEBUG_TYPE "dagcombine"
20193323Sed#include "llvm/CodeGen/SelectionDAG.h"
21193323Sed#include "llvm/DerivedTypes.h"
22198090Srdivacky#include "llvm/LLVMContext.h"
23193323Sed#include "llvm/CodeGen/MachineFunction.h"
24193323Sed#include "llvm/CodeGen/MachineFrameInfo.h"
25193323Sed#include "llvm/CodeGen/PseudoSourceValue.h"
26193323Sed#include "llvm/Analysis/AliasAnalysis.h"
27193323Sed#include "llvm/Target/TargetData.h"
28193323Sed#include "llvm/Target/TargetLowering.h"
29193323Sed#include "llvm/Target/TargetMachine.h"
30193323Sed#include "llvm/Target/TargetOptions.h"
31193323Sed#include "llvm/ADT/SmallPtrSet.h"
32193323Sed#include "llvm/ADT/Statistic.h"
33193323Sed#include "llvm/Support/CommandLine.h"
34193323Sed#include "llvm/Support/Debug.h"
35198090Srdivacky#include "llvm/Support/ErrorHandling.h"
36193323Sed#include "llvm/Support/MathExtras.h"
37198090Srdivacky#include "llvm/Support/raw_ostream.h"
38193323Sed#include <algorithm>
39193323Sedusing namespace llvm;
40193323Sed
41193323SedSTATISTIC(NodesCombined   , "Number of dag nodes combined");
42193323SedSTATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43193323SedSTATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44193323SedSTATISTIC(OpsNarrowed     , "Number of load/op/store narrowed");
45218893SdimSTATISTIC(LdStFP2Int      , "Number of fp load/store pairs transformed to int");
46193323Sed
47193323Sednamespace {
48193323Sed  static cl::opt<bool>
49193323Sed    CombinerAA("combiner-alias-analysis", cl::Hidden,
50193323Sed               cl::desc("Turn on alias analysis during testing"));
51193323Sed
52193323Sed  static cl::opt<bool>
53193323Sed    CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54193323Sed               cl::desc("Include global information in alias analysis"));
55193323Sed
56193323Sed//------------------------------ DAGCombiner ---------------------------------//
57193323Sed
58198892Srdivacky  class DAGCombiner {
59193323Sed    SelectionDAG &DAG;
60193323Sed    const TargetLowering &TLI;
61193323Sed    CombineLevel Level;
62193323Sed    CodeGenOpt::Level OptLevel;
63193323Sed    bool LegalOperations;
64193323Sed    bool LegalTypes;
65193323Sed
66193323Sed    // Worklist of all of the nodes that need to be simplified.
67193323Sed    std::vector<SDNode*> WorkList;
68193323Sed
69193323Sed    // AA - Used for DAG load/store alias analysis.
70193323Sed    AliasAnalysis &AA;
71193323Sed
72193323Sed    /// AddUsersToWorkList - When an instruction is simplified, add all users of
73193323Sed    /// the instruction to the work lists because they might get more simplified
74193323Sed    /// now.
75193323Sed    ///
76193323Sed    void AddUsersToWorkList(SDNode *N) {
77193323Sed      for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
78193323Sed           UI != UE; ++UI)
79193323Sed        AddToWorkList(*UI);
80193323Sed    }
81193323Sed
82193323Sed    /// visit - call the node-specific routine that knows how to fold each
83193323Sed    /// particular type of node.
84193323Sed    SDValue visit(SDNode *N);
85193323Sed
86193323Sed  public:
87193323Sed    /// AddToWorkList - Add to the work list making sure it's instance is at the
88193323Sed    /// the back (next to be processed.)
89193323Sed    void AddToWorkList(SDNode *N) {
90193323Sed      removeFromWorkList(N);
91193323Sed      WorkList.push_back(N);
92193323Sed    }
93193323Sed
94193323Sed    /// removeFromWorkList - remove all instances of N from the worklist.
95193323Sed    ///
96193323Sed    void removeFromWorkList(SDNode *N) {
97193323Sed      WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
98193323Sed                     WorkList.end());
99193323Sed    }
100193323Sed
101193323Sed    SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
102193323Sed                      bool AddTo = true);
103193323Sed
104193323Sed    SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105193323Sed      return CombineTo(N, &Res, 1, AddTo);
106193323Sed    }
107193323Sed
108193323Sed    SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
109193323Sed                      bool AddTo = true) {
110193323Sed      SDValue To[] = { Res0, Res1 };
111193323Sed      return CombineTo(N, To, 2, AddTo);
112193323Sed    }
113193323Sed
114193323Sed    void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
115193323Sed
116193323Sed  private:
117193323Sed
118193323Sed    /// SimplifyDemandedBits - Check the specified integer node value to see if
119193323Sed    /// it can be simplified or if things it uses can be simplified by bit
120193323Sed    /// propagation.  If so, return true.
121193323Sed    bool SimplifyDemandedBits(SDValue Op) {
122200581Srdivacky      unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123200581Srdivacky      APInt Demanded = APInt::getAllOnesValue(BitWidth);
124193323Sed      return SimplifyDemandedBits(Op, Demanded);
125193323Sed    }
126193323Sed
127193323Sed    bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
128193323Sed
129193323Sed    bool CombineToPreIndexedLoadStore(SDNode *N);
130193323Sed    bool CombineToPostIndexedLoadStore(SDNode *N);
131193323Sed
132207618Srdivacky    void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133207618Srdivacky    SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134207618Srdivacky    SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135207618Srdivacky    SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136207618Srdivacky    SDValue PromoteIntBinOp(SDValue Op);
137207618Srdivacky    SDValue PromoteIntShiftOp(SDValue Op);
138207618Srdivacky    SDValue PromoteExtend(SDValue Op);
139207618Srdivacky    bool PromoteLoad(SDValue Op);
140193323Sed
141224145Sdim    void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
142224145Sdim                         SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
143224145Sdim                         ISD::NodeType ExtType);
144224145Sdim
145193323Sed    /// combine - call the node-specific routine that knows how to fold each
146193323Sed    /// particular type of node. If that doesn't do anything, try the
147193323Sed    /// target-specific DAG combines.
148193323Sed    SDValue combine(SDNode *N);
149193323Sed
150193323Sed    // Visitation implementation - Implement dag node combining for different
151193323Sed    // node types.  The semantics are as follows:
152193323Sed    // Return Value:
153193323Sed    //   SDValue.getNode() == 0 - No change was made
154193323Sed    //   SDValue.getNode() == N - N was replaced, is dead and has been handled.
155193323Sed    //   otherwise              - N should be replaced by the returned Operand.
156193323Sed    //
157193323Sed    SDValue visitTokenFactor(SDNode *N);
158193323Sed    SDValue visitMERGE_VALUES(SDNode *N);
159193323Sed    SDValue visitADD(SDNode *N);
160193323Sed    SDValue visitSUB(SDNode *N);
161193323Sed    SDValue visitADDC(SDNode *N);
162193323Sed    SDValue visitADDE(SDNode *N);
163193323Sed    SDValue visitMUL(SDNode *N);
164193323Sed    SDValue visitSDIV(SDNode *N);
165193323Sed    SDValue visitUDIV(SDNode *N);
166193323Sed    SDValue visitSREM(SDNode *N);
167193323Sed    SDValue visitUREM(SDNode *N);
168193323Sed    SDValue visitMULHU(SDNode *N);
169193323Sed    SDValue visitMULHS(SDNode *N);
170193323Sed    SDValue visitSMUL_LOHI(SDNode *N);
171193323Sed    SDValue visitUMUL_LOHI(SDNode *N);
172223017Sdim    SDValue visitSMULO(SDNode *N);
173223017Sdim    SDValue visitUMULO(SDNode *N);
174193323Sed    SDValue visitSDIVREM(SDNode *N);
175193323Sed    SDValue visitUDIVREM(SDNode *N);
176193323Sed    SDValue visitAND(SDNode *N);
177193323Sed    SDValue visitOR(SDNode *N);
178193323Sed    SDValue visitXOR(SDNode *N);
179193323Sed    SDValue SimplifyVBinOp(SDNode *N);
180193323Sed    SDValue visitSHL(SDNode *N);
181193323Sed    SDValue visitSRA(SDNode *N);
182193323Sed    SDValue visitSRL(SDNode *N);
183193323Sed    SDValue visitCTLZ(SDNode *N);
184193323Sed    SDValue visitCTTZ(SDNode *N);
185193323Sed    SDValue visitCTPOP(SDNode *N);
186193323Sed    SDValue visitSELECT(SDNode *N);
187193323Sed    SDValue visitSELECT_CC(SDNode *N);
188193323Sed    SDValue visitSETCC(SDNode *N);
189193323Sed    SDValue visitSIGN_EXTEND(SDNode *N);
190193323Sed    SDValue visitZERO_EXTEND(SDNode *N);
191193323Sed    SDValue visitANY_EXTEND(SDNode *N);
192193323Sed    SDValue visitSIGN_EXTEND_INREG(SDNode *N);
193193323Sed    SDValue visitTRUNCATE(SDNode *N);
194218893Sdim    SDValue visitBITCAST(SDNode *N);
195193323Sed    SDValue visitBUILD_PAIR(SDNode *N);
196193323Sed    SDValue visitFADD(SDNode *N);
197193323Sed    SDValue visitFSUB(SDNode *N);
198193323Sed    SDValue visitFMUL(SDNode *N);
199193323Sed    SDValue visitFDIV(SDNode *N);
200193323Sed    SDValue visitFREM(SDNode *N);
201193323Sed    SDValue visitFCOPYSIGN(SDNode *N);
202193323Sed    SDValue visitSINT_TO_FP(SDNode *N);
203193323Sed    SDValue visitUINT_TO_FP(SDNode *N);
204193323Sed    SDValue visitFP_TO_SINT(SDNode *N);
205193323Sed    SDValue visitFP_TO_UINT(SDNode *N);
206193323Sed    SDValue visitFP_ROUND(SDNode *N);
207193323Sed    SDValue visitFP_ROUND_INREG(SDNode *N);
208193323Sed    SDValue visitFP_EXTEND(SDNode *N);
209193323Sed    SDValue visitFNEG(SDNode *N);
210193323Sed    SDValue visitFABS(SDNode *N);
211193323Sed    SDValue visitBRCOND(SDNode *N);
212193323Sed    SDValue visitBR_CC(SDNode *N);
213193323Sed    SDValue visitLOAD(SDNode *N);
214193323Sed    SDValue visitSTORE(SDNode *N);
215193323Sed    SDValue visitINSERT_VECTOR_ELT(SDNode *N);
216193323Sed    SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
217193323Sed    SDValue visitBUILD_VECTOR(SDNode *N);
218193323Sed    SDValue visitCONCAT_VECTORS(SDNode *N);
219226633Sdim    SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
220193323Sed    SDValue visitVECTOR_SHUFFLE(SDNode *N);
221210299Sed    SDValue visitMEMBARRIER(SDNode *N);
222193323Sed
223193323Sed    SDValue XformToShuffleWithZero(SDNode *N);
224193323Sed    SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
225193323Sed
226193323Sed    SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
227193323Sed
228193323Sed    bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
229193323Sed    SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
230193323Sed    SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
231193323Sed    SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
232193323Sed                             SDValue N3, ISD::CondCode CC,
233193323Sed                             bool NotExtCompare = false);
234198090Srdivacky    SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
235193323Sed                          DebugLoc DL, bool foldBooleans = true);
236193323Sed    SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
237193323Sed                                         unsigned HiOp);
238198090Srdivacky    SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
239218893Sdim    SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
240193323Sed    SDValue BuildSDIV(SDNode *N);
241193323Sed    SDValue BuildUDIV(SDNode *N);
242224145Sdim    SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
243224145Sdim                               bool DemandHighBits = true);
244224145Sdim    SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
245193323Sed    SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
246193323Sed    SDValue ReduceLoadWidth(SDNode *N);
247193323Sed    SDValue ReduceLoadOpStoreWidth(SDNode *N);
248218893Sdim    SDValue TransformFPLoadStorePair(SDNode *N);
249193323Sed
250193323Sed    SDValue GetDemandedBits(SDValue V, const APInt &Mask);
251193323Sed
252193323Sed    /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
253193323Sed    /// looking for aliasing nodes and adding them to the Aliases vector.
254193323Sed    void GatherAllAliases(SDNode *N, SDValue OriginalChain,
255193323Sed                          SmallVector<SDValue, 8> &Aliases);
256193323Sed
257193323Sed    /// isAlias - Return true if there is any possibility that the two addresses
258193323Sed    /// overlap.
259193323Sed    bool isAlias(SDValue Ptr1, int64_t Size1,
260193323Sed                 const Value *SrcValue1, int SrcValueOffset1,
261198090Srdivacky                 unsigned SrcValueAlign1,
262218893Sdim                 const MDNode *TBAAInfo1,
263193323Sed                 SDValue Ptr2, int64_t Size2,
264198090Srdivacky                 const Value *SrcValue2, int SrcValueOffset2,
265218893Sdim                 unsigned SrcValueAlign2,
266218893Sdim                 const MDNode *TBAAInfo2) const;
267193323Sed
268193323Sed    /// FindAliasInfo - Extracts the relevant alias information from the memory
269193323Sed    /// node.  Returns true if the operand was a load.
270193323Sed    bool FindAliasInfo(SDNode *N,
271193323Sed                       SDValue &Ptr, int64_t &Size,
272198090Srdivacky                       const Value *&SrcValue, int &SrcValueOffset,
273218893Sdim                       unsigned &SrcValueAlignment,
274218893Sdim                       const MDNode *&TBAAInfo) const;
275193323Sed
276193323Sed    /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
277193323Sed    /// looking for a better chain (aliasing node.)
278193323Sed    SDValue FindBetterChain(SDNode *N, SDValue Chain);
279193323Sed
280207618Srdivacky  public:
281207618Srdivacky    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
282207618Srdivacky      : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
283207618Srdivacky        OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
284207618Srdivacky
285207618Srdivacky    /// Run - runs the dag combiner on all nodes in the work list
286207618Srdivacky    void Run(CombineLevel AtLevel);
287218893Sdim
288207618Srdivacky    SelectionDAG &getDAG() const { return DAG; }
289218893Sdim
290193323Sed    /// getShiftAmountTy - Returns a type large enough to hold any valid
291193323Sed    /// shift amount - before type legalization these can be huge.
292219077Sdim    EVT getShiftAmountTy(EVT LHSTy) {
293219077Sdim      return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
294193323Sed    }
295218893Sdim
296207618Srdivacky    /// isTypeLegal - This method returns true if we are running before type
297207618Srdivacky    /// legalization or if the specified VT is legal.
298207618Srdivacky    bool isTypeLegal(const EVT &VT) {
299207618Srdivacky      if (!LegalTypes) return true;
300207618Srdivacky      return TLI.isTypeLegal(VT);
301207618Srdivacky    }
302193323Sed  };
303193323Sed}
304193323Sed
305193323Sed
306193323Sednamespace {
307193323Sed/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
308193323Sed/// nodes from the worklist.
309198892Srdivackyclass WorkListRemover : public SelectionDAG::DAGUpdateListener {
310193323Sed  DAGCombiner &DC;
311193323Sedpublic:
312193323Sed  explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
313193323Sed
314193323Sed  virtual void NodeDeleted(SDNode *N, SDNode *E) {
315193323Sed    DC.removeFromWorkList(N);
316193323Sed  }
317193323Sed
318193323Sed  virtual void NodeUpdated(SDNode *N) {
319193323Sed    // Ignore updates.
320193323Sed  }
321193323Sed};
322193323Sed}
323193323Sed
324193323Sed//===----------------------------------------------------------------------===//
325193323Sed//  TargetLowering::DAGCombinerInfo implementation
326193323Sed//===----------------------------------------------------------------------===//
327193323Sed
328193323Sedvoid TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
329193323Sed  ((DAGCombiner*)DC)->AddToWorkList(N);
330193323Sed}
331193323Sed
332221345Sdimvoid TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
333221345Sdim  ((DAGCombiner*)DC)->removeFromWorkList(N);
334221345Sdim}
335221345Sdim
336193323SedSDValue TargetLowering::DAGCombinerInfo::
337193323SedCombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
338193323Sed  return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
339193323Sed}
340193323Sed
341193323SedSDValue TargetLowering::DAGCombinerInfo::
342193323SedCombineTo(SDNode *N, SDValue Res, bool AddTo) {
343193323Sed  return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
344193323Sed}
345193323Sed
346193323Sed
347193323SedSDValue TargetLowering::DAGCombinerInfo::
348193323SedCombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
349193323Sed  return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
350193323Sed}
351193323Sed
352193323Sedvoid TargetLowering::DAGCombinerInfo::
353193323SedCommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
354193323Sed  return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
355193323Sed}
356193323Sed
357193323Sed//===----------------------------------------------------------------------===//
358193323Sed// Helper Functions
359193323Sed//===----------------------------------------------------------------------===//
360193323Sed
361193323Sed/// isNegatibleForFree - Return 1 if we can compute the negated form of the
362193323Sed/// specified expression for the same cost as the expression itself, or 2 if we
363193323Sed/// can compute the negated form more cheaply than the expression itself.
364193323Sedstatic char isNegatibleForFree(SDValue Op, bool LegalOperations,
365193323Sed                               unsigned Depth = 0) {
366193323Sed  // No compile time optimizations on this type.
367193323Sed  if (Op.getValueType() == MVT::ppcf128)
368193323Sed    return 0;
369193323Sed
370193323Sed  // fneg is removable even if it has multiple uses.
371193323Sed  if (Op.getOpcode() == ISD::FNEG) return 2;
372193323Sed
373193323Sed  // Don't allow anything with multiple uses.
374193323Sed  if (!Op.hasOneUse()) return 0;
375193323Sed
376193323Sed  // Don't recurse exponentially.
377193323Sed  if (Depth > 6) return 0;
378193323Sed
379193323Sed  switch (Op.getOpcode()) {
380193323Sed  default: return false;
381193323Sed  case ISD::ConstantFP:
382193323Sed    // Don't invert constant FP values after legalize.  The negated constant
383193323Sed    // isn't necessarily legal.
384193323Sed    return LegalOperations ? 0 : 1;
385193323Sed  case ISD::FADD:
386193323Sed    // FIXME: determine better conditions for this xform.
387193323Sed    if (!UnsafeFPMath) return 0;
388193323Sed
389193323Sed    // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
390193323Sed    if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
391193323Sed      return V;
392193323Sed    // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
393193323Sed    return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
394193323Sed  case ISD::FSUB:
395193323Sed    // We can't turn -(A-B) into B-A when we honor signed zeros.
396193323Sed    if (!UnsafeFPMath) return 0;
397193323Sed
398193323Sed    // fold (fneg (fsub A, B)) -> (fsub B, A)
399193323Sed    return 1;
400193323Sed
401193323Sed  case ISD::FMUL:
402193323Sed  case ISD::FDIV:
403193323Sed    if (HonorSignDependentRoundingFPMath()) return 0;
404193323Sed
405193323Sed    // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
406193323Sed    if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
407193323Sed      return V;
408193323Sed
409193323Sed    return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
410193323Sed
411193323Sed  case ISD::FP_EXTEND:
412193323Sed  case ISD::FP_ROUND:
413193323Sed  case ISD::FSIN:
414193323Sed    return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
415193323Sed  }
416193323Sed}
417193323Sed
418193323Sed/// GetNegatedExpression - If isNegatibleForFree returns true, this function
419193323Sed/// returns the newly negated expression.
420193323Sedstatic SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
421193323Sed                                    bool LegalOperations, unsigned Depth = 0) {
422193323Sed  // fneg is removable even if it has multiple uses.
423193323Sed  if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
424193323Sed
425193323Sed  // Don't allow anything with multiple uses.
426193323Sed  assert(Op.hasOneUse() && "Unknown reuse!");
427193323Sed
428193323Sed  assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
429193323Sed  switch (Op.getOpcode()) {
430198090Srdivacky  default: llvm_unreachable("Unknown code");
431193323Sed  case ISD::ConstantFP: {
432193323Sed    APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
433193323Sed    V.changeSign();
434193323Sed    return DAG.getConstantFP(V, Op.getValueType());
435193323Sed  }
436193323Sed  case ISD::FADD:
437193323Sed    // FIXME: determine better conditions for this xform.
438193323Sed    assert(UnsafeFPMath);
439193323Sed
440193323Sed    // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
441193323Sed    if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
442193323Sed      return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
443193323Sed                         GetNegatedExpression(Op.getOperand(0), DAG,
444193323Sed                                              LegalOperations, Depth+1),
445193323Sed                         Op.getOperand(1));
446193323Sed    // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
447193323Sed    return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
448193323Sed                       GetNegatedExpression(Op.getOperand(1), DAG,
449193323Sed                                            LegalOperations, Depth+1),
450193323Sed                       Op.getOperand(0));
451193323Sed  case ISD::FSUB:
452193323Sed    // We can't turn -(A-B) into B-A when we honor signed zeros.
453193323Sed    assert(UnsafeFPMath);
454193323Sed
455193323Sed    // fold (fneg (fsub 0, B)) -> B
456193323Sed    if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
457193323Sed      if (N0CFP->getValueAPF().isZero())
458193323Sed        return Op.getOperand(1);
459193323Sed
460193323Sed    // fold (fneg (fsub A, B)) -> (fsub B, A)
461193323Sed    return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
462193323Sed                       Op.getOperand(1), Op.getOperand(0));
463193323Sed
464193323Sed  case ISD::FMUL:
465193323Sed  case ISD::FDIV:
466193323Sed    assert(!HonorSignDependentRoundingFPMath());
467193323Sed
468193323Sed    // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
469193323Sed    if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
470193323Sed      return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
471193323Sed                         GetNegatedExpression(Op.getOperand(0), DAG,
472193323Sed                                              LegalOperations, Depth+1),
473193323Sed                         Op.getOperand(1));
474193323Sed
475193323Sed    // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
476193323Sed    return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
477193323Sed                       Op.getOperand(0),
478193323Sed                       GetNegatedExpression(Op.getOperand(1), DAG,
479193323Sed                                            LegalOperations, Depth+1));
480193323Sed
481193323Sed  case ISD::FP_EXTEND:
482193323Sed  case ISD::FSIN:
483193323Sed    return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
484193323Sed                       GetNegatedExpression(Op.getOperand(0), DAG,
485193323Sed                                            LegalOperations, Depth+1));
486193323Sed  case ISD::FP_ROUND:
487193323Sed      return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
488193323Sed                         GetNegatedExpression(Op.getOperand(0), DAG,
489193323Sed                                              LegalOperations, Depth+1),
490193323Sed                         Op.getOperand(1));
491193323Sed  }
492193323Sed}
493193323Sed
494193323Sed
495193323Sed// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
496193323Sed// that selects between the values 1 and 0, making it equivalent to a setcc.
497193323Sed// Also, set the incoming LHS, RHS, and CC references to the appropriate
498193323Sed// nodes based on the type of node we are checking.  This simplifies life a
499193323Sed// bit for the callers.
500193323Sedstatic bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
501193323Sed                              SDValue &CC) {
502193323Sed  if (N.getOpcode() == ISD::SETCC) {
503193323Sed    LHS = N.getOperand(0);
504193323Sed    RHS = N.getOperand(1);
505193323Sed    CC  = N.getOperand(2);
506193323Sed    return true;
507193323Sed  }
508193323Sed  if (N.getOpcode() == ISD::SELECT_CC &&
509193323Sed      N.getOperand(2).getOpcode() == ISD::Constant &&
510193323Sed      N.getOperand(3).getOpcode() == ISD::Constant &&
511193323Sed      cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
512193323Sed      cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
513193323Sed    LHS = N.getOperand(0);
514193323Sed    RHS = N.getOperand(1);
515193323Sed    CC  = N.getOperand(4);
516193323Sed    return true;
517193323Sed  }
518193323Sed  return false;
519193323Sed}
520193323Sed
521193323Sed// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
522193323Sed// one use.  If this is true, it allows the users to invert the operation for
523193323Sed// free when it is profitable to do so.
524193323Sedstatic bool isOneUseSetCC(SDValue N) {
525193323Sed  SDValue N0, N1, N2;
526193323Sed  if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
527193323Sed    return true;
528193323Sed  return false;
529193323Sed}
530193323Sed
531193323SedSDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
532193323Sed                                    SDValue N0, SDValue N1) {
533198090Srdivacky  EVT VT = N0.getValueType();
534193323Sed  if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
535193323Sed    if (isa<ConstantSDNode>(N1)) {
536193323Sed      // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
537193323Sed      SDValue OpNode =
538193323Sed        DAG.FoldConstantArithmetic(Opc, VT,
539193323Sed                                   cast<ConstantSDNode>(N0.getOperand(1)),
540193323Sed                                   cast<ConstantSDNode>(N1));
541193323Sed      return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
542223017Sdim    }
543223017Sdim    if (N0.hasOneUse()) {
544193323Sed      // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
545193323Sed      SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
546193323Sed                                   N0.getOperand(0), N1);
547193323Sed      AddToWorkList(OpNode.getNode());
548193323Sed      return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
549193323Sed    }
550193323Sed  }
551193323Sed
552193323Sed  if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
553193323Sed    if (isa<ConstantSDNode>(N0)) {
554193323Sed      // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
555193323Sed      SDValue OpNode =
556193323Sed        DAG.FoldConstantArithmetic(Opc, VT,
557193323Sed                                   cast<ConstantSDNode>(N1.getOperand(1)),
558193323Sed                                   cast<ConstantSDNode>(N0));
559193323Sed      return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
560223017Sdim    }
561223017Sdim    if (N1.hasOneUse()) {
562193323Sed      // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
563193323Sed      SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
564193323Sed                                   N1.getOperand(0), N0);
565193323Sed      AddToWorkList(OpNode.getNode());
566193323Sed      return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
567193323Sed    }
568193323Sed  }
569193323Sed
570193323Sed  return SDValue();
571193323Sed}
572193323Sed
573193323SedSDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
574193323Sed                               bool AddTo) {
575193323Sed  assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
576193323Sed  ++NodesCombined;
577202375Srdivacky  DEBUG(dbgs() << "\nReplacing.1 ";
578198090Srdivacky        N->dump(&DAG);
579202375Srdivacky        dbgs() << "\nWith: ";
580198090Srdivacky        To[0].getNode()->dump(&DAG);
581202375Srdivacky        dbgs() << " and " << NumTo-1 << " other values\n";
582198090Srdivacky        for (unsigned i = 0, e = NumTo; i != e; ++i)
583200581Srdivacky          assert((!To[i].getNode() ||
584200581Srdivacky                  N->getValueType(i) == To[i].getValueType()) &&
585193323Sed                 "Cannot combine value to value of different type!"));
586193323Sed  WorkListRemover DeadNodes(*this);
587193323Sed  DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
588193323Sed
589193323Sed  if (AddTo) {
590193323Sed    // Push the new nodes and any users onto the worklist
591193323Sed    for (unsigned i = 0, e = NumTo; i != e; ++i) {
592193323Sed      if (To[i].getNode()) {
593193323Sed        AddToWorkList(To[i].getNode());
594193323Sed        AddUsersToWorkList(To[i].getNode());
595193323Sed      }
596193323Sed    }
597193323Sed  }
598193323Sed
599193323Sed  // Finally, if the node is now dead, remove it from the graph.  The node
600193323Sed  // may not be dead if the replacement process recursively simplified to
601193323Sed  // something else needing this node.
602193323Sed  if (N->use_empty()) {
603193323Sed    // Nodes can be reintroduced into the worklist.  Make sure we do not
604193323Sed    // process a node that has been replaced.
605193323Sed    removeFromWorkList(N);
606193323Sed
607193323Sed    // Finally, since the node is now dead, remove it from the graph.
608193323Sed    DAG.DeleteNode(N);
609193323Sed  }
610193323Sed  return SDValue(N, 0);
611193323Sed}
612193323Sed
613207618Srdivackyvoid DAGCombiner::
614207618SrdivackyCommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
615193323Sed  // Replace all uses.  If any nodes become isomorphic to other nodes and
616193323Sed  // are deleted, make sure to remove them from our worklist.
617193323Sed  WorkListRemover DeadNodes(*this);
618193323Sed  DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
619193323Sed
620193323Sed  // Push the new node and any (possibly new) users onto the worklist.
621193323Sed  AddToWorkList(TLO.New.getNode());
622193323Sed  AddUsersToWorkList(TLO.New.getNode());
623193323Sed
624193323Sed  // Finally, if the node is now dead, remove it from the graph.  The node
625193323Sed  // may not be dead if the replacement process recursively simplified to
626193323Sed  // something else needing this node.
627193323Sed  if (TLO.Old.getNode()->use_empty()) {
628193323Sed    removeFromWorkList(TLO.Old.getNode());
629193323Sed
630193323Sed    // If the operands of this node are only used by the node, they will now
631193323Sed    // be dead.  Make sure to visit them first to delete dead nodes early.
632193323Sed    for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
633193323Sed      if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
634193323Sed        AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
635193323Sed
636193323Sed    DAG.DeleteNode(TLO.Old.getNode());
637193323Sed  }
638193323Sed}
639193323Sed
640193323Sed/// SimplifyDemandedBits - Check the specified integer node value to see if
641193323Sed/// it can be simplified or if things it uses can be simplified by bit
642193323Sed/// propagation.  If so, return true.
643193323Sedbool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
644207618Srdivacky  TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
645193323Sed  APInt KnownZero, KnownOne;
646193323Sed  if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
647193323Sed    return false;
648193323Sed
649193323Sed  // Revisit the node.
650193323Sed  AddToWorkList(Op.getNode());
651193323Sed
652193323Sed  // Replace the old value with the new one.
653193323Sed  ++NodesCombined;
654218893Sdim  DEBUG(dbgs() << "\nReplacing.2 ";
655198090Srdivacky        TLO.Old.getNode()->dump(&DAG);
656202375Srdivacky        dbgs() << "\nWith: ";
657198090Srdivacky        TLO.New.getNode()->dump(&DAG);
658202375Srdivacky        dbgs() << '\n');
659193323Sed
660193323Sed  CommitTargetLoweringOpt(TLO);
661193323Sed  return true;
662193323Sed}
663193323Sed
664207618Srdivackyvoid DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
665207618Srdivacky  DebugLoc dl = Load->getDebugLoc();
666207618Srdivacky  EVT VT = Load->getValueType(0);
667207618Srdivacky  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
668207618Srdivacky
669207618Srdivacky  DEBUG(dbgs() << "\nReplacing.9 ";
670207618Srdivacky        Load->dump(&DAG);
671207618Srdivacky        dbgs() << "\nWith: ";
672207618Srdivacky        Trunc.getNode()->dump(&DAG);
673207618Srdivacky        dbgs() << '\n');
674207618Srdivacky  WorkListRemover DeadNodes(*this);
675207618Srdivacky  DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
676207618Srdivacky  DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
677207618Srdivacky                                &DeadNodes);
678207618Srdivacky  removeFromWorkList(Load);
679207618Srdivacky  DAG.DeleteNode(Load);
680207618Srdivacky  AddToWorkList(Trunc.getNode());
681207618Srdivacky}
682207618Srdivacky
683207618SrdivackySDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
684207618Srdivacky  Replace = false;
685207618Srdivacky  DebugLoc dl = Op.getDebugLoc();
686207618Srdivacky  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
687207618Srdivacky    EVT MemVT = LD->getMemoryVT();
688207618Srdivacky    ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
689219077Sdim      ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
690218893Sdim                                                  : ISD::EXTLOAD)
691207618Srdivacky      : LD->getExtensionType();
692207618Srdivacky    Replace = true;
693218893Sdim    return DAG.getExtLoad(ExtType, dl, PVT,
694207618Srdivacky                          LD->getChain(), LD->getBasePtr(),
695218893Sdim                          LD->getPointerInfo(),
696207618Srdivacky                          MemVT, LD->isVolatile(),
697207618Srdivacky                          LD->isNonTemporal(), LD->getAlignment());
698207618Srdivacky  }
699207618Srdivacky
700207618Srdivacky  unsigned Opc = Op.getOpcode();
701207618Srdivacky  switch (Opc) {
702207618Srdivacky  default: break;
703207618Srdivacky  case ISD::AssertSext:
704207618Srdivacky    return DAG.getNode(ISD::AssertSext, dl, PVT,
705207618Srdivacky                       SExtPromoteOperand(Op.getOperand(0), PVT),
706207618Srdivacky                       Op.getOperand(1));
707207618Srdivacky  case ISD::AssertZext:
708207618Srdivacky    return DAG.getNode(ISD::AssertZext, dl, PVT,
709207618Srdivacky                       ZExtPromoteOperand(Op.getOperand(0), PVT),
710207618Srdivacky                       Op.getOperand(1));
711207618Srdivacky  case ISD::Constant: {
712207618Srdivacky    unsigned ExtOpc =
713207618Srdivacky      Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
714207618Srdivacky    return DAG.getNode(ExtOpc, dl, PVT, Op);
715207618Srdivacky  }
716218893Sdim  }
717207618Srdivacky
718207618Srdivacky  if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
719207618Srdivacky    return SDValue();
720207618Srdivacky  return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
721207618Srdivacky}
722207618Srdivacky
723207618SrdivackySDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
724207618Srdivacky  if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
725207618Srdivacky    return SDValue();
726207618Srdivacky  EVT OldVT = Op.getValueType();
727207618Srdivacky  DebugLoc dl = Op.getDebugLoc();
728207618Srdivacky  bool Replace = false;
729207618Srdivacky  SDValue NewOp = PromoteOperand(Op, PVT, Replace);
730207618Srdivacky  if (NewOp.getNode() == 0)
731207618Srdivacky    return SDValue();
732207618Srdivacky  AddToWorkList(NewOp.getNode());
733207618Srdivacky
734207618Srdivacky  if (Replace)
735207618Srdivacky    ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
736207618Srdivacky  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
737207618Srdivacky                     DAG.getValueType(OldVT));
738207618Srdivacky}
739207618Srdivacky
740207618SrdivackySDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
741207618Srdivacky  EVT OldVT = Op.getValueType();
742207618Srdivacky  DebugLoc dl = Op.getDebugLoc();
743207618Srdivacky  bool Replace = false;
744207618Srdivacky  SDValue NewOp = PromoteOperand(Op, PVT, Replace);
745207618Srdivacky  if (NewOp.getNode() == 0)
746207618Srdivacky    return SDValue();
747207618Srdivacky  AddToWorkList(NewOp.getNode());
748207618Srdivacky
749207618Srdivacky  if (Replace)
750207618Srdivacky    ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
751207618Srdivacky  return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
752207618Srdivacky}
753207618Srdivacky
754207618Srdivacky/// PromoteIntBinOp - Promote the specified integer binary operation if the
755207618Srdivacky/// target indicates it is beneficial. e.g. On x86, it's usually better to
756207618Srdivacky/// promote i16 operations to i32 since i16 instructions are longer.
757207618SrdivackySDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
758207618Srdivacky  if (!LegalOperations)
759207618Srdivacky    return SDValue();
760207618Srdivacky
761207618Srdivacky  EVT VT = Op.getValueType();
762207618Srdivacky  if (VT.isVector() || !VT.isInteger())
763207618Srdivacky    return SDValue();
764207618Srdivacky
765207618Srdivacky  // If operation type is 'undesirable', e.g. i16 on x86, consider
766207618Srdivacky  // promoting it.
767207618Srdivacky  unsigned Opc = Op.getOpcode();
768207618Srdivacky  if (TLI.isTypeDesirableForOp(Opc, VT))
769207618Srdivacky    return SDValue();
770207618Srdivacky
771207618Srdivacky  EVT PVT = VT;
772207618Srdivacky  // Consult target whether it is a good idea to promote this operation and
773207618Srdivacky  // what's the right type to promote it to.
774207618Srdivacky  if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
775207618Srdivacky    assert(PVT != VT && "Don't know what type to promote to!");
776207618Srdivacky
777207618Srdivacky    bool Replace0 = false;
778207618Srdivacky    SDValue N0 = Op.getOperand(0);
779207618Srdivacky    SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
780207618Srdivacky    if (NN0.getNode() == 0)
781207618Srdivacky      return SDValue();
782207618Srdivacky
783207618Srdivacky    bool Replace1 = false;
784207618Srdivacky    SDValue N1 = Op.getOperand(1);
785208599Srdivacky    SDValue NN1;
786208599Srdivacky    if (N0 == N1)
787208599Srdivacky      NN1 = NN0;
788208599Srdivacky    else {
789208599Srdivacky      NN1 = PromoteOperand(N1, PVT, Replace1);
790208599Srdivacky      if (NN1.getNode() == 0)
791208599Srdivacky        return SDValue();
792208599Srdivacky    }
793207618Srdivacky
794207618Srdivacky    AddToWorkList(NN0.getNode());
795208599Srdivacky    if (NN1.getNode())
796208599Srdivacky      AddToWorkList(NN1.getNode());
797207618Srdivacky
798207618Srdivacky    if (Replace0)
799207618Srdivacky      ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
800207618Srdivacky    if (Replace1)
801207618Srdivacky      ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
802207618Srdivacky
803207618Srdivacky    DEBUG(dbgs() << "\nPromoting ";
804207618Srdivacky          Op.getNode()->dump(&DAG));
805207618Srdivacky    DebugLoc dl = Op.getDebugLoc();
806207618Srdivacky    return DAG.getNode(ISD::TRUNCATE, dl, VT,
807207618Srdivacky                       DAG.getNode(Opc, dl, PVT, NN0, NN1));
808207618Srdivacky  }
809207618Srdivacky  return SDValue();
810207618Srdivacky}
811207618Srdivacky
812207618Srdivacky/// PromoteIntShiftOp - Promote the specified integer shift operation if the
813207618Srdivacky/// target indicates it is beneficial. e.g. On x86, it's usually better to
814207618Srdivacky/// promote i16 operations to i32 since i16 instructions are longer.
815207618SrdivackySDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
816207618Srdivacky  if (!LegalOperations)
817207618Srdivacky    return SDValue();
818207618Srdivacky
819207618Srdivacky  EVT VT = Op.getValueType();
820207618Srdivacky  if (VT.isVector() || !VT.isInteger())
821207618Srdivacky    return SDValue();
822207618Srdivacky
823207618Srdivacky  // If operation type is 'undesirable', e.g. i16 on x86, consider
824207618Srdivacky  // promoting it.
825207618Srdivacky  unsigned Opc = Op.getOpcode();
826207618Srdivacky  if (TLI.isTypeDesirableForOp(Opc, VT))
827207618Srdivacky    return SDValue();
828207618Srdivacky
829207618Srdivacky  EVT PVT = VT;
830207618Srdivacky  // Consult target whether it is a good idea to promote this operation and
831207618Srdivacky  // what's the right type to promote it to.
832207618Srdivacky  if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
833207618Srdivacky    assert(PVT != VT && "Don't know what type to promote to!");
834207618Srdivacky
835207618Srdivacky    bool Replace = false;
836207618Srdivacky    SDValue N0 = Op.getOperand(0);
837207618Srdivacky    if (Opc == ISD::SRA)
838207618Srdivacky      N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
839207618Srdivacky    else if (Opc == ISD::SRL)
840207618Srdivacky      N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
841207618Srdivacky    else
842207618Srdivacky      N0 = PromoteOperand(N0, PVT, Replace);
843207618Srdivacky    if (N0.getNode() == 0)
844207618Srdivacky      return SDValue();
845207618Srdivacky
846207618Srdivacky    AddToWorkList(N0.getNode());
847207618Srdivacky    if (Replace)
848207618Srdivacky      ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
849207618Srdivacky
850207618Srdivacky    DEBUG(dbgs() << "\nPromoting ";
851207618Srdivacky          Op.getNode()->dump(&DAG));
852207618Srdivacky    DebugLoc dl = Op.getDebugLoc();
853207618Srdivacky    return DAG.getNode(ISD::TRUNCATE, dl, VT,
854207618Srdivacky                       DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
855207618Srdivacky  }
856207618Srdivacky  return SDValue();
857207618Srdivacky}
858207618Srdivacky
859207618SrdivackySDValue DAGCombiner::PromoteExtend(SDValue Op) {
860207618Srdivacky  if (!LegalOperations)
861207618Srdivacky    return SDValue();
862207618Srdivacky
863207618Srdivacky  EVT VT = Op.getValueType();
864207618Srdivacky  if (VT.isVector() || !VT.isInteger())
865207618Srdivacky    return SDValue();
866207618Srdivacky
867207618Srdivacky  // If operation type is 'undesirable', e.g. i16 on x86, consider
868207618Srdivacky  // promoting it.
869207618Srdivacky  unsigned Opc = Op.getOpcode();
870207618Srdivacky  if (TLI.isTypeDesirableForOp(Opc, VT))
871207618Srdivacky    return SDValue();
872207618Srdivacky
873207618Srdivacky  EVT PVT = VT;
874207618Srdivacky  // Consult target whether it is a good idea to promote this operation and
875207618Srdivacky  // what's the right type to promote it to.
876207618Srdivacky  if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
877207618Srdivacky    assert(PVT != VT && "Don't know what type to promote to!");
878207618Srdivacky    // fold (aext (aext x)) -> (aext x)
879207618Srdivacky    // fold (aext (zext x)) -> (zext x)
880207618Srdivacky    // fold (aext (sext x)) -> (sext x)
881207618Srdivacky    DEBUG(dbgs() << "\nPromoting ";
882207618Srdivacky          Op.getNode()->dump(&DAG));
883207618Srdivacky    return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
884207618Srdivacky  }
885207618Srdivacky  return SDValue();
886207618Srdivacky}
887207618Srdivacky
888207618Srdivackybool DAGCombiner::PromoteLoad(SDValue Op) {
889207618Srdivacky  if (!LegalOperations)
890207618Srdivacky    return false;
891207618Srdivacky
892207618Srdivacky  EVT VT = Op.getValueType();
893207618Srdivacky  if (VT.isVector() || !VT.isInteger())
894207618Srdivacky    return false;
895207618Srdivacky
896207618Srdivacky  // If operation type is 'undesirable', e.g. i16 on x86, consider
897207618Srdivacky  // promoting it.
898207618Srdivacky  unsigned Opc = Op.getOpcode();
899207618Srdivacky  if (TLI.isTypeDesirableForOp(Opc, VT))
900207618Srdivacky    return false;
901207618Srdivacky
902207618Srdivacky  EVT PVT = VT;
903207618Srdivacky  // Consult target whether it is a good idea to promote this operation and
904207618Srdivacky  // what's the right type to promote it to.
905207618Srdivacky  if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
906207618Srdivacky    assert(PVT != VT && "Don't know what type to promote to!");
907207618Srdivacky
908207618Srdivacky    DebugLoc dl = Op.getDebugLoc();
909207618Srdivacky    SDNode *N = Op.getNode();
910207618Srdivacky    LoadSDNode *LD = cast<LoadSDNode>(N);
911207618Srdivacky    EVT MemVT = LD->getMemoryVT();
912207618Srdivacky    ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
913219077Sdim      ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
914218893Sdim                                                  : ISD::EXTLOAD)
915207618Srdivacky      : LD->getExtensionType();
916218893Sdim    SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
917207618Srdivacky                                   LD->getChain(), LD->getBasePtr(),
918218893Sdim                                   LD->getPointerInfo(),
919207618Srdivacky                                   MemVT, LD->isVolatile(),
920207618Srdivacky                                   LD->isNonTemporal(), LD->getAlignment());
921207618Srdivacky    SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
922207618Srdivacky
923207618Srdivacky    DEBUG(dbgs() << "\nPromoting ";
924207618Srdivacky          N->dump(&DAG);
925207618Srdivacky          dbgs() << "\nTo: ";
926207618Srdivacky          Result.getNode()->dump(&DAG);
927207618Srdivacky          dbgs() << '\n');
928207618Srdivacky    WorkListRemover DeadNodes(*this);
929207618Srdivacky    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
930207618Srdivacky    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
931207618Srdivacky    removeFromWorkList(N);
932207618Srdivacky    DAG.DeleteNode(N);
933207618Srdivacky    AddToWorkList(Result.getNode());
934207618Srdivacky    return true;
935207618Srdivacky  }
936207618Srdivacky  return false;
937207618Srdivacky}
938207618Srdivacky
939207618Srdivacky
940193323Sed//===----------------------------------------------------------------------===//
941193323Sed//  Main DAG Combiner implementation
942193323Sed//===----------------------------------------------------------------------===//
943193323Sed
944193323Sedvoid DAGCombiner::Run(CombineLevel AtLevel) {
945193323Sed  // set the instance variables, so that the various visit routines may use it.
946193323Sed  Level = AtLevel;
947193323Sed  LegalOperations = Level >= NoIllegalOperations;
948193323Sed  LegalTypes = Level >= NoIllegalTypes;
949193323Sed
950193323Sed  // Add all the dag nodes to the worklist.
951193323Sed  WorkList.reserve(DAG.allnodes_size());
952193323Sed  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
953193323Sed       E = DAG.allnodes_end(); I != E; ++I)
954193323Sed    WorkList.push_back(I);
955193323Sed
956193323Sed  // Create a dummy node (which is not added to allnodes), that adds a reference
957193323Sed  // to the root node, preventing it from being deleted, and tracking any
958193323Sed  // changes of the root.
959193323Sed  HandleSDNode Dummy(DAG.getRoot());
960193323Sed
961193323Sed  // The root of the dag may dangle to deleted nodes until the dag combiner is
962193323Sed  // done.  Set it to null to avoid confusion.
963193323Sed  DAG.setRoot(SDValue());
964193323Sed
965193323Sed  // while the worklist isn't empty, inspect the node on the end of it and
966193323Sed  // try and combine it.
967193323Sed  while (!WorkList.empty()) {
968193323Sed    SDNode *N = WorkList.back();
969193323Sed    WorkList.pop_back();
970193323Sed
971193323Sed    // If N has no uses, it is dead.  Make sure to revisit all N's operands once
972193323Sed    // N is deleted from the DAG, since they too may now be dead or may have a
973193323Sed    // reduced number of uses, allowing other xforms.
974193323Sed    if (N->use_empty() && N != &Dummy) {
975193323Sed      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
976193323Sed        AddToWorkList(N->getOperand(i).getNode());
977193323Sed
978193323Sed      DAG.DeleteNode(N);
979193323Sed      continue;
980193323Sed    }
981193323Sed
982193323Sed    SDValue RV = combine(N);
983193323Sed
984193323Sed    if (RV.getNode() == 0)
985193323Sed      continue;
986193323Sed
987193323Sed    ++NodesCombined;
988193323Sed
989193323Sed    // If we get back the same node we passed in, rather than a new node or
990193323Sed    // zero, we know that the node must have defined multiple values and
991193323Sed    // CombineTo was used.  Since CombineTo takes care of the worklist
992193323Sed    // mechanics for us, we have no work to do in this case.
993193323Sed    if (RV.getNode() == N)
994193323Sed      continue;
995193323Sed
996193323Sed    assert(N->getOpcode() != ISD::DELETED_NODE &&
997193323Sed           RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
998193323Sed           "Node was deleted but visit returned new node!");
999193323Sed
1000218893Sdim    DEBUG(dbgs() << "\nReplacing.3 ";
1001198090Srdivacky          N->dump(&DAG);
1002202375Srdivacky          dbgs() << "\nWith: ";
1003198090Srdivacky          RV.getNode()->dump(&DAG);
1004202375Srdivacky          dbgs() << '\n');
1005224145Sdim
1006223017Sdim    // Transfer debug value.
1007223017Sdim    DAG.TransferDbgValues(SDValue(N, 0), RV);
1008193323Sed    WorkListRemover DeadNodes(*this);
1009193323Sed    if (N->getNumValues() == RV.getNode()->getNumValues())
1010193323Sed      DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
1011193323Sed    else {
1012193323Sed      assert(N->getValueType(0) == RV.getValueType() &&
1013193323Sed             N->getNumValues() == 1 && "Type mismatch");
1014193323Sed      SDValue OpV = RV;
1015193323Sed      DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
1016193323Sed    }
1017193323Sed
1018193323Sed    // Push the new node and any users onto the worklist
1019193323Sed    AddToWorkList(RV.getNode());
1020193323Sed    AddUsersToWorkList(RV.getNode());
1021193323Sed
1022193323Sed    // Add any uses of the old node to the worklist in case this node is the
1023193323Sed    // last one that uses them.  They may become dead after this node is
1024193323Sed    // deleted.
1025193323Sed    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1026193323Sed      AddToWorkList(N->getOperand(i).getNode());
1027193323Sed
1028193323Sed    // Finally, if the node is now dead, remove it from the graph.  The node
1029193323Sed    // may not be dead if the replacement process recursively simplified to
1030193323Sed    // something else needing this node.
1031193323Sed    if (N->use_empty()) {
1032193323Sed      // Nodes can be reintroduced into the worklist.  Make sure we do not
1033193323Sed      // process a node that has been replaced.
1034193323Sed      removeFromWorkList(N);
1035193323Sed
1036193323Sed      // Finally, since the node is now dead, remove it from the graph.
1037193323Sed      DAG.DeleteNode(N);
1038193323Sed    }
1039193323Sed  }
1040193323Sed
1041193323Sed  // If the root changed (e.g. it was a dead load, update the root).
1042193323Sed  DAG.setRoot(Dummy.getValue());
1043193323Sed}
1044193323Sed
1045193323SedSDValue DAGCombiner::visit(SDNode *N) {
1046207618Srdivacky  switch (N->getOpcode()) {
1047193323Sed  default: break;
1048193323Sed  case ISD::TokenFactor:        return visitTokenFactor(N);
1049193323Sed  case ISD::MERGE_VALUES:       return visitMERGE_VALUES(N);
1050193323Sed  case ISD::ADD:                return visitADD(N);
1051193323Sed  case ISD::SUB:                return visitSUB(N);
1052193323Sed  case ISD::ADDC:               return visitADDC(N);
1053193323Sed  case ISD::ADDE:               return visitADDE(N);
1054193323Sed  case ISD::MUL:                return visitMUL(N);
1055193323Sed  case ISD::SDIV:               return visitSDIV(N);
1056193323Sed  case ISD::UDIV:               return visitUDIV(N);
1057193323Sed  case ISD::SREM:               return visitSREM(N);
1058193323Sed  case ISD::UREM:               return visitUREM(N);
1059193323Sed  case ISD::MULHU:              return visitMULHU(N);
1060193323Sed  case ISD::MULHS:              return visitMULHS(N);
1061193323Sed  case ISD::SMUL_LOHI:          return visitSMUL_LOHI(N);
1062193323Sed  case ISD::UMUL_LOHI:          return visitUMUL_LOHI(N);
1063223017Sdim  case ISD::SMULO:              return visitSMULO(N);
1064223017Sdim  case ISD::UMULO:              return visitUMULO(N);
1065193323Sed  case ISD::SDIVREM:            return visitSDIVREM(N);
1066193323Sed  case ISD::UDIVREM:            return visitUDIVREM(N);
1067193323Sed  case ISD::AND:                return visitAND(N);
1068193323Sed  case ISD::OR:                 return visitOR(N);
1069193323Sed  case ISD::XOR:                return visitXOR(N);
1070193323Sed  case ISD::SHL:                return visitSHL(N);
1071193323Sed  case ISD::SRA:                return visitSRA(N);
1072193323Sed  case ISD::SRL:                return visitSRL(N);
1073193323Sed  case ISD::CTLZ:               return visitCTLZ(N);
1074193323Sed  case ISD::CTTZ:               return visitCTTZ(N);
1075193323Sed  case ISD::CTPOP:              return visitCTPOP(N);
1076193323Sed  case ISD::SELECT:             return visitSELECT(N);
1077193323Sed  case ISD::SELECT_CC:          return visitSELECT_CC(N);
1078193323Sed  case ISD::SETCC:              return visitSETCC(N);
1079193323Sed  case ISD::SIGN_EXTEND:        return visitSIGN_EXTEND(N);
1080193323Sed  case ISD::ZERO_EXTEND:        return visitZERO_EXTEND(N);
1081193323Sed  case ISD::ANY_EXTEND:         return visitANY_EXTEND(N);
1082193323Sed  case ISD::SIGN_EXTEND_INREG:  return visitSIGN_EXTEND_INREG(N);
1083193323Sed  case ISD::TRUNCATE:           return visitTRUNCATE(N);
1084218893Sdim  case ISD::BITCAST:            return visitBITCAST(N);
1085193323Sed  case ISD::BUILD_PAIR:         return visitBUILD_PAIR(N);
1086193323Sed  case ISD::FADD:               return visitFADD(N);
1087193323Sed  case ISD::FSUB:               return visitFSUB(N);
1088193323Sed  case ISD::FMUL:               return visitFMUL(N);
1089193323Sed  case ISD::FDIV:               return visitFDIV(N);
1090193323Sed  case ISD::FREM:               return visitFREM(N);
1091193323Sed  case ISD::FCOPYSIGN:          return visitFCOPYSIGN(N);
1092193323Sed  case ISD::SINT_TO_FP:         return visitSINT_TO_FP(N);
1093193323Sed  case ISD::UINT_TO_FP:         return visitUINT_TO_FP(N);
1094193323Sed  case ISD::FP_TO_SINT:         return visitFP_TO_SINT(N);
1095193323Sed  case ISD::FP_TO_UINT:         return visitFP_TO_UINT(N);
1096193323Sed  case ISD::FP_ROUND:           return visitFP_ROUND(N);
1097193323Sed  case ISD::FP_ROUND_INREG:     return visitFP_ROUND_INREG(N);
1098193323Sed  case ISD::FP_EXTEND:          return visitFP_EXTEND(N);
1099193323Sed  case ISD::FNEG:               return visitFNEG(N);
1100193323Sed  case ISD::FABS:               return visitFABS(N);
1101193323Sed  case ISD::BRCOND:             return visitBRCOND(N);
1102193323Sed  case ISD::BR_CC:              return visitBR_CC(N);
1103193323Sed  case ISD::LOAD:               return visitLOAD(N);
1104193323Sed  case ISD::STORE:              return visitSTORE(N);
1105193323Sed  case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
1106193323Sed  case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1107193323Sed  case ISD::BUILD_VECTOR:       return visitBUILD_VECTOR(N);
1108193323Sed  case ISD::CONCAT_VECTORS:     return visitCONCAT_VECTORS(N);
1109226633Sdim  case ISD::EXTRACT_SUBVECTOR:  return visitEXTRACT_SUBVECTOR(N);
1110193323Sed  case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
1111210299Sed  case ISD::MEMBARRIER:         return visitMEMBARRIER(N);
1112193323Sed  }
1113193323Sed  return SDValue();
1114193323Sed}
1115193323Sed
1116193323SedSDValue DAGCombiner::combine(SDNode *N) {
1117193323Sed  SDValue RV = visit(N);
1118193323Sed
1119193323Sed  // If nothing happened, try a target-specific DAG combine.
1120193323Sed  if (RV.getNode() == 0) {
1121193323Sed    assert(N->getOpcode() != ISD::DELETED_NODE &&
1122193323Sed           "Node was deleted but visit returned NULL!");
1123193323Sed
1124193323Sed    if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1125193323Sed        TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1126193323Sed
1127193323Sed      // Expose the DAG combiner to the target combiner impls.
1128193323Sed      TargetLowering::DAGCombinerInfo
1129198090Srdivacky        DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1130193323Sed
1131193323Sed      RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1132193323Sed    }
1133193323Sed  }
1134193323Sed
1135207618Srdivacky  // If nothing happened still, try promoting the operation.
1136207618Srdivacky  if (RV.getNode() == 0) {
1137207618Srdivacky    switch (N->getOpcode()) {
1138207618Srdivacky    default: break;
1139207618Srdivacky    case ISD::ADD:
1140207618Srdivacky    case ISD::SUB:
1141207618Srdivacky    case ISD::MUL:
1142207618Srdivacky    case ISD::AND:
1143207618Srdivacky    case ISD::OR:
1144207618Srdivacky    case ISD::XOR:
1145207618Srdivacky      RV = PromoteIntBinOp(SDValue(N, 0));
1146207618Srdivacky      break;
1147207618Srdivacky    case ISD::SHL:
1148207618Srdivacky    case ISD::SRA:
1149207618Srdivacky    case ISD::SRL:
1150207618Srdivacky      RV = PromoteIntShiftOp(SDValue(N, 0));
1151207618Srdivacky      break;
1152207618Srdivacky    case ISD::SIGN_EXTEND:
1153207618Srdivacky    case ISD::ZERO_EXTEND:
1154207618Srdivacky    case ISD::ANY_EXTEND:
1155207618Srdivacky      RV = PromoteExtend(SDValue(N, 0));
1156207618Srdivacky      break;
1157207618Srdivacky    case ISD::LOAD:
1158207618Srdivacky      if (PromoteLoad(SDValue(N, 0)))
1159207618Srdivacky        RV = SDValue(N, 0);
1160207618Srdivacky      break;
1161207618Srdivacky    }
1162207618Srdivacky  }
1163207618Srdivacky
1164193323Sed  // If N is a commutative binary node, try commuting it to enable more
1165193323Sed  // sdisel CSE.
1166193323Sed  if (RV.getNode() == 0 &&
1167193323Sed      SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1168193323Sed      N->getNumValues() == 1) {
1169193323Sed    SDValue N0 = N->getOperand(0);
1170193323Sed    SDValue N1 = N->getOperand(1);
1171193323Sed
1172193323Sed    // Constant operands are canonicalized to RHS.
1173193323Sed    if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1174193323Sed      SDValue Ops[] = { N1, N0 };
1175193323Sed      SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1176193323Sed                                            Ops, 2);
1177193323Sed      if (CSENode)
1178193323Sed        return SDValue(CSENode, 0);
1179193323Sed    }
1180193323Sed  }
1181193323Sed
1182193323Sed  return RV;
1183193323Sed}
1184193323Sed
1185193323Sed/// getInputChainForNode - Given a node, return its input chain if it has one,
1186193323Sed/// otherwise return a null sd operand.
1187193323Sedstatic SDValue getInputChainForNode(SDNode *N) {
1188193323Sed  if (unsigned NumOps = N->getNumOperands()) {
1189193323Sed    if (N->getOperand(0).getValueType() == MVT::Other)
1190193323Sed      return N->getOperand(0);
1191193323Sed    else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1192193323Sed      return N->getOperand(NumOps-1);
1193193323Sed    for (unsigned i = 1; i < NumOps-1; ++i)
1194193323Sed      if (N->getOperand(i).getValueType() == MVT::Other)
1195193323Sed        return N->getOperand(i);
1196193323Sed  }
1197193323Sed  return SDValue();
1198193323Sed}
1199193323Sed
1200193323SedSDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1201193323Sed  // If N has two operands, where one has an input chain equal to the other,
1202193323Sed  // the 'other' chain is redundant.
1203193323Sed  if (N->getNumOperands() == 2) {
1204193323Sed    if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1205193323Sed      return N->getOperand(0);
1206193323Sed    if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1207193323Sed      return N->getOperand(1);
1208193323Sed  }
1209193323Sed
1210193323Sed  SmallVector<SDNode *, 8> TFs;     // List of token factors to visit.
1211193323Sed  SmallVector<SDValue, 8> Ops;    // Ops for replacing token factor.
1212193323Sed  SmallPtrSet<SDNode*, 16> SeenOps;
1213193323Sed  bool Changed = false;             // If we should replace this token factor.
1214193323Sed
1215193323Sed  // Start out with this token factor.
1216193323Sed  TFs.push_back(N);
1217193323Sed
1218193323Sed  // Iterate through token factors.  The TFs grows when new token factors are
1219193323Sed  // encountered.
1220193323Sed  for (unsigned i = 0; i < TFs.size(); ++i) {
1221193323Sed    SDNode *TF = TFs[i];
1222193323Sed
1223193323Sed    // Check each of the operands.
1224193323Sed    for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1225193323Sed      SDValue Op = TF->getOperand(i);
1226193323Sed
1227193323Sed      switch (Op.getOpcode()) {
1228193323Sed      case ISD::EntryToken:
1229193323Sed        // Entry tokens don't need to be added to the list. They are
1230193323Sed        // rededundant.
1231193323Sed        Changed = true;
1232193323Sed        break;
1233193323Sed
1234193323Sed      case ISD::TokenFactor:
1235198090Srdivacky        if (Op.hasOneUse() &&
1236193323Sed            std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1237193323Sed          // Queue up for processing.
1238193323Sed          TFs.push_back(Op.getNode());
1239193323Sed          // Clean up in case the token factor is removed.
1240193323Sed          AddToWorkList(Op.getNode());
1241193323Sed          Changed = true;
1242193323Sed          break;
1243193323Sed        }
1244193323Sed        // Fall thru
1245193323Sed
1246193323Sed      default:
1247193323Sed        // Only add if it isn't already in the list.
1248193323Sed        if (SeenOps.insert(Op.getNode()))
1249193323Sed          Ops.push_back(Op);
1250193323Sed        else
1251193323Sed          Changed = true;
1252193323Sed        break;
1253193323Sed      }
1254193323Sed    }
1255193323Sed  }
1256218893Sdim
1257193323Sed  SDValue Result;
1258193323Sed
1259193323Sed  // If we've change things around then replace token factor.
1260193323Sed  if (Changed) {
1261193323Sed    if (Ops.empty()) {
1262193323Sed      // The entry token is the only possible outcome.
1263193323Sed      Result = DAG.getEntryNode();
1264193323Sed    } else {
1265193323Sed      // New and improved token factor.
1266193323Sed      Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1267193323Sed                           MVT::Other, &Ops[0], Ops.size());
1268193323Sed    }
1269193323Sed
1270193323Sed    // Don't add users to work list.
1271193323Sed    return CombineTo(N, Result, false);
1272193323Sed  }
1273193323Sed
1274193323Sed  return Result;
1275193323Sed}
1276193323Sed
1277193323Sed/// MERGE_VALUES can always be eliminated.
1278193323SedSDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1279193323Sed  WorkListRemover DeadNodes(*this);
1280198090Srdivacky  // Replacing results may cause a different MERGE_VALUES to suddenly
1281198090Srdivacky  // be CSE'd with N, and carry its uses with it. Iterate until no
1282198090Srdivacky  // uses remain, to ensure that the node can be safely deleted.
1283198090Srdivacky  do {
1284198090Srdivacky    for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1285198090Srdivacky      DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1286198090Srdivacky                                    &DeadNodes);
1287198090Srdivacky  } while (!N->use_empty());
1288193323Sed  removeFromWorkList(N);
1289193323Sed  DAG.DeleteNode(N);
1290193323Sed  return SDValue(N, 0);   // Return N so it doesn't get rechecked!
1291193323Sed}
1292193323Sed
1293193323Sedstatic
1294193323SedSDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1295193323Sed                              SelectionDAG &DAG) {
1296198090Srdivacky  EVT VT = N0.getValueType();
1297193323Sed  SDValue N00 = N0.getOperand(0);
1298193323Sed  SDValue N01 = N0.getOperand(1);
1299193323Sed  ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1300193323Sed
1301193323Sed  if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1302193323Sed      isa<ConstantSDNode>(N00.getOperand(1))) {
1303193323Sed    // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1304193323Sed    N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1305193323Sed                     DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1306193323Sed                                 N00.getOperand(0), N01),
1307193323Sed                     DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1308193323Sed                                 N00.getOperand(1), N01));
1309193323Sed    return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1310193323Sed  }
1311193323Sed
1312193323Sed  return SDValue();
1313193323Sed}
1314193323Sed
1315193323SedSDValue DAGCombiner::visitADD(SDNode *N) {
1316193323Sed  SDValue N0 = N->getOperand(0);
1317193323Sed  SDValue N1 = N->getOperand(1);
1318193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1319193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1320198090Srdivacky  EVT VT = N0.getValueType();
1321193323Sed
1322193323Sed  // fold vector ops
1323193323Sed  if (VT.isVector()) {
1324193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
1325193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
1326193323Sed  }
1327193323Sed
1328193323Sed  // fold (add x, undef) -> undef
1329193323Sed  if (N0.getOpcode() == ISD::UNDEF)
1330193323Sed    return N0;
1331193323Sed  if (N1.getOpcode() == ISD::UNDEF)
1332193323Sed    return N1;
1333193323Sed  // fold (add c1, c2) -> c1+c2
1334193323Sed  if (N0C && N1C)
1335193323Sed    return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1336193323Sed  // canonicalize constant to RHS
1337193323Sed  if (N0C && !N1C)
1338193323Sed    return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1339193323Sed  // fold (add x, 0) -> x
1340193323Sed  if (N1C && N1C->isNullValue())
1341193323Sed    return N0;
1342193323Sed  // fold (add Sym, c) -> Sym+c
1343193323Sed  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1344193323Sed    if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1345193323Sed        GA->getOpcode() == ISD::GlobalAddress)
1346210299Sed      return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1347193323Sed                                  GA->getOffset() +
1348193323Sed                                    (uint64_t)N1C->getSExtValue());
1349193323Sed  // fold ((c1-A)+c2) -> (c1+c2)-A
1350193323Sed  if (N1C && N0.getOpcode() == ISD::SUB)
1351193323Sed    if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1352193323Sed      return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1353193323Sed                         DAG.getConstant(N1C->getAPIntValue()+
1354193323Sed                                         N0C->getAPIntValue(), VT),
1355193323Sed                         N0.getOperand(1));
1356193323Sed  // reassociate add
1357193323Sed  SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1358193323Sed  if (RADD.getNode() != 0)
1359193323Sed    return RADD;
1360193323Sed  // fold ((0-A) + B) -> B-A
1361193323Sed  if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1362193323Sed      cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1363193323Sed    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1364193323Sed  // fold (A + (0-B)) -> A-B
1365193323Sed  if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1366193323Sed      cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1367193323Sed    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1368193323Sed  // fold (A+(B-A)) -> B
1369193323Sed  if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1370193323Sed    return N1.getOperand(0);
1371193323Sed  // fold ((B-A)+A) -> B
1372193323Sed  if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1373193323Sed    return N0.getOperand(0);
1374193323Sed  // fold (A+(B-(A+C))) to (B-C)
1375193323Sed  if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1376193323Sed      N0 == N1.getOperand(1).getOperand(0))
1377193323Sed    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1378193323Sed                       N1.getOperand(1).getOperand(1));
1379193323Sed  // fold (A+(B-(C+A))) to (B-C)
1380193323Sed  if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1381193323Sed      N0 == N1.getOperand(1).getOperand(1))
1382193323Sed    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1383193323Sed                       N1.getOperand(1).getOperand(0));
1384193323Sed  // fold (A+((B-A)+or-C)) to (B+or-C)
1385193323Sed  if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1386193323Sed      N1.getOperand(0).getOpcode() == ISD::SUB &&
1387193323Sed      N0 == N1.getOperand(0).getOperand(1))
1388193323Sed    return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1389193323Sed                       N1.getOperand(0).getOperand(0), N1.getOperand(1));
1390193323Sed
1391193323Sed  // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1392193323Sed  if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1393193323Sed    SDValue N00 = N0.getOperand(0);
1394193323Sed    SDValue N01 = N0.getOperand(1);
1395193323Sed    SDValue N10 = N1.getOperand(0);
1396193323Sed    SDValue N11 = N1.getOperand(1);
1397193323Sed
1398193323Sed    if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1399193323Sed      return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1400193323Sed                         DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1401193323Sed                         DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1402193323Sed  }
1403193323Sed
1404193323Sed  if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1405193323Sed    return SDValue(N, 0);
1406193323Sed
1407193323Sed  // fold (a+b) -> (a|b) iff a and b share no bits.
1408193323Sed  if (VT.isInteger() && !VT.isVector()) {
1409193323Sed    APInt LHSZero, LHSOne;
1410193323Sed    APInt RHSZero, RHSOne;
1411204642Srdivacky    APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1412193323Sed    DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1413193323Sed
1414193323Sed    if (LHSZero.getBoolValue()) {
1415193323Sed      DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1416193323Sed
1417193323Sed      // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1418193323Sed      // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1419193323Sed      if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1420193323Sed          (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1421193323Sed        return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1422193323Sed    }
1423193323Sed  }
1424193323Sed
1425193323Sed  // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1426193323Sed  if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1427193323Sed    SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1428193323Sed    if (Result.getNode()) return Result;
1429193323Sed  }
1430193323Sed  if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1431193323Sed    SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1432193323Sed    if (Result.getNode()) return Result;
1433193323Sed  }
1434193323Sed
1435202878Srdivacky  // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1436202878Srdivacky  if (N1.getOpcode() == ISD::SHL &&
1437202878Srdivacky      N1.getOperand(0).getOpcode() == ISD::SUB)
1438202878Srdivacky    if (ConstantSDNode *C =
1439202878Srdivacky          dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1440202878Srdivacky      if (C->getAPIntValue() == 0)
1441202878Srdivacky        return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1442202878Srdivacky                           DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1443202878Srdivacky                                       N1.getOperand(0).getOperand(1),
1444202878Srdivacky                                       N1.getOperand(1)));
1445202878Srdivacky  if (N0.getOpcode() == ISD::SHL &&
1446202878Srdivacky      N0.getOperand(0).getOpcode() == ISD::SUB)
1447202878Srdivacky    if (ConstantSDNode *C =
1448202878Srdivacky          dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1449202878Srdivacky      if (C->getAPIntValue() == 0)
1450202878Srdivacky        return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1451202878Srdivacky                           DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1452202878Srdivacky                                       N0.getOperand(0).getOperand(1),
1453202878Srdivacky                                       N0.getOperand(1)));
1454202878Srdivacky
1455218893Sdim  if (N1.getOpcode() == ISD::AND) {
1456218893Sdim    SDValue AndOp0 = N1.getOperand(0);
1457218893Sdim    ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1458218893Sdim    unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1459218893Sdim    unsigned DestBits = VT.getScalarType().getSizeInBits();
1460218893Sdim
1461218893Sdim    // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1462218893Sdim    // and similar xforms where the inner op is either ~0 or 0.
1463218893Sdim    if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1464218893Sdim      DebugLoc DL = N->getDebugLoc();
1465218893Sdim      return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1466218893Sdim    }
1467218893Sdim  }
1468218893Sdim
1469218893Sdim  // add (sext i1), X -> sub X, (zext i1)
1470218893Sdim  if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1471218893Sdim      N0.getOperand(0).getValueType() == MVT::i1 &&
1472218893Sdim      !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1473218893Sdim    DebugLoc DL = N->getDebugLoc();
1474218893Sdim    SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1475218893Sdim    return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1476218893Sdim  }
1477218893Sdim
1478193323Sed  return SDValue();
1479193323Sed}
1480193323Sed
1481193323SedSDValue DAGCombiner::visitADDC(SDNode *N) {
1482193323Sed  SDValue N0 = N->getOperand(0);
1483193323Sed  SDValue N1 = N->getOperand(1);
1484193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1485193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1486198090Srdivacky  EVT VT = N0.getValueType();
1487193323Sed
1488193323Sed  // If the flag result is dead, turn this into an ADD.
1489193323Sed  if (N->hasNUsesOfValue(0, 1))
1490193323Sed    return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1491193323Sed                     DAG.getNode(ISD::CARRY_FALSE,
1492218893Sdim                                 N->getDebugLoc(), MVT::Glue));
1493193323Sed
1494193323Sed  // canonicalize constant to RHS.
1495193323Sed  if (N0C && !N1C)
1496193323Sed    return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1497193323Sed
1498193323Sed  // fold (addc x, 0) -> x + no carry out
1499193323Sed  if (N1C && N1C->isNullValue())
1500193323Sed    return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1501218893Sdim                                        N->getDebugLoc(), MVT::Glue));
1502193323Sed
1503193323Sed  // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1504193323Sed  APInt LHSZero, LHSOne;
1505193323Sed  APInt RHSZero, RHSOne;
1506204642Srdivacky  APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1507193323Sed  DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1508193323Sed
1509193323Sed  if (LHSZero.getBoolValue()) {
1510193323Sed    DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1511193323Sed
1512193323Sed    // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1513193323Sed    // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1514193323Sed    if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1515193323Sed        (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1516193323Sed      return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1517193323Sed                       DAG.getNode(ISD::CARRY_FALSE,
1518218893Sdim                                   N->getDebugLoc(), MVT::Glue));
1519193323Sed  }
1520193323Sed
1521193323Sed  return SDValue();
1522193323Sed}
1523193323Sed
1524193323SedSDValue DAGCombiner::visitADDE(SDNode *N) {
1525193323Sed  SDValue N0 = N->getOperand(0);
1526193323Sed  SDValue N1 = N->getOperand(1);
1527193323Sed  SDValue CarryIn = N->getOperand(2);
1528193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1529193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1530193323Sed
1531193323Sed  // canonicalize constant to RHS
1532193323Sed  if (N0C && !N1C)
1533193323Sed    return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1534193323Sed                       N1, N0, CarryIn);
1535193323Sed
1536193323Sed  // fold (adde x, y, false) -> (addc x, y)
1537193323Sed  if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1538193323Sed    return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1539193323Sed
1540193323Sed  return SDValue();
1541193323Sed}
1542193323Sed
1543218893Sdim// Since it may not be valid to emit a fold to zero for vector initializers
1544218893Sdim// check if we can before folding.
1545218893Sdimstatic SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1546219077Sdim                             SelectionDAG &DAG, bool LegalOperations) {
1547218893Sdim  if (!VT.isVector()) {
1548218893Sdim    return DAG.getConstant(0, VT);
1549223017Sdim  }
1550223017Sdim  if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1551218893Sdim    // Produce a vector of zeros.
1552218893Sdim    SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1553218893Sdim    std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1554218893Sdim    return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1555218893Sdim      &Ops[0], Ops.size());
1556218893Sdim  }
1557218893Sdim  return SDValue();
1558218893Sdim}
1559218893Sdim
1560193323SedSDValue DAGCombiner::visitSUB(SDNode *N) {
1561193323Sed  SDValue N0 = N->getOperand(0);
1562193323Sed  SDValue N1 = N->getOperand(1);
1563193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1564193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1565224145Sdim  ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1566224145Sdim    dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1567198090Srdivacky  EVT VT = N0.getValueType();
1568193323Sed
1569193323Sed  // fold vector ops
1570193323Sed  if (VT.isVector()) {
1571193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
1572193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
1573193323Sed  }
1574193323Sed
1575193323Sed  // fold (sub x, x) -> 0
1576218893Sdim  // FIXME: Refactor this and xor and other similar operations together.
1577193323Sed  if (N0 == N1)
1578218893Sdim    return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1579193323Sed  // fold (sub c1, c2) -> c1-c2
1580193323Sed  if (N0C && N1C)
1581193323Sed    return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1582193323Sed  // fold (sub x, c) -> (add x, -c)
1583193323Sed  if (N1C)
1584193323Sed    return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1585193323Sed                       DAG.getConstant(-N1C->getAPIntValue(), VT));
1586202878Srdivacky  // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1587202878Srdivacky  if (N0C && N0C->isAllOnesValue())
1588202878Srdivacky    return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1589218893Sdim  // fold A-(A-B) -> B
1590218893Sdim  if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1591218893Sdim    return N1.getOperand(1);
1592193323Sed  // fold (A+B)-A -> B
1593193323Sed  if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1594193323Sed    return N0.getOperand(1);
1595193323Sed  // fold (A+B)-B -> A
1596193323Sed  if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1597193323Sed    return N0.getOperand(0);
1598224145Sdim  // fold C2-(A+C1) -> (C2-C1)-A
1599224145Sdim  if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1600224145Sdim    SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1601224145Sdim    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1602224145Sdim		       N1.getOperand(0));
1603224145Sdim  }
1604193323Sed  // fold ((A+(B+or-C))-B) -> A+or-C
1605193323Sed  if (N0.getOpcode() == ISD::ADD &&
1606193323Sed      (N0.getOperand(1).getOpcode() == ISD::SUB ||
1607193323Sed       N0.getOperand(1).getOpcode() == ISD::ADD) &&
1608193323Sed      N0.getOperand(1).getOperand(0) == N1)
1609193323Sed    return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1610193323Sed                       N0.getOperand(0), N0.getOperand(1).getOperand(1));
1611193323Sed  // fold ((A+(C+B))-B) -> A+C
1612193323Sed  if (N0.getOpcode() == ISD::ADD &&
1613193323Sed      N0.getOperand(1).getOpcode() == ISD::ADD &&
1614193323Sed      N0.getOperand(1).getOperand(1) == N1)
1615193323Sed    return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1616193323Sed                       N0.getOperand(0), N0.getOperand(1).getOperand(0));
1617193323Sed  // fold ((A-(B-C))-C) -> A-B
1618193323Sed  if (N0.getOpcode() == ISD::SUB &&
1619193323Sed      N0.getOperand(1).getOpcode() == ISD::SUB &&
1620193323Sed      N0.getOperand(1).getOperand(1) == N1)
1621193323Sed    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1622193323Sed                       N0.getOperand(0), N0.getOperand(1).getOperand(0));
1623193323Sed
1624193323Sed  // If either operand of a sub is undef, the result is undef
1625193323Sed  if (N0.getOpcode() == ISD::UNDEF)
1626193323Sed    return N0;
1627193323Sed  if (N1.getOpcode() == ISD::UNDEF)
1628193323Sed    return N1;
1629193323Sed
1630193323Sed  // If the relocation model supports it, consider symbol offsets.
1631193323Sed  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1632193323Sed    if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1633193323Sed      // fold (sub Sym, c) -> Sym-c
1634193323Sed      if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1635210299Sed        return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1636193323Sed                                    GA->getOffset() -
1637193323Sed                                      (uint64_t)N1C->getSExtValue());
1638193323Sed      // fold (sub Sym+c1, Sym+c2) -> c1-c2
1639193323Sed      if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1640193323Sed        if (GA->getGlobal() == GB->getGlobal())
1641193323Sed          return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1642193323Sed                                 VT);
1643193323Sed    }
1644193323Sed
1645193323Sed  return SDValue();
1646193323Sed}
1647193323Sed
1648193323SedSDValue DAGCombiner::visitMUL(SDNode *N) {
1649193323Sed  SDValue N0 = N->getOperand(0);
1650193323Sed  SDValue N1 = N->getOperand(1);
1651193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1652193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1653198090Srdivacky  EVT VT = N0.getValueType();
1654193323Sed
1655193323Sed  // fold vector ops
1656193323Sed  if (VT.isVector()) {
1657193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
1658193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
1659193323Sed  }
1660193323Sed
1661193323Sed  // fold (mul x, undef) -> 0
1662193323Sed  if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1663193323Sed    return DAG.getConstant(0, VT);
1664193323Sed  // fold (mul c1, c2) -> c1*c2
1665193323Sed  if (N0C && N1C)
1666193323Sed    return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1667193323Sed  // canonicalize constant to RHS
1668193323Sed  if (N0C && !N1C)
1669193323Sed    return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1670193323Sed  // fold (mul x, 0) -> 0
1671193323Sed  if (N1C && N1C->isNullValue())
1672193323Sed    return N1;
1673193323Sed  // fold (mul x, -1) -> 0-x
1674193323Sed  if (N1C && N1C->isAllOnesValue())
1675193323Sed    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1676193323Sed                       DAG.getConstant(0, VT), N0);
1677193323Sed  // fold (mul x, (1 << c)) -> x << c
1678193323Sed  if (N1C && N1C->getAPIntValue().isPowerOf2())
1679193323Sed    return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1680193323Sed                       DAG.getConstant(N1C->getAPIntValue().logBase2(),
1681219077Sdim                                       getShiftAmountTy(N0.getValueType())));
1682193323Sed  // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1683193323Sed  if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1684193323Sed    unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1685193323Sed    // FIXME: If the input is something that is easily negated (e.g. a
1686193323Sed    // single-use add), we should put the negate there.
1687193323Sed    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1688193323Sed                       DAG.getConstant(0, VT),
1689193323Sed                       DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1690219077Sdim                            DAG.getConstant(Log2Val,
1691219077Sdim                                      getShiftAmountTy(N0.getValueType()))));
1692193323Sed  }
1693193323Sed  // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1694193323Sed  if (N1C && N0.getOpcode() == ISD::SHL &&
1695193323Sed      isa<ConstantSDNode>(N0.getOperand(1))) {
1696193323Sed    SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1697193323Sed                             N1, N0.getOperand(1));
1698193323Sed    AddToWorkList(C3.getNode());
1699193323Sed    return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1700193323Sed                       N0.getOperand(0), C3);
1701193323Sed  }
1702193323Sed
1703193323Sed  // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1704193323Sed  // use.
1705193323Sed  {
1706193323Sed    SDValue Sh(0,0), Y(0,0);
1707193323Sed    // Check for both (mul (shl X, C), Y)  and  (mul Y, (shl X, C)).
1708193323Sed    if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1709193323Sed        N0.getNode()->hasOneUse()) {
1710193323Sed      Sh = N0; Y = N1;
1711193323Sed    } else if (N1.getOpcode() == ISD::SHL &&
1712193323Sed               isa<ConstantSDNode>(N1.getOperand(1)) &&
1713193323Sed               N1.getNode()->hasOneUse()) {
1714193323Sed      Sh = N1; Y = N0;
1715193323Sed    }
1716193323Sed
1717193323Sed    if (Sh.getNode()) {
1718193323Sed      SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1719193323Sed                                Sh.getOperand(0), Y);
1720193323Sed      return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1721193323Sed                         Mul, Sh.getOperand(1));
1722193323Sed    }
1723193323Sed  }
1724193323Sed
1725193323Sed  // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1726193323Sed  if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1727193323Sed      isa<ConstantSDNode>(N0.getOperand(1)))
1728193323Sed    return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1729193323Sed                       DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1730193323Sed                                   N0.getOperand(0), N1),
1731193323Sed                       DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1732193323Sed                                   N0.getOperand(1), N1));
1733193323Sed
1734193323Sed  // reassociate mul
1735193323Sed  SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1736193323Sed  if (RMUL.getNode() != 0)
1737193323Sed    return RMUL;
1738193323Sed
1739193323Sed  return SDValue();
1740193323Sed}
1741193323Sed
1742193323SedSDValue DAGCombiner::visitSDIV(SDNode *N) {
1743193323Sed  SDValue N0 = N->getOperand(0);
1744193323Sed  SDValue N1 = N->getOperand(1);
1745193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1746193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1747198090Srdivacky  EVT VT = N->getValueType(0);
1748193323Sed
1749193323Sed  // fold vector ops
1750193323Sed  if (VT.isVector()) {
1751193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
1752193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
1753193323Sed  }
1754193323Sed
1755193323Sed  // fold (sdiv c1, c2) -> c1/c2
1756193323Sed  if (N0C && N1C && !N1C->isNullValue())
1757193323Sed    return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1758193323Sed  // fold (sdiv X, 1) -> X
1759193323Sed  if (N1C && N1C->getSExtValue() == 1LL)
1760193323Sed    return N0;
1761193323Sed  // fold (sdiv X, -1) -> 0-X
1762193323Sed  if (N1C && N1C->isAllOnesValue())
1763193323Sed    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1764193323Sed                       DAG.getConstant(0, VT), N0);
1765193323Sed  // If we know the sign bits of both operands are zero, strength reduce to a
1766193323Sed  // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
1767193323Sed  if (!VT.isVector()) {
1768193323Sed    if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1769193323Sed      return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1770193323Sed                         N0, N1);
1771193323Sed  }
1772193323Sed  // fold (sdiv X, pow2) -> simple ops after legalize
1773193323Sed  if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1774193323Sed      (isPowerOf2_64(N1C->getSExtValue()) ||
1775193323Sed       isPowerOf2_64(-N1C->getSExtValue()))) {
1776193323Sed    // If dividing by powers of two is cheap, then don't perform the following
1777193323Sed    // fold.
1778193323Sed    if (TLI.isPow2DivCheap())
1779193323Sed      return SDValue();
1780193323Sed
1781193323Sed    int64_t pow2 = N1C->getSExtValue();
1782193323Sed    int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1783193323Sed    unsigned lg2 = Log2_64(abs2);
1784193323Sed
1785193323Sed    // Splat the sign bit into the register
1786193323Sed    SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1787193323Sed                              DAG.getConstant(VT.getSizeInBits()-1,
1788219077Sdim                                       getShiftAmountTy(N0.getValueType())));
1789193323Sed    AddToWorkList(SGN.getNode());
1790193323Sed
1791193323Sed    // Add (N0 < 0) ? abs2 - 1 : 0;
1792193323Sed    SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1793193323Sed                              DAG.getConstant(VT.getSizeInBits() - lg2,
1794219077Sdim                                       getShiftAmountTy(SGN.getValueType())));
1795193323Sed    SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1796193323Sed    AddToWorkList(SRL.getNode());
1797193323Sed    AddToWorkList(ADD.getNode());    // Divide by pow2
1798193323Sed    SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1799219077Sdim                  DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1800193323Sed
1801193323Sed    // If we're dividing by a positive value, we're done.  Otherwise, we must
1802193323Sed    // negate the result.
1803193323Sed    if (pow2 > 0)
1804193323Sed      return SRA;
1805193323Sed
1806193323Sed    AddToWorkList(SRA.getNode());
1807193323Sed    return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1808193323Sed                       DAG.getConstant(0, VT), SRA);
1809193323Sed  }
1810193323Sed
1811193323Sed  // if integer divide is expensive and we satisfy the requirements, emit an
1812193323Sed  // alternate sequence.
1813193323Sed  if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1814193323Sed      !TLI.isIntDivCheap()) {
1815193323Sed    SDValue Op = BuildSDIV(N);
1816193323Sed    if (Op.getNode()) return Op;
1817193323Sed  }
1818193323Sed
1819193323Sed  // undef / X -> 0
1820193323Sed  if (N0.getOpcode() == ISD::UNDEF)
1821193323Sed    return DAG.getConstant(0, VT);
1822193323Sed  // X / undef -> undef
1823193323Sed  if (N1.getOpcode() == ISD::UNDEF)
1824193323Sed    return N1;
1825193323Sed
1826193323Sed  return SDValue();
1827193323Sed}
1828193323Sed
1829193323SedSDValue DAGCombiner::visitUDIV(SDNode *N) {
1830193323Sed  SDValue N0 = N->getOperand(0);
1831193323Sed  SDValue N1 = N->getOperand(1);
1832193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1833193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1834198090Srdivacky  EVT VT = N->getValueType(0);
1835193323Sed
1836193323Sed  // fold vector ops
1837193323Sed  if (VT.isVector()) {
1838193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
1839193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
1840193323Sed  }
1841193323Sed
1842193323Sed  // fold (udiv c1, c2) -> c1/c2
1843193323Sed  if (N0C && N1C && !N1C->isNullValue())
1844193323Sed    return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1845193323Sed  // fold (udiv x, (1 << c)) -> x >>u c
1846193323Sed  if (N1C && N1C->getAPIntValue().isPowerOf2())
1847193323Sed    return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1848193323Sed                       DAG.getConstant(N1C->getAPIntValue().logBase2(),
1849219077Sdim                                       getShiftAmountTy(N0.getValueType())));
1850193323Sed  // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1851193323Sed  if (N1.getOpcode() == ISD::SHL) {
1852193323Sed    if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1853193323Sed      if (SHC->getAPIntValue().isPowerOf2()) {
1854198090Srdivacky        EVT ADDVT = N1.getOperand(1).getValueType();
1855193323Sed        SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1856193323Sed                                  N1.getOperand(1),
1857193323Sed                                  DAG.getConstant(SHC->getAPIntValue()
1858193323Sed                                                                  .logBase2(),
1859193323Sed                                                  ADDVT));
1860193323Sed        AddToWorkList(Add.getNode());
1861193323Sed        return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1862193323Sed      }
1863193323Sed    }
1864193323Sed  }
1865193323Sed  // fold (udiv x, c) -> alternate
1866193323Sed  if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1867193323Sed    SDValue Op = BuildUDIV(N);
1868193323Sed    if (Op.getNode()) return Op;
1869193323Sed  }
1870193323Sed
1871193323Sed  // undef / X -> 0
1872193323Sed  if (N0.getOpcode() == ISD::UNDEF)
1873193323Sed    return DAG.getConstant(0, VT);
1874193323Sed  // X / undef -> undef
1875193323Sed  if (N1.getOpcode() == ISD::UNDEF)
1876193323Sed    return N1;
1877193323Sed
1878193323Sed  return SDValue();
1879193323Sed}
1880193323Sed
1881193323SedSDValue DAGCombiner::visitSREM(SDNode *N) {
1882193323Sed  SDValue N0 = N->getOperand(0);
1883193323Sed  SDValue N1 = N->getOperand(1);
1884193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1885193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1886198090Srdivacky  EVT VT = N->getValueType(0);
1887193323Sed
1888193323Sed  // fold (srem c1, c2) -> c1%c2
1889193323Sed  if (N0C && N1C && !N1C->isNullValue())
1890193323Sed    return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1891193323Sed  // If we know the sign bits of both operands are zero, strength reduce to a
1892193323Sed  // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1893193323Sed  if (!VT.isVector()) {
1894193323Sed    if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1895193323Sed      return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1896193323Sed  }
1897193323Sed
1898193323Sed  // If X/C can be simplified by the division-by-constant logic, lower
1899193323Sed  // X%C to the equivalent of X-X/C*C.
1900193323Sed  if (N1C && !N1C->isNullValue()) {
1901193323Sed    SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1902193323Sed    AddToWorkList(Div.getNode());
1903193323Sed    SDValue OptimizedDiv = combine(Div.getNode());
1904193323Sed    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1905193323Sed      SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1906193323Sed                                OptimizedDiv, N1);
1907193323Sed      SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1908193323Sed      AddToWorkList(Mul.getNode());
1909193323Sed      return Sub;
1910193323Sed    }
1911193323Sed  }
1912193323Sed
1913193323Sed  // undef % X -> 0
1914193323Sed  if (N0.getOpcode() == ISD::UNDEF)
1915193323Sed    return DAG.getConstant(0, VT);
1916193323Sed  // X % undef -> undef
1917193323Sed  if (N1.getOpcode() == ISD::UNDEF)
1918193323Sed    return N1;
1919193323Sed
1920193323Sed  return SDValue();
1921193323Sed}
1922193323Sed
1923193323SedSDValue DAGCombiner::visitUREM(SDNode *N) {
1924193323Sed  SDValue N0 = N->getOperand(0);
1925193323Sed  SDValue N1 = N->getOperand(1);
1926193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1927193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1928198090Srdivacky  EVT VT = N->getValueType(0);
1929193323Sed
1930193323Sed  // fold (urem c1, c2) -> c1%c2
1931193323Sed  if (N0C && N1C && !N1C->isNullValue())
1932193323Sed    return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1933193323Sed  // fold (urem x, pow2) -> (and x, pow2-1)
1934193323Sed  if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1935193323Sed    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1936193323Sed                       DAG.getConstant(N1C->getAPIntValue()-1,VT));
1937193323Sed  // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1938193323Sed  if (N1.getOpcode() == ISD::SHL) {
1939193323Sed    if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1940193323Sed      if (SHC->getAPIntValue().isPowerOf2()) {
1941193323Sed        SDValue Add =
1942193323Sed          DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1943193323Sed                 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1944193323Sed                                 VT));
1945193323Sed        AddToWorkList(Add.getNode());
1946193323Sed        return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1947193323Sed      }
1948193323Sed    }
1949193323Sed  }
1950193323Sed
1951193323Sed  // If X/C can be simplified by the division-by-constant logic, lower
1952193323Sed  // X%C to the equivalent of X-X/C*C.
1953193323Sed  if (N1C && !N1C->isNullValue()) {
1954193323Sed    SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1955193323Sed    AddToWorkList(Div.getNode());
1956193323Sed    SDValue OptimizedDiv = combine(Div.getNode());
1957193323Sed    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1958193323Sed      SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1959193323Sed                                OptimizedDiv, N1);
1960193323Sed      SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1961193323Sed      AddToWorkList(Mul.getNode());
1962193323Sed      return Sub;
1963193323Sed    }
1964193323Sed  }
1965193323Sed
1966193323Sed  // undef % X -> 0
1967193323Sed  if (N0.getOpcode() == ISD::UNDEF)
1968193323Sed    return DAG.getConstant(0, VT);
1969193323Sed  // X % undef -> undef
1970193323Sed  if (N1.getOpcode() == ISD::UNDEF)
1971193323Sed    return N1;
1972193323Sed
1973193323Sed  return SDValue();
1974193323Sed}
1975193323Sed
1976193323SedSDValue DAGCombiner::visitMULHS(SDNode *N) {
1977193323Sed  SDValue N0 = N->getOperand(0);
1978193323Sed  SDValue N1 = N->getOperand(1);
1979193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1980198090Srdivacky  EVT VT = N->getValueType(0);
1981218893Sdim  DebugLoc DL = N->getDebugLoc();
1982193323Sed
1983193323Sed  // fold (mulhs x, 0) -> 0
1984193323Sed  if (N1C && N1C->isNullValue())
1985193323Sed    return N1;
1986193323Sed  // fold (mulhs x, 1) -> (sra x, size(x)-1)
1987193323Sed  if (N1C && N1C->getAPIntValue() == 1)
1988193323Sed    return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1989193323Sed                       DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1990219077Sdim                                       getShiftAmountTy(N0.getValueType())));
1991193323Sed  // fold (mulhs x, undef) -> 0
1992193323Sed  if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1993193323Sed    return DAG.getConstant(0, VT);
1994193323Sed
1995218893Sdim  // If the type twice as wide is legal, transform the mulhs to a wider multiply
1996218893Sdim  // plus a shift.
1997218893Sdim  if (VT.isSimple() && !VT.isVector()) {
1998218893Sdim    MVT Simple = VT.getSimpleVT();
1999218893Sdim    unsigned SimpleSize = Simple.getSizeInBits();
2000218893Sdim    EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2001218893Sdim    if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2002218893Sdim      N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2003218893Sdim      N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2004218893Sdim      N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2005218893Sdim      N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2006219077Sdim            DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2007218893Sdim      return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2008218893Sdim    }
2009218893Sdim  }
2010219077Sdim
2011193323Sed  return SDValue();
2012193323Sed}
2013193323Sed
2014193323SedSDValue DAGCombiner::visitMULHU(SDNode *N) {
2015193323Sed  SDValue N0 = N->getOperand(0);
2016193323Sed  SDValue N1 = N->getOperand(1);
2017193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2018198090Srdivacky  EVT VT = N->getValueType(0);
2019218893Sdim  DebugLoc DL = N->getDebugLoc();
2020193323Sed
2021193323Sed  // fold (mulhu x, 0) -> 0
2022193323Sed  if (N1C && N1C->isNullValue())
2023193323Sed    return N1;
2024193323Sed  // fold (mulhu x, 1) -> 0
2025193323Sed  if (N1C && N1C->getAPIntValue() == 1)
2026193323Sed    return DAG.getConstant(0, N0.getValueType());
2027193323Sed  // fold (mulhu x, undef) -> 0
2028193323Sed  if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2029193323Sed    return DAG.getConstant(0, VT);
2030193323Sed
2031218893Sdim  // If the type twice as wide is legal, transform the mulhu to a wider multiply
2032218893Sdim  // plus a shift.
2033218893Sdim  if (VT.isSimple() && !VT.isVector()) {
2034218893Sdim    MVT Simple = VT.getSimpleVT();
2035218893Sdim    unsigned SimpleSize = Simple.getSizeInBits();
2036218893Sdim    EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2037218893Sdim    if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2038218893Sdim      N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2039218893Sdim      N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2040218893Sdim      N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2041218893Sdim      N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2042219077Sdim            DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2043218893Sdim      return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2044218893Sdim    }
2045218893Sdim  }
2046219077Sdim
2047193323Sed  return SDValue();
2048193323Sed}
2049193323Sed
2050193323Sed/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2051193323Sed/// compute two values. LoOp and HiOp give the opcodes for the two computations
2052193323Sed/// that are being performed. Return true if a simplification was made.
2053193323Sed///
2054193323SedSDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2055193323Sed                                                unsigned HiOp) {
2056193323Sed  // If the high half is not needed, just compute the low half.
2057193323Sed  bool HiExists = N->hasAnyUseOfValue(1);
2058193323Sed  if (!HiExists &&
2059193323Sed      (!LegalOperations ||
2060193323Sed       TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2061193323Sed    SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2062193323Sed                              N->op_begin(), N->getNumOperands());
2063193323Sed    return CombineTo(N, Res, Res);
2064193323Sed  }
2065193323Sed
2066193323Sed  // If the low half is not needed, just compute the high half.
2067193323Sed  bool LoExists = N->hasAnyUseOfValue(0);
2068193323Sed  if (!LoExists &&
2069193323Sed      (!LegalOperations ||
2070193323Sed       TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2071193323Sed    SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2072193323Sed                              N->op_begin(), N->getNumOperands());
2073193323Sed    return CombineTo(N, Res, Res);
2074193323Sed  }
2075193323Sed
2076193323Sed  // If both halves are used, return as it is.
2077193323Sed  if (LoExists && HiExists)
2078193323Sed    return SDValue();
2079193323Sed
2080193323Sed  // If the two computed results can be simplified separately, separate them.
2081193323Sed  if (LoExists) {
2082193323Sed    SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2083193323Sed                             N->op_begin(), N->getNumOperands());
2084193323Sed    AddToWorkList(Lo.getNode());
2085193323Sed    SDValue LoOpt = combine(Lo.getNode());
2086193323Sed    if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2087193323Sed        (!LegalOperations ||
2088193323Sed         TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2089193323Sed      return CombineTo(N, LoOpt, LoOpt);
2090193323Sed  }
2091193323Sed
2092193323Sed  if (HiExists) {
2093193323Sed    SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2094193323Sed                             N->op_begin(), N->getNumOperands());
2095193323Sed    AddToWorkList(Hi.getNode());
2096193323Sed    SDValue HiOpt = combine(Hi.getNode());
2097193323Sed    if (HiOpt.getNode() && HiOpt != Hi &&
2098193323Sed        (!LegalOperations ||
2099193323Sed         TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2100193323Sed      return CombineTo(N, HiOpt, HiOpt);
2101193323Sed  }
2102193323Sed
2103193323Sed  return SDValue();
2104193323Sed}
2105193323Sed
2106193323SedSDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2107193323Sed  SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2108193323Sed  if (Res.getNode()) return Res;
2109193323Sed
2110218893Sdim  EVT VT = N->getValueType(0);
2111218893Sdim  DebugLoc DL = N->getDebugLoc();
2112218893Sdim
2113218893Sdim  // If the type twice as wide is legal, transform the mulhu to a wider multiply
2114218893Sdim  // plus a shift.
2115218893Sdim  if (VT.isSimple() && !VT.isVector()) {
2116218893Sdim    MVT Simple = VT.getSimpleVT();
2117218893Sdim    unsigned SimpleSize = Simple.getSizeInBits();
2118218893Sdim    EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2119218893Sdim    if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2120218893Sdim      SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2121218893Sdim      SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2122218893Sdim      Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2123218893Sdim      // Compute the high part as N1.
2124218893Sdim      Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2125219077Sdim            DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2126218893Sdim      Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2127218893Sdim      // Compute the low part as N0.
2128218893Sdim      Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2129218893Sdim      return CombineTo(N, Lo, Hi);
2130218893Sdim    }
2131218893Sdim  }
2132219077Sdim
2133193323Sed  return SDValue();
2134193323Sed}
2135193323Sed
2136193323SedSDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2137193323Sed  SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2138193323Sed  if (Res.getNode()) return Res;
2139193323Sed
2140218893Sdim  EVT VT = N->getValueType(0);
2141218893Sdim  DebugLoc DL = N->getDebugLoc();
2142219077Sdim
2143218893Sdim  // If the type twice as wide is legal, transform the mulhu to a wider multiply
2144218893Sdim  // plus a shift.
2145218893Sdim  if (VT.isSimple() && !VT.isVector()) {
2146218893Sdim    MVT Simple = VT.getSimpleVT();
2147218893Sdim    unsigned SimpleSize = Simple.getSizeInBits();
2148218893Sdim    EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2149218893Sdim    if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2150218893Sdim      SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2151218893Sdim      SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2152218893Sdim      Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2153218893Sdim      // Compute the high part as N1.
2154218893Sdim      Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2155219077Sdim            DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2156218893Sdim      Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2157218893Sdim      // Compute the low part as N0.
2158218893Sdim      Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2159218893Sdim      return CombineTo(N, Lo, Hi);
2160218893Sdim    }
2161218893Sdim  }
2162219077Sdim
2163193323Sed  return SDValue();
2164193323Sed}
2165193323Sed
2166223017SdimSDValue DAGCombiner::visitSMULO(SDNode *N) {
2167223017Sdim  // (smulo x, 2) -> (saddo x, x)
2168223017Sdim  if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2169223017Sdim    if (C2->getAPIntValue() == 2)
2170223017Sdim      return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2171223017Sdim                         N->getOperand(0), N->getOperand(0));
2172223017Sdim
2173223017Sdim  return SDValue();
2174223017Sdim}
2175223017Sdim
2176223017SdimSDValue DAGCombiner::visitUMULO(SDNode *N) {
2177223017Sdim  // (umulo x, 2) -> (uaddo x, x)
2178223017Sdim  if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2179223017Sdim    if (C2->getAPIntValue() == 2)
2180223017Sdim      return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2181223017Sdim                         N->getOperand(0), N->getOperand(0));
2182223017Sdim
2183223017Sdim  return SDValue();
2184223017Sdim}
2185223017Sdim
2186193323SedSDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2187193323Sed  SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2188193323Sed  if (Res.getNode()) return Res;
2189193323Sed
2190193323Sed  return SDValue();
2191193323Sed}
2192193323Sed
2193193323SedSDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2194193323Sed  SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2195193323Sed  if (Res.getNode()) return Res;
2196193323Sed
2197193323Sed  return SDValue();
2198193323Sed}
2199193323Sed
2200193323Sed/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2201193323Sed/// two operands of the same opcode, try to simplify it.
2202193323SedSDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2203193323Sed  SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2204198090Srdivacky  EVT VT = N0.getValueType();
2205193323Sed  assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2206193323Sed
2207202375Srdivacky  // Bail early if none of these transforms apply.
2208202375Srdivacky  if (N0.getNode()->getNumOperands() == 0) return SDValue();
2209202375Srdivacky
2210193323Sed  // For each of OP in AND/OR/XOR:
2211193323Sed  // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2212193323Sed  // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2213193323Sed  // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2214210299Sed  // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2215200581Srdivacky  //
2216200581Srdivacky  // do not sink logical op inside of a vector extend, since it may combine
2217200581Srdivacky  // into a vsetcc.
2218202375Srdivacky  EVT Op0VT = N0.getOperand(0).getValueType();
2219202375Srdivacky  if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2220193323Sed       N0.getOpcode() == ISD::SIGN_EXTEND ||
2221207618Srdivacky       // Avoid infinite looping with PromoteIntBinOp.
2222207618Srdivacky       (N0.getOpcode() == ISD::ANY_EXTEND &&
2223207618Srdivacky        (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2224210299Sed       (N0.getOpcode() == ISD::TRUNCATE &&
2225210299Sed        (!TLI.isZExtFree(VT, Op0VT) ||
2226210299Sed         !TLI.isTruncateFree(Op0VT, VT)) &&
2227210299Sed        TLI.isTypeLegal(Op0VT))) &&
2228200581Srdivacky      !VT.isVector() &&
2229202375Srdivacky      Op0VT == N1.getOperand(0).getValueType() &&
2230202375Srdivacky      (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2231193323Sed    SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2232193323Sed                                 N0.getOperand(0).getValueType(),
2233193323Sed                                 N0.getOperand(0), N1.getOperand(0));
2234193323Sed    AddToWorkList(ORNode.getNode());
2235193323Sed    return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2236193323Sed  }
2237193323Sed
2238193323Sed  // For each of OP in SHL/SRL/SRA/AND...
2239193323Sed  //   fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2240193323Sed  //   fold (or  (OP x, z), (OP y, z)) -> (OP (or  x, y), z)
2241193323Sed  //   fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2242193323Sed  if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2243193323Sed       N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2244193323Sed      N0.getOperand(1) == N1.getOperand(1)) {
2245193323Sed    SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2246193323Sed                                 N0.getOperand(0).getValueType(),
2247193323Sed                                 N0.getOperand(0), N1.getOperand(0));
2248193323Sed    AddToWorkList(ORNode.getNode());
2249193323Sed    return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2250193323Sed                       ORNode, N0.getOperand(1));
2251193323Sed  }
2252193323Sed
2253193323Sed  return SDValue();
2254193323Sed}
2255193323Sed
2256193323SedSDValue DAGCombiner::visitAND(SDNode *N) {
2257193323Sed  SDValue N0 = N->getOperand(0);
2258193323Sed  SDValue N1 = N->getOperand(1);
2259193323Sed  SDValue LL, LR, RL, RR, CC0, CC1;
2260193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2261193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2262198090Srdivacky  EVT VT = N1.getValueType();
2263204792Srdivacky  unsigned BitWidth = VT.getScalarType().getSizeInBits();
2264193323Sed
2265193323Sed  // fold vector ops
2266193323Sed  if (VT.isVector()) {
2267193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
2268193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
2269193323Sed  }
2270193323Sed
2271193323Sed  // fold (and x, undef) -> 0
2272193323Sed  if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2273193323Sed    return DAG.getConstant(0, VT);
2274193323Sed  // fold (and c1, c2) -> c1&c2
2275193323Sed  if (N0C && N1C)
2276193323Sed    return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2277193323Sed  // canonicalize constant to RHS
2278193323Sed  if (N0C && !N1C)
2279193323Sed    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2280193323Sed  // fold (and x, -1) -> x
2281193323Sed  if (N1C && N1C->isAllOnesValue())
2282193323Sed    return N0;
2283193323Sed  // if (and x, c) is known to be zero, return 0
2284193323Sed  if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2285193323Sed                                   APInt::getAllOnesValue(BitWidth)))
2286193323Sed    return DAG.getConstant(0, VT);
2287193323Sed  // reassociate and
2288193323Sed  SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2289193323Sed  if (RAND.getNode() != 0)
2290193323Sed    return RAND;
2291204642Srdivacky  // fold (and (or x, C), D) -> D if (C & D) == D
2292193323Sed  if (N1C && N0.getOpcode() == ISD::OR)
2293193323Sed    if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2294193323Sed      if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2295193323Sed        return N1;
2296193323Sed  // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2297193323Sed  if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2298193323Sed    SDValue N0Op0 = N0.getOperand(0);
2299193323Sed    APInt Mask = ~N1C->getAPIntValue();
2300218893Sdim    Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2301193323Sed    if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2302193323Sed      SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2303193323Sed                                 N0.getValueType(), N0Op0);
2304193323Sed
2305193323Sed      // Replace uses of the AND with uses of the Zero extend node.
2306193323Sed      CombineTo(N, Zext);
2307193323Sed
2308193323Sed      // We actually want to replace all uses of the any_extend with the
2309193323Sed      // zero_extend, to avoid duplicating things.  This will later cause this
2310193323Sed      // AND to be folded.
2311193323Sed      CombineTo(N0.getNode(), Zext);
2312193323Sed      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
2313193323Sed    }
2314193323Sed  }
2315193323Sed  // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2316193323Sed  if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2317193323Sed    ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2318193323Sed    ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2319193323Sed
2320193323Sed    if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2321193323Sed        LL.getValueType().isInteger()) {
2322193323Sed      // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2323193323Sed      if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2324193323Sed        SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2325193323Sed                                     LR.getValueType(), LL, RL);
2326193323Sed        AddToWorkList(ORNode.getNode());
2327193323Sed        return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2328193323Sed      }
2329193323Sed      // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2330193323Sed      if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2331193323Sed        SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2332193323Sed                                      LR.getValueType(), LL, RL);
2333193323Sed        AddToWorkList(ANDNode.getNode());
2334193323Sed        return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2335193323Sed      }
2336193323Sed      // fold (and (setgt X,  -1), (setgt Y,  -1)) -> (setgt (or X, Y), -1)
2337193323Sed      if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2338193323Sed        SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2339193323Sed                                     LR.getValueType(), LL, RL);
2340193323Sed        AddToWorkList(ORNode.getNode());
2341193323Sed        return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2342193323Sed      }
2343193323Sed    }
2344193323Sed    // canonicalize equivalent to ll == rl
2345193323Sed    if (LL == RR && LR == RL) {
2346193323Sed      Op1 = ISD::getSetCCSwappedOperands(Op1);
2347193323Sed      std::swap(RL, RR);
2348193323Sed    }
2349193323Sed    if (LL == RL && LR == RR) {
2350193323Sed      bool isInteger = LL.getValueType().isInteger();
2351193323Sed      ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2352193323Sed      if (Result != ISD::SETCC_INVALID &&
2353193323Sed          (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2354193323Sed        return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2355193323Sed                            LL, LR, Result);
2356193323Sed    }
2357193323Sed  }
2358193323Sed
2359193323Sed  // Simplify: (and (op x...), (op y...))  -> (op (and x, y))
2360193323Sed  if (N0.getOpcode() == N1.getOpcode()) {
2361193323Sed    SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2362193323Sed    if (Tmp.getNode()) return Tmp;
2363193323Sed  }
2364193323Sed
2365193323Sed  // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2366193323Sed  // fold (and (sra)) -> (and (srl)) when possible.
2367193323Sed  if (!VT.isVector() &&
2368193323Sed      SimplifyDemandedBits(SDValue(N, 0)))
2369193323Sed    return SDValue(N, 0);
2370202375Srdivacky
2371193323Sed  // fold (zext_inreg (extload x)) -> (zextload x)
2372193323Sed  if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2373193323Sed    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2374198090Srdivacky    EVT MemVT = LN0->getMemoryVT();
2375193323Sed    // If we zero all the possible extended bits, then we can turn this into
2376193323Sed    // a zextload if we are running before legalize or the operation is legal.
2377204792Srdivacky    unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2378193323Sed    if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2379204792Srdivacky                           BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2380193323Sed        ((!LegalOperations && !LN0->isVolatile()) ||
2381198090Srdivacky         TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2382218893Sdim      SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2383193323Sed                                       LN0->getChain(), LN0->getBasePtr(),
2384218893Sdim                                       LN0->getPointerInfo(), MemVT,
2385203954Srdivacky                                       LN0->isVolatile(), LN0->isNonTemporal(),
2386203954Srdivacky                                       LN0->getAlignment());
2387193323Sed      AddToWorkList(N);
2388193323Sed      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2389193323Sed      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
2390193323Sed    }
2391193323Sed  }
2392193323Sed  // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2393193323Sed  if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2394193323Sed      N0.hasOneUse()) {
2395193323Sed    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2396198090Srdivacky    EVT MemVT = LN0->getMemoryVT();
2397193323Sed    // If we zero all the possible extended bits, then we can turn this into
2398193323Sed    // a zextload if we are running before legalize or the operation is legal.
2399204792Srdivacky    unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2400193323Sed    if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2401204792Srdivacky                           BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2402193323Sed        ((!LegalOperations && !LN0->isVolatile()) ||
2403198090Srdivacky         TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2404218893Sdim      SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2405193323Sed                                       LN0->getChain(),
2406218893Sdim                                       LN0->getBasePtr(), LN0->getPointerInfo(),
2407218893Sdim                                       MemVT,
2408203954Srdivacky                                       LN0->isVolatile(), LN0->isNonTemporal(),
2409203954Srdivacky                                       LN0->getAlignment());
2410193323Sed      AddToWorkList(N);
2411193323Sed      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2412193323Sed      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
2413193323Sed    }
2414193323Sed  }
2415193323Sed
2416193323Sed  // fold (and (load x), 255) -> (zextload x, i8)
2417193323Sed  // fold (and (extload x, i16), 255) -> (zextload x, i8)
2418202375Srdivacky  // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2419202375Srdivacky  if (N1C && (N0.getOpcode() == ISD::LOAD ||
2420202375Srdivacky              (N0.getOpcode() == ISD::ANY_EXTEND &&
2421202375Srdivacky               N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2422202375Srdivacky    bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2423202375Srdivacky    LoadSDNode *LN0 = HasAnyExt
2424202375Srdivacky      ? cast<LoadSDNode>(N0.getOperand(0))
2425202375Srdivacky      : cast<LoadSDNode>(N0);
2426193323Sed    if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2427202375Srdivacky        LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2428193323Sed      uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2429202375Srdivacky      if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2430202375Srdivacky        EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2431202375Srdivacky        EVT LoadedVT = LN0->getMemoryVT();
2432193323Sed
2433202375Srdivacky        if (ExtVT == LoadedVT &&
2434202375Srdivacky            (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2435202375Srdivacky          EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2436218893Sdim
2437218893Sdim          SDValue NewLoad =
2438218893Sdim            DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2439202375Srdivacky                           LN0->getChain(), LN0->getBasePtr(),
2440218893Sdim                           LN0->getPointerInfo(),
2441203954Srdivacky                           ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2442203954Srdivacky                           LN0->getAlignment());
2443202375Srdivacky          AddToWorkList(N);
2444202375Srdivacky          CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2445202375Srdivacky          return SDValue(N, 0);   // Return N so it doesn't get rechecked!
2446202375Srdivacky        }
2447218893Sdim
2448202375Srdivacky        // Do not change the width of a volatile load.
2449202375Srdivacky        // Do not generate loads of non-round integer types since these can
2450202375Srdivacky        // be expensive (and would be wrong if the type is not byte sized).
2451202375Srdivacky        if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2452202375Srdivacky            (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2453202375Srdivacky          EVT PtrType = LN0->getOperand(1).getValueType();
2454193323Sed
2455202375Srdivacky          unsigned Alignment = LN0->getAlignment();
2456202375Srdivacky          SDValue NewPtr = LN0->getBasePtr();
2457193323Sed
2458202375Srdivacky          // For big endian targets, we need to add an offset to the pointer
2459202375Srdivacky          // to load the correct bytes.  For little endian systems, we merely
2460202375Srdivacky          // need to read fewer bytes from the same pointer.
2461202375Srdivacky          if (TLI.isBigEndian()) {
2462202375Srdivacky            unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2463202375Srdivacky            unsigned EVTStoreBytes = ExtVT.getStoreSize();
2464202375Srdivacky            unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2465202375Srdivacky            NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2466202375Srdivacky                                 NewPtr, DAG.getConstant(PtrOff, PtrType));
2467202375Srdivacky            Alignment = MinAlign(Alignment, PtrOff);
2468202375Srdivacky          }
2469193323Sed
2470202375Srdivacky          AddToWorkList(NewPtr.getNode());
2471218893Sdim
2472202375Srdivacky          EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2473202375Srdivacky          SDValue Load =
2474218893Sdim            DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2475202375Srdivacky                           LN0->getChain(), NewPtr,
2476218893Sdim                           LN0->getPointerInfo(),
2477203954Srdivacky                           ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2478203954Srdivacky                           Alignment);
2479202375Srdivacky          AddToWorkList(N);
2480202375Srdivacky          CombineTo(LN0, Load, Load.getValue(1));
2481202375Srdivacky          return SDValue(N, 0);   // Return N so it doesn't get rechecked!
2482193323Sed        }
2483193323Sed      }
2484193323Sed    }
2485193323Sed  }
2486193323Sed
2487193323Sed  return SDValue();
2488193323Sed}
2489193323Sed
2490224145Sdim/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2491224145Sdim///
2492224145SdimSDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2493224145Sdim                                        bool DemandHighBits) {
2494224145Sdim  if (!LegalOperations)
2495224145Sdim    return SDValue();
2496224145Sdim
2497224145Sdim  EVT VT = N->getValueType(0);
2498224145Sdim  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2499224145Sdim    return SDValue();
2500224145Sdim  if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2501224145Sdim    return SDValue();
2502224145Sdim
2503224145Sdim  // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2504224145Sdim  bool LookPassAnd0 = false;
2505224145Sdim  bool LookPassAnd1 = false;
2506224145Sdim  if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2507224145Sdim      std::swap(N0, N1);
2508224145Sdim  if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2509224145Sdim      std::swap(N0, N1);
2510224145Sdim  if (N0.getOpcode() == ISD::AND) {
2511224145Sdim    if (!N0.getNode()->hasOneUse())
2512224145Sdim      return SDValue();
2513224145Sdim    ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2514224145Sdim    if (!N01C || N01C->getZExtValue() != 0xFF00)
2515224145Sdim      return SDValue();
2516224145Sdim    N0 = N0.getOperand(0);
2517224145Sdim    LookPassAnd0 = true;
2518224145Sdim  }
2519224145Sdim
2520224145Sdim  if (N1.getOpcode() == ISD::AND) {
2521224145Sdim    if (!N1.getNode()->hasOneUse())
2522224145Sdim      return SDValue();
2523224145Sdim    ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2524224145Sdim    if (!N11C || N11C->getZExtValue() != 0xFF)
2525224145Sdim      return SDValue();
2526224145Sdim    N1 = N1.getOperand(0);
2527224145Sdim    LookPassAnd1 = true;
2528224145Sdim  }
2529224145Sdim
2530224145Sdim  if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2531224145Sdim    std::swap(N0, N1);
2532224145Sdim  if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2533224145Sdim    return SDValue();
2534224145Sdim  if (!N0.getNode()->hasOneUse() ||
2535224145Sdim      !N1.getNode()->hasOneUse())
2536224145Sdim    return SDValue();
2537224145Sdim
2538224145Sdim  ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2539224145Sdim  ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2540224145Sdim  if (!N01C || !N11C)
2541224145Sdim    return SDValue();
2542224145Sdim  if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2543224145Sdim    return SDValue();
2544224145Sdim
2545224145Sdim  // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2546224145Sdim  SDValue N00 = N0->getOperand(0);
2547224145Sdim  if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2548224145Sdim    if (!N00.getNode()->hasOneUse())
2549224145Sdim      return SDValue();
2550224145Sdim    ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2551224145Sdim    if (!N001C || N001C->getZExtValue() != 0xFF)
2552224145Sdim      return SDValue();
2553224145Sdim    N00 = N00.getOperand(0);
2554224145Sdim    LookPassAnd0 = true;
2555224145Sdim  }
2556224145Sdim
2557224145Sdim  SDValue N10 = N1->getOperand(0);
2558224145Sdim  if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2559224145Sdim    if (!N10.getNode()->hasOneUse())
2560224145Sdim      return SDValue();
2561224145Sdim    ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2562224145Sdim    if (!N101C || N101C->getZExtValue() != 0xFF00)
2563224145Sdim      return SDValue();
2564224145Sdim    N10 = N10.getOperand(0);
2565224145Sdim    LookPassAnd1 = true;
2566224145Sdim  }
2567224145Sdim
2568224145Sdim  if (N00 != N10)
2569224145Sdim    return SDValue();
2570224145Sdim
2571224145Sdim  // Make sure everything beyond the low halfword is zero since the SRL 16
2572224145Sdim  // will clear the top bits.
2573224145Sdim  unsigned OpSizeInBits = VT.getSizeInBits();
2574224145Sdim  if (DemandHighBits && OpSizeInBits > 16 &&
2575224145Sdim      (!LookPassAnd0 || !LookPassAnd1) &&
2576224145Sdim      !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2577224145Sdim    return SDValue();
2578224145Sdim
2579224145Sdim  SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2580224145Sdim  if (OpSizeInBits > 16)
2581224145Sdim    Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2582224145Sdim                      DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2583224145Sdim  return Res;
2584224145Sdim}
2585224145Sdim
2586224145Sdim/// isBSwapHWordElement - Return true if the specified node is an element
2587224145Sdim/// that makes up a 32-bit packed halfword byteswap. i.e.
2588224145Sdim/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2589224145Sdimstatic bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2590224145Sdim  if (!N.getNode()->hasOneUse())
2591224145Sdim    return false;
2592224145Sdim
2593224145Sdim  unsigned Opc = N.getOpcode();
2594224145Sdim  if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2595224145Sdim    return false;
2596224145Sdim
2597224145Sdim  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2598224145Sdim  if (!N1C)
2599224145Sdim    return false;
2600224145Sdim
2601224145Sdim  unsigned Num;
2602224145Sdim  switch (N1C->getZExtValue()) {
2603224145Sdim  default:
2604224145Sdim    return false;
2605224145Sdim  case 0xFF:       Num = 0; break;
2606224145Sdim  case 0xFF00:     Num = 1; break;
2607224145Sdim  case 0xFF0000:   Num = 2; break;
2608224145Sdim  case 0xFF000000: Num = 3; break;
2609224145Sdim  }
2610224145Sdim
2611224145Sdim  // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2612224145Sdim  SDValue N0 = N.getOperand(0);
2613224145Sdim  if (Opc == ISD::AND) {
2614224145Sdim    if (Num == 0 || Num == 2) {
2615224145Sdim      // (x >> 8) & 0xff
2616224145Sdim      // (x >> 8) & 0xff0000
2617224145Sdim      if (N0.getOpcode() != ISD::SRL)
2618224145Sdim        return false;
2619224145Sdim      ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2620224145Sdim      if (!C || C->getZExtValue() != 8)
2621224145Sdim        return false;
2622224145Sdim    } else {
2623224145Sdim      // (x << 8) & 0xff00
2624224145Sdim      // (x << 8) & 0xff000000
2625224145Sdim      if (N0.getOpcode() != ISD::SHL)
2626224145Sdim        return false;
2627224145Sdim      ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2628224145Sdim      if (!C || C->getZExtValue() != 8)
2629224145Sdim        return false;
2630224145Sdim    }
2631224145Sdim  } else if (Opc == ISD::SHL) {
2632224145Sdim    // (x & 0xff) << 8
2633224145Sdim    // (x & 0xff0000) << 8
2634224145Sdim    if (Num != 0 && Num != 2)
2635224145Sdim      return false;
2636224145Sdim    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2637224145Sdim    if (!C || C->getZExtValue() != 8)
2638224145Sdim      return false;
2639224145Sdim  } else { // Opc == ISD::SRL
2640224145Sdim    // (x & 0xff00) >> 8
2641224145Sdim    // (x & 0xff000000) >> 8
2642224145Sdim    if (Num != 1 && Num != 3)
2643224145Sdim      return false;
2644224145Sdim    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2645224145Sdim    if (!C || C->getZExtValue() != 8)
2646224145Sdim      return false;
2647224145Sdim  }
2648224145Sdim
2649224145Sdim  if (Parts[Num])
2650224145Sdim    return false;
2651224145Sdim
2652224145Sdim  Parts[Num] = N0.getOperand(0).getNode();
2653224145Sdim  return true;
2654224145Sdim}
2655224145Sdim
2656224145Sdim/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2657224145Sdim/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2658224145Sdim/// => (rotl (bswap x), 16)
2659224145SdimSDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2660224145Sdim  if (!LegalOperations)
2661224145Sdim    return SDValue();
2662224145Sdim
2663224145Sdim  EVT VT = N->getValueType(0);
2664224145Sdim  if (VT != MVT::i32)
2665224145Sdim    return SDValue();
2666224145Sdim  if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2667224145Sdim    return SDValue();
2668224145Sdim
2669224145Sdim  SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2670224145Sdim  // Look for either
2671224145Sdim  // (or (or (and), (and)), (or (and), (and)))
2672224145Sdim  // (or (or (or (and), (and)), (and)), (and))
2673224145Sdim  if (N0.getOpcode() != ISD::OR)
2674224145Sdim    return SDValue();
2675224145Sdim  SDValue N00 = N0.getOperand(0);
2676224145Sdim  SDValue N01 = N0.getOperand(1);
2677224145Sdim
2678224145Sdim  if (N1.getOpcode() == ISD::OR) {
2679224145Sdim    // (or (or (and), (and)), (or (and), (and)))
2680224145Sdim    SDValue N000 = N00.getOperand(0);
2681224145Sdim    if (!isBSwapHWordElement(N000, Parts))
2682224145Sdim      return SDValue();
2683224145Sdim
2684224145Sdim    SDValue N001 = N00.getOperand(1);
2685224145Sdim    if (!isBSwapHWordElement(N001, Parts))
2686224145Sdim      return SDValue();
2687224145Sdim    SDValue N010 = N01.getOperand(0);
2688224145Sdim    if (!isBSwapHWordElement(N010, Parts))
2689224145Sdim      return SDValue();
2690224145Sdim    SDValue N011 = N01.getOperand(1);
2691224145Sdim    if (!isBSwapHWordElement(N011, Parts))
2692224145Sdim      return SDValue();
2693224145Sdim  } else {
2694224145Sdim    // (or (or (or (and), (and)), (and)), (and))
2695224145Sdim    if (!isBSwapHWordElement(N1, Parts))
2696224145Sdim      return SDValue();
2697224145Sdim    if (!isBSwapHWordElement(N01, Parts))
2698224145Sdim      return SDValue();
2699224145Sdim    if (N00.getOpcode() != ISD::OR)
2700224145Sdim      return SDValue();
2701224145Sdim    SDValue N000 = N00.getOperand(0);
2702224145Sdim    if (!isBSwapHWordElement(N000, Parts))
2703224145Sdim      return SDValue();
2704224145Sdim    SDValue N001 = N00.getOperand(1);
2705224145Sdim    if (!isBSwapHWordElement(N001, Parts))
2706224145Sdim      return SDValue();
2707224145Sdim  }
2708224145Sdim
2709224145Sdim  // Make sure the parts are all coming from the same node.
2710224145Sdim  if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2711224145Sdim    return SDValue();
2712224145Sdim
2713224145Sdim  SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2714224145Sdim                              SDValue(Parts[0],0));
2715224145Sdim
2716224145Sdim  // Result of the bswap should be rotated by 16. If it's not legal, than
2717224145Sdim  // do  (x << 16) | (x >> 16).
2718224145Sdim  SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2719224145Sdim  if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2720224145Sdim    return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2721224145Sdim  else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2722224145Sdim    return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2723224145Sdim  return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2724224145Sdim                     DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2725224145Sdim                     DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2726224145Sdim}
2727224145Sdim
2728193323SedSDValue DAGCombiner::visitOR(SDNode *N) {
2729193323Sed  SDValue N0 = N->getOperand(0);
2730193323Sed  SDValue N1 = N->getOperand(1);
2731193323Sed  SDValue LL, LR, RL, RR, CC0, CC1;
2732193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2733193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2734198090Srdivacky  EVT VT = N1.getValueType();
2735193323Sed
2736193323Sed  // fold vector ops
2737193323Sed  if (VT.isVector()) {
2738193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
2739193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
2740193323Sed  }
2741193323Sed
2742193323Sed  // fold (or x, undef) -> -1
2743210299Sed  if (!LegalOperations &&
2744210299Sed      (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2745200581Srdivacky    EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2746200581Srdivacky    return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2747200581Srdivacky  }
2748193323Sed  // fold (or c1, c2) -> c1|c2
2749193323Sed  if (N0C && N1C)
2750193323Sed    return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2751193323Sed  // canonicalize constant to RHS
2752193323Sed  if (N0C && !N1C)
2753193323Sed    return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2754193323Sed  // fold (or x, 0) -> x
2755193323Sed  if (N1C && N1C->isNullValue())
2756193323Sed    return N0;
2757193323Sed  // fold (or x, -1) -> -1
2758193323Sed  if (N1C && N1C->isAllOnesValue())
2759193323Sed    return N1;
2760193323Sed  // fold (or x, c) -> c iff (x & ~c) == 0
2761193323Sed  if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2762193323Sed    return N1;
2763224145Sdim
2764224145Sdim  // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
2765224145Sdim  SDValue BSwap = MatchBSwapHWord(N, N0, N1);
2766224145Sdim  if (BSwap.getNode() != 0)
2767224145Sdim    return BSwap;
2768224145Sdim  BSwap = MatchBSwapHWordLow(N, N0, N1);
2769224145Sdim  if (BSwap.getNode() != 0)
2770224145Sdim    return BSwap;
2771224145Sdim
2772193323Sed  // reassociate or
2773193323Sed  SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2774193323Sed  if (ROR.getNode() != 0)
2775193323Sed    return ROR;
2776193323Sed  // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2777204642Srdivacky  // iff (c1 & c2) == 0.
2778193323Sed  if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2779193323Sed             isa<ConstantSDNode>(N0.getOperand(1))) {
2780193323Sed    ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2781204642Srdivacky    if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2782204642Srdivacky      return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2783204642Srdivacky                         DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2784204642Srdivacky                                     N0.getOperand(0), N1),
2785204642Srdivacky                         DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2786193323Sed  }
2787193323Sed  // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2788193323Sed  if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2789193323Sed    ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2790193323Sed    ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2791193323Sed
2792193323Sed    if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2793193323Sed        LL.getValueType().isInteger()) {
2794193323Sed      // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2795193323Sed      // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2796193323Sed      if (cast<ConstantSDNode>(LR)->isNullValue() &&
2797193323Sed          (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2798193323Sed        SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2799193323Sed                                     LR.getValueType(), LL, RL);
2800193323Sed        AddToWorkList(ORNode.getNode());
2801193323Sed        return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2802193323Sed      }
2803193323Sed      // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2804193323Sed      // fold (or (setgt X, -1), (setgt Y  -1)) -> (setgt (and X, Y), -1)
2805193323Sed      if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2806193323Sed          (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2807193323Sed        SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2808193323Sed                                      LR.getValueType(), LL, RL);
2809193323Sed        AddToWorkList(ANDNode.getNode());
2810193323Sed        return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2811193323Sed      }
2812193323Sed    }
2813193323Sed    // canonicalize equivalent to ll == rl
2814193323Sed    if (LL == RR && LR == RL) {
2815193323Sed      Op1 = ISD::getSetCCSwappedOperands(Op1);
2816193323Sed      std::swap(RL, RR);
2817193323Sed    }
2818193323Sed    if (LL == RL && LR == RR) {
2819193323Sed      bool isInteger = LL.getValueType().isInteger();
2820193323Sed      ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2821193323Sed      if (Result != ISD::SETCC_INVALID &&
2822193323Sed          (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2823193323Sed        return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2824193323Sed                            LL, LR, Result);
2825193323Sed    }
2826193323Sed  }
2827193323Sed
2828193323Sed  // Simplify: (or (op x...), (op y...))  -> (op (or x, y))
2829193323Sed  if (N0.getOpcode() == N1.getOpcode()) {
2830193323Sed    SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2831193323Sed    if (Tmp.getNode()) return Tmp;
2832193323Sed  }
2833193323Sed
2834193323Sed  // (or (and X, C1), (and Y, C2))  -> (and (or X, Y), C3) if possible.
2835193323Sed  if (N0.getOpcode() == ISD::AND &&
2836193323Sed      N1.getOpcode() == ISD::AND &&
2837193323Sed      N0.getOperand(1).getOpcode() == ISD::Constant &&
2838193323Sed      N1.getOperand(1).getOpcode() == ISD::Constant &&
2839193323Sed      // Don't increase # computations.
2840193323Sed      (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2841193323Sed    // We can only do this xform if we know that bits from X that are set in C2
2842193323Sed    // but not in C1 are already zero.  Likewise for Y.
2843193323Sed    const APInt &LHSMask =
2844193323Sed      cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2845193323Sed    const APInt &RHSMask =
2846193323Sed      cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2847193323Sed
2848193323Sed    if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2849193323Sed        DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2850193323Sed      SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2851193323Sed                              N0.getOperand(0), N1.getOperand(0));
2852193323Sed      return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2853193323Sed                         DAG.getConstant(LHSMask | RHSMask, VT));
2854193323Sed    }
2855193323Sed  }
2856193323Sed
2857193323Sed  // See if this is some rotate idiom.
2858193323Sed  if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2859193323Sed    return SDValue(Rot, 0);
2860193323Sed
2861210299Sed  // Simplify the operands using demanded-bits information.
2862210299Sed  if (!VT.isVector() &&
2863210299Sed      SimplifyDemandedBits(SDValue(N, 0)))
2864210299Sed    return SDValue(N, 0);
2865210299Sed
2866193323Sed  return SDValue();
2867193323Sed}
2868193323Sed
2869193323Sed/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2870193323Sedstatic bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2871193323Sed  if (Op.getOpcode() == ISD::AND) {
2872193323Sed    if (isa<ConstantSDNode>(Op.getOperand(1))) {
2873193323Sed      Mask = Op.getOperand(1);
2874193323Sed      Op = Op.getOperand(0);
2875193323Sed    } else {
2876193323Sed      return false;
2877193323Sed    }
2878193323Sed  }
2879193323Sed
2880193323Sed  if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2881193323Sed    Shift = Op;
2882193323Sed    return true;
2883193323Sed  }
2884193323Sed
2885193323Sed  return false;
2886193323Sed}
2887193323Sed
2888193323Sed// MatchRotate - Handle an 'or' of two operands.  If this is one of the many
2889193323Sed// idioms for rotate, and if the target supports rotation instructions, generate
2890193323Sed// a rot[lr].
2891193323SedSDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2892193323Sed  // Must be a legal type.  Expanded 'n promoted things won't work with rotates.
2893198090Srdivacky  EVT VT = LHS.getValueType();
2894193323Sed  if (!TLI.isTypeLegal(VT)) return 0;
2895193323Sed
2896193323Sed  // The target must have at least one rotate flavor.
2897193323Sed  bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2898193323Sed  bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2899193323Sed  if (!HasROTL && !HasROTR) return 0;
2900193323Sed
2901193323Sed  // Match "(X shl/srl V1) & V2" where V2 may not be present.
2902193323Sed  SDValue LHSShift;   // The shift.
2903193323Sed  SDValue LHSMask;    // AND value if any.
2904193323Sed  if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2905193323Sed    return 0; // Not part of a rotate.
2906193323Sed
2907193323Sed  SDValue RHSShift;   // The shift.
2908193323Sed  SDValue RHSMask;    // AND value if any.
2909193323Sed  if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2910193323Sed    return 0; // Not part of a rotate.
2911193323Sed
2912193323Sed  if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2913193323Sed    return 0;   // Not shifting the same value.
2914193323Sed
2915193323Sed  if (LHSShift.getOpcode() == RHSShift.getOpcode())
2916193323Sed    return 0;   // Shifts must disagree.
2917193323Sed
2918193323Sed  // Canonicalize shl to left side in a shl/srl pair.
2919193323Sed  if (RHSShift.getOpcode() == ISD::SHL) {
2920193323Sed    std::swap(LHS, RHS);
2921193323Sed    std::swap(LHSShift, RHSShift);
2922193323Sed    std::swap(LHSMask , RHSMask );
2923193323Sed  }
2924193323Sed
2925193323Sed  unsigned OpSizeInBits = VT.getSizeInBits();
2926193323Sed  SDValue LHSShiftArg = LHSShift.getOperand(0);
2927193323Sed  SDValue LHSShiftAmt = LHSShift.getOperand(1);
2928193323Sed  SDValue RHSShiftAmt = RHSShift.getOperand(1);
2929193323Sed
2930193323Sed  // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2931193323Sed  // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2932193323Sed  if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2933193323Sed      RHSShiftAmt.getOpcode() == ISD::Constant) {
2934193323Sed    uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2935193323Sed    uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2936193323Sed    if ((LShVal + RShVal) != OpSizeInBits)
2937193323Sed      return 0;
2938193323Sed
2939193323Sed    SDValue Rot;
2940193323Sed    if (HasROTL)
2941193323Sed      Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2942193323Sed    else
2943193323Sed      Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2944193323Sed
2945193323Sed    // If there is an AND of either shifted operand, apply it to the result.
2946193323Sed    if (LHSMask.getNode() || RHSMask.getNode()) {
2947193323Sed      APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2948193323Sed
2949193323Sed      if (LHSMask.getNode()) {
2950193323Sed        APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2951193323Sed        Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2952193323Sed      }
2953193323Sed      if (RHSMask.getNode()) {
2954193323Sed        APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2955193323Sed        Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2956193323Sed      }
2957193323Sed
2958193323Sed      Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2959193323Sed    }
2960193323Sed
2961193323Sed    return Rot.getNode();
2962193323Sed  }
2963193323Sed
2964193323Sed  // If there is a mask here, and we have a variable shift, we can't be sure
2965193323Sed  // that we're masking out the right stuff.
2966193323Sed  if (LHSMask.getNode() || RHSMask.getNode())
2967193323Sed    return 0;
2968193323Sed
2969193323Sed  // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2970193323Sed  // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2971193323Sed  if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2972193323Sed      LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2973193323Sed    if (ConstantSDNode *SUBC =
2974193323Sed          dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2975193323Sed      if (SUBC->getAPIntValue() == OpSizeInBits) {
2976193323Sed        if (HasROTL)
2977193323Sed          return DAG.getNode(ISD::ROTL, DL, VT,
2978193323Sed                             LHSShiftArg, LHSShiftAmt).getNode();
2979193323Sed        else
2980193323Sed          return DAG.getNode(ISD::ROTR, DL, VT,
2981193323Sed                             LHSShiftArg, RHSShiftAmt).getNode();
2982193323Sed      }
2983193323Sed    }
2984193323Sed  }
2985193323Sed
2986193323Sed  // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2987193323Sed  // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2988193323Sed  if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2989193323Sed      RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2990193323Sed    if (ConstantSDNode *SUBC =
2991193323Sed          dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2992193323Sed      if (SUBC->getAPIntValue() == OpSizeInBits) {
2993193323Sed        if (HasROTR)
2994193323Sed          return DAG.getNode(ISD::ROTR, DL, VT,
2995193323Sed                             LHSShiftArg, RHSShiftAmt).getNode();
2996193323Sed        else
2997193323Sed          return DAG.getNode(ISD::ROTL, DL, VT,
2998193323Sed                             LHSShiftArg, LHSShiftAmt).getNode();
2999193323Sed      }
3000193323Sed    }
3001193323Sed  }
3002193323Sed
3003193323Sed  // Look for sign/zext/any-extended or truncate cases:
3004193323Sed  if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3005193323Sed       || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3006193323Sed       || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3007193323Sed       || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3008193323Sed      (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3009193323Sed       || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3010193323Sed       || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3011193323Sed       || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3012193323Sed    SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3013193323Sed    SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3014193323Sed    if (RExtOp0.getOpcode() == ISD::SUB &&
3015193323Sed        RExtOp0.getOperand(1) == LExtOp0) {
3016193323Sed      // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3017193323Sed      //   (rotl x, y)
3018193323Sed      // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3019193323Sed      //   (rotr x, (sub 32, y))
3020193323Sed      if (ConstantSDNode *SUBC =
3021193323Sed            dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3022193323Sed        if (SUBC->getAPIntValue() == OpSizeInBits) {
3023193323Sed          return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3024193323Sed                             LHSShiftArg,
3025193323Sed                             HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3026193323Sed        }
3027193323Sed      }
3028193323Sed    } else if (LExtOp0.getOpcode() == ISD::SUB &&
3029193323Sed               RExtOp0 == LExtOp0.getOperand(1)) {
3030193323Sed      // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3031193323Sed      //   (rotr x, y)
3032193323Sed      // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3033193323Sed      //   (rotl x, (sub 32, y))
3034193323Sed      if (ConstantSDNode *SUBC =
3035193323Sed            dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3036193323Sed        if (SUBC->getAPIntValue() == OpSizeInBits) {
3037193323Sed          return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3038193323Sed                             LHSShiftArg,
3039193323Sed                             HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3040193323Sed        }
3041193323Sed      }
3042193323Sed    }
3043193323Sed  }
3044193323Sed
3045193323Sed  return 0;
3046193323Sed}
3047193323Sed
3048193323SedSDValue DAGCombiner::visitXOR(SDNode *N) {
3049193323Sed  SDValue N0 = N->getOperand(0);
3050193323Sed  SDValue N1 = N->getOperand(1);
3051193323Sed  SDValue LHS, RHS, CC;
3052193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3053193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3054198090Srdivacky  EVT VT = N0.getValueType();
3055193323Sed
3056193323Sed  // fold vector ops
3057193323Sed  if (VT.isVector()) {
3058193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
3059193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
3060193323Sed  }
3061193323Sed
3062193323Sed  // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3063193323Sed  if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3064193323Sed    return DAG.getConstant(0, VT);
3065193323Sed  // fold (xor x, undef) -> undef
3066193323Sed  if (N0.getOpcode() == ISD::UNDEF)
3067193323Sed    return N0;
3068193323Sed  if (N1.getOpcode() == ISD::UNDEF)
3069193323Sed    return N1;
3070193323Sed  // fold (xor c1, c2) -> c1^c2
3071193323Sed  if (N0C && N1C)
3072193323Sed    return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3073193323Sed  // canonicalize constant to RHS
3074193323Sed  if (N0C && !N1C)
3075193323Sed    return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3076193323Sed  // fold (xor x, 0) -> x
3077193323Sed  if (N1C && N1C->isNullValue())
3078193323Sed    return N0;
3079193323Sed  // reassociate xor
3080193323Sed  SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3081193323Sed  if (RXOR.getNode() != 0)
3082193323Sed    return RXOR;
3083193323Sed
3084193323Sed  // fold !(x cc y) -> (x !cc y)
3085193323Sed  if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3086193323Sed    bool isInt = LHS.getValueType().isInteger();
3087193323Sed    ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3088193323Sed                                               isInt);
3089193323Sed
3090193323Sed    if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3091193323Sed      switch (N0.getOpcode()) {
3092193323Sed      default:
3093198090Srdivacky        llvm_unreachable("Unhandled SetCC Equivalent!");
3094193323Sed      case ISD::SETCC:
3095193323Sed        return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3096193323Sed      case ISD::SELECT_CC:
3097193323Sed        return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3098193323Sed                               N0.getOperand(3), NotCC);
3099193323Sed      }
3100193323Sed    }
3101193323Sed  }
3102193323Sed
3103193323Sed  // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3104193323Sed  if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3105193323Sed      N0.getNode()->hasOneUse() &&
3106193323Sed      isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3107193323Sed    SDValue V = N0.getOperand(0);
3108193323Sed    V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3109193323Sed                    DAG.getConstant(1, V.getValueType()));
3110193323Sed    AddToWorkList(V.getNode());
3111193323Sed    return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3112193323Sed  }
3113193323Sed
3114193323Sed  // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3115193323Sed  if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3116193323Sed      (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3117193323Sed    SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3118193323Sed    if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3119193323Sed      unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3120193323Sed      LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3121193323Sed      RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3122193323Sed      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3123193323Sed      return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3124193323Sed    }
3125193323Sed  }
3126193323Sed  // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3127193323Sed  if (N1C && N1C->isAllOnesValue() &&
3128193323Sed      (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3129193323Sed    SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3130193323Sed    if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3131193323Sed      unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3132193323Sed      LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3133193323Sed      RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3134193323Sed      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3135193323Sed      return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3136193323Sed    }
3137193323Sed  }
3138193323Sed  // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3139193323Sed  if (N1C && N0.getOpcode() == ISD::XOR) {
3140193323Sed    ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3141193323Sed    ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3142193323Sed    if (N00C)
3143193323Sed      return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3144193323Sed                         DAG.getConstant(N1C->getAPIntValue() ^
3145193323Sed                                         N00C->getAPIntValue(), VT));
3146193323Sed    if (N01C)
3147193323Sed      return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3148193323Sed                         DAG.getConstant(N1C->getAPIntValue() ^
3149193323Sed                                         N01C->getAPIntValue(), VT));
3150193323Sed  }
3151193323Sed  // fold (xor x, x) -> 0
3152218893Sdim  if (N0 == N1)
3153218893Sdim    return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3154193323Sed
3155193323Sed  // Simplify: xor (op x...), (op y...)  -> (op (xor x, y))
3156193323Sed  if (N0.getOpcode() == N1.getOpcode()) {
3157193323Sed    SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3158193323Sed    if (Tmp.getNode()) return Tmp;
3159193323Sed  }
3160193323Sed
3161193323Sed  // Simplify the expression using non-local knowledge.
3162193323Sed  if (!VT.isVector() &&
3163193323Sed      SimplifyDemandedBits(SDValue(N, 0)))
3164193323Sed    return SDValue(N, 0);
3165193323Sed
3166193323Sed  return SDValue();
3167193323Sed}
3168193323Sed
3169193323Sed/// visitShiftByConstant - Handle transforms common to the three shifts, when
3170193323Sed/// the shift amount is a constant.
3171193323SedSDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3172193323Sed  SDNode *LHS = N->getOperand(0).getNode();
3173193323Sed  if (!LHS->hasOneUse()) return SDValue();
3174193323Sed
3175193323Sed  // We want to pull some binops through shifts, so that we have (and (shift))
3176193323Sed  // instead of (shift (and)), likewise for add, or, xor, etc.  This sort of
3177193323Sed  // thing happens with address calculations, so it's important to canonicalize
3178193323Sed  // it.
3179193323Sed  bool HighBitSet = false;  // Can we transform this if the high bit is set?
3180193323Sed
3181193323Sed  switch (LHS->getOpcode()) {
3182193323Sed  default: return SDValue();
3183193323Sed  case ISD::OR:
3184193323Sed  case ISD::XOR:
3185193323Sed    HighBitSet = false; // We can only transform sra if the high bit is clear.
3186193323Sed    break;
3187193323Sed  case ISD::AND:
3188193323Sed    HighBitSet = true;  // We can only transform sra if the high bit is set.
3189193323Sed    break;
3190193323Sed  case ISD::ADD:
3191193323Sed    if (N->getOpcode() != ISD::SHL)
3192193323Sed      return SDValue(); // only shl(add) not sr[al](add).
3193193323Sed    HighBitSet = false; // We can only transform sra if the high bit is clear.
3194193323Sed    break;
3195193323Sed  }
3196193323Sed
3197193323Sed  // We require the RHS of the binop to be a constant as well.
3198193323Sed  ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3199193323Sed  if (!BinOpCst) return SDValue();
3200193323Sed
3201193323Sed  // FIXME: disable this unless the input to the binop is a shift by a constant.
3202193323Sed  // If it is not a shift, it pessimizes some common cases like:
3203193323Sed  //
3204193323Sed  //    void foo(int *X, int i) { X[i & 1235] = 1; }
3205193323Sed  //    int bar(int *X, int i) { return X[i & 255]; }
3206193323Sed  SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3207193323Sed  if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3208193323Sed       BinOpLHSVal->getOpcode() != ISD::SRA &&
3209193323Sed       BinOpLHSVal->getOpcode() != ISD::SRL) ||
3210193323Sed      !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3211193323Sed    return SDValue();
3212193323Sed
3213198090Srdivacky  EVT VT = N->getValueType(0);
3214193323Sed
3215193323Sed  // If this is a signed shift right, and the high bit is modified by the
3216193323Sed  // logical operation, do not perform the transformation. The highBitSet
3217193323Sed  // boolean indicates the value of the high bit of the constant which would
3218193323Sed  // cause it to be modified for this operation.
3219193323Sed  if (N->getOpcode() == ISD::SRA) {
3220193323Sed    bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3221193323Sed    if (BinOpRHSSignSet != HighBitSet)
3222193323Sed      return SDValue();
3223193323Sed  }
3224193323Sed
3225193323Sed  // Fold the constants, shifting the binop RHS by the shift amount.
3226193323Sed  SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3227193323Sed                               N->getValueType(0),
3228193323Sed                               LHS->getOperand(1), N->getOperand(1));
3229193323Sed
3230193323Sed  // Create the new shift.
3231218893Sdim  SDValue NewShift = DAG.getNode(N->getOpcode(),
3232218893Sdim                                 LHS->getOperand(0).getDebugLoc(),
3233193323Sed                                 VT, LHS->getOperand(0), N->getOperand(1));
3234193323Sed
3235193323Sed  // Create the new binop.
3236193323Sed  return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3237193323Sed}
3238193323Sed
3239193323SedSDValue DAGCombiner::visitSHL(SDNode *N) {
3240193323Sed  SDValue N0 = N->getOperand(0);
3241193323Sed  SDValue N1 = N->getOperand(1);
3242193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3243193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3244198090Srdivacky  EVT VT = N0.getValueType();
3245200581Srdivacky  unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3246193323Sed
3247193323Sed  // fold (shl c1, c2) -> c1<<c2
3248193323Sed  if (N0C && N1C)
3249193323Sed    return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3250193323Sed  // fold (shl 0, x) -> 0
3251193323Sed  if (N0C && N0C->isNullValue())
3252193323Sed    return N0;
3253193323Sed  // fold (shl x, c >= size(x)) -> undef
3254193323Sed  if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3255193323Sed    return DAG.getUNDEF(VT);
3256193323Sed  // fold (shl x, 0) -> x
3257193323Sed  if (N1C && N1C->isNullValue())
3258193323Sed    return N0;
3259224145Sdim  // fold (shl undef, x) -> 0
3260224145Sdim  if (N0.getOpcode() == ISD::UNDEF)
3261224145Sdim    return DAG.getConstant(0, VT);
3262193323Sed  // if (shl x, c) is known to be zero, return 0
3263193323Sed  if (DAG.MaskedValueIsZero(SDValue(N, 0),
3264200581Srdivacky                            APInt::getAllOnesValue(OpSizeInBits)))
3265193323Sed    return DAG.getConstant(0, VT);
3266193323Sed  // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3267193323Sed  if (N1.getOpcode() == ISD::TRUNCATE &&
3268193323Sed      N1.getOperand(0).getOpcode() == ISD::AND &&
3269193323Sed      N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3270193323Sed    SDValue N101 = N1.getOperand(0).getOperand(1);
3271193323Sed    if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3272198090Srdivacky      EVT TruncVT = N1.getValueType();
3273193323Sed      SDValue N100 = N1.getOperand(0).getOperand(0);
3274193323Sed      APInt TruncC = N101C->getAPIntValue();
3275218893Sdim      TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3276193323Sed      return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3277193323Sed                         DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3278193323Sed                                     DAG.getNode(ISD::TRUNCATE,
3279193323Sed                                                 N->getDebugLoc(),
3280193323Sed                                                 TruncVT, N100),
3281193323Sed                                     DAG.getConstant(TruncC, TruncVT)));
3282193323Sed    }
3283193323Sed  }
3284193323Sed
3285193323Sed  if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3286193323Sed    return SDValue(N, 0);
3287193323Sed
3288193323Sed  // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3289193323Sed  if (N1C && N0.getOpcode() == ISD::SHL &&
3290193323Sed      N0.getOperand(1).getOpcode() == ISD::Constant) {
3291193323Sed    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3292193323Sed    uint64_t c2 = N1C->getZExtValue();
3293218893Sdim    if (c1 + c2 >= OpSizeInBits)
3294193323Sed      return DAG.getConstant(0, VT);
3295193323Sed    return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3296193323Sed                       DAG.getConstant(c1 + c2, N1.getValueType()));
3297193323Sed  }
3298218893Sdim
3299218893Sdim  // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3300218893Sdim  // For this to be valid, the second form must not preserve any of the bits
3301218893Sdim  // that are shifted out by the inner shift in the first form.  This means
3302218893Sdim  // the outer shift size must be >= the number of bits added by the ext.
3303218893Sdim  // As a corollary, we don't care what kind of ext it is.
3304218893Sdim  if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3305218893Sdim              N0.getOpcode() == ISD::ANY_EXTEND ||
3306218893Sdim              N0.getOpcode() == ISD::SIGN_EXTEND) &&
3307218893Sdim      N0.getOperand(0).getOpcode() == ISD::SHL &&
3308218893Sdim      isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3309219077Sdim    uint64_t c1 =
3310218893Sdim      cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3311218893Sdim    uint64_t c2 = N1C->getZExtValue();
3312218893Sdim    EVT InnerShiftVT = N0.getOperand(0).getValueType();
3313218893Sdim    uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3314218893Sdim    if (c2 >= OpSizeInBits - InnerShiftSize) {
3315218893Sdim      if (c1 + c2 >= OpSizeInBits)
3316218893Sdim        return DAG.getConstant(0, VT);
3317218893Sdim      return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3318218893Sdim                         DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3319218893Sdim                                     N0.getOperand(0)->getOperand(0)),
3320218893Sdim                         DAG.getConstant(c1 + c2, N1.getValueType()));
3321218893Sdim    }
3322218893Sdim  }
3323218893Sdim
3324223017Sdim  // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3325223017Sdim  //                               (and (srl x, (sub c1, c2), MASK)
3326193323Sed  if (N1C && N0.getOpcode() == ISD::SRL &&
3327193323Sed      N0.getOperand(1).getOpcode() == ISD::Constant) {
3328193323Sed    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3329198090Srdivacky    if (c1 < VT.getSizeInBits()) {
3330198090Srdivacky      uint64_t c2 = N1C->getZExtValue();
3331223017Sdim      APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3332223017Sdim                                         VT.getSizeInBits() - c1);
3333223017Sdim      SDValue Shift;
3334223017Sdim      if (c2 > c1) {
3335223017Sdim        Mask = Mask.shl(c2-c1);
3336223017Sdim        Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3337223017Sdim                            DAG.getConstant(c2-c1, N1.getValueType()));
3338223017Sdim      } else {
3339223017Sdim        Mask = Mask.lshr(c1-c2);
3340223017Sdim        Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3341223017Sdim                            DAG.getConstant(c1-c2, N1.getValueType()));
3342223017Sdim      }
3343223017Sdim      return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3344223017Sdim                         DAG.getConstant(Mask, VT));
3345198090Srdivacky    }
3346193323Sed  }
3347193323Sed  // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3348198090Srdivacky  if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3349198090Srdivacky    SDValue HiBitsMask =
3350198090Srdivacky      DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3351198090Srdivacky                                            VT.getSizeInBits() -
3352198090Srdivacky                                              N1C->getZExtValue()),
3353198090Srdivacky                      VT);
3354193323Sed    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3355198090Srdivacky                       HiBitsMask);
3356198090Srdivacky  }
3357193323Sed
3358207618Srdivacky  if (N1C) {
3359207618Srdivacky    SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3360207618Srdivacky    if (NewSHL.getNode())
3361207618Srdivacky      return NewSHL;
3362207618Srdivacky  }
3363207618Srdivacky
3364207618Srdivacky  return SDValue();
3365193323Sed}
3366193323Sed
3367193323SedSDValue DAGCombiner::visitSRA(SDNode *N) {
3368193323Sed  SDValue N0 = N->getOperand(0);
3369193323Sed  SDValue N1 = N->getOperand(1);
3370193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3371193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3372198090Srdivacky  EVT VT = N0.getValueType();
3373200581Srdivacky  unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3374193323Sed
3375193323Sed  // fold (sra c1, c2) -> (sra c1, c2)
3376193323Sed  if (N0C && N1C)
3377193323Sed    return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3378193323Sed  // fold (sra 0, x) -> 0
3379193323Sed  if (N0C && N0C->isNullValue())
3380193323Sed    return N0;
3381193323Sed  // fold (sra -1, x) -> -1
3382193323Sed  if (N0C && N0C->isAllOnesValue())
3383193323Sed    return N0;
3384193323Sed  // fold (sra x, (setge c, size(x))) -> undef
3385200581Srdivacky  if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3386193323Sed    return DAG.getUNDEF(VT);
3387193323Sed  // fold (sra x, 0) -> x
3388193323Sed  if (N1C && N1C->isNullValue())
3389193323Sed    return N0;
3390193323Sed  // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3391193323Sed  // sext_inreg.
3392193323Sed  if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3393200581Srdivacky    unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3394202375Srdivacky    EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3395202375Srdivacky    if (VT.isVector())
3396202375Srdivacky      ExtVT = EVT::getVectorVT(*DAG.getContext(),
3397202375Srdivacky                               ExtVT, VT.getVectorNumElements());
3398202375Srdivacky    if ((!LegalOperations ||
3399202375Srdivacky         TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3400193323Sed      return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3401202375Srdivacky                         N0.getOperand(0), DAG.getValueType(ExtVT));
3402193323Sed  }
3403193323Sed
3404193323Sed  // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3405193323Sed  if (N1C && N0.getOpcode() == ISD::SRA) {
3406193323Sed    if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3407193323Sed      unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3408200581Srdivacky      if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3409193323Sed      return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3410193323Sed                         DAG.getConstant(Sum, N1C->getValueType(0)));
3411193323Sed    }
3412193323Sed  }
3413193323Sed
3414193323Sed  // fold (sra (shl X, m), (sub result_size, n))
3415193323Sed  // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3416193323Sed  // result_size - n != m.
3417193323Sed  // If truncate is free for the target sext(shl) is likely to result in better
3418193323Sed  // code.
3419193323Sed  if (N0.getOpcode() == ISD::SHL) {
3420193323Sed    // Get the two constanst of the shifts, CN0 = m, CN = n.
3421193323Sed    const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3422193323Sed    if (N01C && N1C) {
3423193323Sed      // Determine what the truncate's result bitsize and type would be.
3424198090Srdivacky      EVT TruncVT =
3425218893Sdim        EVT::getIntegerVT(*DAG.getContext(),
3426218893Sdim                          OpSizeInBits - N1C->getZExtValue());
3427193323Sed      // Determine the residual right-shift amount.
3428193323Sed      signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3429193323Sed
3430193323Sed      // If the shift is not a no-op (in which case this should be just a sign
3431193323Sed      // extend already), the truncated to type is legal, sign_extend is legal
3432203954Srdivacky      // on that type, and the truncate to that type is both legal and free,
3433193323Sed      // perform the transform.
3434193323Sed      if ((ShiftAmt > 0) &&
3435193323Sed          TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3436193323Sed          TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3437193323Sed          TLI.isTruncateFree(VT, TruncVT)) {
3438193323Sed
3439219077Sdim          SDValue Amt = DAG.getConstant(ShiftAmt,
3440219077Sdim              getShiftAmountTy(N0.getOperand(0).getValueType()));
3441193323Sed          SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3442193323Sed                                      N0.getOperand(0), Amt);
3443193323Sed          SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3444193323Sed                                      Shift);
3445193323Sed          return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3446193323Sed                             N->getValueType(0), Trunc);
3447193323Sed      }
3448193323Sed    }
3449193323Sed  }
3450193323Sed
3451193323Sed  // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3452193323Sed  if (N1.getOpcode() == ISD::TRUNCATE &&
3453193323Sed      N1.getOperand(0).getOpcode() == ISD::AND &&
3454193323Sed      N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3455193323Sed    SDValue N101 = N1.getOperand(0).getOperand(1);
3456193323Sed    if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3457198090Srdivacky      EVT TruncVT = N1.getValueType();
3458193323Sed      SDValue N100 = N1.getOperand(0).getOperand(0);
3459193323Sed      APInt TruncC = N101C->getAPIntValue();
3460218893Sdim      TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3461193323Sed      return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3462193323Sed                         DAG.getNode(ISD::AND, N->getDebugLoc(),
3463193323Sed                                     TruncVT,
3464193323Sed                                     DAG.getNode(ISD::TRUNCATE,
3465193323Sed                                                 N->getDebugLoc(),
3466193323Sed                                                 TruncVT, N100),
3467193323Sed                                     DAG.getConstant(TruncC, TruncVT)));
3468193323Sed    }
3469193323Sed  }
3470193323Sed
3471218893Sdim  // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3472218893Sdim  //      if c1 is equal to the number of bits the trunc removes
3473218893Sdim  if (N0.getOpcode() == ISD::TRUNCATE &&
3474218893Sdim      (N0.getOperand(0).getOpcode() == ISD::SRL ||
3475218893Sdim       N0.getOperand(0).getOpcode() == ISD::SRA) &&
3476218893Sdim      N0.getOperand(0).hasOneUse() &&
3477218893Sdim      N0.getOperand(0).getOperand(1).hasOneUse() &&
3478218893Sdim      N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3479218893Sdim    EVT LargeVT = N0.getOperand(0).getValueType();
3480218893Sdim    ConstantSDNode *LargeShiftAmt =
3481218893Sdim      cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3482218893Sdim
3483218893Sdim    if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3484218893Sdim        LargeShiftAmt->getZExtValue()) {
3485218893Sdim      SDValue Amt =
3486218893Sdim        DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3487219077Sdim              getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3488218893Sdim      SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3489218893Sdim                                N0.getOperand(0).getOperand(0), Amt);
3490218893Sdim      return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3491218893Sdim    }
3492218893Sdim  }
3493218893Sdim
3494193323Sed  // Simplify, based on bits shifted out of the LHS.
3495193323Sed  if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3496193323Sed    return SDValue(N, 0);
3497193323Sed
3498193323Sed
3499193323Sed  // If the sign bit is known to be zero, switch this to a SRL.
3500193323Sed  if (DAG.SignBitIsZero(N0))
3501193323Sed    return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3502193323Sed
3503207618Srdivacky  if (N1C) {
3504207618Srdivacky    SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3505207618Srdivacky    if (NewSRA.getNode())
3506207618Srdivacky      return NewSRA;
3507207618Srdivacky  }
3508207618Srdivacky
3509207618Srdivacky  return SDValue();
3510193323Sed}
3511193323Sed
3512193323SedSDValue DAGCombiner::visitSRL(SDNode *N) {
3513193323Sed  SDValue N0 = N->getOperand(0);
3514193323Sed  SDValue N1 = N->getOperand(1);
3515193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3516193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3517198090Srdivacky  EVT VT = N0.getValueType();
3518200581Srdivacky  unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3519193323Sed
3520193323Sed  // fold (srl c1, c2) -> c1 >>u c2
3521193323Sed  if (N0C && N1C)
3522193323Sed    return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3523193323Sed  // fold (srl 0, x) -> 0
3524193323Sed  if (N0C && N0C->isNullValue())
3525193323Sed    return N0;
3526193323Sed  // fold (srl x, c >= size(x)) -> undef
3527193323Sed  if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3528193323Sed    return DAG.getUNDEF(VT);
3529193323Sed  // fold (srl x, 0) -> x
3530193323Sed  if (N1C && N1C->isNullValue())
3531193323Sed    return N0;
3532193323Sed  // if (srl x, c) is known to be zero, return 0
3533193323Sed  if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3534193323Sed                                   APInt::getAllOnesValue(OpSizeInBits)))
3535193323Sed    return DAG.getConstant(0, VT);
3536193323Sed
3537193323Sed  // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3538193323Sed  if (N1C && N0.getOpcode() == ISD::SRL &&
3539193323Sed      N0.getOperand(1).getOpcode() == ISD::Constant) {
3540193323Sed    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3541193323Sed    uint64_t c2 = N1C->getZExtValue();
3542218893Sdim    if (c1 + c2 >= OpSizeInBits)
3543193323Sed      return DAG.getConstant(0, VT);
3544193323Sed    return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3545193323Sed                       DAG.getConstant(c1 + c2, N1.getValueType()));
3546193323Sed  }
3547218893Sdim
3548218893Sdim  // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3549218893Sdim  if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3550218893Sdim      N0.getOperand(0).getOpcode() == ISD::SRL &&
3551218893Sdim      isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3552219077Sdim    uint64_t c1 =
3553218893Sdim      cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3554218893Sdim    uint64_t c2 = N1C->getZExtValue();
3555218893Sdim    EVT InnerShiftVT = N0.getOperand(0).getValueType();
3556218893Sdim    EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3557218893Sdim    uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3558218893Sdim    // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3559218893Sdim    if (c1 + OpSizeInBits == InnerShiftSize) {
3560218893Sdim      if (c1 + c2 >= InnerShiftSize)
3561218893Sdim        return DAG.getConstant(0, VT);
3562218893Sdim      return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3563219077Sdim                         DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3564218893Sdim                                     N0.getOperand(0)->getOperand(0),
3565218893Sdim                                     DAG.getConstant(c1 + c2, ShiftCountVT)));
3566218893Sdim    }
3567218893Sdim  }
3568218893Sdim
3569207618Srdivacky  // fold (srl (shl x, c), c) -> (and x, cst2)
3570207618Srdivacky  if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3571207618Srdivacky      N0.getValueSizeInBits() <= 64) {
3572207618Srdivacky    uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3573207618Srdivacky    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3574207618Srdivacky                       DAG.getConstant(~0ULL >> ShAmt, VT));
3575207618Srdivacky  }
3576193323Sed
3577218893Sdim
3578193323Sed  // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3579193323Sed  if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3580193323Sed    // Shifting in all undef bits?
3581198090Srdivacky    EVT SmallVT = N0.getOperand(0).getValueType();
3582193323Sed    if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3583193323Sed      return DAG.getUNDEF(VT);
3584193323Sed
3585207618Srdivacky    if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3586221345Sdim      uint64_t ShiftAmt = N1C->getZExtValue();
3587207618Srdivacky      SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3588221345Sdim                                       N0.getOperand(0),
3589221345Sdim                          DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3590207618Srdivacky      AddToWorkList(SmallShift.getNode());
3591207618Srdivacky      return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3592207618Srdivacky    }
3593193323Sed  }
3594193323Sed
3595193323Sed  // fold (srl (sra X, Y), 31) -> (srl X, 31).  This srl only looks at the sign
3596193323Sed  // bit, which is unmodified by sra.
3597193323Sed  if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3598193323Sed    if (N0.getOpcode() == ISD::SRA)
3599193323Sed      return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3600193323Sed  }
3601193323Sed
3602193323Sed  // fold (srl (ctlz x), "5") -> x  iff x has one bit set (the low bit).
3603193323Sed  if (N1C && N0.getOpcode() == ISD::CTLZ &&
3604193323Sed      N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3605193323Sed    APInt KnownZero, KnownOne;
3606204642Srdivacky    APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3607193323Sed    DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3608193323Sed
3609193323Sed    // If any of the input bits are KnownOne, then the input couldn't be all
3610193323Sed    // zeros, thus the result of the srl will always be zero.
3611193323Sed    if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3612193323Sed
3613193323Sed    // If all of the bits input the to ctlz node are known to be zero, then
3614193323Sed    // the result of the ctlz is "32" and the result of the shift is one.
3615193323Sed    APInt UnknownBits = ~KnownZero & Mask;
3616193323Sed    if (UnknownBits == 0) return DAG.getConstant(1, VT);
3617193323Sed
3618193323Sed    // Otherwise, check to see if there is exactly one bit input to the ctlz.
3619193323Sed    if ((UnknownBits & (UnknownBits - 1)) == 0) {
3620193323Sed      // Okay, we know that only that the single bit specified by UnknownBits
3621193323Sed      // could be set on input to the CTLZ node. If this bit is set, the SRL
3622193323Sed      // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3623193323Sed      // to an SRL/XOR pair, which is likely to simplify more.
3624193323Sed      unsigned ShAmt = UnknownBits.countTrailingZeros();
3625193323Sed      SDValue Op = N0.getOperand(0);
3626193323Sed
3627193323Sed      if (ShAmt) {
3628193323Sed        Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3629219077Sdim                  DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3630193323Sed        AddToWorkList(Op.getNode());
3631193323Sed      }
3632193323Sed
3633193323Sed      return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3634193323Sed                         Op, DAG.getConstant(1, VT));
3635193323Sed    }
3636193323Sed  }
3637193323Sed
3638193323Sed  // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3639193323Sed  if (N1.getOpcode() == ISD::TRUNCATE &&
3640193323Sed      N1.getOperand(0).getOpcode() == ISD::AND &&
3641193323Sed      N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3642193323Sed    SDValue N101 = N1.getOperand(0).getOperand(1);
3643193323Sed    if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3644198090Srdivacky      EVT TruncVT = N1.getValueType();
3645193323Sed      SDValue N100 = N1.getOperand(0).getOperand(0);
3646193323Sed      APInt TruncC = N101C->getAPIntValue();
3647218893Sdim      TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3648193323Sed      return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3649193323Sed                         DAG.getNode(ISD::AND, N->getDebugLoc(),
3650193323Sed                                     TruncVT,
3651193323Sed                                     DAG.getNode(ISD::TRUNCATE,
3652193323Sed                                                 N->getDebugLoc(),
3653193323Sed                                                 TruncVT, N100),
3654193323Sed                                     DAG.getConstant(TruncC, TruncVT)));
3655193323Sed    }
3656193323Sed  }
3657193323Sed
3658193323Sed  // fold operands of srl based on knowledge that the low bits are not
3659193323Sed  // demanded.
3660193323Sed  if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3661193323Sed    return SDValue(N, 0);
3662193323Sed
3663201360Srdivacky  if (N1C) {
3664201360Srdivacky    SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3665201360Srdivacky    if (NewSRL.getNode())
3666201360Srdivacky      return NewSRL;
3667201360Srdivacky  }
3668201360Srdivacky
3669210299Sed  // Attempt to convert a srl of a load into a narrower zero-extending load.
3670210299Sed  SDValue NarrowLoad = ReduceLoadWidth(N);
3671210299Sed  if (NarrowLoad.getNode())
3672210299Sed    return NarrowLoad;
3673210299Sed
3674201360Srdivacky  // Here is a common situation. We want to optimize:
3675201360Srdivacky  //
3676201360Srdivacky  //   %a = ...
3677201360Srdivacky  //   %b = and i32 %a, 2
3678201360Srdivacky  //   %c = srl i32 %b, 1
3679201360Srdivacky  //   brcond i32 %c ...
3680201360Srdivacky  //
3681201360Srdivacky  // into
3682218893Sdim  //
3683201360Srdivacky  //   %a = ...
3684201360Srdivacky  //   %b = and %a, 2
3685201360Srdivacky  //   %c = setcc eq %b, 0
3686201360Srdivacky  //   brcond %c ...
3687201360Srdivacky  //
3688201360Srdivacky  // However when after the source operand of SRL is optimized into AND, the SRL
3689201360Srdivacky  // itself may not be optimized further. Look for it and add the BRCOND into
3690201360Srdivacky  // the worklist.
3691202375Srdivacky  if (N->hasOneUse()) {
3692202375Srdivacky    SDNode *Use = *N->use_begin();
3693202375Srdivacky    if (Use->getOpcode() == ISD::BRCOND)
3694202375Srdivacky      AddToWorkList(Use);
3695202375Srdivacky    else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3696202375Srdivacky      // Also look pass the truncate.
3697202375Srdivacky      Use = *Use->use_begin();
3698202375Srdivacky      if (Use->getOpcode() == ISD::BRCOND)
3699202375Srdivacky        AddToWorkList(Use);
3700202375Srdivacky    }
3701202375Srdivacky  }
3702201360Srdivacky
3703201360Srdivacky  return SDValue();
3704193323Sed}
3705193323Sed
3706193323SedSDValue DAGCombiner::visitCTLZ(SDNode *N) {
3707193323Sed  SDValue N0 = N->getOperand(0);
3708198090Srdivacky  EVT VT = N->getValueType(0);
3709193323Sed
3710193323Sed  // fold (ctlz c1) -> c2
3711193323Sed  if (isa<ConstantSDNode>(N0))
3712193323Sed    return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3713193323Sed  return SDValue();
3714193323Sed}
3715193323Sed
3716193323SedSDValue DAGCombiner::visitCTTZ(SDNode *N) {
3717193323Sed  SDValue N0 = N->getOperand(0);
3718198090Srdivacky  EVT VT = N->getValueType(0);
3719193323Sed
3720193323Sed  // fold (cttz c1) -> c2
3721193323Sed  if (isa<ConstantSDNode>(N0))
3722193323Sed    return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3723193323Sed  return SDValue();
3724193323Sed}
3725193323Sed
3726193323SedSDValue DAGCombiner::visitCTPOP(SDNode *N) {
3727193323Sed  SDValue N0 = N->getOperand(0);
3728198090Srdivacky  EVT VT = N->getValueType(0);
3729193323Sed
3730193323Sed  // fold (ctpop c1) -> c2
3731193323Sed  if (isa<ConstantSDNode>(N0))
3732193323Sed    return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3733193323Sed  return SDValue();
3734193323Sed}
3735193323Sed
3736193323SedSDValue DAGCombiner::visitSELECT(SDNode *N) {
3737193323Sed  SDValue N0 = N->getOperand(0);
3738193323Sed  SDValue N1 = N->getOperand(1);
3739193323Sed  SDValue N2 = N->getOperand(2);
3740193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3741193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3742193323Sed  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3743198090Srdivacky  EVT VT = N->getValueType(0);
3744198090Srdivacky  EVT VT0 = N0.getValueType();
3745193323Sed
3746193323Sed  // fold (select C, X, X) -> X
3747193323Sed  if (N1 == N2)
3748193323Sed    return N1;
3749193323Sed  // fold (select true, X, Y) -> X
3750193323Sed  if (N0C && !N0C->isNullValue())
3751193323Sed    return N1;
3752193323Sed  // fold (select false, X, Y) -> Y
3753193323Sed  if (N0C && N0C->isNullValue())
3754193323Sed    return N2;
3755193323Sed  // fold (select C, 1, X) -> (or C, X)
3756193323Sed  if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3757193323Sed    return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3758193323Sed  // fold (select C, 0, 1) -> (xor C, 1)
3759193323Sed  if (VT.isInteger() &&
3760193323Sed      (VT0 == MVT::i1 ||
3761193323Sed       (VT0.isInteger() &&
3762226633Sdim        TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
3763193323Sed      N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3764193323Sed    SDValue XORNode;
3765193323Sed    if (VT == VT0)
3766193323Sed      return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3767193323Sed                         N0, DAG.getConstant(1, VT0));
3768193323Sed    XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3769193323Sed                          N0, DAG.getConstant(1, VT0));
3770193323Sed    AddToWorkList(XORNode.getNode());
3771193323Sed    if (VT.bitsGT(VT0))
3772193323Sed      return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3773193323Sed    return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3774193323Sed  }
3775193323Sed  // fold (select C, 0, X) -> (and (not C), X)
3776193323Sed  if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3777193323Sed    SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3778193323Sed    AddToWorkList(NOTNode.getNode());
3779193323Sed    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3780193323Sed  }
3781193323Sed  // fold (select C, X, 1) -> (or (not C), X)
3782193323Sed  if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3783193323Sed    SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3784193323Sed    AddToWorkList(NOTNode.getNode());
3785193323Sed    return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3786193323Sed  }
3787193323Sed  // fold (select C, X, 0) -> (and C, X)
3788193323Sed  if (VT == MVT::i1 && N2C && N2C->isNullValue())
3789193323Sed    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3790193323Sed  // fold (select X, X, Y) -> (or X, Y)
3791193323Sed  // fold (select X, 1, Y) -> (or X, Y)
3792193323Sed  if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3793193323Sed    return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3794193323Sed  // fold (select X, Y, X) -> (and X, Y)
3795193323Sed  // fold (select X, Y, 0) -> (and X, Y)
3796193323Sed  if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3797193323Sed    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3798193323Sed
3799193323Sed  // If we can fold this based on the true/false value, do so.
3800193323Sed  if (SimplifySelectOps(N, N1, N2))
3801193323Sed    return SDValue(N, 0);  // Don't revisit N.
3802193323Sed
3803193323Sed  // fold selects based on a setcc into other things, such as min/max/abs
3804193323Sed  if (N0.getOpcode() == ISD::SETCC) {
3805193323Sed    // FIXME:
3806193323Sed    // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3807193323Sed    // having to say they don't support SELECT_CC on every type the DAG knows
3808193323Sed    // about, since there is no way to mark an opcode illegal at all value types
3809198090Srdivacky    if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3810198090Srdivacky        TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3811193323Sed      return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3812193323Sed                         N0.getOperand(0), N0.getOperand(1),
3813193323Sed                         N1, N2, N0.getOperand(2));
3814193323Sed    return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3815193323Sed  }
3816193323Sed
3817193323Sed  return SDValue();
3818193323Sed}
3819193323Sed
3820193323SedSDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3821193323Sed  SDValue N0 = N->getOperand(0);
3822193323Sed  SDValue N1 = N->getOperand(1);
3823193323Sed  SDValue N2 = N->getOperand(2);
3824193323Sed  SDValue N3 = N->getOperand(3);
3825193323Sed  SDValue N4 = N->getOperand(4);
3826193323Sed  ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3827193323Sed
3828193323Sed  // fold select_cc lhs, rhs, x, x, cc -> x
3829193323Sed  if (N2 == N3)
3830193323Sed    return N2;
3831193323Sed
3832193323Sed  // Determine if the condition we're dealing with is constant
3833193323Sed  SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3834193323Sed                              N0, N1, CC, N->getDebugLoc(), false);
3835193323Sed  if (SCC.getNode()) AddToWorkList(SCC.getNode());
3836193323Sed
3837193323Sed  if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3838193323Sed    if (!SCCC->isNullValue())
3839193323Sed      return N2;    // cond always true -> true val
3840193323Sed    else
3841193323Sed      return N3;    // cond always false -> false val
3842193323Sed  }
3843193323Sed
3844193323Sed  // Fold to a simpler select_cc
3845193323Sed  if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3846193323Sed    return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3847193323Sed                       SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3848193323Sed                       SCC.getOperand(2));
3849193323Sed
3850193323Sed  // If we can fold this based on the true/false value, do so.
3851193323Sed  if (SimplifySelectOps(N, N2, N3))
3852193323Sed    return SDValue(N, 0);  // Don't revisit N.
3853193323Sed
3854193323Sed  // fold select_cc into other things, such as min/max/abs
3855193323Sed  return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3856193323Sed}
3857193323Sed
3858193323SedSDValue DAGCombiner::visitSETCC(SDNode *N) {
3859193323Sed  return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3860193323Sed                       cast<CondCodeSDNode>(N->getOperand(2))->get(),
3861193323Sed                       N->getDebugLoc());
3862193323Sed}
3863193323Sed
3864193323Sed// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3865193323Sed// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3866193323Sed// transformation. Returns true if extension are possible and the above
3867193323Sed// mentioned transformation is profitable.
3868193323Sedstatic bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3869193323Sed                                    unsigned ExtOpc,
3870193323Sed                                    SmallVector<SDNode*, 4> &ExtendNodes,
3871193323Sed                                    const TargetLowering &TLI) {
3872193323Sed  bool HasCopyToRegUses = false;
3873193323Sed  bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3874193323Sed  for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3875193323Sed                            UE = N0.getNode()->use_end();
3876193323Sed       UI != UE; ++UI) {
3877193323Sed    SDNode *User = *UI;
3878193323Sed    if (User == N)
3879193323Sed      continue;
3880193323Sed    if (UI.getUse().getResNo() != N0.getResNo())
3881193323Sed      continue;
3882193323Sed    // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3883193323Sed    if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3884193323Sed      ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3885193323Sed      if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3886193323Sed        // Sign bits will be lost after a zext.
3887193323Sed        return false;
3888193323Sed      bool Add = false;
3889193323Sed      for (unsigned i = 0; i != 2; ++i) {
3890193323Sed        SDValue UseOp = User->getOperand(i);
3891193323Sed        if (UseOp == N0)
3892193323Sed          continue;
3893193323Sed        if (!isa<ConstantSDNode>(UseOp))
3894193323Sed          return false;
3895193323Sed        Add = true;
3896193323Sed      }
3897193323Sed      if (Add)
3898193323Sed        ExtendNodes.push_back(User);
3899193323Sed      continue;
3900193323Sed    }
3901193323Sed    // If truncates aren't free and there are users we can't
3902193323Sed    // extend, it isn't worthwhile.
3903193323Sed    if (!isTruncFree)
3904193323Sed      return false;
3905193323Sed    // Remember if this value is live-out.
3906193323Sed    if (User->getOpcode() == ISD::CopyToReg)
3907193323Sed      HasCopyToRegUses = true;
3908193323Sed  }
3909193323Sed
3910193323Sed  if (HasCopyToRegUses) {
3911193323Sed    bool BothLiveOut = false;
3912193323Sed    for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3913193323Sed         UI != UE; ++UI) {
3914193323Sed      SDUse &Use = UI.getUse();
3915193323Sed      if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3916193323Sed        BothLiveOut = true;
3917193323Sed        break;
3918193323Sed      }
3919193323Sed    }
3920193323Sed    if (BothLiveOut)
3921193323Sed      // Both unextended and extended values are live out. There had better be
3922218893Sdim      // a good reason for the transformation.
3923193323Sed      return ExtendNodes.size();
3924193323Sed  }
3925193323Sed  return true;
3926193323Sed}
3927193323Sed
3928224145Sdimvoid DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
3929224145Sdim                                  SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
3930224145Sdim                                  ISD::NodeType ExtType) {
3931224145Sdim  // Extend SetCC uses if necessary.
3932224145Sdim  for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3933224145Sdim    SDNode *SetCC = SetCCs[i];
3934224145Sdim    SmallVector<SDValue, 4> Ops;
3935224145Sdim
3936224145Sdim    for (unsigned j = 0; j != 2; ++j) {
3937224145Sdim      SDValue SOp = SetCC->getOperand(j);
3938224145Sdim      if (SOp == Trunc)
3939224145Sdim        Ops.push_back(ExtLoad);
3940224145Sdim      else
3941224145Sdim        Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
3942224145Sdim    }
3943224145Sdim
3944224145Sdim    Ops.push_back(SetCC->getOperand(2));
3945224145Sdim    CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
3946224145Sdim                                 &Ops[0], Ops.size()));
3947224145Sdim  }
3948224145Sdim}
3949224145Sdim
3950193323SedSDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3951193323Sed  SDValue N0 = N->getOperand(0);
3952198090Srdivacky  EVT VT = N->getValueType(0);
3953193323Sed
3954193323Sed  // fold (sext c1) -> c1
3955193323Sed  if (isa<ConstantSDNode>(N0))
3956193323Sed    return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3957193323Sed
3958193323Sed  // fold (sext (sext x)) -> (sext x)
3959193323Sed  // fold (sext (aext x)) -> (sext x)
3960193323Sed  if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3961193323Sed    return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3962193323Sed                       N0.getOperand(0));
3963193323Sed
3964193323Sed  if (N0.getOpcode() == ISD::TRUNCATE) {
3965193323Sed    // fold (sext (truncate (load x))) -> (sext (smaller load x))
3966193323Sed    // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3967193323Sed    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3968193323Sed    if (NarrowLoad.getNode()) {
3969208599Srdivacky      SDNode* oye = N0.getNode()->getOperand(0).getNode();
3970208599Srdivacky      if (NarrowLoad.getNode() != N0.getNode()) {
3971193323Sed        CombineTo(N0.getNode(), NarrowLoad);
3972208599Srdivacky        // CombineTo deleted the truncate, if needed, but not what's under it.
3973208599Srdivacky        AddToWorkList(oye);
3974208599Srdivacky      }
3975193323Sed      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
3976193323Sed    }
3977193323Sed
3978193323Sed    // See if the value being truncated is already sign extended.  If so, just
3979193323Sed    // eliminate the trunc/sext pair.
3980193323Sed    SDValue Op = N0.getOperand(0);
3981202375Srdivacky    unsigned OpBits   = Op.getValueType().getScalarType().getSizeInBits();
3982202375Srdivacky    unsigned MidBits  = N0.getValueType().getScalarType().getSizeInBits();
3983202375Srdivacky    unsigned DestBits = VT.getScalarType().getSizeInBits();
3984193323Sed    unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3985193323Sed
3986193323Sed    if (OpBits == DestBits) {
3987193323Sed      // Op is i32, Mid is i8, and Dest is i32.  If Op has more than 24 sign
3988193323Sed      // bits, it is already ready.
3989193323Sed      if (NumSignBits > DestBits-MidBits)
3990193323Sed        return Op;
3991193323Sed    } else if (OpBits < DestBits) {
3992193323Sed      // Op is i32, Mid is i8, and Dest is i64.  If Op has more than 24 sign
3993193323Sed      // bits, just sext from i32.
3994193323Sed      if (NumSignBits > OpBits-MidBits)
3995193323Sed        return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3996193323Sed    } else {
3997193323Sed      // Op is i64, Mid is i8, and Dest is i32.  If Op has more than 56 sign
3998193323Sed      // bits, just truncate to i32.
3999193323Sed      if (NumSignBits > OpBits-MidBits)
4000193323Sed        return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4001193323Sed    }
4002193323Sed
4003193323Sed    // fold (sext (truncate x)) -> (sextinreg x).
4004193323Sed    if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4005193323Sed                                                 N0.getValueType())) {
4006202375Srdivacky      if (OpBits < DestBits)
4007193323Sed        Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4008202375Srdivacky      else if (OpBits > DestBits)
4009193323Sed        Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4010193323Sed      return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4011202375Srdivacky                         DAG.getValueType(N0.getValueType()));
4012193323Sed    }
4013193323Sed  }
4014193323Sed
4015193323Sed  // fold (sext (load x)) -> (sext (truncate (sextload x)))
4016219077Sdim  // None of the supported targets knows how to perform load and sign extend
4017221345Sdim  // on vectors in one instruction.  We only perform this transformation on
4018221345Sdim  // scalars.
4019219077Sdim  if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4020193323Sed      ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4021193323Sed       TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4022193323Sed    bool DoXform = true;
4023193323Sed    SmallVector<SDNode*, 4> SetCCs;
4024193323Sed    if (!N0.hasOneUse())
4025193323Sed      DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4026193323Sed    if (DoXform) {
4027193323Sed      LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4028218893Sdim      SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4029193323Sed                                       LN0->getChain(),
4030218893Sdim                                       LN0->getBasePtr(), LN0->getPointerInfo(),
4031193323Sed                                       N0.getValueType(),
4032203954Srdivacky                                       LN0->isVolatile(), LN0->isNonTemporal(),
4033203954Srdivacky                                       LN0->getAlignment());
4034193323Sed      CombineTo(N, ExtLoad);
4035193323Sed      SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4036193323Sed                                  N0.getValueType(), ExtLoad);
4037193323Sed      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4038224145Sdim      ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4039224145Sdim                      ISD::SIGN_EXTEND);
4040193323Sed      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4041193323Sed    }
4042193323Sed  }
4043193323Sed
4044193323Sed  // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4045193323Sed  // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4046193323Sed  if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4047193323Sed      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4048193323Sed    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4049198090Srdivacky    EVT MemVT = LN0->getMemoryVT();
4050193323Sed    if ((!LegalOperations && !LN0->isVolatile()) ||
4051198090Srdivacky        TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4052218893Sdim      SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4053193323Sed                                       LN0->getChain(),
4054218893Sdim                                       LN0->getBasePtr(), LN0->getPointerInfo(),
4055218893Sdim                                       MemVT,
4056203954Srdivacky                                       LN0->isVolatile(), LN0->isNonTemporal(),
4057203954Srdivacky                                       LN0->getAlignment());
4058193323Sed      CombineTo(N, ExtLoad);
4059193323Sed      CombineTo(N0.getNode(),
4060193323Sed                DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4061193323Sed                            N0.getValueType(), ExtLoad),
4062193323Sed                ExtLoad.getValue(1));
4063193323Sed      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4064193323Sed    }
4065193323Sed  }
4066193323Sed
4067224145Sdim  // fold (sext (and/or/xor (load x), cst)) ->
4068224145Sdim  //      (and/or/xor (sextload x), (sext cst))
4069224145Sdim  if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4070224145Sdim       N0.getOpcode() == ISD::XOR) &&
4071224145Sdim      isa<LoadSDNode>(N0.getOperand(0)) &&
4072224145Sdim      N0.getOperand(1).getOpcode() == ISD::Constant &&
4073224145Sdim      TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4074224145Sdim      (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4075224145Sdim    LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4076224145Sdim    if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4077224145Sdim      bool DoXform = true;
4078224145Sdim      SmallVector<SDNode*, 4> SetCCs;
4079224145Sdim      if (!N0.hasOneUse())
4080224145Sdim        DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4081224145Sdim                                          SetCCs, TLI);
4082224145Sdim      if (DoXform) {
4083224145Sdim        SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4084224145Sdim                                         LN0->getChain(), LN0->getBasePtr(),
4085224145Sdim                                         LN0->getPointerInfo(),
4086224145Sdim                                         LN0->getMemoryVT(),
4087224145Sdim                                         LN0->isVolatile(),
4088224145Sdim                                         LN0->isNonTemporal(),
4089224145Sdim                                         LN0->getAlignment());
4090224145Sdim        APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4091224145Sdim        Mask = Mask.sext(VT.getSizeInBits());
4092224145Sdim        SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4093224145Sdim                                  ExtLoad, DAG.getConstant(Mask, VT));
4094224145Sdim        SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4095224145Sdim                                    N0.getOperand(0).getDebugLoc(),
4096224145Sdim                                    N0.getOperand(0).getValueType(), ExtLoad);
4097224145Sdim        CombineTo(N, And);
4098224145Sdim        CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4099224145Sdim        ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4100224145Sdim                        ISD::SIGN_EXTEND);
4101224145Sdim        return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4102224145Sdim      }
4103224145Sdim    }
4104224145Sdim  }
4105224145Sdim
4106193323Sed  if (N0.getOpcode() == ISD::SETCC) {
4107198090Srdivacky    // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4108207618Srdivacky    // Only do this before legalize for now.
4109207618Srdivacky    if (VT.isVector() && !LegalOperations) {
4110207618Srdivacky      EVT N0VT = N0.getOperand(0).getValueType();
4111198090Srdivacky        // We know that the # elements of the results is the same as the
4112198090Srdivacky        // # elements of the compare (and the # elements of the compare result
4113198090Srdivacky        // for that matter).  Check to see that they are the same size.  If so,
4114198090Srdivacky        // we know that the element size of the sext'd result matches the
4115198090Srdivacky        // element size of the compare operands.
4116207618Srdivacky      if (VT.getSizeInBits() == N0VT.getSizeInBits())
4117226633Sdim        return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4118210299Sed                             N0.getOperand(1),
4119210299Sed                             cast<CondCodeSDNode>(N0.getOperand(2))->get());
4120207618Srdivacky      // If the desired elements are smaller or larger than the source
4121207618Srdivacky      // elements we can use a matching integer vector type and then
4122207618Srdivacky      // truncate/sign extend
4123207618Srdivacky      else {
4124210299Sed        EVT MatchingElementType =
4125210299Sed          EVT::getIntegerVT(*DAG.getContext(),
4126210299Sed                            N0VT.getScalarType().getSizeInBits());
4127210299Sed        EVT MatchingVectorType =
4128210299Sed          EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4129210299Sed                           N0VT.getVectorNumElements());
4130210299Sed        SDValue VsetCC =
4131226633Sdim          DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4132210299Sed                        N0.getOperand(1),
4133210299Sed                        cast<CondCodeSDNode>(N0.getOperand(2))->get());
4134210299Sed        return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4135207618Srdivacky      }
4136198090Srdivacky    }
4137207618Srdivacky
4138198090Srdivacky    // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4139207618Srdivacky    unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4140198090Srdivacky    SDValue NegOne =
4141207618Srdivacky      DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4142193323Sed    SDValue SCC =
4143193323Sed      SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4144198090Srdivacky                       NegOne, DAG.getConstant(0, VT),
4145193323Sed                       cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4146193323Sed    if (SCC.getNode()) return SCC;
4147203954Srdivacky    if (!LegalOperations ||
4148203954Srdivacky        TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4149203954Srdivacky      return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4150203954Srdivacky                         DAG.getSetCC(N->getDebugLoc(),
4151203954Srdivacky                                      TLI.getSetCCResultType(VT),
4152203954Srdivacky                                      N0.getOperand(0), N0.getOperand(1),
4153203954Srdivacky                                 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4154203954Srdivacky                         NegOne, DAG.getConstant(0, VT));
4155218893Sdim  }
4156193323Sed
4157193323Sed  // fold (sext x) -> (zext x) if the sign bit is known zero.
4158193323Sed  if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4159193323Sed      DAG.SignBitIsZero(N0))
4160193323Sed    return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4161193323Sed
4162193323Sed  return SDValue();
4163193323Sed}
4164193323Sed
4165193323SedSDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4166193323Sed  SDValue N0 = N->getOperand(0);
4167198090Srdivacky  EVT VT = N->getValueType(0);
4168193323Sed
4169193323Sed  // fold (zext c1) -> c1
4170193323Sed  if (isa<ConstantSDNode>(N0))
4171193323Sed    return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4172193323Sed  // fold (zext (zext x)) -> (zext x)
4173193323Sed  // fold (zext (aext x)) -> (zext x)
4174193323Sed  if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4175193323Sed    return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4176193323Sed                       N0.getOperand(0));
4177193323Sed
4178193323Sed  // fold (zext (truncate (load x))) -> (zext (smaller load x))
4179193323Sed  // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4180193323Sed  if (N0.getOpcode() == ISD::TRUNCATE) {
4181193323Sed    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4182193323Sed    if (NarrowLoad.getNode()) {
4183208599Srdivacky      SDNode* oye = N0.getNode()->getOperand(0).getNode();
4184208599Srdivacky      if (NarrowLoad.getNode() != N0.getNode()) {
4185193323Sed        CombineTo(N0.getNode(), NarrowLoad);
4186208599Srdivacky        // CombineTo deleted the truncate, if needed, but not what's under it.
4187208599Srdivacky        AddToWorkList(oye);
4188208599Srdivacky      }
4189221345Sdim      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4190193323Sed    }
4191193323Sed  }
4192193323Sed
4193193323Sed  // fold (zext (truncate x)) -> (and x, mask)
4194193323Sed  if (N0.getOpcode() == ISD::TRUNCATE &&
4195210299Sed      (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4196218893Sdim
4197218893Sdim    // fold (zext (truncate (load x))) -> (zext (smaller load x))
4198218893Sdim    // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4199218893Sdim    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4200218893Sdim    if (NarrowLoad.getNode()) {
4201218893Sdim      SDNode* oye = N0.getNode()->getOperand(0).getNode();
4202218893Sdim      if (NarrowLoad.getNode() != N0.getNode()) {
4203218893Sdim        CombineTo(N0.getNode(), NarrowLoad);
4204218893Sdim        // CombineTo deleted the truncate, if needed, but not what's under it.
4205218893Sdim        AddToWorkList(oye);
4206218893Sdim      }
4207218893Sdim      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4208218893Sdim    }
4209218893Sdim
4210193323Sed    SDValue Op = N0.getOperand(0);
4211193323Sed    if (Op.getValueType().bitsLT(VT)) {
4212193323Sed      Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4213193323Sed    } else if (Op.getValueType().bitsGT(VT)) {
4214193323Sed      Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4215193323Sed    }
4216200581Srdivacky    return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4217200581Srdivacky                                  N0.getValueType().getScalarType());
4218193323Sed  }
4219193323Sed
4220193323Sed  // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4221193323Sed  // if either of the casts is not free.
4222193323Sed  if (N0.getOpcode() == ISD::AND &&
4223193323Sed      N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4224193323Sed      N0.getOperand(1).getOpcode() == ISD::Constant &&
4225193323Sed      (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4226193323Sed                           N0.getValueType()) ||
4227193323Sed       !TLI.isZExtFree(N0.getValueType(), VT))) {
4228193323Sed    SDValue X = N0.getOperand(0).getOperand(0);
4229193323Sed    if (X.getValueType().bitsLT(VT)) {
4230193323Sed      X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4231193323Sed    } else if (X.getValueType().bitsGT(VT)) {
4232193323Sed      X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4233193323Sed    }
4234193323Sed    APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4235218893Sdim    Mask = Mask.zext(VT.getSizeInBits());
4236193323Sed    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4237193323Sed                       X, DAG.getConstant(Mask, VT));
4238193323Sed  }
4239193323Sed
4240193323Sed  // fold (zext (load x)) -> (zext (truncate (zextload x)))
4241219077Sdim  // None of the supported targets knows how to perform load and vector_zext
4242221345Sdim  // on vectors in one instruction.  We only perform this transformation on
4243221345Sdim  // scalars.
4244219077Sdim  if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4245193323Sed      ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4246193323Sed       TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4247193323Sed    bool DoXform = true;
4248193323Sed    SmallVector<SDNode*, 4> SetCCs;
4249193323Sed    if (!N0.hasOneUse())
4250193323Sed      DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4251193323Sed    if (DoXform) {
4252193323Sed      LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4253218893Sdim      SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4254193323Sed                                       LN0->getChain(),
4255218893Sdim                                       LN0->getBasePtr(), LN0->getPointerInfo(),
4256193323Sed                                       N0.getValueType(),
4257203954Srdivacky                                       LN0->isVolatile(), LN0->isNonTemporal(),
4258203954Srdivacky                                       LN0->getAlignment());
4259193323Sed      CombineTo(N, ExtLoad);
4260193323Sed      SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4261193323Sed                                  N0.getValueType(), ExtLoad);
4262193323Sed      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4263193323Sed
4264224145Sdim      ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4265224145Sdim                      ISD::ZERO_EXTEND);
4266224145Sdim      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4267224145Sdim    }
4268224145Sdim  }
4269193323Sed
4270224145Sdim  // fold (zext (and/or/xor (load x), cst)) ->
4271224145Sdim  //      (and/or/xor (zextload x), (zext cst))
4272224145Sdim  if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4273224145Sdim       N0.getOpcode() == ISD::XOR) &&
4274224145Sdim      isa<LoadSDNode>(N0.getOperand(0)) &&
4275224145Sdim      N0.getOperand(1).getOpcode() == ISD::Constant &&
4276224145Sdim      TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4277224145Sdim      (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4278224145Sdim    LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4279224145Sdim    if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4280224145Sdim      bool DoXform = true;
4281224145Sdim      SmallVector<SDNode*, 4> SetCCs;
4282224145Sdim      if (!N0.hasOneUse())
4283224145Sdim        DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4284224145Sdim                                          SetCCs, TLI);
4285224145Sdim      if (DoXform) {
4286224145Sdim        SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4287224145Sdim                                         LN0->getChain(), LN0->getBasePtr(),
4288224145Sdim                                         LN0->getPointerInfo(),
4289224145Sdim                                         LN0->getMemoryVT(),
4290224145Sdim                                         LN0->isVolatile(),
4291224145Sdim                                         LN0->isNonTemporal(),
4292224145Sdim                                         LN0->getAlignment());
4293224145Sdim        APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4294224145Sdim        Mask = Mask.zext(VT.getSizeInBits());
4295224145Sdim        SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4296224145Sdim                                  ExtLoad, DAG.getConstant(Mask, VT));
4297224145Sdim        SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4298224145Sdim                                    N0.getOperand(0).getDebugLoc(),
4299224145Sdim                                    N0.getOperand(0).getValueType(), ExtLoad);
4300224145Sdim        CombineTo(N, And);
4301224145Sdim        CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4302224145Sdim        ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4303224145Sdim                        ISD::ZERO_EXTEND);
4304224145Sdim        return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4305193323Sed      }
4306193323Sed    }
4307193323Sed  }
4308193323Sed
4309193323Sed  // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4310193323Sed  // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4311193323Sed  if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4312193323Sed      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4313193323Sed    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4314198090Srdivacky    EVT MemVT = LN0->getMemoryVT();
4315193323Sed    if ((!LegalOperations && !LN0->isVolatile()) ||
4316198090Srdivacky        TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4317218893Sdim      SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4318193323Sed                                       LN0->getChain(),
4319218893Sdim                                       LN0->getBasePtr(), LN0->getPointerInfo(),
4320218893Sdim                                       MemVT,
4321203954Srdivacky                                       LN0->isVolatile(), LN0->isNonTemporal(),
4322203954Srdivacky                                       LN0->getAlignment());
4323193323Sed      CombineTo(N, ExtLoad);
4324193323Sed      CombineTo(N0.getNode(),
4325193323Sed                DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4326193323Sed                            ExtLoad),
4327193323Sed                ExtLoad.getValue(1));
4328193323Sed      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4329193323Sed    }
4330193323Sed  }
4331193323Sed
4332193323Sed  if (N0.getOpcode() == ISD::SETCC) {
4333208599Srdivacky    if (!LegalOperations && VT.isVector()) {
4334208599Srdivacky      // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4335208599Srdivacky      // Only do this before legalize for now.
4336208599Srdivacky      EVT N0VT = N0.getOperand(0).getValueType();
4337208599Srdivacky      EVT EltVT = VT.getVectorElementType();
4338208599Srdivacky      SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4339208599Srdivacky                                    DAG.getConstant(1, EltVT));
4340223017Sdim      if (VT.getSizeInBits() == N0VT.getSizeInBits())
4341208599Srdivacky        // We know that the # elements of the results is the same as the
4342208599Srdivacky        // # elements of the compare (and the # elements of the compare result
4343208599Srdivacky        // for that matter).  Check to see that they are the same size.  If so,
4344208599Srdivacky        // we know that the element size of the sext'd result matches the
4345208599Srdivacky        // element size of the compare operands.
4346208599Srdivacky        return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4347226633Sdim                           DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4348208599Srdivacky                                         N0.getOperand(1),
4349208599Srdivacky                                 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4350208599Srdivacky                           DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4351208599Srdivacky                                       &OneOps[0], OneOps.size()));
4352223017Sdim
4353223017Sdim      // If the desired elements are smaller or larger than the source
4354223017Sdim      // elements we can use a matching integer vector type and then
4355223017Sdim      // truncate/sign extend
4356223017Sdim      EVT MatchingElementType =
4357223017Sdim        EVT::getIntegerVT(*DAG.getContext(),
4358223017Sdim                          N0VT.getScalarType().getSizeInBits());
4359223017Sdim      EVT MatchingVectorType =
4360223017Sdim        EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4361223017Sdim                         N0VT.getVectorNumElements());
4362223017Sdim      SDValue VsetCC =
4363226633Sdim        DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4364223017Sdim                      N0.getOperand(1),
4365223017Sdim                      cast<CondCodeSDNode>(N0.getOperand(2))->get());
4366223017Sdim      return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4367223017Sdim                         DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4368223017Sdim                         DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4369223017Sdim                                     &OneOps[0], OneOps.size()));
4370208599Srdivacky    }
4371208599Srdivacky
4372208599Srdivacky    // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4373193323Sed    SDValue SCC =
4374193323Sed      SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4375193323Sed                       DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4376193323Sed                       cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4377193323Sed    if (SCC.getNode()) return SCC;
4378193323Sed  }
4379193323Sed
4380200581Srdivacky  // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4381200581Srdivacky  if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4382200581Srdivacky      isa<ConstantSDNode>(N0.getOperand(1)) &&
4383200581Srdivacky      N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4384200581Srdivacky      N0.hasOneUse()) {
4385218893Sdim    SDValue ShAmt = N0.getOperand(1);
4386218893Sdim    unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4387200581Srdivacky    if (N0.getOpcode() == ISD::SHL) {
4388218893Sdim      SDValue InnerZExt = N0.getOperand(0);
4389200581Srdivacky      // If the original shl may be shifting out bits, do not perform this
4390200581Srdivacky      // transformation.
4391218893Sdim      unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4392218893Sdim        InnerZExt.getOperand(0).getValueType().getSizeInBits();
4393218893Sdim      if (ShAmtVal > KnownZeroBits)
4394200581Srdivacky        return SDValue();
4395200581Srdivacky    }
4396218893Sdim
4397218893Sdim    DebugLoc DL = N->getDebugLoc();
4398219077Sdim
4399219077Sdim    // Ensure that the shift amount is wide enough for the shifted value.
4400218893Sdim    if (VT.getSizeInBits() >= 256)
4401218893Sdim      ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4402219077Sdim
4403218893Sdim    return DAG.getNode(N0.getOpcode(), DL, VT,
4404218893Sdim                       DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4405218893Sdim                       ShAmt);
4406200581Srdivacky  }
4407200581Srdivacky
4408193323Sed  return SDValue();
4409193323Sed}
4410193323Sed
4411193323SedSDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4412193323Sed  SDValue N0 = N->getOperand(0);
4413198090Srdivacky  EVT VT = N->getValueType(0);
4414193323Sed
4415193323Sed  // fold (aext c1) -> c1
4416193323Sed  if (isa<ConstantSDNode>(N0))
4417193323Sed    return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4418193323Sed  // fold (aext (aext x)) -> (aext x)
4419193323Sed  // fold (aext (zext x)) -> (zext x)
4420193323Sed  // fold (aext (sext x)) -> (sext x)
4421193323Sed  if (N0.getOpcode() == ISD::ANY_EXTEND  ||
4422193323Sed      N0.getOpcode() == ISD::ZERO_EXTEND ||
4423193323Sed      N0.getOpcode() == ISD::SIGN_EXTEND)
4424193323Sed    return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4425193323Sed
4426193323Sed  // fold (aext (truncate (load x))) -> (aext (smaller load x))
4427193323Sed  // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4428193323Sed  if (N0.getOpcode() == ISD::TRUNCATE) {
4429193323Sed    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4430193323Sed    if (NarrowLoad.getNode()) {
4431208599Srdivacky      SDNode* oye = N0.getNode()->getOperand(0).getNode();
4432208599Srdivacky      if (NarrowLoad.getNode() != N0.getNode()) {
4433193323Sed        CombineTo(N0.getNode(), NarrowLoad);
4434208599Srdivacky        // CombineTo deleted the truncate, if needed, but not what's under it.
4435208599Srdivacky        AddToWorkList(oye);
4436208599Srdivacky      }
4437221345Sdim      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4438193323Sed    }
4439193323Sed  }
4440193323Sed
4441193323Sed  // fold (aext (truncate x))
4442193323Sed  if (N0.getOpcode() == ISD::TRUNCATE) {
4443193323Sed    SDValue TruncOp = N0.getOperand(0);
4444193323Sed    if (TruncOp.getValueType() == VT)
4445193323Sed      return TruncOp; // x iff x size == zext size.
4446193323Sed    if (TruncOp.getValueType().bitsGT(VT))
4447193323Sed      return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4448193323Sed    return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4449193323Sed  }
4450193323Sed
4451193323Sed  // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4452193323Sed  // if the trunc is not free.
4453193323Sed  if (N0.getOpcode() == ISD::AND &&
4454193323Sed      N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4455193323Sed      N0.getOperand(1).getOpcode() == ISD::Constant &&
4456193323Sed      !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4457193323Sed                          N0.getValueType())) {
4458193323Sed    SDValue X = N0.getOperand(0).getOperand(0);
4459193323Sed    if (X.getValueType().bitsLT(VT)) {
4460193323Sed      X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4461193323Sed    } else if (X.getValueType().bitsGT(VT)) {
4462193323Sed      X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4463193323Sed    }
4464193323Sed    APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4465218893Sdim    Mask = Mask.zext(VT.getSizeInBits());
4466193323Sed    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4467193323Sed                       X, DAG.getConstant(Mask, VT));
4468193323Sed  }
4469193323Sed
4470193323Sed  // fold (aext (load x)) -> (aext (truncate (extload x)))
4471219077Sdim  // None of the supported targets knows how to perform load and any_ext
4472221345Sdim  // on vectors in one instruction.  We only perform this transformation on
4473221345Sdim  // scalars.
4474219077Sdim  if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4475193323Sed      ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4476193323Sed       TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4477193323Sed    bool DoXform = true;
4478193323Sed    SmallVector<SDNode*, 4> SetCCs;
4479193323Sed    if (!N0.hasOneUse())
4480193323Sed      DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4481193323Sed    if (DoXform) {
4482193323Sed      LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4483218893Sdim      SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4484193323Sed                                       LN0->getChain(),
4485218893Sdim                                       LN0->getBasePtr(), LN0->getPointerInfo(),
4486193323Sed                                       N0.getValueType(),
4487203954Srdivacky                                       LN0->isVolatile(), LN0->isNonTemporal(),
4488203954Srdivacky                                       LN0->getAlignment());
4489193323Sed      CombineTo(N, ExtLoad);
4490193323Sed      SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4491193323Sed                                  N0.getValueType(), ExtLoad);
4492193323Sed      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4493224145Sdim      ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4494224145Sdim                      ISD::ANY_EXTEND);
4495193323Sed      return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4496193323Sed    }
4497193323Sed  }
4498193323Sed
4499193323Sed  // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4500193323Sed  // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4501193323Sed  // fold (aext ( extload x)) -> (aext (truncate (extload  x)))
4502193323Sed  if (N0.getOpcode() == ISD::LOAD &&
4503193323Sed      !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4504193323Sed      N0.hasOneUse()) {
4505193323Sed    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4506198090Srdivacky    EVT MemVT = LN0->getMemoryVT();
4507218893Sdim    SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4508218893Sdim                                     VT, LN0->getChain(), LN0->getBasePtr(),
4509218893Sdim                                     LN0->getPointerInfo(), MemVT,
4510203954Srdivacky                                     LN0->isVolatile(), LN0->isNonTemporal(),
4511203954Srdivacky                                     LN0->getAlignment());
4512193323Sed    CombineTo(N, ExtLoad);
4513193323Sed    CombineTo(N0.getNode(),
4514193323Sed              DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4515193323Sed                          N0.getValueType(), ExtLoad),
4516193323Sed              ExtLoad.getValue(1));
4517193323Sed    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4518193323Sed  }
4519193323Sed
4520193323Sed  if (N0.getOpcode() == ISD::SETCC) {
4521208599Srdivacky    // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4522208599Srdivacky    // Only do this before legalize for now.
4523208599Srdivacky    if (VT.isVector() && !LegalOperations) {
4524208599Srdivacky      EVT N0VT = N0.getOperand(0).getValueType();
4525208599Srdivacky        // We know that the # elements of the results is the same as the
4526208599Srdivacky        // # elements of the compare (and the # elements of the compare result
4527208599Srdivacky        // for that matter).  Check to see that they are the same size.  If so,
4528208599Srdivacky        // we know that the element size of the sext'd result matches the
4529208599Srdivacky        // element size of the compare operands.
4530208599Srdivacky      if (VT.getSizeInBits() == N0VT.getSizeInBits())
4531226633Sdim        return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4532210299Sed                             N0.getOperand(1),
4533210299Sed                             cast<CondCodeSDNode>(N0.getOperand(2))->get());
4534208599Srdivacky      // If the desired elements are smaller or larger than the source
4535208599Srdivacky      // elements we can use a matching integer vector type and then
4536208599Srdivacky      // truncate/sign extend
4537208599Srdivacky      else {
4538210299Sed        EVT MatchingElementType =
4539210299Sed          EVT::getIntegerVT(*DAG.getContext(),
4540210299Sed                            N0VT.getScalarType().getSizeInBits());
4541210299Sed        EVT MatchingVectorType =
4542210299Sed          EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4543210299Sed                           N0VT.getVectorNumElements());
4544210299Sed        SDValue VsetCC =
4545226633Sdim          DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4546210299Sed                        N0.getOperand(1),
4547210299Sed                        cast<CondCodeSDNode>(N0.getOperand(2))->get());
4548210299Sed        return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4549208599Srdivacky      }
4550208599Srdivacky    }
4551208599Srdivacky
4552208599Srdivacky    // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4553193323Sed    SDValue SCC =
4554193323Sed      SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4555193323Sed                       DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4556193323Sed                       cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4557193323Sed    if (SCC.getNode())
4558193323Sed      return SCC;
4559193323Sed  }
4560193323Sed
4561193323Sed  return SDValue();
4562193323Sed}
4563193323Sed
4564193323Sed/// GetDemandedBits - See if the specified operand can be simplified with the
4565193323Sed/// knowledge that only the bits specified by Mask are used.  If so, return the
4566193323Sed/// simpler operand, otherwise return a null SDValue.
4567193323SedSDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4568193323Sed  switch (V.getOpcode()) {
4569193323Sed  default: break;
4570193323Sed  case ISD::OR:
4571193323Sed  case ISD::XOR:
4572193323Sed    // If the LHS or RHS don't contribute bits to the or, drop them.
4573193323Sed    if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4574193323Sed      return V.getOperand(1);
4575193323Sed    if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4576193323Sed      return V.getOperand(0);
4577193323Sed    break;
4578193323Sed  case ISD::SRL:
4579193323Sed    // Only look at single-use SRLs.
4580193323Sed    if (!V.getNode()->hasOneUse())
4581193323Sed      break;
4582193323Sed    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4583193323Sed      // See if we can recursively simplify the LHS.
4584193323Sed      unsigned Amt = RHSC->getZExtValue();
4585193323Sed
4586193323Sed      // Watch out for shift count overflow though.
4587193323Sed      if (Amt >= Mask.getBitWidth()) break;
4588193323Sed      APInt NewMask = Mask << Amt;
4589193323Sed      SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4590193323Sed      if (SimplifyLHS.getNode())
4591193323Sed        return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4592193323Sed                           SimplifyLHS, V.getOperand(1));
4593193323Sed    }
4594193323Sed  }
4595193323Sed  return SDValue();
4596193323Sed}
4597193323Sed
4598193323Sed/// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4599193323Sed/// bits and then truncated to a narrower type and where N is a multiple
4600193323Sed/// of number of bits of the narrower type, transform it to a narrower load
4601193323Sed/// from address + N / num of bits of new type. If the result is to be
4602193323Sed/// extended, also fold the extension to form a extending load.
4603193323SedSDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4604193323Sed  unsigned Opc = N->getOpcode();
4605210299Sed
4606193323Sed  ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4607193323Sed  SDValue N0 = N->getOperand(0);
4608198090Srdivacky  EVT VT = N->getValueType(0);
4609198090Srdivacky  EVT ExtVT = VT;
4610193323Sed
4611193323Sed  // This transformation isn't valid for vector loads.
4612193323Sed  if (VT.isVector())
4613193323Sed    return SDValue();
4614193323Sed
4615202375Srdivacky  // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4616193323Sed  // extended to VT.
4617193323Sed  if (Opc == ISD::SIGN_EXTEND_INREG) {
4618193323Sed    ExtType = ISD::SEXTLOAD;
4619198090Srdivacky    ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4620210299Sed  } else if (Opc == ISD::SRL) {
4621218893Sdim    // Another special-case: SRL is basically zero-extending a narrower value.
4622210299Sed    ExtType = ISD::ZEXTLOAD;
4623210299Sed    N0 = SDValue(N, 0);
4624210299Sed    ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4625210299Sed    if (!N01) return SDValue();
4626210299Sed    ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4627210299Sed                              VT.getSizeInBits() - N01->getZExtValue());
4628193323Sed  }
4629218893Sdim  if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4630218893Sdim    return SDValue();
4631193323Sed
4632198090Srdivacky  unsigned EVTBits = ExtVT.getSizeInBits();
4633219077Sdim
4634218893Sdim  // Do not generate loads of non-round integer types since these can
4635218893Sdim  // be expensive (and would be wrong if the type is not byte sized).
4636218893Sdim  if (!ExtVT.isRound())
4637218893Sdim    return SDValue();
4638219077Sdim
4639193323Sed  unsigned ShAmt = 0;
4640218893Sdim  if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4641193323Sed    if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4642193323Sed      ShAmt = N01->getZExtValue();
4643193323Sed      // Is the shift amount a multiple of size of VT?
4644193323Sed      if ((ShAmt & (EVTBits-1)) == 0) {
4645193323Sed        N0 = N0.getOperand(0);
4646198090Srdivacky        // Is the load width a multiple of size of VT?
4647198090Srdivacky        if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4648193323Sed          return SDValue();
4649193323Sed      }
4650218893Sdim
4651218893Sdim      // At this point, we must have a load or else we can't do the transform.
4652218893Sdim      if (!isa<LoadSDNode>(N0)) return SDValue();
4653219077Sdim
4654218893Sdim      // If the shift amount is larger than the input type then we're not
4655218893Sdim      // accessing any of the loaded bytes.  If the load was a zextload/extload
4656218893Sdim      // then the result of the shift+trunc is zero/undef (handled elsewhere).
4657218893Sdim      // If the load was a sextload then the result is a splat of the sign bit
4658218893Sdim      // of the extended byte.  This is not worth optimizing for.
4659218893Sdim      if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4660218893Sdim        return SDValue();
4661193323Sed    }
4662193323Sed  }
4663193323Sed
4664218893Sdim  // If the load is shifted left (and the result isn't shifted back right),
4665218893Sdim  // we can fold the truncate through the shift.
4666218893Sdim  unsigned ShLeftAmt = 0;
4667218893Sdim  if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4668218893Sdim      ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4669218893Sdim    if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4670218893Sdim      ShLeftAmt = N01->getZExtValue();
4671218893Sdim      N0 = N0.getOperand(0);
4672193323Sed    }
4673218893Sdim  }
4674219077Sdim
4675218893Sdim  // If we haven't found a load, we can't narrow it.  Don't transform one with
4676218893Sdim  // multiple uses, this would require adding a new load.
4677218893Sdim  if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4678218893Sdim      // Don't change the width of a volatile load.
4679218893Sdim      cast<LoadSDNode>(N0)->isVolatile())
4680218893Sdim    return SDValue();
4681219077Sdim
4682218893Sdim  // Verify that we are actually reducing a load width here.
4683218893Sdim  if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4684218893Sdim    return SDValue();
4685219077Sdim
4686218893Sdim  LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4687218893Sdim  EVT PtrType = N0.getOperand(1).getValueType();
4688193323Sed
4689218893Sdim  // For big endian targets, we need to adjust the offset to the pointer to
4690218893Sdim  // load the correct bytes.
4691218893Sdim  if (TLI.isBigEndian()) {
4692218893Sdim    unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4693218893Sdim    unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4694218893Sdim    ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4695218893Sdim  }
4696193323Sed
4697218893Sdim  uint64_t PtrOff = ShAmt / 8;
4698218893Sdim  unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4699218893Sdim  SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4700218893Sdim                               PtrType, LN0->getBasePtr(),
4701218893Sdim                               DAG.getConstant(PtrOff, PtrType));
4702218893Sdim  AddToWorkList(NewPtr.getNode());
4703193323Sed
4704218893Sdim  SDValue Load;
4705218893Sdim  if (ExtType == ISD::NON_EXTLOAD)
4706218893Sdim    Load =  DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4707218893Sdim                        LN0->getPointerInfo().getWithOffset(PtrOff),
4708218893Sdim                        LN0->isVolatile(), LN0->isNonTemporal(), NewAlign);
4709218893Sdim  else
4710218893Sdim    Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4711218893Sdim                          LN0->getPointerInfo().getWithOffset(PtrOff),
4712218893Sdim                          ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4713218893Sdim                          NewAlign);
4714193323Sed
4715218893Sdim  // Replace the old load's chain with the new load's chain.
4716218893Sdim  WorkListRemover DeadNodes(*this);
4717218893Sdim  DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4718218893Sdim                                &DeadNodes);
4719218893Sdim
4720218893Sdim  // Shift the result left, if we've swallowed a left shift.
4721218893Sdim  SDValue Result = Load;
4722218893Sdim  if (ShLeftAmt != 0) {
4723219077Sdim    EVT ShImmTy = getShiftAmountTy(Result.getValueType());
4724218893Sdim    if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4725218893Sdim      ShImmTy = VT;
4726218893Sdim    Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4727218893Sdim                         Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4728193323Sed  }
4729193323Sed
4730218893Sdim  // Return the new loaded value.
4731218893Sdim  return Result;
4732193323Sed}
4733193323Sed
4734193323SedSDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4735193323Sed  SDValue N0 = N->getOperand(0);
4736193323Sed  SDValue N1 = N->getOperand(1);
4737198090Srdivacky  EVT VT = N->getValueType(0);
4738198090Srdivacky  EVT EVT = cast<VTSDNode>(N1)->getVT();
4739200581Srdivacky  unsigned VTBits = VT.getScalarType().getSizeInBits();
4740202375Srdivacky  unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4741193323Sed
4742193323Sed  // fold (sext_in_reg c1) -> c1
4743193323Sed  if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4744193323Sed    return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4745193323Sed
4746193323Sed  // If the input is already sign extended, just drop the extension.
4747200581Srdivacky  if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4748193323Sed    return N0;
4749193323Sed
4750193323Sed  // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4751193323Sed  if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4752193323Sed      EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4753193323Sed    return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4754193323Sed                       N0.getOperand(0), N1);
4755193323Sed  }
4756193323Sed
4757193323Sed  // fold (sext_in_reg (sext x)) -> (sext x)
4758193323Sed  // fold (sext_in_reg (aext x)) -> (sext x)
4759193323Sed  // if x is small enough.
4760193323Sed  if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4761193323Sed    SDValue N00 = N0.getOperand(0);
4762207618Srdivacky    if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4763207618Srdivacky        (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4764193323Sed      return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4765193323Sed  }
4766193323Sed
4767193323Sed  // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4768193323Sed  if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4769193323Sed    return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4770193323Sed
4771193323Sed  // fold operands of sext_in_reg based on knowledge that the top bits are not
4772193323Sed  // demanded.
4773193323Sed  if (SimplifyDemandedBits(SDValue(N, 0)))
4774193323Sed    return SDValue(N, 0);
4775193323Sed
4776193323Sed  // fold (sext_in_reg (load x)) -> (smaller sextload x)
4777193323Sed  // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4778193323Sed  SDValue NarrowLoad = ReduceLoadWidth(N);
4779193323Sed  if (NarrowLoad.getNode())
4780193323Sed    return NarrowLoad;
4781193323Sed
4782193323Sed  // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4783193323Sed  // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4784193323Sed  // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4785193323Sed  if (N0.getOpcode() == ISD::SRL) {
4786193323Sed    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4787200581Srdivacky      if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4788193323Sed        // We can turn this into an SRA iff the input to the SRL is already sign
4789193323Sed        // extended enough.
4790193323Sed        unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4791200581Srdivacky        if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4792193323Sed          return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4793193323Sed                             N0.getOperand(0), N0.getOperand(1));
4794193323Sed      }
4795193323Sed  }
4796193323Sed
4797193323Sed  // fold (sext_inreg (extload x)) -> (sextload x)
4798193323Sed  if (ISD::isEXTLoad(N0.getNode()) &&
4799193323Sed      ISD::isUNINDEXEDLoad(N0.getNode()) &&
4800193323Sed      EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4801193323Sed      ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4802193323Sed       TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4803193323Sed    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4804218893Sdim    SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4805193323Sed                                     LN0->getChain(),
4806218893Sdim                                     LN0->getBasePtr(), LN0->getPointerInfo(),
4807218893Sdim                                     EVT,
4808203954Srdivacky                                     LN0->isVolatile(), LN0->isNonTemporal(),
4809203954Srdivacky                                     LN0->getAlignment());
4810193323Sed    CombineTo(N, ExtLoad);
4811193323Sed    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4812193323Sed    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4813193323Sed  }
4814193323Sed  // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4815193323Sed  if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4816193323Sed      N0.hasOneUse() &&
4817193323Sed      EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4818193323Sed      ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4819193323Sed       TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4820193323Sed    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4821218893Sdim    SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4822193323Sed                                     LN0->getChain(),
4823218893Sdim                                     LN0->getBasePtr(), LN0->getPointerInfo(),
4824218893Sdim                                     EVT,
4825203954Srdivacky                                     LN0->isVolatile(), LN0->isNonTemporal(),
4826203954Srdivacky                                     LN0->getAlignment());
4827193323Sed    CombineTo(N, ExtLoad);
4828193323Sed    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4829193323Sed    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
4830193323Sed  }
4831224145Sdim
4832224145Sdim  // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
4833224145Sdim  if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
4834224145Sdim    SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
4835224145Sdim                                       N0.getOperand(1), false);
4836224145Sdim    if (BSwap.getNode() != 0)
4837224145Sdim      return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4838224145Sdim                         BSwap, N1);
4839224145Sdim  }
4840224145Sdim
4841193323Sed  return SDValue();
4842193323Sed}
4843193323Sed
4844193323SedSDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4845193323Sed  SDValue N0 = N->getOperand(0);
4846198090Srdivacky  EVT VT = N->getValueType(0);
4847193323Sed
4848193323Sed  // noop truncate
4849193323Sed  if (N0.getValueType() == N->getValueType(0))
4850193323Sed    return N0;
4851193323Sed  // fold (truncate c1) -> c1
4852193323Sed  if (isa<ConstantSDNode>(N0))
4853193323Sed    return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4854193323Sed  // fold (truncate (truncate x)) -> (truncate x)
4855193323Sed  if (N0.getOpcode() == ISD::TRUNCATE)
4856193323Sed    return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4857193323Sed  // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4858207618Srdivacky  if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4859207618Srdivacky      N0.getOpcode() == ISD::SIGN_EXTEND ||
4860193323Sed      N0.getOpcode() == ISD::ANY_EXTEND) {
4861193323Sed    if (N0.getOperand(0).getValueType().bitsLT(VT))
4862193323Sed      // if the source is smaller than the dest, we still need an extend
4863193323Sed      return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4864193323Sed                         N0.getOperand(0));
4865193323Sed    else if (N0.getOperand(0).getValueType().bitsGT(VT))
4866193323Sed      // if the source is larger than the dest, than we just need the truncate
4867193323Sed      return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4868193323Sed    else
4869193323Sed      // if the source and dest are the same type, we can drop both the extend
4870202375Srdivacky      // and the truncate.
4871193323Sed      return N0.getOperand(0);
4872193323Sed  }
4873193323Sed
4874193323Sed  // See if we can simplify the input to this truncate through knowledge that
4875219077Sdim  // only the low bits are being used.
4876219077Sdim  // For example "trunc (or (shl x, 8), y)" // -> trunc y
4877221345Sdim  // Currently we only perform this optimization on scalars because vectors
4878219077Sdim  // may have different active low bits.
4879219077Sdim  if (!VT.isVector()) {
4880219077Sdim    SDValue Shorter =
4881219077Sdim      GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4882219077Sdim                                               VT.getSizeInBits()));
4883219077Sdim    if (Shorter.getNode())
4884219077Sdim      return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4885219077Sdim  }
4886193323Sed  // fold (truncate (load x)) -> (smaller load x)
4887193323Sed  // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4888210299Sed  if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4889210299Sed    SDValue Reduced = ReduceLoadWidth(N);
4890210299Sed    if (Reduced.getNode())
4891210299Sed      return Reduced;
4892210299Sed  }
4893210299Sed
4894210299Sed  // Simplify the operands using demanded-bits information.
4895210299Sed  if (!VT.isVector() &&
4896210299Sed      SimplifyDemandedBits(SDValue(N, 0)))
4897210299Sed    return SDValue(N, 0);
4898210299Sed
4899207618Srdivacky  return SDValue();
4900193323Sed}
4901193323Sed
4902193323Sedstatic SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4903193323Sed  SDValue Elt = N->getOperand(i);
4904193323Sed  if (Elt.getOpcode() != ISD::MERGE_VALUES)
4905193323Sed    return Elt.getNode();
4906193323Sed  return Elt.getOperand(Elt.getResNo()).getNode();
4907193323Sed}
4908193323Sed
4909193323Sed/// CombineConsecutiveLoads - build_pair (load, load) -> load
4910193323Sed/// if load locations are consecutive.
4911198090SrdivackySDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4912193323Sed  assert(N->getOpcode() == ISD::BUILD_PAIR);
4913193323Sed
4914193574Sed  LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4915193574Sed  LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4916218893Sdim  if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
4917218893Sdim      LD1->getPointerInfo().getAddrSpace() !=
4918218893Sdim         LD2->getPointerInfo().getAddrSpace())
4919193323Sed    return SDValue();
4920198090Srdivacky  EVT LD1VT = LD1->getValueType(0);
4921193323Sed
4922193323Sed  if (ISD::isNON_EXTLoad(LD2) &&
4923193323Sed      LD2->hasOneUse() &&
4924193323Sed      // If both are volatile this would reduce the number of volatile loads.
4925193323Sed      // If one is volatile it might be ok, but play conservative and bail out.
4926193574Sed      !LD1->isVolatile() &&
4927193574Sed      !LD2->isVolatile() &&
4928200581Srdivacky      DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4929193574Sed    unsigned Align = LD1->getAlignment();
4930193323Sed    unsigned NewAlign = TLI.getTargetData()->
4931198090Srdivacky      getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4932193323Sed
4933193323Sed    if (NewAlign <= Align &&
4934193323Sed        (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4935193574Sed      return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4936218893Sdim                         LD1->getBasePtr(), LD1->getPointerInfo(),
4937218893Sdim                         false, false, Align);
4938193323Sed  }
4939193323Sed
4940193323Sed  return SDValue();
4941193323Sed}
4942193323Sed
4943218893SdimSDValue DAGCombiner::visitBITCAST(SDNode *N) {
4944193323Sed  SDValue N0 = N->getOperand(0);
4945198090Srdivacky  EVT VT = N->getValueType(0);
4946193323Sed
4947193323Sed  // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4948193323Sed  // Only do this before legalize, since afterward the target may be depending
4949193323Sed  // on the bitconvert.
4950193323Sed  // First check to see if this is all constant.
4951193323Sed  if (!LegalTypes &&
4952193323Sed      N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4953193323Sed      VT.isVector()) {
4954193323Sed    bool isSimple = true;
4955193323Sed    for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4956193323Sed      if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4957193323Sed          N0.getOperand(i).getOpcode() != ISD::Constant &&
4958193323Sed          N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4959193323Sed        isSimple = false;
4960193323Sed        break;
4961193323Sed      }
4962193323Sed
4963198090Srdivacky    EVT DestEltVT = N->getValueType(0).getVectorElementType();
4964193323Sed    assert(!DestEltVT.isVector() &&
4965193323Sed           "Element type of vector ValueType must not be vector!");
4966193323Sed    if (isSimple)
4967218893Sdim      return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4968193323Sed  }
4969193323Sed
4970193323Sed  // If the input is a constant, let getNode fold it.
4971193323Sed  if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4972218893Sdim    SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
4973198090Srdivacky    if (Res.getNode() != N) {
4974198090Srdivacky      if (!LegalOperations ||
4975198090Srdivacky          TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4976198090Srdivacky        return Res;
4977198090Srdivacky
4978198090Srdivacky      // Folding it resulted in an illegal node, and it's too late to
4979198090Srdivacky      // do that. Clean up the old node and forego the transformation.
4980198090Srdivacky      // Ideally this won't happen very often, because instcombine
4981198090Srdivacky      // and the earlier dagcombine runs (where illegal nodes are
4982198090Srdivacky      // permitted) should have folded most of them already.
4983198090Srdivacky      DAG.DeleteNode(Res.getNode());
4984198090Srdivacky    }
4985193323Sed  }
4986193323Sed
4987193323Sed  // (conv (conv x, t1), t2) -> (conv x, t2)
4988218893Sdim  if (N0.getOpcode() == ISD::BITCAST)
4989218893Sdim    return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
4990193323Sed                       N0.getOperand(0));
4991193323Sed
4992193323Sed  // fold (conv (load x)) -> (load (conv*)x)
4993193323Sed  // If the resultant load doesn't need a higher alignment than the original!
4994193323Sed  if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4995193323Sed      // Do not change the width of a volatile load.
4996193323Sed      !cast<LoadSDNode>(N0)->isVolatile() &&
4997193323Sed      (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4998193323Sed    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4999193323Sed    unsigned Align = TLI.getTargetData()->
5000198090Srdivacky      getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5001193323Sed    unsigned OrigAlign = LN0->getAlignment();
5002193323Sed
5003193323Sed    if (Align <= OrigAlign) {
5004193323Sed      SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5005218893Sdim                                 LN0->getBasePtr(), LN0->getPointerInfo(),
5006203954Srdivacky                                 LN0->isVolatile(), LN0->isNonTemporal(),
5007203954Srdivacky                                 OrigAlign);
5008193323Sed      AddToWorkList(N);
5009193323Sed      CombineTo(N0.getNode(),
5010218893Sdim                DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5011193323Sed                            N0.getValueType(), Load),
5012193323Sed                Load.getValue(1));
5013193323Sed      return Load;
5014193323Sed    }
5015193323Sed  }
5016193323Sed
5017193323Sed  // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5018193323Sed  // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5019193323Sed  // This often reduces constant pool loads.
5020193323Sed  if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
5021193323Sed      N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5022218893Sdim    SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5023193323Sed                                  N0.getOperand(0));
5024193323Sed    AddToWorkList(NewConv.getNode());
5025193323Sed
5026193323Sed    APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5027193323Sed    if (N0.getOpcode() == ISD::FNEG)
5028193323Sed      return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5029193323Sed                         NewConv, DAG.getConstant(SignBit, VT));
5030193323Sed    assert(N0.getOpcode() == ISD::FABS);
5031193323Sed    return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5032193323Sed                       NewConv, DAG.getConstant(~SignBit, VT));
5033193323Sed  }
5034193323Sed
5035193323Sed  // fold (bitconvert (fcopysign cst, x)) ->
5036193323Sed  //         (or (and (bitconvert x), sign), (and cst, (not sign)))
5037193323Sed  // Note that we don't handle (copysign x, cst) because this can always be
5038193323Sed  // folded to an fneg or fabs.
5039193323Sed  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5040193323Sed      isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5041193323Sed      VT.isInteger() && !VT.isVector()) {
5042193323Sed    unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5043198090Srdivacky    EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5044207618Srdivacky    if (isTypeLegal(IntXVT)) {
5045218893Sdim      SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5046193323Sed                              IntXVT, N0.getOperand(1));
5047193323Sed      AddToWorkList(X.getNode());
5048193323Sed
5049193323Sed      // If X has a different width than the result/lhs, sext it or truncate it.
5050193323Sed      unsigned VTWidth = VT.getSizeInBits();
5051193323Sed      if (OrigXWidth < VTWidth) {
5052193323Sed        X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5053193323Sed        AddToWorkList(X.getNode());
5054193323Sed      } else if (OrigXWidth > VTWidth) {
5055193323Sed        // To get the sign bit in the right place, we have to shift it right
5056193323Sed        // before truncating.
5057193323Sed        X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5058193323Sed                        X.getValueType(), X,
5059193323Sed                        DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5060193323Sed        AddToWorkList(X.getNode());
5061193323Sed        X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5062193323Sed        AddToWorkList(X.getNode());
5063193323Sed      }
5064193323Sed
5065193323Sed      APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5066193323Sed      X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5067193323Sed                      X, DAG.getConstant(SignBit, VT));
5068193323Sed      AddToWorkList(X.getNode());
5069193323Sed
5070218893Sdim      SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5071193323Sed                                VT, N0.getOperand(0));
5072193323Sed      Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5073193323Sed                        Cst, DAG.getConstant(~SignBit, VT));
5074193323Sed      AddToWorkList(Cst.getNode());
5075193323Sed
5076193323Sed      return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5077193323Sed    }
5078193323Sed  }
5079193323Sed
5080193323Sed  // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5081193323Sed  if (N0.getOpcode() == ISD::BUILD_PAIR) {
5082193323Sed    SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5083193323Sed    if (CombineLD.getNode())
5084193323Sed      return CombineLD;
5085193323Sed  }
5086193323Sed
5087193323Sed  return SDValue();
5088193323Sed}
5089193323Sed
5090193323SedSDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5091198090Srdivacky  EVT VT = N->getValueType(0);
5092193323Sed  return CombineConsecutiveLoads(N, VT);
5093193323Sed}
5094193323Sed
5095218893Sdim/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5096193323Sed/// node with Constant, ConstantFP or Undef operands.  DstEltVT indicates the
5097193323Sed/// destination element value type.
5098193323SedSDValue DAGCombiner::
5099218893SdimConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5100198090Srdivacky  EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5101193323Sed
5102193323Sed  // If this is already the right type, we're done.
5103193323Sed  if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5104193323Sed
5105193323Sed  unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5106193323Sed  unsigned DstBitSize = DstEltVT.getSizeInBits();
5107193323Sed
5108193323Sed  // If this is a conversion of N elements of one type to N elements of another
5109193323Sed  // type, convert each element.  This handles FP<->INT cases.
5110193323Sed  if (SrcBitSize == DstBitSize) {
5111212904Sdim    EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5112212904Sdim                              BV->getValueType(0).getVectorNumElements());
5113212904Sdim
5114212904Sdim    // Due to the FP element handling below calling this routine recursively,
5115212904Sdim    // we can end up with a scalar-to-vector node here.
5116212904Sdim    if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5117218893Sdim      return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5118218893Sdim                         DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5119212904Sdim                                     DstEltVT, BV->getOperand(0)));
5120218893Sdim
5121193323Sed    SmallVector<SDValue, 8> Ops;
5122193323Sed    for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5123193323Sed      SDValue Op = BV->getOperand(i);
5124193323Sed      // If the vector element type is not legal, the BUILD_VECTOR operands
5125193323Sed      // are promoted and implicitly truncated.  Make that explicit here.
5126193323Sed      if (Op.getValueType() != SrcEltVT)
5127193323Sed        Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5128218893Sdim      Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5129193323Sed                                DstEltVT, Op));
5130193323Sed      AddToWorkList(Ops.back().getNode());
5131193323Sed    }
5132193323Sed    return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5133193323Sed                       &Ops[0], Ops.size());
5134193323Sed  }
5135193323Sed
5136193323Sed  // Otherwise, we're growing or shrinking the elements.  To avoid having to
5137193323Sed  // handle annoying details of growing/shrinking FP values, we convert them to
5138193323Sed  // int first.
5139193323Sed  if (SrcEltVT.isFloatingPoint()) {
5140193323Sed    // Convert the input float vector to a int vector where the elements are the
5141193323Sed    // same sizes.
5142193323Sed    assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5143198090Srdivacky    EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5144218893Sdim    BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5145193323Sed    SrcEltVT = IntVT;
5146193323Sed  }
5147193323Sed
5148193323Sed  // Now we know the input is an integer vector.  If the output is a FP type,
5149193323Sed  // convert to integer first, then to FP of the right size.
5150193323Sed  if (DstEltVT.isFloatingPoint()) {
5151193323Sed    assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5152198090Srdivacky    EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5153218893Sdim    SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5154193323Sed
5155193323Sed    // Next, convert to FP elements of the same size.
5156218893Sdim    return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5157193323Sed  }
5158193323Sed
5159193323Sed  // Okay, we know the src/dst types are both integers of differing types.
5160193323Sed  // Handling growing first.
5161193323Sed  assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5162193323Sed  if (SrcBitSize < DstBitSize) {
5163193323Sed    unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5164193323Sed
5165193323Sed    SmallVector<SDValue, 8> Ops;
5166193323Sed    for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5167193323Sed         i += NumInputsPerOutput) {
5168193323Sed      bool isLE = TLI.isLittleEndian();
5169193323Sed      APInt NewBits = APInt(DstBitSize, 0);
5170193323Sed      bool EltIsUndef = true;
5171193323Sed      for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5172193323Sed        // Shift the previously computed bits over.
5173193323Sed        NewBits <<= SrcBitSize;
5174193323Sed        SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5175193323Sed        if (Op.getOpcode() == ISD::UNDEF) continue;
5176193323Sed        EltIsUndef = false;
5177193323Sed
5178218893Sdim        NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5179207618Srdivacky                   zextOrTrunc(SrcBitSize).zext(DstBitSize);
5180193323Sed      }
5181193323Sed
5182193323Sed      if (EltIsUndef)
5183193323Sed        Ops.push_back(DAG.getUNDEF(DstEltVT));
5184193323Sed      else
5185193323Sed        Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5186193323Sed    }
5187193323Sed
5188198090Srdivacky    EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5189193323Sed    return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5190193323Sed                       &Ops[0], Ops.size());
5191193323Sed  }
5192193323Sed
5193193323Sed  // Finally, this must be the case where we are shrinking elements: each input
5194193323Sed  // turns into multiple outputs.
5195193323Sed  bool isS2V = ISD::isScalarToVector(BV);
5196193323Sed  unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5197198090Srdivacky  EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5198198090Srdivacky                            NumOutputsPerInput*BV->getNumOperands());
5199193323Sed  SmallVector<SDValue, 8> Ops;
5200193323Sed
5201193323Sed  for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5202193323Sed    if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5203193323Sed      for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5204193323Sed        Ops.push_back(DAG.getUNDEF(DstEltVT));
5205193323Sed      continue;
5206193323Sed    }
5207193323Sed
5208218893Sdim    APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5209218893Sdim                  getAPIntValue().zextOrTrunc(SrcBitSize);
5210193323Sed
5211193323Sed    for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5212218893Sdim      APInt ThisVal = OpVal.trunc(DstBitSize);
5213193323Sed      Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5214218893Sdim      if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5215193323Sed        // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5216193323Sed        return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5217193323Sed                           Ops[0]);
5218193323Sed      OpVal = OpVal.lshr(DstBitSize);
5219193323Sed    }
5220193323Sed
5221193323Sed    // For big endian targets, swap the order of the pieces of each element.
5222193323Sed    if (TLI.isBigEndian())
5223193323Sed      std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5224193323Sed  }
5225193323Sed
5226193323Sed  return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5227193323Sed                     &Ops[0], Ops.size());
5228193323Sed}
5229193323Sed
5230193323SedSDValue DAGCombiner::visitFADD(SDNode *N) {
5231193323Sed  SDValue N0 = N->getOperand(0);
5232193323Sed  SDValue N1 = N->getOperand(1);
5233193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5234193323Sed  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5235198090Srdivacky  EVT VT = N->getValueType(0);
5236193323Sed
5237193323Sed  // fold vector ops
5238193323Sed  if (VT.isVector()) {
5239193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
5240193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
5241193323Sed  }
5242193323Sed
5243193323Sed  // fold (fadd c1, c2) -> (fadd c1, c2)
5244193323Sed  if (N0CFP && N1CFP && VT != MVT::ppcf128)
5245193323Sed    return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5246193323Sed  // canonicalize constant to RHS
5247193323Sed  if (N0CFP && !N1CFP)
5248193323Sed    return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5249193323Sed  // fold (fadd A, 0) -> A
5250193323Sed  if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5251193323Sed    return N0;
5252193323Sed  // fold (fadd A, (fneg B)) -> (fsub A, B)
5253193323Sed  if (isNegatibleForFree(N1, LegalOperations) == 2)
5254193323Sed    return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5255193323Sed                       GetNegatedExpression(N1, DAG, LegalOperations));
5256193323Sed  // fold (fadd (fneg A), B) -> (fsub B, A)
5257193323Sed  if (isNegatibleForFree(N0, LegalOperations) == 2)
5258193323Sed    return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5259193323Sed                       GetNegatedExpression(N0, DAG, LegalOperations));
5260193323Sed
5261193323Sed  // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5262193323Sed  if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
5263193323Sed      N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5264193323Sed    return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5265193323Sed                       DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5266193323Sed                                   N0.getOperand(1), N1));
5267193323Sed
5268193323Sed  return SDValue();
5269193323Sed}
5270193323Sed
5271193323SedSDValue DAGCombiner::visitFSUB(SDNode *N) {
5272193323Sed  SDValue N0 = N->getOperand(0);
5273193323Sed  SDValue N1 = N->getOperand(1);
5274193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5275193323Sed  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5276198090Srdivacky  EVT VT = N->getValueType(0);
5277193323Sed
5278193323Sed  // fold vector ops
5279193323Sed  if (VT.isVector()) {
5280193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
5281193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
5282193323Sed  }
5283193323Sed
5284193323Sed  // fold (fsub c1, c2) -> c1-c2
5285193323Sed  if (N0CFP && N1CFP && VT != MVT::ppcf128)
5286193323Sed    return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5287193323Sed  // fold (fsub A, 0) -> A
5288193323Sed  if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5289193323Sed    return N0;
5290193323Sed  // fold (fsub 0, B) -> -B
5291193323Sed  if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
5292193323Sed    if (isNegatibleForFree(N1, LegalOperations))
5293193323Sed      return GetNegatedExpression(N1, DAG, LegalOperations);
5294193323Sed    if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5295193323Sed      return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5296193323Sed  }
5297193323Sed  // fold (fsub A, (fneg B)) -> (fadd A, B)
5298193323Sed  if (isNegatibleForFree(N1, LegalOperations))
5299193323Sed    return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5300193323Sed                       GetNegatedExpression(N1, DAG, LegalOperations));
5301193323Sed
5302193323Sed  return SDValue();
5303193323Sed}
5304193323Sed
5305193323SedSDValue DAGCombiner::visitFMUL(SDNode *N) {
5306193323Sed  SDValue N0 = N->getOperand(0);
5307193323Sed  SDValue N1 = N->getOperand(1);
5308193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5309193323Sed  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5310198090Srdivacky  EVT VT = N->getValueType(0);
5311193323Sed
5312193323Sed  // fold vector ops
5313193323Sed  if (VT.isVector()) {
5314193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
5315193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
5316193323Sed  }
5317193323Sed
5318193323Sed  // fold (fmul c1, c2) -> c1*c2
5319193323Sed  if (N0CFP && N1CFP && VT != MVT::ppcf128)
5320193323Sed    return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5321193323Sed  // canonicalize constant to RHS
5322193323Sed  if (N0CFP && !N1CFP)
5323193323Sed    return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5324193323Sed  // fold (fmul A, 0) -> 0
5325193323Sed  if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5326193323Sed    return N1;
5327193574Sed  // fold (fmul A, 0) -> 0, vector edition.
5328193574Sed  if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
5329193574Sed    return N1;
5330193323Sed  // fold (fmul X, 2.0) -> (fadd X, X)
5331193323Sed  if (N1CFP && N1CFP->isExactlyValue(+2.0))
5332193323Sed    return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5333198090Srdivacky  // fold (fmul X, -1.0) -> (fneg X)
5334193323Sed  if (N1CFP && N1CFP->isExactlyValue(-1.0))
5335193323Sed    if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5336193323Sed      return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5337193323Sed
5338193323Sed  // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5339193323Sed  if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5340193323Sed    if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5341193323Sed      // Both can be negated for free, check to see if at least one is cheaper
5342193323Sed      // negated.
5343193323Sed      if (LHSNeg == 2 || RHSNeg == 2)
5344193323Sed        return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5345193323Sed                           GetNegatedExpression(N0, DAG, LegalOperations),
5346193323Sed                           GetNegatedExpression(N1, DAG, LegalOperations));
5347193323Sed    }
5348193323Sed  }
5349193323Sed
5350193323Sed  // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5351193323Sed  if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
5352193323Sed      N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5353193323Sed    return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5354193323Sed                       DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5355193323Sed                                   N0.getOperand(1), N1));
5356193323Sed
5357193323Sed  return SDValue();
5358193323Sed}
5359193323Sed
5360193323SedSDValue DAGCombiner::visitFDIV(SDNode *N) {
5361193323Sed  SDValue N0 = N->getOperand(0);
5362193323Sed  SDValue N1 = N->getOperand(1);
5363193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5364193323Sed  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5365198090Srdivacky  EVT VT = N->getValueType(0);
5366193323Sed
5367193323Sed  // fold vector ops
5368193323Sed  if (VT.isVector()) {
5369193323Sed    SDValue FoldedVOp = SimplifyVBinOp(N);
5370193323Sed    if (FoldedVOp.getNode()) return FoldedVOp;
5371193323Sed  }
5372193323Sed
5373193323Sed  // fold (fdiv c1, c2) -> c1/c2
5374193323Sed  if (N0CFP && N1CFP && VT != MVT::ppcf128)
5375193323Sed    return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5376193323Sed
5377193323Sed
5378193323Sed  // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5379193323Sed  if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5380193323Sed    if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5381193323Sed      // Both can be negated for free, check to see if at least one is cheaper
5382193323Sed      // negated.
5383193323Sed      if (LHSNeg == 2 || RHSNeg == 2)
5384193323Sed        return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5385193323Sed                           GetNegatedExpression(N0, DAG, LegalOperations),
5386193323Sed                           GetNegatedExpression(N1, DAG, LegalOperations));
5387193323Sed    }
5388193323Sed  }
5389193323Sed
5390193323Sed  return SDValue();
5391193323Sed}
5392193323Sed
5393193323SedSDValue DAGCombiner::visitFREM(SDNode *N) {
5394193323Sed  SDValue N0 = N->getOperand(0);
5395193323Sed  SDValue N1 = N->getOperand(1);
5396193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5397193323Sed  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5398198090Srdivacky  EVT VT = N->getValueType(0);
5399193323Sed
5400193323Sed  // fold (frem c1, c2) -> fmod(c1,c2)
5401193323Sed  if (N0CFP && N1CFP && VT != MVT::ppcf128)
5402193323Sed    return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5403193323Sed
5404193323Sed  return SDValue();
5405193323Sed}
5406193323Sed
5407193323SedSDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5408193323Sed  SDValue N0 = N->getOperand(0);
5409193323Sed  SDValue N1 = N->getOperand(1);
5410193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5411193323Sed  ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5412198090Srdivacky  EVT VT = N->getValueType(0);
5413193323Sed
5414193323Sed  if (N0CFP && N1CFP && VT != MVT::ppcf128)  // Constant fold
5415193323Sed    return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5416193323Sed
5417193323Sed  if (N1CFP) {
5418193323Sed    const APFloat& V = N1CFP->getValueAPF();
5419193323Sed    // copysign(x, c1) -> fabs(x)       iff ispos(c1)
5420193323Sed    // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5421193323Sed    if (!V.isNegative()) {
5422193323Sed      if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5423193323Sed        return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5424193323Sed    } else {
5425193323Sed      if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5426193323Sed        return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5427193323Sed                           DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5428193323Sed    }
5429193323Sed  }
5430193323Sed
5431193323Sed  // copysign(fabs(x), y) -> copysign(x, y)
5432193323Sed  // copysign(fneg(x), y) -> copysign(x, y)
5433193323Sed  // copysign(copysign(x,z), y) -> copysign(x, y)
5434193323Sed  if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5435193323Sed      N0.getOpcode() == ISD::FCOPYSIGN)
5436193323Sed    return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5437193323Sed                       N0.getOperand(0), N1);
5438193323Sed
5439193323Sed  // copysign(x, abs(y)) -> abs(x)
5440193323Sed  if (N1.getOpcode() == ISD::FABS)
5441193323Sed    return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5442193323Sed
5443193323Sed  // copysign(x, copysign(y,z)) -> copysign(x, z)
5444193323Sed  if (N1.getOpcode() == ISD::FCOPYSIGN)
5445193323Sed    return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5446193323Sed                       N0, N1.getOperand(1));
5447193323Sed
5448193323Sed  // copysign(x, fp_extend(y)) -> copysign(x, y)
5449193323Sed  // copysign(x, fp_round(y)) -> copysign(x, y)
5450193323Sed  if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5451193323Sed    return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5452193323Sed                       N0, N1.getOperand(0));
5453193323Sed
5454193323Sed  return SDValue();
5455193323Sed}
5456193323Sed
5457193323SedSDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5458193323Sed  SDValue N0 = N->getOperand(0);
5459193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5460198090Srdivacky  EVT VT = N->getValueType(0);
5461198090Srdivacky  EVT OpVT = N0.getValueType();
5462193323Sed
5463193323Sed  // fold (sint_to_fp c1) -> c1fp
5464221345Sdim  if (N0C && OpVT != MVT::ppcf128 &&
5465221345Sdim      // ...but only if the target supports immediate floating-point values
5466224145Sdim      (Level == llvm::Unrestricted ||
5467224145Sdim       TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5468193323Sed    return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5469193323Sed
5470193323Sed  // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5471193323Sed  // but UINT_TO_FP is legal on this target, try to convert.
5472193323Sed  if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5473193323Sed      TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5474193323Sed    // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5475193323Sed    if (DAG.SignBitIsZero(N0))
5476193323Sed      return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5477193323Sed  }
5478193323Sed
5479193323Sed  return SDValue();
5480193323Sed}
5481193323Sed
5482193323SedSDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5483193323Sed  SDValue N0 = N->getOperand(0);
5484193323Sed  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5485198090Srdivacky  EVT VT = N->getValueType(0);
5486198090Srdivacky  EVT OpVT = N0.getValueType();
5487193323Sed
5488193323Sed  // fold (uint_to_fp c1) -> c1fp
5489221345Sdim  if (N0C && OpVT != MVT::ppcf128 &&
5490221345Sdim      // ...but only if the target supports immediate floating-point values
5491224145Sdim      (Level == llvm::Unrestricted ||
5492224145Sdim       TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5493193323Sed    return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5494193323Sed
5495193323Sed  // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5496193323Sed  // but SINT_TO_FP is legal on this target, try to convert.
5497193323Sed  if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5498193323Sed      TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5499193323Sed    // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5500193323Sed    if (DAG.SignBitIsZero(N0))
5501193323Sed      return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5502193323Sed  }
5503193323Sed
5504193323Sed  return SDValue();
5505193323Sed}
5506193323Sed
5507193323SedSDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5508193323Sed  SDValue N0 = N->getOperand(0);
5509193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5510198090Srdivacky  EVT VT = N->getValueType(0);
5511193323Sed
5512193323Sed  // fold (fp_to_sint c1fp) -> c1
5513193323Sed  if (N0CFP)
5514193323Sed    return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5515193323Sed
5516193323Sed  return SDValue();
5517193323Sed}
5518193323Sed
5519193323SedSDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5520193323Sed  SDValue N0 = N->getOperand(0);
5521193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5522198090Srdivacky  EVT VT = N->getValueType(0);
5523193323Sed
5524193323Sed  // fold (fp_to_uint c1fp) -> c1
5525193323Sed  if (N0CFP && VT != MVT::ppcf128)
5526193323Sed    return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5527193323Sed
5528193323Sed  return SDValue();
5529193323Sed}
5530193323Sed
5531193323SedSDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5532193323Sed  SDValue N0 = N->getOperand(0);
5533193323Sed  SDValue N1 = N->getOperand(1);
5534193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5535198090Srdivacky  EVT VT = N->getValueType(0);
5536193323Sed
5537193323Sed  // fold (fp_round c1fp) -> c1fp
5538193323Sed  if (N0CFP && N0.getValueType() != MVT::ppcf128)
5539193323Sed    return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5540193323Sed
5541193323Sed  // fold (fp_round (fp_extend x)) -> x
5542193323Sed  if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5543193323Sed    return N0.getOperand(0);
5544193323Sed
5545193323Sed  // fold (fp_round (fp_round x)) -> (fp_round x)
5546193323Sed  if (N0.getOpcode() == ISD::FP_ROUND) {
5547193323Sed    // This is a value preserving truncation if both round's are.
5548193323Sed    bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5549193323Sed                   N0.getNode()->getConstantOperandVal(1) == 1;
5550193323Sed    return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5551193323Sed                       DAG.getIntPtrConstant(IsTrunc));
5552193323Sed  }
5553193323Sed
5554193323Sed  // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5555193323Sed  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5556193323Sed    SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5557193323Sed                              N0.getOperand(0), N1);
5558193323Sed    AddToWorkList(Tmp.getNode());
5559193323Sed    return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5560193323Sed                       Tmp, N0.getOperand(1));
5561193323Sed  }
5562193323Sed
5563193323Sed  return SDValue();
5564193323Sed}
5565193323Sed
5566193323SedSDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5567193323Sed  SDValue N0 = N->getOperand(0);
5568198090Srdivacky  EVT VT = N->getValueType(0);
5569198090Srdivacky  EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5570193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5571193323Sed
5572193323Sed  // fold (fp_round_inreg c1fp) -> c1fp
5573207618Srdivacky  if (N0CFP && isTypeLegal(EVT)) {
5574193323Sed    SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5575193323Sed    return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5576193323Sed  }
5577193323Sed
5578193323Sed  return SDValue();
5579193323Sed}
5580193323Sed
5581193323SedSDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5582193323Sed  SDValue N0 = N->getOperand(0);
5583193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5584198090Srdivacky  EVT VT = N->getValueType(0);
5585193323Sed
5586193323Sed  // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5587193323Sed  if (N->hasOneUse() &&
5588193323Sed      N->use_begin()->getOpcode() == ISD::FP_ROUND)
5589193323Sed    return SDValue();
5590193323Sed
5591193323Sed  // fold (fp_extend c1fp) -> c1fp
5592193323Sed  if (N0CFP && VT != MVT::ppcf128)
5593193323Sed    return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5594193323Sed
5595193323Sed  // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5596193323Sed  // value of X.
5597193323Sed  if (N0.getOpcode() == ISD::FP_ROUND
5598193323Sed      && N0.getNode()->getConstantOperandVal(1) == 1) {
5599193323Sed    SDValue In = N0.getOperand(0);
5600193323Sed    if (In.getValueType() == VT) return In;
5601193323Sed    if (VT.bitsLT(In.getValueType()))
5602193323Sed      return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5603193323Sed                         In, N0.getOperand(1));
5604193323Sed    return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5605193323Sed  }
5606193323Sed
5607193323Sed  // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5608193323Sed  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5609193323Sed      ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5610193323Sed       TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5611193323Sed    LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5612218893Sdim    SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
5613193323Sed                                     LN0->getChain(),
5614218893Sdim                                     LN0->getBasePtr(), LN0->getPointerInfo(),
5615193323Sed                                     N0.getValueType(),
5616203954Srdivacky                                     LN0->isVolatile(), LN0->isNonTemporal(),
5617203954Srdivacky                                     LN0->getAlignment());
5618193323Sed    CombineTo(N, ExtLoad);
5619193323Sed    CombineTo(N0.getNode(),
5620193323Sed              DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5621193323Sed                          N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5622193323Sed              ExtLoad.getValue(1));
5623193323Sed    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
5624193323Sed  }
5625193323Sed
5626193323Sed  return SDValue();
5627193323Sed}
5628193323Sed
5629193323SedSDValue DAGCombiner::visitFNEG(SDNode *N) {
5630193323Sed  SDValue N0 = N->getOperand(0);
5631198396Srdivacky  EVT VT = N->getValueType(0);
5632193323Sed
5633193323Sed  if (isNegatibleForFree(N0, LegalOperations))
5634193323Sed    return GetNegatedExpression(N0, DAG, LegalOperations);
5635193323Sed
5636193323Sed  // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5637193323Sed  // constant pool values.
5638218893Sdim  if (N0.getOpcode() == ISD::BITCAST &&
5639198396Srdivacky      !VT.isVector() &&
5640198396Srdivacky      N0.getNode()->hasOneUse() &&
5641198396Srdivacky      N0.getOperand(0).getValueType().isInteger()) {
5642193323Sed    SDValue Int = N0.getOperand(0);
5643198090Srdivacky    EVT IntVT = Int.getValueType();
5644193323Sed    if (IntVT.isInteger() && !IntVT.isVector()) {
5645193323Sed      Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5646193323Sed              DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5647193323Sed      AddToWorkList(Int.getNode());
5648218893Sdim      return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5649198396Srdivacky                         VT, Int);
5650193323Sed    }
5651193323Sed  }
5652193323Sed
5653193323Sed  return SDValue();
5654193323Sed}
5655193323Sed
5656193323SedSDValue DAGCombiner::visitFABS(SDNode *N) {
5657193323Sed  SDValue N0 = N->getOperand(0);
5658193323Sed  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5659198090Srdivacky  EVT VT = N->getValueType(0);
5660193323Sed
5661193323Sed  // fold (fabs c1) -> fabs(c1)
5662193323Sed  if (N0CFP && VT != MVT::ppcf128)
5663193323Sed    return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5664193323Sed  // fold (fabs (fabs x)) -> (fabs x)
5665193323Sed  if (N0.getOpcode() == ISD::FABS)
5666193323Sed    return N->getOperand(0);
5667193323Sed  // fold (fabs (fneg x)) -> (fabs x)
5668193323Sed  // fold (fabs (fcopysign x, y)) -> (fabs x)
5669193323Sed  if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5670193323Sed    return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5671193323Sed
5672193323Sed  // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5673193323Sed  // constant pool values.
5674218893Sdim  if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5675193323Sed      N0.getOperand(0).getValueType().isInteger() &&
5676193323Sed      !N0.getOperand(0).getValueType().isVector()) {
5677193323Sed    SDValue Int = N0.getOperand(0);
5678198090Srdivacky    EVT IntVT = Int.getValueType();
5679193323Sed    if (IntVT.isInteger() && !IntVT.isVector()) {
5680193323Sed      Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5681193323Sed             DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5682193323Sed      AddToWorkList(Int.getNode());
5683218893Sdim      return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5684193323Sed                         N->getValueType(0), Int);
5685193323Sed    }
5686193323Sed  }
5687193323Sed
5688193323Sed  return SDValue();
5689193323Sed}
5690193323Sed
5691193323SedSDValue DAGCombiner::visitBRCOND(SDNode *N) {
5692193323Sed  SDValue Chain = N->getOperand(0);
5693193323Sed  SDValue N1 = N->getOperand(1);
5694193323Sed  SDValue N2 = N->getOperand(2);
5695193323Sed
5696199481Srdivacky  // If N is a constant we could fold this into a fallthrough or unconditional
5697199481Srdivacky  // branch. However that doesn't happen very often in normal code, because
5698199481Srdivacky  // Instcombine/SimplifyCFG should have handled the available opportunities.
5699199481Srdivacky  // If we did this folding here, it would be necessary to update the
5700199481Srdivacky  // MachineBasicBlock CFG, which is awkward.
5701199481Srdivacky
5702193323Sed  // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5703193323Sed  // on the target.
5704193323Sed  if (N1.getOpcode() == ISD::SETCC &&
5705193323Sed      TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5706193323Sed    return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5707193323Sed                       Chain, N1.getOperand(2),
5708193323Sed                       N1.getOperand(0), N1.getOperand(1), N2);
5709193323Sed  }
5710193323Sed
5711218893Sdim  if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5712218893Sdim      ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5713218893Sdim       (N1.getOperand(0).hasOneUse() &&
5714218893Sdim        N1.getOperand(0).getOpcode() == ISD::SRL))) {
5715218893Sdim    SDNode *Trunc = 0;
5716218893Sdim    if (N1.getOpcode() == ISD::TRUNCATE) {
5717218893Sdim      // Look pass the truncate.
5718218893Sdim      Trunc = N1.getNode();
5719218893Sdim      N1 = N1.getOperand(0);
5720218893Sdim    }
5721202375Srdivacky
5722193323Sed    // Match this pattern so that we can generate simpler code:
5723193323Sed    //
5724193323Sed    //   %a = ...
5725193323Sed    //   %b = and i32 %a, 2
5726193323Sed    //   %c = srl i32 %b, 1
5727193323Sed    //   brcond i32 %c ...
5728193323Sed    //
5729193323Sed    // into
5730218893Sdim    //
5731193323Sed    //   %a = ...
5732202375Srdivacky    //   %b = and i32 %a, 2
5733193323Sed    //   %c = setcc eq %b, 0
5734193323Sed    //   brcond %c ...
5735193323Sed    //
5736193323Sed    // This applies only when the AND constant value has one bit set and the
5737193323Sed    // SRL constant is equal to the log2 of the AND constant. The back-end is
5738193323Sed    // smart enough to convert the result into a TEST/JMP sequence.
5739193323Sed    SDValue Op0 = N1.getOperand(0);
5740193323Sed    SDValue Op1 = N1.getOperand(1);
5741193323Sed
5742193323Sed    if (Op0.getOpcode() == ISD::AND &&
5743193323Sed        Op1.getOpcode() == ISD::Constant) {
5744193323Sed      SDValue AndOp1 = Op0.getOperand(1);
5745193323Sed
5746193323Sed      if (AndOp1.getOpcode() == ISD::Constant) {
5747193323Sed        const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5748193323Sed
5749193323Sed        if (AndConst.isPowerOf2() &&
5750193323Sed            cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5751193323Sed          SDValue SetCC =
5752193323Sed            DAG.getSetCC(N->getDebugLoc(),
5753193323Sed                         TLI.getSetCCResultType(Op0.getValueType()),
5754193323Sed                         Op0, DAG.getConstant(0, Op0.getValueType()),
5755193323Sed                         ISD::SETNE);
5756193323Sed
5757202375Srdivacky          SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5758202375Srdivacky                                          MVT::Other, Chain, SetCC, N2);
5759202375Srdivacky          // Don't add the new BRCond into the worklist or else SimplifySelectCC
5760202375Srdivacky          // will convert it back to (X & C1) >> C2.
5761202375Srdivacky          CombineTo(N, NewBRCond, false);
5762202375Srdivacky          // Truncate is dead.
5763202375Srdivacky          if (Trunc) {
5764202375Srdivacky            removeFromWorkList(Trunc);
5765202375Srdivacky            DAG.DeleteNode(Trunc);
5766202375Srdivacky          }
5767193323Sed          // Replace the uses of SRL with SETCC
5768204642Srdivacky          WorkListRemover DeadNodes(*this);
5769204642Srdivacky          DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5770193323Sed          removeFromWorkList(N1.getNode());
5771193323Sed          DAG.DeleteNode(N1.getNode());
5772202375Srdivacky          return SDValue(N, 0);   // Return N so it doesn't get rechecked!
5773193323Sed        }
5774193323Sed      }
5775193323Sed    }
5776218893Sdim
5777218893Sdim    if (Trunc)
5778218893Sdim      // Restore N1 if the above transformation doesn't match.
5779218893Sdim      N1 = N->getOperand(1);
5780193323Sed  }
5781218893Sdim
5782204642Srdivacky  // Transform br(xor(x, y)) -> br(x != y)
5783204642Srdivacky  // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5784204642Srdivacky  if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5785204642Srdivacky    SDNode *TheXor = N1.getNode();
5786204642Srdivacky    SDValue Op0 = TheXor->getOperand(0);
5787204642Srdivacky    SDValue Op1 = TheXor->getOperand(1);
5788204642Srdivacky    if (Op0.getOpcode() == Op1.getOpcode()) {
5789204642Srdivacky      // Avoid missing important xor optimizations.
5790204642Srdivacky      SDValue Tmp = visitXOR(TheXor);
5791207618Srdivacky      if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5792204642Srdivacky        DEBUG(dbgs() << "\nReplacing.8 ";
5793204642Srdivacky              TheXor->dump(&DAG);
5794204642Srdivacky              dbgs() << "\nWith: ";
5795204642Srdivacky              Tmp.getNode()->dump(&DAG);
5796204642Srdivacky              dbgs() << '\n');
5797204642Srdivacky        WorkListRemover DeadNodes(*this);
5798204642Srdivacky        DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5799204642Srdivacky        removeFromWorkList(TheXor);
5800204642Srdivacky        DAG.DeleteNode(TheXor);
5801204642Srdivacky        return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5802204642Srdivacky                           MVT::Other, Chain, Tmp, N2);
5803204642Srdivacky      }
5804204642Srdivacky    }
5805193323Sed
5806204642Srdivacky    if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5807204642Srdivacky      bool Equal = false;
5808204642Srdivacky      if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5809204642Srdivacky        if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5810204642Srdivacky            Op0.getOpcode() == ISD::XOR) {
5811204642Srdivacky          TheXor = Op0.getNode();
5812204642Srdivacky          Equal = true;
5813204642Srdivacky        }
5814204642Srdivacky
5815218893Sdim      EVT SetCCVT = N1.getValueType();
5816204642Srdivacky      if (LegalTypes)
5817204642Srdivacky        SetCCVT = TLI.getSetCCResultType(SetCCVT);
5818204642Srdivacky      SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5819204642Srdivacky                                   SetCCVT,
5820204642Srdivacky                                   Op0, Op1,
5821204642Srdivacky                                   Equal ? ISD::SETEQ : ISD::SETNE);
5822204642Srdivacky      // Replace the uses of XOR with SETCC
5823204642Srdivacky      WorkListRemover DeadNodes(*this);
5824218893Sdim      DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5825218893Sdim      removeFromWorkList(N1.getNode());
5826218893Sdim      DAG.DeleteNode(N1.getNode());
5827204642Srdivacky      return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5828204642Srdivacky                         MVT::Other, Chain, SetCC, N2);
5829204642Srdivacky    }
5830204642Srdivacky  }
5831204642Srdivacky
5832193323Sed  return SDValue();
5833193323Sed}
5834193323Sed
5835193323Sed// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5836193323Sed//
5837193323SedSDValue DAGCombiner::visitBR_CC(SDNode *N) {
5838193323Sed  CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5839193323Sed  SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5840193323Sed
5841199481Srdivacky  // If N is a constant we could fold this into a fallthrough or unconditional
5842199481Srdivacky  // branch. However that doesn't happen very often in normal code, because
5843199481Srdivacky  // Instcombine/SimplifyCFG should have handled the available opportunities.
5844199481Srdivacky  // If we did this folding here, it would be necessary to update the
5845199481Srdivacky  // MachineBasicBlock CFG, which is awkward.
5846199481Srdivacky
5847193323Sed  // Use SimplifySetCC to simplify SETCC's.
5848193323Sed  SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5849193323Sed                               CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5850193323Sed                               false);
5851193323Sed  if (Simp.getNode()) AddToWorkList(Simp.getNode());
5852193323Sed
5853193323Sed  // fold to a simpler setcc
5854193323Sed  if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5855193323Sed    return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5856193323Sed                       N->getOperand(0), Simp.getOperand(2),
5857193323Sed                       Simp.getOperand(0), Simp.getOperand(1),
5858193323Sed                       N->getOperand(4));
5859193323Sed
5860193323Sed  return SDValue();
5861193323Sed}
5862193323Sed
5863193323Sed/// CombineToPreIndexedLoadStore - Try turning a load / store into a
5864193323Sed/// pre-indexed load / store when the base pointer is an add or subtract
5865193323Sed/// and it has other uses besides the load / store. After the
5866193323Sed/// transformation, the new indexed load / store has effectively folded
5867193323Sed/// the add / subtract in and all of its other uses are redirected to the
5868193323Sed/// new load / store.
5869193323Sedbool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5870193323Sed  if (!LegalOperations)
5871193323Sed    return false;
5872193323Sed
5873193323Sed  bool isLoad = true;
5874193323Sed  SDValue Ptr;
5875198090Srdivacky  EVT VT;
5876193323Sed  if (LoadSDNode *LD  = dyn_cast<LoadSDNode>(N)) {
5877193323Sed    if (LD->isIndexed())
5878193323Sed      return false;
5879193323Sed    VT = LD->getMemoryVT();
5880193323Sed    if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5881193323Sed        !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5882193323Sed      return false;
5883193323Sed    Ptr = LD->getBasePtr();
5884193323Sed  } else if (StoreSDNode *ST  = dyn_cast<StoreSDNode>(N)) {
5885193323Sed    if (ST->isIndexed())
5886193323Sed      return false;
5887193323Sed    VT = ST->getMemoryVT();
5888193323Sed    if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5889193323Sed        !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5890193323Sed      return false;
5891193323Sed    Ptr = ST->getBasePtr();
5892193323Sed    isLoad = false;
5893193323Sed  } else {
5894193323Sed    return false;
5895193323Sed  }
5896193323Sed
5897193323Sed  // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5898193323Sed  // out.  There is no reason to make this a preinc/predec.
5899193323Sed  if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5900193323Sed      Ptr.getNode()->hasOneUse())
5901193323Sed    return false;
5902193323Sed
5903193323Sed  // Ask the target to do addressing mode selection.
5904193323Sed  SDValue BasePtr;
5905193323Sed  SDValue Offset;
5906193323Sed  ISD::MemIndexedMode AM = ISD::UNINDEXED;
5907193323Sed  if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5908193323Sed    return false;
5909193323Sed  // Don't create a indexed load / store with zero offset.
5910193323Sed  if (isa<ConstantSDNode>(Offset) &&
5911193323Sed      cast<ConstantSDNode>(Offset)->isNullValue())
5912193323Sed    return false;
5913193323Sed
5914193323Sed  // Try turning it into a pre-indexed load / store except when:
5915193323Sed  // 1) The new base ptr is a frame index.
5916193323Sed  // 2) If N is a store and the new base ptr is either the same as or is a
5917193323Sed  //    predecessor of the value being stored.
5918193323Sed  // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5919193323Sed  //    that would create a cycle.
5920193323Sed  // 4) All uses are load / store ops that use it as old base ptr.
5921193323Sed
5922193323Sed  // Check #1.  Preinc'ing a frame index would require copying the stack pointer
5923193323Sed  // (plus the implicit offset) to a register to preinc anyway.
5924193323Sed  if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5925193323Sed    return false;
5926193323Sed
5927193323Sed  // Check #2.
5928193323Sed  if (!isLoad) {
5929193323Sed    SDValue Val = cast<StoreSDNode>(N)->getValue();
5930193323Sed    if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5931193323Sed      return false;
5932193323Sed  }
5933193323Sed
5934193323Sed  // Now check for #3 and #4.
5935193323Sed  bool RealUse = false;
5936224145Sdim
5937224145Sdim  // Caches for hasPredecessorHelper
5938224145Sdim  SmallPtrSet<const SDNode *, 32> Visited;
5939224145Sdim  SmallVector<const SDNode *, 16> Worklist;
5940224145Sdim
5941193323Sed  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5942193323Sed         E = Ptr.getNode()->use_end(); I != E; ++I) {
5943193323Sed    SDNode *Use = *I;
5944193323Sed    if (Use == N)
5945193323Sed      continue;
5946224145Sdim    if (N->hasPredecessorHelper(Use, Visited, Worklist))
5947193323Sed      return false;
5948193323Sed
5949193323Sed    if (!((Use->getOpcode() == ISD::LOAD &&
5950193323Sed           cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5951193323Sed          (Use->getOpcode() == ISD::STORE &&
5952193323Sed           cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5953193323Sed      RealUse = true;
5954193323Sed  }
5955193323Sed
5956193323Sed  if (!RealUse)
5957193323Sed    return false;
5958193323Sed
5959193323Sed  SDValue Result;
5960193323Sed  if (isLoad)
5961193323Sed    Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5962193323Sed                                BasePtr, Offset, AM);
5963193323Sed  else
5964193323Sed    Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5965193323Sed                                 BasePtr, Offset, AM);
5966193323Sed  ++PreIndexedNodes;
5967193323Sed  ++NodesCombined;
5968202375Srdivacky  DEBUG(dbgs() << "\nReplacing.4 ";
5969198090Srdivacky        N->dump(&DAG);
5970202375Srdivacky        dbgs() << "\nWith: ";
5971198090Srdivacky        Result.getNode()->dump(&DAG);
5972202375Srdivacky        dbgs() << '\n');
5973193323Sed  WorkListRemover DeadNodes(*this);
5974193323Sed  if (isLoad) {
5975193323Sed    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5976193323Sed                                  &DeadNodes);
5977193323Sed    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5978193323Sed                                  &DeadNodes);
5979193323Sed  } else {
5980193323Sed    DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5981193323Sed                                  &DeadNodes);
5982193323Sed  }
5983193323Sed
5984193323Sed  // Finally, since the node is now dead, remove it from the graph.
5985193323Sed  DAG.DeleteNode(N);
5986193323Sed
5987193323Sed  // Replace the uses of Ptr with uses of the updated base value.
5988193323Sed  DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5989193323Sed                                &DeadNodes);
5990193323Sed  removeFromWorkList(Ptr.getNode());
5991193323Sed  DAG.DeleteNode(Ptr.getNode());
5992193323Sed
5993193323Sed  return true;
5994193323Sed}
5995193323Sed
5996193323Sed/// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5997193323Sed/// add / sub of the base pointer node into a post-indexed load / store.
5998193323Sed/// The transformation folded the add / subtract into the new indexed
5999193323Sed/// load / store effectively and all of its uses are redirected to the
6000193323Sed/// new load / store.
6001193323Sedbool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6002193323Sed  if (!LegalOperations)
6003193323Sed    return false;
6004193323Sed
6005193323Sed  bool isLoad = true;
6006193323Sed  SDValue Ptr;
6007198090Srdivacky  EVT VT;
6008193323Sed  if (LoadSDNode *LD  = dyn_cast<LoadSDNode>(N)) {
6009193323Sed    if (LD->isIndexed())
6010193323Sed      return false;
6011193323Sed    VT = LD->getMemoryVT();
6012193323Sed    if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6013193323Sed        !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6014193323Sed      return false;
6015193323Sed    Ptr = LD->getBasePtr();
6016193323Sed  } else if (StoreSDNode *ST  = dyn_cast<StoreSDNode>(N)) {
6017193323Sed    if (ST->isIndexed())
6018193323Sed      return false;
6019193323Sed    VT = ST->getMemoryVT();
6020193323Sed    if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6021193323Sed        !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6022193323Sed      return false;
6023193323Sed    Ptr = ST->getBasePtr();
6024193323Sed    isLoad = false;
6025193323Sed  } else {
6026193323Sed    return false;
6027193323Sed  }
6028193323Sed
6029193323Sed  if (Ptr.getNode()->hasOneUse())
6030193323Sed    return false;
6031193323Sed
6032193323Sed  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6033193323Sed         E = Ptr.getNode()->use_end(); I != E; ++I) {
6034193323Sed    SDNode *Op = *I;
6035193323Sed    if (Op == N ||
6036193323Sed        (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6037193323Sed      continue;
6038193323Sed
6039193323Sed    SDValue BasePtr;
6040193323Sed    SDValue Offset;
6041193323Sed    ISD::MemIndexedMode AM = ISD::UNINDEXED;
6042193323Sed    if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6043193323Sed      // Don't create a indexed load / store with zero offset.
6044193323Sed      if (isa<ConstantSDNode>(Offset) &&
6045193323Sed          cast<ConstantSDNode>(Offset)->isNullValue())
6046193323Sed        continue;
6047193323Sed
6048193323Sed      // Try turning it into a post-indexed load / store except when
6049193323Sed      // 1) All uses are load / store ops that use it as base ptr.
6050193323Sed      // 2) Op must be independent of N, i.e. Op is neither a predecessor
6051193323Sed      //    nor a successor of N. Otherwise, if Op is folded that would
6052193323Sed      //    create a cycle.
6053193323Sed
6054193323Sed      if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6055193323Sed        continue;
6056193323Sed
6057193323Sed      // Check for #1.
6058193323Sed      bool TryNext = false;
6059193323Sed      for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6060193323Sed             EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6061193323Sed        SDNode *Use = *II;
6062193323Sed        if (Use == Ptr.getNode())
6063193323Sed          continue;
6064193323Sed
6065193323Sed        // If all the uses are load / store addresses, then don't do the
6066193323Sed        // transformation.
6067193323Sed        if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6068193323Sed          bool RealUse = false;
6069193323Sed          for (SDNode::use_iterator III = Use->use_begin(),
6070193323Sed                 EEE = Use->use_end(); III != EEE; ++III) {
6071193323Sed            SDNode *UseUse = *III;
6072193323Sed            if (!((UseUse->getOpcode() == ISD::LOAD &&
6073193323Sed                   cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
6074193323Sed                  (UseUse->getOpcode() == ISD::STORE &&
6075193323Sed                   cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
6076193323Sed              RealUse = true;
6077193323Sed          }
6078193323Sed
6079193323Sed          if (!RealUse) {
6080193323Sed            TryNext = true;
6081193323Sed            break;
6082193323Sed          }
6083193323Sed        }
6084193323Sed      }
6085193323Sed
6086193323Sed      if (TryNext)
6087193323Sed        continue;
6088193323Sed
6089193323Sed      // Check for #2
6090193323Sed      if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6091193323Sed        SDValue Result = isLoad
6092193323Sed          ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6093193323Sed                               BasePtr, Offset, AM)
6094193323Sed          : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6095193323Sed                                BasePtr, Offset, AM);
6096193323Sed        ++PostIndexedNodes;
6097193323Sed        ++NodesCombined;
6098202375Srdivacky        DEBUG(dbgs() << "\nReplacing.5 ";
6099198090Srdivacky              N->dump(&DAG);
6100202375Srdivacky              dbgs() << "\nWith: ";
6101198090Srdivacky              Result.getNode()->dump(&DAG);
6102202375Srdivacky              dbgs() << '\n');
6103193323Sed        WorkListRemover DeadNodes(*this);
6104193323Sed        if (isLoad) {
6105193323Sed          DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6106193323Sed                                        &DeadNodes);
6107193323Sed          DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6108193323Sed                                        &DeadNodes);
6109193323Sed        } else {
6110193323Sed          DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6111193323Sed                                        &DeadNodes);
6112193323Sed        }
6113193323Sed
6114193323Sed        // Finally, since the node is now dead, remove it from the graph.
6115193323Sed        DAG.DeleteNode(N);
6116193323Sed
6117193323Sed        // Replace the uses of Use with uses of the updated base value.
6118193323Sed        DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6119193323Sed                                      Result.getValue(isLoad ? 1 : 0),
6120193323Sed                                      &DeadNodes);
6121193323Sed        removeFromWorkList(Op);
6122193323Sed        DAG.DeleteNode(Op);
6123193323Sed        return true;
6124193323Sed      }
6125193323Sed    }
6126193323Sed  }
6127193323Sed
6128193323Sed  return false;
6129193323Sed}
6130193323Sed
6131193323SedSDValue DAGCombiner::visitLOAD(SDNode *N) {
6132193323Sed  LoadSDNode *LD  = cast<LoadSDNode>(N);
6133193323Sed  SDValue Chain = LD->getChain();
6134193323Sed  SDValue Ptr   = LD->getBasePtr();
6135193323Sed
6136193323Sed  // If load is not volatile and there are no uses of the loaded value (and
6137193323Sed  // the updated indexed value in case of indexed loads), change uses of the
6138193323Sed  // chain value into uses of the chain input (i.e. delete the dead load).
6139193323Sed  if (!LD->isVolatile()) {
6140193323Sed    if (N->getValueType(1) == MVT::Other) {
6141193323Sed      // Unindexed loads.
6142193323Sed      if (N->hasNUsesOfValue(0, 0)) {
6143193323Sed        // It's not safe to use the two value CombineTo variant here. e.g.
6144193323Sed        // v1, chain2 = load chain1, loc
6145193323Sed        // v2, chain3 = load chain2, loc
6146193323Sed        // v3         = add v2, c
6147193323Sed        // Now we replace use of chain2 with chain1.  This makes the second load
6148193323Sed        // isomorphic to the one we are deleting, and thus makes this load live.
6149202375Srdivacky        DEBUG(dbgs() << "\nReplacing.6 ";
6150198090Srdivacky              N->dump(&DAG);
6151202375Srdivacky              dbgs() << "\nWith chain: ";
6152198090Srdivacky              Chain.getNode()->dump(&DAG);
6153202375Srdivacky              dbgs() << "\n");
6154193323Sed        WorkListRemover DeadNodes(*this);
6155193323Sed        DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
6156193323Sed
6157193323Sed        if (N->use_empty()) {
6158193323Sed          removeFromWorkList(N);
6159193323Sed          DAG.DeleteNode(N);
6160193323Sed        }
6161193323Sed
6162193323Sed        return SDValue(N, 0);   // Return N so it doesn't get rechecked!
6163193323Sed      }
6164193323Sed    } else {
6165193323Sed      // Indexed loads.
6166193323Sed      assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
6167193323Sed      if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
6168193323Sed        SDValue Undef = DAG.getUNDEF(N->getValueType(0));
6169204642Srdivacky        DEBUG(dbgs() << "\nReplacing.7 ";
6170198090Srdivacky              N->dump(&DAG);
6171202375Srdivacky              dbgs() << "\nWith: ";
6172198090Srdivacky              Undef.getNode()->dump(&DAG);
6173202375Srdivacky              dbgs() << " and 2 other values\n");
6174193323Sed        WorkListRemover DeadNodes(*this);
6175193323Sed        DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
6176193323Sed        DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
6177193323Sed                                      DAG.getUNDEF(N->getValueType(1)),
6178193323Sed                                      &DeadNodes);
6179193323Sed        DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
6180193323Sed        removeFromWorkList(N);
6181193323Sed        DAG.DeleteNode(N);
6182193323Sed        return SDValue(N, 0);   // Return N so it doesn't get rechecked!
6183193323Sed      }
6184193323Sed    }
6185193323Sed  }
6186193323Sed
6187193323Sed  // If this load is directly stored, replace the load value with the stored
6188193323Sed  // value.
6189193323Sed  // TODO: Handle store large -> read small portion.
6190193323Sed  // TODO: Handle TRUNCSTORE/LOADEXT
6191221345Sdim  if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6192193323Sed    if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6193193323Sed      StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
6194193323Sed      if (PrevST->getBasePtr() == Ptr &&
6195193323Sed          PrevST->getValue().getValueType() == N->getValueType(0))
6196193323Sed      return CombineTo(N, Chain.getOperand(1), Chain);
6197193323Sed    }
6198193323Sed  }
6199193323Sed
6200206083Srdivacky  // Try to infer better alignment information than the load already has.
6201206083Srdivacky  if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
6202206083Srdivacky    if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6203206083Srdivacky      if (Align > LD->getAlignment())
6204218893Sdim        return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
6205218893Sdim                              LD->getValueType(0),
6206218893Sdim                              Chain, Ptr, LD->getPointerInfo(),
6207218893Sdim                              LD->getMemoryVT(),
6208206083Srdivacky                              LD->isVolatile(), LD->isNonTemporal(), Align);
6209206083Srdivacky    }
6210206083Srdivacky  }
6211206083Srdivacky
6212193323Sed  if (CombinerAA) {
6213193323Sed    // Walk up chain skipping non-aliasing memory nodes.
6214193323Sed    SDValue BetterChain = FindBetterChain(N, Chain);
6215193323Sed
6216193323Sed    // If there is a better chain.
6217193323Sed    if (Chain != BetterChain) {
6218193323Sed      SDValue ReplLoad;
6219193323Sed
6220193323Sed      // Replace the chain to void dependency.
6221193323Sed      if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6222193323Sed        ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
6223218893Sdim                               BetterChain, Ptr, LD->getPointerInfo(),
6224203954Srdivacky                               LD->isVolatile(), LD->isNonTemporal(),
6225203954Srdivacky                               LD->getAlignment());
6226193323Sed      } else {
6227218893Sdim        ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
6228218893Sdim                                  LD->getValueType(0),
6229218893Sdim                                  BetterChain, Ptr, LD->getPointerInfo(),
6230193323Sed                                  LD->getMemoryVT(),
6231193323Sed                                  LD->isVolatile(),
6232203954Srdivacky                                  LD->isNonTemporal(),
6233193323Sed                                  LD->getAlignment());
6234193323Sed      }
6235193323Sed
6236193323Sed      // Create token factor to keep old chain connected.
6237193323Sed      SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6238193323Sed                                  MVT::Other, Chain, ReplLoad.getValue(1));
6239218893Sdim
6240198090Srdivacky      // Make sure the new and old chains are cleaned up.
6241198090Srdivacky      AddToWorkList(Token.getNode());
6242218893Sdim
6243193323Sed      // Replace uses with load result and token factor. Don't add users
6244193323Sed      // to work list.
6245193323Sed      return CombineTo(N, ReplLoad.getValue(0), Token, false);
6246193323Sed    }
6247193323Sed  }
6248193323Sed
6249193323Sed  // Try transforming N to an indexed load.
6250193323Sed  if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6251193323Sed    return SDValue(N, 0);
6252193323Sed
6253193323Sed  return SDValue();
6254193323Sed}
6255193323Sed
6256207618Srdivacky/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
6257207618Srdivacky/// load is having specific bytes cleared out.  If so, return the byte size
6258207618Srdivacky/// being masked out and the shift amount.
6259207618Srdivackystatic std::pair<unsigned, unsigned>
6260207618SrdivackyCheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
6261207618Srdivacky  std::pair<unsigned, unsigned> Result(0, 0);
6262218893Sdim
6263207618Srdivacky  // Check for the structure we're looking for.
6264207618Srdivacky  if (V->getOpcode() != ISD::AND ||
6265207618Srdivacky      !isa<ConstantSDNode>(V->getOperand(1)) ||
6266207618Srdivacky      !ISD::isNormalLoad(V->getOperand(0).getNode()))
6267207618Srdivacky    return Result;
6268218893Sdim
6269207618Srdivacky  // Check the chain and pointer.
6270207618Srdivacky  LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
6271207618Srdivacky  if (LD->getBasePtr() != Ptr) return Result;  // Not from same pointer.
6272218893Sdim
6273207618Srdivacky  // The store should be chained directly to the load or be an operand of a
6274207618Srdivacky  // tokenfactor.
6275207618Srdivacky  if (LD == Chain.getNode())
6276207618Srdivacky    ; // ok.
6277207618Srdivacky  else if (Chain->getOpcode() != ISD::TokenFactor)
6278207618Srdivacky    return Result; // Fail.
6279207618Srdivacky  else {
6280207618Srdivacky    bool isOk = false;
6281207618Srdivacky    for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
6282207618Srdivacky      if (Chain->getOperand(i).getNode() == LD) {
6283207618Srdivacky        isOk = true;
6284207618Srdivacky        break;
6285207618Srdivacky      }
6286207618Srdivacky    if (!isOk) return Result;
6287207618Srdivacky  }
6288218893Sdim
6289207618Srdivacky  // This only handles simple types.
6290207618Srdivacky  if (V.getValueType() != MVT::i16 &&
6291207618Srdivacky      V.getValueType() != MVT::i32 &&
6292207618Srdivacky      V.getValueType() != MVT::i64)
6293207618Srdivacky    return Result;
6294193323Sed
6295207618Srdivacky  // Check the constant mask.  Invert it so that the bits being masked out are
6296207618Srdivacky  // 0 and the bits being kept are 1.  Use getSExtValue so that leading bits
6297207618Srdivacky  // follow the sign bit for uniformity.
6298207618Srdivacky  uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6299207618Srdivacky  unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6300207618Srdivacky  if (NotMaskLZ & 7) return Result;  // Must be multiple of a byte.
6301207618Srdivacky  unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6302207618Srdivacky  if (NotMaskTZ & 7) return Result;  // Must be multiple of a byte.
6303207618Srdivacky  if (NotMaskLZ == 64) return Result;  // All zero mask.
6304218893Sdim
6305207618Srdivacky  // See if we have a continuous run of bits.  If so, we have 0*1+0*
6306207618Srdivacky  if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6307207618Srdivacky    return Result;
6308207618Srdivacky
6309207618Srdivacky  // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6310207618Srdivacky  if (V.getValueType() != MVT::i64 && NotMaskLZ)
6311207618Srdivacky    NotMaskLZ -= 64-V.getValueSizeInBits();
6312218893Sdim
6313207618Srdivacky  unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6314207618Srdivacky  switch (MaskedBytes) {
6315218893Sdim  case 1:
6316218893Sdim  case 2:
6317207618Srdivacky  case 4: break;
6318207618Srdivacky  default: return Result; // All one mask, or 5-byte mask.
6319207618Srdivacky  }
6320218893Sdim
6321207618Srdivacky  // Verify that the first bit starts at a multiple of mask so that the access
6322207618Srdivacky  // is aligned the same as the access width.
6323207618Srdivacky  if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6324218893Sdim
6325207618Srdivacky  Result.first = MaskedBytes;
6326207618Srdivacky  Result.second = NotMaskTZ/8;
6327207618Srdivacky  return Result;
6328207618Srdivacky}
6329207618Srdivacky
6330207618Srdivacky
6331207618Srdivacky/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6332207618Srdivacky/// provides a value as specified by MaskInfo.  If so, replace the specified
6333207618Srdivacky/// store with a narrower store of truncated IVal.
6334207618Srdivackystatic SDNode *
6335207618SrdivackyShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6336207618Srdivacky                                SDValue IVal, StoreSDNode *St,
6337207618Srdivacky                                DAGCombiner *DC) {
6338207618Srdivacky  unsigned NumBytes = MaskInfo.first;
6339207618Srdivacky  unsigned ByteShift = MaskInfo.second;
6340207618Srdivacky  SelectionDAG &DAG = DC->getDAG();
6341218893Sdim
6342207618Srdivacky  // Check to see if IVal is all zeros in the part being masked in by the 'or'
6343207618Srdivacky  // that uses this.  If not, this is not a replacement.
6344207618Srdivacky  APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6345207618Srdivacky                                  ByteShift*8, (ByteShift+NumBytes)*8);
6346207618Srdivacky  if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6347218893Sdim
6348207618Srdivacky  // Check that it is legal on the target to do this.  It is legal if the new
6349207618Srdivacky  // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6350207618Srdivacky  // legalization.
6351207618Srdivacky  MVT VT = MVT::getIntegerVT(NumBytes*8);
6352207618Srdivacky  if (!DC->isTypeLegal(VT))
6353207618Srdivacky    return 0;
6354218893Sdim
6355207618Srdivacky  // Okay, we can do this!  Replace the 'St' store with a store of IVal that is
6356207618Srdivacky  // shifted by ByteShift and truncated down to NumBytes.
6357207618Srdivacky  if (ByteShift)
6358207618Srdivacky    IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6359219077Sdim                       DAG.getConstant(ByteShift*8,
6360219077Sdim                                    DC->getShiftAmountTy(IVal.getValueType())));
6361207618Srdivacky
6362207618Srdivacky  // Figure out the offset for the store and the alignment of the access.
6363207618Srdivacky  unsigned StOffset;
6364207618Srdivacky  unsigned NewAlign = St->getAlignment();
6365207618Srdivacky
6366207618Srdivacky  if (DAG.getTargetLoweringInfo().isLittleEndian())
6367207618Srdivacky    StOffset = ByteShift;
6368207618Srdivacky  else
6369207618Srdivacky    StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6370218893Sdim
6371207618Srdivacky  SDValue Ptr = St->getBasePtr();
6372207618Srdivacky  if (StOffset) {
6373207618Srdivacky    Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6374207618Srdivacky                      Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6375207618Srdivacky    NewAlign = MinAlign(NewAlign, StOffset);
6376207618Srdivacky  }
6377218893Sdim
6378207618Srdivacky  // Truncate down to the new size.
6379207618Srdivacky  IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6380218893Sdim
6381207618Srdivacky  ++OpsNarrowed;
6382218893Sdim  return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6383218893Sdim                      St->getPointerInfo().getWithOffset(StOffset),
6384207618Srdivacky                      false, false, NewAlign).getNode();
6385207618Srdivacky}
6386207618Srdivacky
6387207618Srdivacky
6388193323Sed/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6389193323Sed/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6390193323Sed/// of the loaded bits, try narrowing the load and store if it would end up
6391193323Sed/// being a win for performance or code size.
6392193323SedSDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6393193323Sed  StoreSDNode *ST  = cast<StoreSDNode>(N);
6394193323Sed  if (ST->isVolatile())
6395193323Sed    return SDValue();
6396193323Sed
6397193323Sed  SDValue Chain = ST->getChain();
6398193323Sed  SDValue Value = ST->getValue();
6399193323Sed  SDValue Ptr   = ST->getBasePtr();
6400198090Srdivacky  EVT VT = Value.getValueType();
6401193323Sed
6402193323Sed  if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6403193323Sed    return SDValue();
6404193323Sed
6405193323Sed  unsigned Opc = Value.getOpcode();
6406218893Sdim
6407207618Srdivacky  // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6408207618Srdivacky  // is a byte mask indicating a consecutive number of bytes, check to see if
6409207618Srdivacky  // Y is known to provide just those bytes.  If so, we try to replace the
6410207618Srdivacky  // load + replace + store sequence with a single (narrower) store, which makes
6411207618Srdivacky  // the load dead.
6412207618Srdivacky  if (Opc == ISD::OR) {
6413207618Srdivacky    std::pair<unsigned, unsigned> MaskedLoad;
6414207618Srdivacky    MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6415207618Srdivacky    if (MaskedLoad.first)
6416207618Srdivacky      if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6417207618Srdivacky                                                  Value.getOperand(1), ST,this))
6418207618Srdivacky        return SDValue(NewST, 0);
6419218893Sdim
6420207618Srdivacky    // Or is commutative, so try swapping X and Y.
6421207618Srdivacky    MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6422207618Srdivacky    if (MaskedLoad.first)
6423207618Srdivacky      if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6424207618Srdivacky                                                  Value.getOperand(0), ST,this))
6425207618Srdivacky        return SDValue(NewST, 0);
6426207618Srdivacky  }
6427218893Sdim
6428193323Sed  if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6429193323Sed      Value.getOperand(1).getOpcode() != ISD::Constant)
6430193323Sed    return SDValue();
6431193323Sed
6432193323Sed  SDValue N0 = Value.getOperand(0);
6433212904Sdim  if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6434212904Sdim      Chain == SDValue(N0.getNode(), 1)) {
6435193323Sed    LoadSDNode *LD = cast<LoadSDNode>(N0);
6436218893Sdim    if (LD->getBasePtr() != Ptr ||
6437218893Sdim        LD->getPointerInfo().getAddrSpace() !=
6438218893Sdim        ST->getPointerInfo().getAddrSpace())
6439193323Sed      return SDValue();
6440193323Sed
6441193323Sed    // Find the type to narrow it the load / op / store to.
6442193323Sed    SDValue N1 = Value.getOperand(1);
6443193323Sed    unsigned BitWidth = N1.getValueSizeInBits();
6444193323Sed    APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6445193323Sed    if (Opc == ISD::AND)
6446193323Sed      Imm ^= APInt::getAllOnesValue(BitWidth);
6447193323Sed    if (Imm == 0 || Imm.isAllOnesValue())
6448193323Sed      return SDValue();
6449193323Sed    unsigned ShAmt = Imm.countTrailingZeros();
6450193323Sed    unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6451193323Sed    unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6452198090Srdivacky    EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6453193323Sed    while (NewBW < BitWidth &&
6454193323Sed           !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6455193323Sed             TLI.isNarrowingProfitable(VT, NewVT))) {
6456193323Sed      NewBW = NextPowerOf2(NewBW);
6457198090Srdivacky      NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6458193323Sed    }
6459193323Sed    if (NewBW >= BitWidth)
6460193323Sed      return SDValue();
6461193323Sed
6462193323Sed    // If the lsb changed does not start at the type bitwidth boundary,
6463193323Sed    // start at the previous one.
6464193323Sed    if (ShAmt % NewBW)
6465193323Sed      ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6466193323Sed    APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6467193323Sed    if ((Imm & Mask) == Imm) {
6468193323Sed      APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6469193323Sed      if (Opc == ISD::AND)
6470193323Sed        NewImm ^= APInt::getAllOnesValue(NewBW);
6471193323Sed      uint64_t PtrOff = ShAmt / 8;
6472193323Sed      // For big endian targets, we need to adjust the offset to the pointer to
6473193323Sed      // load the correct bytes.
6474193323Sed      if (TLI.isBigEndian())
6475193323Sed        PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6476193323Sed
6477193323Sed      unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6478226633Sdim      Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6479207618Srdivacky      if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6480193323Sed        return SDValue();
6481193323Sed
6482193323Sed      SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6483193323Sed                                   Ptr.getValueType(), Ptr,
6484193323Sed                                   DAG.getConstant(PtrOff, Ptr.getValueType()));
6485193323Sed      SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6486193323Sed                                  LD->getChain(), NewPtr,
6487218893Sdim                                  LD->getPointerInfo().getWithOffset(PtrOff),
6488203954Srdivacky                                  LD->isVolatile(), LD->isNonTemporal(),
6489203954Srdivacky                                  NewAlign);
6490193323Sed      SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6491193323Sed                                   DAG.getConstant(NewImm, NewVT));
6492193323Sed      SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6493193323Sed                                   NewVal, NewPtr,
6494218893Sdim                                   ST->getPointerInfo().getWithOffset(PtrOff),
6495203954Srdivacky                                   false, false, NewAlign);
6496193323Sed
6497193323Sed      AddToWorkList(NewPtr.getNode());
6498193323Sed      AddToWorkList(NewLD.getNode());
6499193323Sed      AddToWorkList(NewVal.getNode());
6500193323Sed      WorkListRemover DeadNodes(*this);
6501193323Sed      DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6502193323Sed                                    &DeadNodes);
6503193323Sed      ++OpsNarrowed;
6504193323Sed      return NewST;
6505193323Sed    }
6506193323Sed  }
6507193323Sed
6508193323Sed  return SDValue();
6509193323Sed}
6510193323Sed
6511218893Sdim/// TransformFPLoadStorePair - For a given floating point load / store pair,
6512218893Sdim/// if the load value isn't used by any other operations, then consider
6513218893Sdim/// transforming the pair to integer load / store operations if the target
6514218893Sdim/// deems the transformation profitable.
6515218893SdimSDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6516218893Sdim  StoreSDNode *ST  = cast<StoreSDNode>(N);
6517218893Sdim  SDValue Chain = ST->getChain();
6518218893Sdim  SDValue Value = ST->getValue();
6519218893Sdim  if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6520218893Sdim      Value.hasOneUse() &&
6521218893Sdim      Chain == SDValue(Value.getNode(), 1)) {
6522218893Sdim    LoadSDNode *LD = cast<LoadSDNode>(Value);
6523218893Sdim    EVT VT = LD->getMemoryVT();
6524218893Sdim    if (!VT.isFloatingPoint() ||
6525218893Sdim        VT != ST->getMemoryVT() ||
6526218893Sdim        LD->isNonTemporal() ||
6527218893Sdim        ST->isNonTemporal() ||
6528218893Sdim        LD->getPointerInfo().getAddrSpace() != 0 ||
6529218893Sdim        ST->getPointerInfo().getAddrSpace() != 0)
6530218893Sdim      return SDValue();
6531218893Sdim
6532218893Sdim    EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6533218893Sdim    if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6534218893Sdim        !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6535218893Sdim        !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6536218893Sdim        !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
6537218893Sdim      return SDValue();
6538218893Sdim
6539218893Sdim    unsigned LDAlign = LD->getAlignment();
6540218893Sdim    unsigned STAlign = ST->getAlignment();
6541226633Sdim    Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
6542218893Sdim    unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
6543218893Sdim    if (LDAlign < ABIAlign || STAlign < ABIAlign)
6544218893Sdim      return SDValue();
6545218893Sdim
6546218893Sdim    SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
6547218893Sdim                                LD->getChain(), LD->getBasePtr(),
6548218893Sdim                                LD->getPointerInfo(),
6549218893Sdim                                false, false, LDAlign);
6550218893Sdim
6551218893Sdim    SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
6552218893Sdim                                 NewLD, ST->getBasePtr(),
6553218893Sdim                                 ST->getPointerInfo(),
6554218893Sdim                                 false, false, STAlign);
6555218893Sdim
6556218893Sdim    AddToWorkList(NewLD.getNode());
6557218893Sdim    AddToWorkList(NewST.getNode());
6558218893Sdim    WorkListRemover DeadNodes(*this);
6559218893Sdim    DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1),
6560218893Sdim                                  &DeadNodes);
6561218893Sdim    ++LdStFP2Int;
6562218893Sdim    return NewST;
6563218893Sdim  }
6564218893Sdim
6565218893Sdim  return SDValue();
6566218893Sdim}
6567218893Sdim
6568193323SedSDValue DAGCombiner::visitSTORE(SDNode *N) {
6569193323Sed  StoreSDNode *ST  = cast<StoreSDNode>(N);
6570193323Sed  SDValue Chain = ST->getChain();
6571193323Sed  SDValue Value = ST->getValue();
6572193323Sed  SDValue Ptr   = ST->getBasePtr();
6573193323Sed
6574193323Sed  // If this is a store of a bit convert, store the input value if the
6575193323Sed  // resultant store does not need a higher alignment than the original.
6576218893Sdim  if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6577193323Sed      ST->isUnindexed()) {
6578193323Sed    unsigned OrigAlign = ST->getAlignment();
6579198090Srdivacky    EVT SVT = Value.getOperand(0).getValueType();
6580193323Sed    unsigned Align = TLI.getTargetData()->
6581198090Srdivacky      getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6582193323Sed    if (Align <= OrigAlign &&
6583193323Sed        ((!LegalOperations && !ST->isVolatile()) ||
6584193323Sed         TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6585193323Sed      return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6586218893Sdim                          Ptr, ST->getPointerInfo(), ST->isVolatile(),
6587203954Srdivacky                          ST->isNonTemporal(), OrigAlign);
6588193323Sed  }
6589193323Sed
6590221345Sdim  // Turn 'store undef, Ptr' -> nothing.
6591221345Sdim  if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
6592221345Sdim    return Chain;
6593221345Sdim
6594193323Sed  // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6595193323Sed  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6596193323Sed    // NOTE: If the original store is volatile, this transform must not increase
6597193323Sed    // the number of stores.  For example, on x86-32 an f64 can be stored in one
6598193323Sed    // processor operation but an i64 (which is not legal) requires two.  So the
6599193323Sed    // transform should not be done in this case.
6600193323Sed    if (Value.getOpcode() != ISD::TargetConstantFP) {
6601193323Sed      SDValue Tmp;
6602198090Srdivacky      switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6603198090Srdivacky      default: llvm_unreachable("Unknown FP type");
6604193323Sed      case MVT::f80:    // We don't do this for these yet.
6605193323Sed      case MVT::f128:
6606193323Sed      case MVT::ppcf128:
6607193323Sed        break;
6608193323Sed      case MVT::f32:
6609207618Srdivacky        if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6610193323Sed            TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6611193323Sed          Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6612193323Sed                              bitcastToAPInt().getZExtValue(), MVT::i32);
6613193323Sed          return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6614218893Sdim                              Ptr, ST->getPointerInfo(), ST->isVolatile(),
6615203954Srdivacky                              ST->isNonTemporal(), ST->getAlignment());
6616193323Sed        }
6617193323Sed        break;
6618193323Sed      case MVT::f64:
6619207618Srdivacky        if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6620193323Sed             !ST->isVolatile()) ||
6621193323Sed            TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6622193323Sed          Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6623193323Sed                                getZExtValue(), MVT::i64);
6624193323Sed          return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6625218893Sdim                              Ptr, ST->getPointerInfo(), ST->isVolatile(),
6626203954Srdivacky                              ST->isNonTemporal(), ST->getAlignment());
6627221345Sdim        }
6628221345Sdim
6629221345Sdim        if (!ST->isVolatile() &&
6630221345Sdim            TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6631193323Sed          // Many FP stores are not made apparent until after legalize, e.g. for
6632193323Sed          // argument passing.  Since this is so common, custom legalize the
6633193323Sed          // 64-bit integer store into two 32-bit stores.
6634193323Sed          uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6635193323Sed          SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6636193323Sed          SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6637193323Sed          if (TLI.isBigEndian()) std::swap(Lo, Hi);
6638193323Sed
6639193323Sed          unsigned Alignment = ST->getAlignment();
6640193323Sed          bool isVolatile = ST->isVolatile();
6641203954Srdivacky          bool isNonTemporal = ST->isNonTemporal();
6642193323Sed
6643193323Sed          SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6644218893Sdim                                     Ptr, ST->getPointerInfo(),
6645203954Srdivacky                                     isVolatile, isNonTemporal,
6646203954Srdivacky                                     ST->getAlignment());
6647193323Sed          Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6648193323Sed                            DAG.getConstant(4, Ptr.getValueType()));
6649193323Sed          Alignment = MinAlign(Alignment, 4U);
6650193323Sed          SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6651218893Sdim                                     Ptr, ST->getPointerInfo().getWithOffset(4),
6652218893Sdim                                     isVolatile, isNonTemporal,
6653203954Srdivacky                                     Alignment);
6654193323Sed          return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6655193323Sed                             St0, St1);
6656193323Sed        }
6657193323Sed
6658193323Sed        break;
6659193323Sed      }
6660193323Sed    }
6661193323Sed  }
6662193323Sed
6663206083Srdivacky  // Try to infer better alignment information than the store already has.
6664206083Srdivacky  if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6665206083Srdivacky    if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6666206083Srdivacky      if (Align > ST->getAlignment())
6667206083Srdivacky        return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6668218893Sdim                                 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6669206083Srdivacky                                 ST->isVolatile(), ST->isNonTemporal(), Align);
6670206083Srdivacky    }
6671206083Srdivacky  }
6672206083Srdivacky
6673218893Sdim  // Try transforming a pair floating point load / store ops to integer
6674218893Sdim  // load / store ops.
6675218893Sdim  SDValue NewST = TransformFPLoadStorePair(N);
6676218893Sdim  if (NewST.getNode())
6677218893Sdim    return NewST;
6678218893Sdim
6679193323Sed  if (CombinerAA) {
6680193323Sed    // Walk up chain skipping non-aliasing memory nodes.
6681193323Sed    SDValue BetterChain = FindBetterChain(N, Chain);
6682193323Sed
6683193323Sed    // If there is a better chain.
6684193323Sed    if (Chain != BetterChain) {
6685198090Srdivacky      SDValue ReplStore;
6686198090Srdivacky
6687193323Sed      // Replace the chain to avoid dependency.
6688193323Sed      if (ST->isTruncatingStore()) {
6689193323Sed        ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6690218893Sdim                                      ST->getPointerInfo(),
6691203954Srdivacky                                      ST->getMemoryVT(), ST->isVolatile(),
6692203954Srdivacky                                      ST->isNonTemporal(), ST->getAlignment());
6693193323Sed      } else {
6694193323Sed        ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6695218893Sdim                                 ST->getPointerInfo(),
6696203954Srdivacky                                 ST->isVolatile(), ST->isNonTemporal(),
6697203954Srdivacky                                 ST->getAlignment());
6698193323Sed      }
6699193323Sed
6700193323Sed      // Create token to keep both nodes around.
6701193323Sed      SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6702193323Sed                                  MVT::Other, Chain, ReplStore);
6703193323Sed
6704198090Srdivacky      // Make sure the new and old chains are cleaned up.
6705198090Srdivacky      AddToWorkList(Token.getNode());
6706198090Srdivacky
6707193323Sed      // Don't add users to work list.
6708193323Sed      return CombineTo(N, Token, false);
6709193323Sed    }
6710193323Sed  }
6711193323Sed
6712193323Sed  // Try transforming N to an indexed store.
6713193323Sed  if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6714193323Sed    return SDValue(N, 0);
6715193323Sed
6716193323Sed  // FIXME: is there such a thing as a truncating indexed store?
6717193323Sed  if (ST->isTruncatingStore() && ST->isUnindexed() &&
6718193323Sed      Value.getValueType().isInteger()) {
6719193323Sed    // See if we can simplify the input to this truncstore with knowledge that
6720193323Sed    // only the low bits are being used.  For example:
6721193323Sed    // "truncstore (or (shl x, 8), y), i8"  -> "truncstore y, i8"
6722193323Sed    SDValue Shorter =
6723193323Sed      GetDemandedBits(Value,
6724224145Sdim                      APInt::getLowBitsSet(
6725224145Sdim                        Value.getValueType().getScalarType().getSizeInBits(),
6726224145Sdim                        ST->getMemoryVT().getScalarType().getSizeInBits()));
6727193323Sed    AddToWorkList(Value.getNode());
6728193323Sed    if (Shorter.getNode())
6729193323Sed      return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6730218893Sdim                               Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6731203954Srdivacky                               ST->isVolatile(), ST->isNonTemporal(),
6732203954Srdivacky                               ST->getAlignment());
6733193323Sed
6734193323Sed    // Otherwise, see if we can simplify the operation with
6735193323Sed    // SimplifyDemandedBits, which only works if the value has a single use.
6736193323Sed    if (SimplifyDemandedBits(Value,
6737218893Sdim                        APInt::getLowBitsSet(
6738218893Sdim                          Value.getValueType().getScalarType().getSizeInBits(),
6739218893Sdim                          ST->getMemoryVT().getScalarType().getSizeInBits())))
6740193323Sed      return SDValue(N, 0);
6741193323Sed  }
6742193323Sed
6743193323Sed  // If this is a load followed by a store to the same location, then the store
6744193323Sed  // is dead/noop.
6745193323Sed  if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6746193323Sed    if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6747193323Sed        ST->isUnindexed() && !ST->isVolatile() &&
6748193323Sed        // There can't be any side effects between the load and store, such as
6749193323Sed        // a call or store.
6750193323Sed        Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6751193323Sed      // The store is dead, remove it.
6752193323Sed      return Chain;
6753193323Sed    }
6754193323Sed  }
6755193323Sed
6756193323Sed  // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6757193323Sed  // truncating store.  We can do this even if this is already a truncstore.
6758193323Sed  if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6759193323Sed      && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6760193323Sed      TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6761193323Sed                            ST->getMemoryVT())) {
6762193323Sed    return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6763218893Sdim                             Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6764203954Srdivacky                             ST->isVolatile(), ST->isNonTemporal(),
6765203954Srdivacky                             ST->getAlignment());
6766193323Sed  }
6767193323Sed
6768193323Sed  return ReduceLoadOpStoreWidth(N);
6769193323Sed}
6770193323Sed
6771193323SedSDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6772193323Sed  SDValue InVec = N->getOperand(0);
6773193323Sed  SDValue InVal = N->getOperand(1);
6774193323Sed  SDValue EltNo = N->getOperand(2);
6775226633Sdim  DebugLoc dl = N->getDebugLoc();
6776193323Sed
6777208599Srdivacky  // If the inserted element is an UNDEF, just use the input vector.
6778208599Srdivacky  if (InVal.getOpcode() == ISD::UNDEF)
6779208599Srdivacky    return InVec;
6780208599Srdivacky
6781218893Sdim  EVT VT = InVec.getValueType();
6782218893Sdim
6783219077Sdim  // If we can't generate a legal BUILD_VECTOR, exit
6784218893Sdim  if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
6785218893Sdim    return SDValue();
6786218893Sdim
6787226633Sdim  // Check that we know which element is being inserted
6788226633Sdim  if (!isa<ConstantSDNode>(EltNo))
6789226633Sdim    return SDValue();
6790226633Sdim  unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6791226633Sdim
6792226633Sdim  // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
6793226633Sdim  // be converted to a BUILD_VECTOR).  Fill in the Ops vector with the
6794226633Sdim  // vector elements.
6795226633Sdim  SmallVector<SDValue, 8> Ops;
6796226633Sdim  if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
6797226633Sdim    Ops.append(InVec.getNode()->op_begin(),
6798226633Sdim               InVec.getNode()->op_end());
6799226633Sdim  } else if (InVec.getOpcode() == ISD::UNDEF) {
6800226633Sdim    unsigned NElts = VT.getVectorNumElements();
6801226633Sdim    Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
6802226633Sdim  } else {
6803226633Sdim    return SDValue();
6804193323Sed  }
6805193323Sed
6806226633Sdim  // Insert the element
6807226633Sdim  if (Elt < Ops.size()) {
6808226633Sdim    // All the operands of BUILD_VECTOR must have the same type;
6809226633Sdim    // we enforce that here.
6810226633Sdim    EVT OpVT = Ops[0].getValueType();
6811226633Sdim    if (InVal.getValueType() != OpVT)
6812226633Sdim      InVal = OpVT.bitsGT(InVal.getValueType()) ?
6813226633Sdim                DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
6814226633Sdim                DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
6815226633Sdim    Ops[Elt] = InVal;
6816193323Sed  }
6817226633Sdim
6818226633Sdim  // Return the new vector
6819226633Sdim  return DAG.getNode(ISD::BUILD_VECTOR, dl,
6820226633Sdim                     VT, &Ops[0], Ops.size());
6821193323Sed}
6822193323Sed
6823193323SedSDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6824193323Sed  // (vextract (scalar_to_vector val, 0) -> val
6825193323Sed  SDValue InVec = N->getOperand(0);
6826193323Sed
6827223017Sdim  if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6828223017Sdim    // Check if the result type doesn't match the inserted element type. A
6829223017Sdim    // SCALAR_TO_VECTOR may truncate the inserted element and the
6830223017Sdim    // EXTRACT_VECTOR_ELT may widen the extracted vector.
6831223017Sdim    SDValue InOp = InVec.getOperand(0);
6832223017Sdim    EVT NVT = N->getValueType(0);
6833223017Sdim    if (InOp.getValueType() != NVT) {
6834223017Sdim      assert(InOp.getValueType().isInteger() && NVT.isInteger());
6835223017Sdim      return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6836223017Sdim    }
6837223017Sdim    return InOp;
6838223017Sdim  }
6839193323Sed
6840193323Sed  // Perform only after legalization to ensure build_vector / vector_shuffle
6841193323Sed  // optimizations have already been done.
6842193323Sed  if (!LegalOperations) return SDValue();
6843193323Sed
6844193323Sed  // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6845193323Sed  // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6846193323Sed  // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6847193323Sed  SDValue EltNo = N->getOperand(1);
6848193323Sed
6849193323Sed  if (isa<ConstantSDNode>(EltNo)) {
6850218893Sdim    int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6851193323Sed    bool NewLoad = false;
6852193323Sed    bool BCNumEltsChanged = false;
6853198090Srdivacky    EVT VT = InVec.getValueType();
6854198090Srdivacky    EVT ExtVT = VT.getVectorElementType();
6855198090Srdivacky    EVT LVT = ExtVT;
6856193323Sed
6857218893Sdim    if (InVec.getOpcode() == ISD::BITCAST) {
6858198090Srdivacky      EVT BCVT = InVec.getOperand(0).getValueType();
6859198090Srdivacky      if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6860193323Sed        return SDValue();
6861193323Sed      if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6862193323Sed        BCNumEltsChanged = true;
6863193323Sed      InVec = InVec.getOperand(0);
6864198090Srdivacky      ExtVT = BCVT.getVectorElementType();
6865193323Sed      NewLoad = true;
6866193323Sed    }
6867193323Sed
6868193323Sed    LoadSDNode *LN0 = NULL;
6869193323Sed    const ShuffleVectorSDNode *SVN = NULL;
6870193323Sed    if (ISD::isNormalLoad(InVec.getNode())) {
6871193323Sed      LN0 = cast<LoadSDNode>(InVec);
6872193323Sed    } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6873198090Srdivacky               InVec.getOperand(0).getValueType() == ExtVT &&
6874193323Sed               ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6875193323Sed      LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6876193323Sed    } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6877193323Sed      // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6878193323Sed      // =>
6879193323Sed      // (load $addr+1*size)
6880193323Sed
6881193323Sed      // If the bit convert changed the number of elements, it is unsafe
6882193323Sed      // to examine the mask.
6883193323Sed      if (BCNumEltsChanged)
6884193323Sed        return SDValue();
6885193323Sed
6886193323Sed      // Select the input vector, guarding against out of range extract vector.
6887193323Sed      unsigned NumElems = VT.getVectorNumElements();
6888218893Sdim      int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
6889193323Sed      InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6890193323Sed
6891218893Sdim      if (InVec.getOpcode() == ISD::BITCAST)
6892193323Sed        InVec = InVec.getOperand(0);
6893193323Sed      if (ISD::isNormalLoad(InVec.getNode())) {
6894193323Sed        LN0 = cast<LoadSDNode>(InVec);
6895207618Srdivacky        Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6896193323Sed      }
6897193323Sed    }
6898193323Sed
6899223017Sdim    if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6900193323Sed      return SDValue();
6901193323Sed
6902218893Sdim    // If Idx was -1 above, Elt is going to be -1, so just return undef.
6903218893Sdim    if (Elt == -1)
6904226633Sdim      return DAG.getUNDEF(LVT);
6905218893Sdim
6906193323Sed    unsigned Align = LN0->getAlignment();
6907193323Sed    if (NewLoad) {
6908193323Sed      // Check the resultant load doesn't need a higher alignment than the
6909193323Sed      // original load.
6910193323Sed      unsigned NewAlign =
6911218893Sdim        TLI.getTargetData()
6912218893Sdim            ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6913193323Sed
6914193323Sed      if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6915193323Sed        return SDValue();
6916193323Sed
6917193323Sed      Align = NewAlign;
6918193323Sed    }
6919193323Sed
6920193323Sed    SDValue NewPtr = LN0->getBasePtr();
6921218893Sdim    unsigned PtrOff = 0;
6922218893Sdim
6923193323Sed    if (Elt) {
6924218893Sdim      PtrOff = LVT.getSizeInBits() * Elt / 8;
6925198090Srdivacky      EVT PtrType = NewPtr.getValueType();
6926193323Sed      if (TLI.isBigEndian())
6927193323Sed        PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6928193323Sed      NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6929193323Sed                           DAG.getConstant(PtrOff, PtrType));
6930193323Sed    }
6931193323Sed
6932193323Sed    return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6933218893Sdim                       LN0->getPointerInfo().getWithOffset(PtrOff),
6934203954Srdivacky                       LN0->isVolatile(), LN0->isNonTemporal(), Align);
6935193323Sed  }
6936193323Sed
6937193323Sed  return SDValue();
6938193323Sed}
6939193323Sed
6940193323SedSDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6941193323Sed  unsigned NumInScalars = N->getNumOperands();
6942198090Srdivacky  EVT VT = N->getValueType(0);
6943193323Sed
6944193323Sed  // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6945193323Sed  // operations.  If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6946193323Sed  // at most two distinct vectors, turn this into a shuffle node.
6947193323Sed  SDValue VecIn1, VecIn2;
6948193323Sed  for (unsigned i = 0; i != NumInScalars; ++i) {
6949193323Sed    // Ignore undef inputs.
6950193323Sed    if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6951193323Sed
6952193323Sed    // If this input is something other than a EXTRACT_VECTOR_ELT with a
6953193323Sed    // constant index, bail out.
6954193323Sed    if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6955193323Sed        !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6956193323Sed      VecIn1 = VecIn2 = SDValue(0, 0);
6957193323Sed      break;
6958193323Sed    }
6959193323Sed
6960193323Sed    // If the input vector type disagrees with the result of the build_vector,
6961193323Sed    // we can't make a shuffle.
6962193323Sed    SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6963193323Sed    if (ExtractedFromVec.getValueType() != VT) {
6964193323Sed      VecIn1 = VecIn2 = SDValue(0, 0);
6965193323Sed      break;
6966193323Sed    }
6967193323Sed
6968193323Sed    // Otherwise, remember this.  We allow up to two distinct input vectors.
6969193323Sed    if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6970193323Sed      continue;
6971193323Sed
6972193323Sed    if (VecIn1.getNode() == 0) {
6973193323Sed      VecIn1 = ExtractedFromVec;
6974193323Sed    } else if (VecIn2.getNode() == 0) {
6975193323Sed      VecIn2 = ExtractedFromVec;
6976193323Sed    } else {
6977193323Sed      // Too many inputs.
6978193323Sed      VecIn1 = VecIn2 = SDValue(0, 0);
6979193323Sed      break;
6980193323Sed    }
6981193323Sed  }
6982193323Sed
6983193323Sed  // If everything is good, we can make a shuffle operation.
6984193323Sed  if (VecIn1.getNode()) {
6985193323Sed    SmallVector<int, 8> Mask;
6986193323Sed    for (unsigned i = 0; i != NumInScalars; ++i) {
6987193323Sed      if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6988193323Sed        Mask.push_back(-1);
6989193323Sed        continue;
6990193323Sed      }
6991193323Sed
6992193323Sed      // If extracting from the first vector, just use the index directly.
6993193323Sed      SDValue Extract = N->getOperand(i);
6994193323Sed      SDValue ExtVal = Extract.getOperand(1);
6995193323Sed      if (Extract.getOperand(0) == VecIn1) {
6996193323Sed        unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6997193323Sed        if (ExtIndex > VT.getVectorNumElements())
6998193323Sed          return SDValue();
6999218893Sdim
7000193323Sed        Mask.push_back(ExtIndex);
7001193323Sed        continue;
7002193323Sed      }
7003193323Sed
7004193323Sed      // Otherwise, use InIdx + VecSize
7005193323Sed      unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7006193323Sed      Mask.push_back(Idx+NumInScalars);
7007193323Sed    }
7008193323Sed
7009193323Sed    // Add count and size info.
7010207618Srdivacky    if (!isTypeLegal(VT))
7011193323Sed      return SDValue();
7012193323Sed
7013193323Sed    // Return the new VECTOR_SHUFFLE node.
7014193323Sed    SDValue Ops[2];
7015193323Sed    Ops[0] = VecIn1;
7016193323Sed    Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7017193323Sed    return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
7018193323Sed  }
7019193323Sed
7020193323Sed  return SDValue();
7021193323Sed}
7022193323Sed
7023193323SedSDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
7024193323Sed  // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
7025193323Sed  // EXTRACT_SUBVECTOR operations.  If so, and if the EXTRACT_SUBVECTOR vector
7026193323Sed  // inputs come from at most two distinct vectors, turn this into a shuffle
7027193323Sed  // node.
7028193323Sed
7029193323Sed  // If we only have one input vector, we don't need to do any concatenation.
7030193323Sed  if (N->getNumOperands() == 1)
7031193323Sed    return N->getOperand(0);
7032193323Sed
7033193323Sed  return SDValue();
7034193323Sed}
7035193323Sed
7036226633SdimSDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
7037226633Sdim  EVT NVT = N->getValueType(0);
7038226633Sdim  SDValue V = N->getOperand(0);
7039226633Sdim
7040226633Sdim  if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
7041226633Sdim    // Handle only simple case where vector being inserted and vector
7042226633Sdim    // being extracted are of same type, and are half size of larger vectors.
7043226633Sdim    EVT BigVT = V->getOperand(0).getValueType();
7044226633Sdim    EVT SmallVT = V->getOperand(1).getValueType();
7045226633Sdim    if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
7046226633Sdim      return SDValue();
7047226633Sdim
7048226633Sdim    // Combine:
7049226633Sdim    //    (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
7050226633Sdim    // Into:
7051226633Sdim    //    indicies are equal => V1
7052226633Sdim    //    otherwise => (extract_subvec V1, ExtIdx)
7053226633Sdim    //
7054226633Sdim    SDValue InsIdx = N->getOperand(1);
7055226633Sdim    SDValue ExtIdx = V->getOperand(2);
7056226633Sdim
7057226633Sdim    if (InsIdx == ExtIdx)
7058226633Sdim      return V->getOperand(1);
7059226633Sdim    return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
7060226633Sdim                       V->getOperand(0), N->getOperand(1));
7061226633Sdim  }
7062226633Sdim
7063226633Sdim  return SDValue();
7064226633Sdim}
7065226633Sdim
7066193323SedSDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
7067198090Srdivacky  EVT VT = N->getValueType(0);
7068193323Sed  unsigned NumElts = VT.getVectorNumElements();
7069193323Sed
7070193323Sed  SDValue N0 = N->getOperand(0);
7071193323Sed
7072193323Sed  assert(N0.getValueType().getVectorNumElements() == NumElts &&
7073193323Sed        "Vector shuffle must be normalized in DAG");
7074193323Sed
7075193323Sed  // FIXME: implement canonicalizations from DAG.getVectorShuffle()
7076193323Sed
7077218893Sdim  // If it is a splat, check if the argument vector is another splat or a
7078218893Sdim  // build_vector with all scalar elements the same.
7079218893Sdim  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7080218893Sdim  if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
7081193323Sed    SDNode *V = N0.getNode();
7082193323Sed
7083193323Sed    // If this is a bit convert that changes the element type of the vector but
7084193323Sed    // not the number of vector elements, look through it.  Be careful not to
7085193323Sed    // look though conversions that change things like v4f32 to v2f64.
7086218893Sdim    if (V->getOpcode() == ISD::BITCAST) {
7087193323Sed      SDValue ConvInput = V->getOperand(0);
7088193323Sed      if (ConvInput.getValueType().isVector() &&
7089193323Sed          ConvInput.getValueType().getVectorNumElements() == NumElts)
7090193323Sed        V = ConvInput.getNode();
7091193323Sed    }
7092193323Sed
7093193323Sed    if (V->getOpcode() == ISD::BUILD_VECTOR) {
7094218893Sdim      assert(V->getNumOperands() == NumElts &&
7095218893Sdim             "BUILD_VECTOR has wrong number of operands");
7096218893Sdim      SDValue Base;
7097218893Sdim      bool AllSame = true;
7098218893Sdim      for (unsigned i = 0; i != NumElts; ++i) {
7099218893Sdim        if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7100218893Sdim          Base = V->getOperand(i);
7101218893Sdim          break;
7102193323Sed        }
7103218893Sdim      }
7104218893Sdim      // Splat of <u, u, u, u>, return <u, u, u, u>
7105218893Sdim      if (!Base.getNode())
7106218893Sdim        return N0;
7107218893Sdim      for (unsigned i = 0; i != NumElts; ++i) {
7108218893Sdim        if (V->getOperand(i) != Base) {
7109218893Sdim          AllSame = false;
7110218893Sdim          break;
7111193323Sed        }
7112193323Sed      }
7113218893Sdim      // Splat of <x, x, x, x>, return <x, x, x, x>
7114218893Sdim      if (AllSame)
7115218893Sdim        return N0;
7116193323Sed    }
7117193323Sed  }
7118193323Sed  return SDValue();
7119193323Sed}
7120193323Sed
7121210299SedSDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
7122210299Sed  if (!TLI.getShouldFoldAtomicFences())
7123210299Sed    return SDValue();
7124210299Sed
7125210299Sed  SDValue atomic = N->getOperand(0);
7126210299Sed  switch (atomic.getOpcode()) {
7127210299Sed    case ISD::ATOMIC_CMP_SWAP:
7128210299Sed    case ISD::ATOMIC_SWAP:
7129210299Sed    case ISD::ATOMIC_LOAD_ADD:
7130210299Sed    case ISD::ATOMIC_LOAD_SUB:
7131210299Sed    case ISD::ATOMIC_LOAD_AND:
7132210299Sed    case ISD::ATOMIC_LOAD_OR:
7133210299Sed    case ISD::ATOMIC_LOAD_XOR:
7134210299Sed    case ISD::ATOMIC_LOAD_NAND:
7135210299Sed    case ISD::ATOMIC_LOAD_MIN:
7136210299Sed    case ISD::ATOMIC_LOAD_MAX:
7137210299Sed    case ISD::ATOMIC_LOAD_UMIN:
7138210299Sed    case ISD::ATOMIC_LOAD_UMAX:
7139210299Sed      break;
7140210299Sed    default:
7141210299Sed      return SDValue();
7142210299Sed  }
7143210299Sed
7144210299Sed  SDValue fence = atomic.getOperand(0);
7145210299Sed  if (fence.getOpcode() != ISD::MEMBARRIER)
7146210299Sed    return SDValue();
7147210299Sed
7148210299Sed  switch (atomic.getOpcode()) {
7149210299Sed    case ISD::ATOMIC_CMP_SWAP:
7150210299Sed      return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7151210299Sed                                    fence.getOperand(0),
7152210299Sed                                    atomic.getOperand(1), atomic.getOperand(2),
7153210299Sed                                    atomic.getOperand(3)), atomic.getResNo());
7154210299Sed    case ISD::ATOMIC_SWAP:
7155210299Sed    case ISD::ATOMIC_LOAD_ADD:
7156210299Sed    case ISD::ATOMIC_LOAD_SUB:
7157210299Sed    case ISD::ATOMIC_LOAD_AND:
7158210299Sed    case ISD::ATOMIC_LOAD_OR:
7159210299Sed    case ISD::ATOMIC_LOAD_XOR:
7160210299Sed    case ISD::ATOMIC_LOAD_NAND:
7161210299Sed    case ISD::ATOMIC_LOAD_MIN:
7162210299Sed    case ISD::ATOMIC_LOAD_MAX:
7163210299Sed    case ISD::ATOMIC_LOAD_UMIN:
7164210299Sed    case ISD::ATOMIC_LOAD_UMAX:
7165210299Sed      return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7166210299Sed                                    fence.getOperand(0),
7167210299Sed                                    atomic.getOperand(1), atomic.getOperand(2)),
7168210299Sed                     atomic.getResNo());
7169210299Sed    default:
7170210299Sed      return SDValue();
7171210299Sed  }
7172210299Sed}
7173210299Sed
7174193323Sed/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
7175193323Sed/// an AND to a vector_shuffle with the destination vector and a zero vector.
7176193323Sed/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
7177193323Sed///      vector_shuffle V, Zero, <0, 4, 2, 4>
7178193323SedSDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
7179198090Srdivacky  EVT VT = N->getValueType(0);
7180193323Sed  DebugLoc dl = N->getDebugLoc();
7181193323Sed  SDValue LHS = N->getOperand(0);
7182193323Sed  SDValue RHS = N->getOperand(1);
7183193323Sed  if (N->getOpcode() == ISD::AND) {
7184218893Sdim    if (RHS.getOpcode() == ISD::BITCAST)
7185193323Sed      RHS = RHS.getOperand(0);
7186193323Sed    if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
7187193323Sed      SmallVector<int, 8> Indices;
7188193323Sed      unsigned NumElts = RHS.getNumOperands();
7189193323Sed      for (unsigned i = 0; i != NumElts; ++i) {
7190193323Sed        SDValue Elt = RHS.getOperand(i);
7191193323Sed        if (!isa<ConstantSDNode>(Elt))
7192193323Sed          return SDValue();
7193193323Sed        else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
7194193323Sed          Indices.push_back(i);
7195193323Sed        else if (cast<ConstantSDNode>(Elt)->isNullValue())
7196193323Sed          Indices.push_back(NumElts);
7197193323Sed        else
7198193323Sed          return SDValue();
7199193323Sed      }
7200193323Sed
7201193323Sed      // Let's see if the target supports this vector_shuffle.
7202198090Srdivacky      EVT RVT = RHS.getValueType();
7203193323Sed      if (!TLI.isVectorClearMaskLegal(Indices, RVT))
7204193323Sed        return SDValue();
7205193323Sed
7206193323Sed      // Return the new VECTOR_SHUFFLE node.
7207198090Srdivacky      EVT EltVT = RVT.getVectorElementType();
7208193323Sed      SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
7209198090Srdivacky                                     DAG.getConstant(0, EltVT));
7210193323Sed      SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7211193323Sed                                 RVT, &ZeroOps[0], ZeroOps.size());
7212218893Sdim      LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
7213193323Sed      SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
7214218893Sdim      return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
7215193323Sed    }
7216193323Sed  }
7217193323Sed
7218193323Sed  return SDValue();
7219193323Sed}
7220193323Sed
7221193323Sed/// SimplifyVBinOp - Visit a binary vector operation, like ADD.
7222193323SedSDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
7223193323Sed  // After legalize, the target may be depending on adds and other
7224193323Sed  // binary ops to provide legal ways to construct constants or other
7225193323Sed  // things. Simplifying them may result in a loss of legality.
7226193323Sed  if (LegalOperations) return SDValue();
7227193323Sed
7228218893Sdim  assert(N->getValueType(0).isVector() &&
7229218893Sdim         "SimplifyVBinOp only works on vectors!");
7230193323Sed
7231193323Sed  SDValue LHS = N->getOperand(0);
7232193323Sed  SDValue RHS = N->getOperand(1);
7233193323Sed  SDValue Shuffle = XformToShuffleWithZero(N);
7234193323Sed  if (Shuffle.getNode()) return Shuffle;
7235193323Sed
7236193323Sed  // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
7237193323Sed  // this operation.
7238193323Sed  if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
7239193323Sed      RHS.getOpcode() == ISD::BUILD_VECTOR) {
7240193323Sed    SmallVector<SDValue, 8> Ops;
7241193323Sed    for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
7242193323Sed      SDValue LHSOp = LHS.getOperand(i);
7243193323Sed      SDValue RHSOp = RHS.getOperand(i);
7244193323Sed      // If these two elements can't be folded, bail out.
7245193323Sed      if ((LHSOp.getOpcode() != ISD::UNDEF &&
7246193323Sed           LHSOp.getOpcode() != ISD::Constant &&
7247193323Sed           LHSOp.getOpcode() != ISD::ConstantFP) ||
7248193323Sed          (RHSOp.getOpcode() != ISD::UNDEF &&
7249193323Sed           RHSOp.getOpcode() != ISD::Constant &&
7250193323Sed           RHSOp.getOpcode() != ISD::ConstantFP))
7251193323Sed        break;
7252193323Sed
7253193323Sed      // Can't fold divide by zero.
7254193323Sed      if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
7255193323Sed          N->getOpcode() == ISD::FDIV) {
7256193323Sed        if ((RHSOp.getOpcode() == ISD::Constant &&
7257193323Sed             cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
7258193323Sed            (RHSOp.getOpcode() == ISD::ConstantFP &&
7259193323Sed             cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
7260193323Sed          break;
7261193323Sed      }
7262193323Sed
7263218893Sdim      EVT VT = LHSOp.getValueType();
7264218893Sdim      assert(RHSOp.getValueType() == VT &&
7265218893Sdim             "SimplifyVBinOp with different BUILD_VECTOR element types");
7266218893Sdim      SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
7267208599Srdivacky                                   LHSOp, RHSOp);
7268208599Srdivacky      if (FoldOp.getOpcode() != ISD::UNDEF &&
7269208599Srdivacky          FoldOp.getOpcode() != ISD::Constant &&
7270208599Srdivacky          FoldOp.getOpcode() != ISD::ConstantFP)
7271208599Srdivacky        break;
7272208599Srdivacky      Ops.push_back(FoldOp);
7273208599Srdivacky      AddToWorkList(FoldOp.getNode());
7274193323Sed    }
7275193323Sed
7276218893Sdim    if (Ops.size() == LHS.getNumOperands())
7277218893Sdim      return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7278218893Sdim                         LHS.getValueType(), &Ops[0], Ops.size());
7279193323Sed  }
7280193323Sed
7281193323Sed  return SDValue();
7282193323Sed}
7283193323Sed
7284193323SedSDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
7285193323Sed                                    SDValue N1, SDValue N2){
7286193323Sed  assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
7287193323Sed
7288193323Sed  SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
7289193323Sed                                 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7290193323Sed
7291193323Sed  // If we got a simplified select_cc node back from SimplifySelectCC, then
7292193323Sed  // break it down into a new SETCC node, and a new SELECT node, and then return
7293193323Sed  // the SELECT node, since we were called with a SELECT node.
7294193323Sed  if (SCC.getNode()) {
7295193323Sed    // Check to see if we got a select_cc back (to turn into setcc/select).
7296193323Sed    // Otherwise, just return whatever node we got back, like fabs.
7297193323Sed    if (SCC.getOpcode() == ISD::SELECT_CC) {
7298193323Sed      SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
7299193323Sed                                  N0.getValueType(),
7300193323Sed                                  SCC.getOperand(0), SCC.getOperand(1),
7301193323Sed                                  SCC.getOperand(4));
7302193323Sed      AddToWorkList(SETCC.getNode());
7303193323Sed      return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
7304193323Sed                         SCC.getOperand(2), SCC.getOperand(3), SETCC);
7305193323Sed    }
7306193323Sed
7307193323Sed    return SCC;
7308193323Sed  }
7309193323Sed  return SDValue();
7310193323Sed}
7311193323Sed
7312193323Sed/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
7313193323Sed/// are the two values being selected between, see if we can simplify the
7314193323Sed/// select.  Callers of this should assume that TheSelect is deleted if this
7315193323Sed/// returns true.  As such, they should return the appropriate thing (e.g. the
7316193323Sed/// node) back to the top-level of the DAG combiner loop to avoid it being
7317193323Sed/// looked at.
7318193323Sedbool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
7319193323Sed                                    SDValue RHS) {
7320193323Sed
7321218893Sdim  // Cannot simplify select with vector condition
7322218893Sdim  if (TheSelect->getOperand(0).getValueType().isVector()) return false;
7323218893Sdim
7324193323Sed  // If this is a select from two identical things, try to pull the operation
7325193323Sed  // through the select.
7326218893Sdim  if (LHS.getOpcode() != RHS.getOpcode() ||
7327218893Sdim      !LHS.hasOneUse() || !RHS.hasOneUse())
7328218893Sdim    return false;
7329218893Sdim
7330218893Sdim  // If this is a load and the token chain is identical, replace the select
7331218893Sdim  // of two loads with a load through a select of the address to load from.
7332218893Sdim  // This triggers in things like "select bool X, 10.0, 123.0" after the FP
7333218893Sdim  // constants have been dropped into the constant pool.
7334218893Sdim  if (LHS.getOpcode() == ISD::LOAD) {
7335218893Sdim    LoadSDNode *LLD = cast<LoadSDNode>(LHS);
7336218893Sdim    LoadSDNode *RLD = cast<LoadSDNode>(RHS);
7337218893Sdim
7338218893Sdim    // Token chains must be identical.
7339218893Sdim    if (LHS.getOperand(0) != RHS.getOperand(0) ||
7340193323Sed        // Do not let this transformation reduce the number of volatile loads.
7341218893Sdim        LLD->isVolatile() || RLD->isVolatile() ||
7342218893Sdim        // If this is an EXTLOAD, the VT's must match.
7343218893Sdim        LLD->getMemoryVT() != RLD->getMemoryVT() ||
7344218893Sdim        // If this is an EXTLOAD, the kind of extension must match.
7345218893Sdim        (LLD->getExtensionType() != RLD->getExtensionType() &&
7346218893Sdim         // The only exception is if one of the extensions is anyext.
7347218893Sdim         LLD->getExtensionType() != ISD::EXTLOAD &&
7348218893Sdim         RLD->getExtensionType() != ISD::EXTLOAD) ||
7349198892Srdivacky        // FIXME: this discards src value information.  This is
7350198892Srdivacky        // over-conservative. It would be beneficial to be able to remember
7351202375Srdivacky        // both potential memory locations.  Since we are discarding
7352202375Srdivacky        // src value info, don't do the transformation if the memory
7353202375Srdivacky        // locations are not in the default address space.
7354218893Sdim        LLD->getPointerInfo().getAddrSpace() != 0 ||
7355218893Sdim        RLD->getPointerInfo().getAddrSpace() != 0)
7356218893Sdim      return false;
7357193323Sed
7358218893Sdim    // Check that the select condition doesn't reach either load.  If so,
7359218893Sdim    // folding this will induce a cycle into the DAG.  If not, this is safe to
7360218893Sdim    // xform, so create a select of the addresses.
7361218893Sdim    SDValue Addr;
7362218893Sdim    if (TheSelect->getOpcode() == ISD::SELECT) {
7363218893Sdim      SDNode *CondNode = TheSelect->getOperand(0).getNode();
7364218893Sdim      if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
7365218893Sdim          (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
7366218893Sdim        return false;
7367218893Sdim      Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
7368218893Sdim                         LLD->getBasePtr().getValueType(),
7369218893Sdim                         TheSelect->getOperand(0), LLD->getBasePtr(),
7370218893Sdim                         RLD->getBasePtr());
7371218893Sdim    } else {  // Otherwise SELECT_CC
7372218893Sdim      SDNode *CondLHS = TheSelect->getOperand(0).getNode();
7373218893Sdim      SDNode *CondRHS = TheSelect->getOperand(1).getNode();
7374193323Sed
7375218893Sdim      if ((LLD->hasAnyUseOfValue(1) &&
7376218893Sdim           (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
7377218893Sdim          (LLD->hasAnyUseOfValue(1) &&
7378218893Sdim           (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
7379218893Sdim        return false;
7380193323Sed
7381218893Sdim      Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
7382218893Sdim                         LLD->getBasePtr().getValueType(),
7383218893Sdim                         TheSelect->getOperand(0),
7384218893Sdim                         TheSelect->getOperand(1),
7385218893Sdim                         LLD->getBasePtr(), RLD->getBasePtr(),
7386218893Sdim                         TheSelect->getOperand(4));
7387193323Sed    }
7388218893Sdim
7389218893Sdim    SDValue Load;
7390218893Sdim    if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
7391218893Sdim      Load = DAG.getLoad(TheSelect->getValueType(0),
7392218893Sdim                         TheSelect->getDebugLoc(),
7393218893Sdim                         // FIXME: Discards pointer info.
7394218893Sdim                         LLD->getChain(), Addr, MachinePointerInfo(),
7395218893Sdim                         LLD->isVolatile(), LLD->isNonTemporal(),
7396218893Sdim                         LLD->getAlignment());
7397218893Sdim    } else {
7398218893Sdim      Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
7399218893Sdim                            RLD->getExtensionType() : LLD->getExtensionType(),
7400218893Sdim                            TheSelect->getDebugLoc(),
7401218893Sdim                            TheSelect->getValueType(0),
7402218893Sdim                            // FIXME: Discards pointer info.
7403218893Sdim                            LLD->getChain(), Addr, MachinePointerInfo(),
7404218893Sdim                            LLD->getMemoryVT(), LLD->isVolatile(),
7405218893Sdim                            LLD->isNonTemporal(), LLD->getAlignment());
7406218893Sdim    }
7407218893Sdim
7408218893Sdim    // Users of the select now use the result of the load.
7409218893Sdim    CombineTo(TheSelect, Load);
7410218893Sdim
7411218893Sdim    // Users of the old loads now use the new load's chain.  We know the
7412218893Sdim    // old-load value is dead now.
7413218893Sdim    CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
7414218893Sdim    CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
7415218893Sdim    return true;
7416193323Sed  }
7417193323Sed
7418193323Sed  return false;
7419193323Sed}
7420193323Sed
7421193323Sed/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7422193323Sed/// where 'cond' is the comparison specified by CC.
7423193323SedSDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7424193323Sed                                      SDValue N2, SDValue N3,
7425193323Sed                                      ISD::CondCode CC, bool NotExtCompare) {
7426193323Sed  // (x ? y : y) -> y.
7427193323Sed  if (N2 == N3) return N2;
7428218893Sdim
7429198090Srdivacky  EVT VT = N2.getValueType();
7430193323Sed  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
7431193323Sed  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
7432193323Sed  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
7433193323Sed
7434193323Sed  // Determine if the condition we're dealing with is constant
7435193323Sed  SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
7436193323Sed                              N0, N1, CC, DL, false);
7437193323Sed  if (SCC.getNode()) AddToWorkList(SCC.getNode());
7438193323Sed  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
7439193323Sed
7440193323Sed  // fold select_cc true, x, y -> x
7441193323Sed  if (SCCC && !SCCC->isNullValue())
7442193323Sed    return N2;
7443193323Sed  // fold select_cc false, x, y -> y
7444193323Sed  if (SCCC && SCCC->isNullValue())
7445193323Sed    return N3;
7446193323Sed
7447193323Sed  // Check to see if we can simplify the select into an fabs node
7448193323Sed  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
7449193323Sed    // Allow either -0.0 or 0.0
7450193323Sed    if (CFP->getValueAPF().isZero()) {
7451193323Sed      // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
7452193323Sed      if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
7453193323Sed          N0 == N2 && N3.getOpcode() == ISD::FNEG &&
7454193323Sed          N2 == N3.getOperand(0))
7455193323Sed        return DAG.getNode(ISD::FABS, DL, VT, N0);
7456193323Sed
7457193323Sed      // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
7458193323Sed      if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
7459193323Sed          N0 == N3 && N2.getOpcode() == ISD::FNEG &&
7460193323Sed          N2.getOperand(0) == N3)
7461193323Sed        return DAG.getNode(ISD::FABS, DL, VT, N3);
7462193323Sed    }
7463193323Sed  }
7464218893Sdim
7465193323Sed  // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
7466193323Sed  // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
7467193323Sed  // in it.  This is a win when the constant is not otherwise available because
7468193323Sed  // it replaces two constant pool loads with one.  We only do this if the FP
7469193323Sed  // type is known to be legal, because if it isn't, then we are before legalize
7470193323Sed  // types an we want the other legalization to happen first (e.g. to avoid
7471193323Sed  // messing with soft float) and if the ConstantFP is not legal, because if
7472193323Sed  // it is legal, we may not need to store the FP constant in a constant pool.
7473193323Sed  if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
7474193323Sed    if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
7475193323Sed      if (TLI.isTypeLegal(N2.getValueType()) &&
7476193323Sed          (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
7477193323Sed           TargetLowering::Legal) &&
7478193323Sed          // If both constants have multiple uses, then we won't need to do an
7479193323Sed          // extra load, they are likely around in registers for other users.
7480193323Sed          (TV->hasOneUse() || FV->hasOneUse())) {
7481193323Sed        Constant *Elts[] = {
7482193323Sed          const_cast<ConstantFP*>(FV->getConstantFPValue()),
7483193323Sed          const_cast<ConstantFP*>(TV->getConstantFPValue())
7484193323Sed        };
7485226633Sdim        Type *FPTy = Elts[0]->getType();
7486193323Sed        const TargetData &TD = *TLI.getTargetData();
7487218893Sdim
7488193323Sed        // Create a ConstantArray of the two constants.
7489224145Sdim        Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
7490193323Sed        SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
7491193323Sed                                            TD.getPrefTypeAlignment(FPTy));
7492193323Sed        unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
7493193323Sed
7494193323Sed        // Get the offsets to the 0 and 1 element of the array so that we can
7495193323Sed        // select between them.
7496193323Sed        SDValue Zero = DAG.getIntPtrConstant(0);
7497193323Sed        unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
7498193323Sed        SDValue One = DAG.getIntPtrConstant(EltSize);
7499218893Sdim
7500193323Sed        SDValue Cond = DAG.getSetCC(DL,
7501193323Sed                                    TLI.getSetCCResultType(N0.getValueType()),
7502193323Sed                                    N0, N1, CC);
7503226633Sdim        AddToWorkList(Cond.getNode());
7504193323Sed        SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
7505193323Sed                                        Cond, One, Zero);
7506226633Sdim        AddToWorkList(CstOffset.getNode());
7507193323Sed        CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
7508193323Sed                            CstOffset);
7509226633Sdim        AddToWorkList(CPIdx.getNode());
7510193323Sed        return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
7511218893Sdim                           MachinePointerInfo::getConstantPool(), false,
7512203954Srdivacky                           false, Alignment);
7513193323Sed
7514193323Sed      }
7515218893Sdim    }
7516193323Sed
7517193323Sed  // Check to see if we can perform the "gzip trick", transforming
7518193323Sed  // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
7519193323Sed  if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
7520193323Sed      N0.getValueType().isInteger() &&
7521193323Sed      N2.getValueType().isInteger() &&
7522193323Sed      (N1C->isNullValue() ||                         // (a < 0) ? b : 0
7523193323Sed       (N1C->getAPIntValue() == 1 && N0 == N2))) {   // (a < 1) ? a : 0
7524198090Srdivacky    EVT XType = N0.getValueType();
7525198090Srdivacky    EVT AType = N2.getValueType();
7526193323Sed    if (XType.bitsGE(AType)) {
7527193323Sed      // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
7528193323Sed      // single-bit constant.
7529193323Sed      if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
7530193323Sed        unsigned ShCtV = N2C->getAPIntValue().logBase2();
7531193323Sed        ShCtV = XType.getSizeInBits()-ShCtV-1;
7532219077Sdim        SDValue ShCt = DAG.getConstant(ShCtV,
7533219077Sdim                                       getShiftAmountTy(N0.getValueType()));
7534193323Sed        SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
7535193323Sed                                    XType, N0, ShCt);
7536193323Sed        AddToWorkList(Shift.getNode());
7537193323Sed
7538193323Sed        if (XType.bitsGT(AType)) {
7539193323Sed          Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7540193323Sed          AddToWorkList(Shift.getNode());
7541193323Sed        }
7542193323Sed
7543193323Sed        return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7544193323Sed      }
7545193323Sed
7546193323Sed      SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
7547193323Sed                                  XType, N0,
7548193323Sed                                  DAG.getConstant(XType.getSizeInBits()-1,
7549219077Sdim                                         getShiftAmountTy(N0.getValueType())));
7550193323Sed      AddToWorkList(Shift.getNode());
7551193323Sed
7552193323Sed      if (XType.bitsGT(AType)) {
7553193323Sed        Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7554193323Sed        AddToWorkList(Shift.getNode());
7555193323Sed      }
7556193323Sed
7557193323Sed      return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7558193323Sed    }
7559193323Sed  }
7560193323Sed
7561218893Sdim  // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
7562218893Sdim  // where y is has a single bit set.
7563218893Sdim  // A plaintext description would be, we can turn the SELECT_CC into an AND
7564218893Sdim  // when the condition can be materialized as an all-ones register.  Any
7565218893Sdim  // single bit-test can be materialized as an all-ones register with
7566218893Sdim  // shift-left and shift-right-arith.
7567218893Sdim  if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
7568218893Sdim      N0->getValueType(0) == VT &&
7569218893Sdim      N1C && N1C->isNullValue() &&
7570218893Sdim      N2C && N2C->isNullValue()) {
7571218893Sdim    SDValue AndLHS = N0->getOperand(0);
7572218893Sdim    ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
7573218893Sdim    if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
7574218893Sdim      // Shift the tested bit over the sign bit.
7575218893Sdim      APInt AndMask = ConstAndRHS->getAPIntValue();
7576218893Sdim      SDValue ShlAmt =
7577219077Sdim        DAG.getConstant(AndMask.countLeadingZeros(),
7578219077Sdim                        getShiftAmountTy(AndLHS.getValueType()));
7579218893Sdim      SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
7580218893Sdim
7581218893Sdim      // Now arithmetic right shift it all the way over, so the result is either
7582218893Sdim      // all-ones, or zero.
7583218893Sdim      SDValue ShrAmt =
7584219077Sdim        DAG.getConstant(AndMask.getBitWidth()-1,
7585219077Sdim                        getShiftAmountTy(Shl.getValueType()));
7586218893Sdim      SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
7587218893Sdim
7588218893Sdim      return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
7589218893Sdim    }
7590218893Sdim  }
7591218893Sdim
7592193323Sed  // fold select C, 16, 0 -> shl C, 4
7593193323Sed  if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
7594226633Sdim    TLI.getBooleanContents(N0.getValueType().isVector()) ==
7595226633Sdim      TargetLowering::ZeroOrOneBooleanContent) {
7596193323Sed
7597193323Sed    // If the caller doesn't want us to simplify this into a zext of a compare,
7598193323Sed    // don't do it.
7599193323Sed    if (NotExtCompare && N2C->getAPIntValue() == 1)
7600193323Sed      return SDValue();
7601193323Sed
7602193323Sed    // Get a SetCC of the condition
7603193323Sed    // FIXME: Should probably make sure that setcc is legal if we ever have a
7604193323Sed    // target where it isn't.
7605193323Sed    SDValue Temp, SCC;
7606193323Sed    // cast from setcc result type to select result type
7607193323Sed    if (LegalTypes) {
7608193323Sed      SCC  = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
7609193323Sed                          N0, N1, CC);
7610193323Sed      if (N2.getValueType().bitsLT(SCC.getValueType()))
7611193323Sed        Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
7612193323Sed      else
7613193323Sed        Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7614193323Sed                           N2.getValueType(), SCC);
7615193323Sed    } else {
7616193323Sed      SCC  = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
7617193323Sed      Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7618193323Sed                         N2.getValueType(), SCC);
7619193323Sed    }
7620193323Sed
7621193323Sed    AddToWorkList(SCC.getNode());
7622193323Sed    AddToWorkList(Temp.getNode());
7623193323Sed
7624193323Sed    if (N2C->getAPIntValue() == 1)
7625193323Sed      return Temp;
7626193323Sed
7627193323Sed    // shl setcc result by log2 n2c
7628193323Sed    return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
7629193323Sed                       DAG.getConstant(N2C->getAPIntValue().logBase2(),
7630219077Sdim                                       getShiftAmountTy(Temp.getValueType())));
7631193323Sed  }
7632193323Sed
7633193323Sed  // Check to see if this is the equivalent of setcc
7634193323Sed  // FIXME: Turn all of these into setcc if setcc if setcc is legal
7635193323Sed  // otherwise, go ahead with the folds.
7636193323Sed  if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
7637198090Srdivacky    EVT XType = N0.getValueType();
7638193323Sed    if (!LegalOperations ||
7639193323Sed        TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
7640193323Sed      SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
7641193323Sed      if (Res.getValueType() != VT)
7642193323Sed        Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
7643193323Sed      return Res;
7644193323Sed    }
7645193323Sed
7646193323Sed    // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
7647193323Sed    if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
7648193323Sed        (!LegalOperations ||
7649193323Sed         TLI.isOperationLegal(ISD::CTLZ, XType))) {
7650193323Sed      SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
7651193323Sed      return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
7652193323Sed                         DAG.getConstant(Log2_32(XType.getSizeInBits()),
7653219077Sdim                                       getShiftAmountTy(Ctlz.getValueType())));
7654193323Sed    }
7655193323Sed    // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
7656193323Sed    if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
7657193323Sed      SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
7658193323Sed                                  XType, DAG.getConstant(0, XType), N0);
7659193323Sed      SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
7660193323Sed      return DAG.getNode(ISD::SRL, DL, XType,
7661193323Sed                         DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
7662193323Sed                         DAG.getConstant(XType.getSizeInBits()-1,
7663219077Sdim                                         getShiftAmountTy(XType)));
7664193323Sed    }
7665193323Sed    // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
7666193323Sed    if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
7667193323Sed      SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
7668193323Sed                                 DAG.getConstant(XType.getSizeInBits()-1,
7669219077Sdim                                         getShiftAmountTy(N0.getValueType())));
7670193323Sed      return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
7671193323Sed    }
7672193323Sed  }
7673193323Sed
7674210299Sed  // Check to see if this is an integer abs.
7675210299Sed  // select_cc setg[te] X,  0,  X, -X ->
7676210299Sed  // select_cc setgt    X, -1,  X, -X ->
7677210299Sed  // select_cc setl[te] X,  0, -X,  X ->
7678210299Sed  // select_cc setlt    X,  1, -X,  X ->
7679193323Sed  // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
7680210299Sed  if (N1C) {
7681210299Sed    ConstantSDNode *SubC = NULL;
7682210299Sed    if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
7683210299Sed         (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
7684210299Sed        N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
7685210299Sed      SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
7686210299Sed    else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
7687210299Sed              (N1C->isOne() && CC == ISD::SETLT)) &&
7688210299Sed             N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
7689210299Sed      SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
7690210299Sed
7691198090Srdivacky    EVT XType = N0.getValueType();
7692210299Sed    if (SubC && SubC->isNullValue() && XType.isInteger()) {
7693210299Sed      SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
7694210299Sed                                  N0,
7695210299Sed                                  DAG.getConstant(XType.getSizeInBits()-1,
7696219077Sdim                                         getShiftAmountTy(N0.getValueType())));
7697210299Sed      SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
7698210299Sed                                XType, N0, Shift);
7699210299Sed      AddToWorkList(Shift.getNode());
7700210299Sed      AddToWorkList(Add.getNode());
7701210299Sed      return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
7702193323Sed    }
7703193323Sed  }
7704193323Sed
7705193323Sed  return SDValue();
7706193323Sed}
7707193323Sed
7708193323Sed/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
7709198090SrdivackySDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
7710193323Sed                                   SDValue N1, ISD::CondCode Cond,
7711193323Sed                                   DebugLoc DL, bool foldBooleans) {
7712193323Sed  TargetLowering::DAGCombinerInfo
7713198090Srdivacky    DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
7714193323Sed  return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
7715193323Sed}
7716193323Sed
7717193323Sed/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
7718193323Sed/// return a DAG expression to select that will generate the same value by
7719193323Sed/// multiplying by a magic number.  See:
7720193323Sed/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7721193323SedSDValue DAGCombiner::BuildSDIV(SDNode *N) {
7722193323Sed  std::vector<SDNode*> Built;
7723193323Sed  SDValue S = TLI.BuildSDIV(N, DAG, &Built);
7724193323Sed
7725193323Sed  for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7726193323Sed       ii != ee; ++ii)
7727193323Sed    AddToWorkList(*ii);
7728193323Sed  return S;
7729193323Sed}
7730193323Sed
7731193323Sed/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
7732193323Sed/// return a DAG expression to select that will generate the same value by
7733193323Sed/// multiplying by a magic number.  See:
7734193323Sed/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7735193323SedSDValue DAGCombiner::BuildUDIV(SDNode *N) {
7736193323Sed  std::vector<SDNode*> Built;
7737193323Sed  SDValue S = TLI.BuildUDIV(N, DAG, &Built);
7738193323Sed
7739193323Sed  for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7740193323Sed       ii != ee; ++ii)
7741193323Sed    AddToWorkList(*ii);
7742193323Sed  return S;
7743193323Sed}
7744193323Sed
7745198090Srdivacky/// FindBaseOffset - Return true if base is a frame index, which is known not
7746218893Sdim// to alias with anything but itself.  Provides base object and offset as
7747218893Sdim// results.
7748198090Srdivackystatic bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
7749207618Srdivacky                           const GlobalValue *&GV, void *&CV) {
7750193323Sed  // Assume it is a primitive operation.
7751198090Srdivacky  Base = Ptr; Offset = 0; GV = 0; CV = 0;
7752193323Sed
7753193323Sed  // If it's an adding a simple constant then integrate the offset.
7754193323Sed  if (Base.getOpcode() == ISD::ADD) {
7755193323Sed    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
7756193323Sed      Base = Base.getOperand(0);
7757193323Sed      Offset += C->getZExtValue();
7758193323Sed    }
7759193323Sed  }
7760218893Sdim
7761198090Srdivacky  // Return the underlying GlobalValue, and update the Offset.  Return false
7762198090Srdivacky  // for GlobalAddressSDNode since the same GlobalAddress may be represented
7763198090Srdivacky  // by multiple nodes with different offsets.
7764198090Srdivacky  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
7765198090Srdivacky    GV = G->getGlobal();
7766198090Srdivacky    Offset += G->getOffset();
7767198090Srdivacky    return false;
7768198090Srdivacky  }
7769193323Sed
7770198090Srdivacky  // Return the underlying Constant value, and update the Offset.  Return false
7771198090Srdivacky  // for ConstantSDNodes since the same constant pool entry may be represented
7772198090Srdivacky  // by multiple nodes with different offsets.
7773198090Srdivacky  if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
7774198090Srdivacky    CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
7775198090Srdivacky                                         : (void *)C->getConstVal();
7776198090Srdivacky    Offset += C->getOffset();
7777198090Srdivacky    return false;
7778198090Srdivacky  }
7779193323Sed  // If it's any of the following then it can't alias with anything but itself.
7780198090Srdivacky  return isa<FrameIndexSDNode>(Base);
7781193323Sed}
7782193323Sed
7783193323Sed/// isAlias - Return true if there is any possibility that the two addresses
7784193323Sed/// overlap.
7785193323Sedbool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7786193323Sed                          const Value *SrcValue1, int SrcValueOffset1,
7787198090Srdivacky                          unsigned SrcValueAlign1,
7788218893Sdim                          const MDNode *TBAAInfo1,
7789193323Sed                          SDValue Ptr2, int64_t Size2,
7790198090Srdivacky                          const Value *SrcValue2, int SrcValueOffset2,
7791218893Sdim                          unsigned SrcValueAlign2,
7792218893Sdim                          const MDNode *TBAAInfo2) const {
7793193323Sed  // If they are the same then they must be aliases.
7794193323Sed  if (Ptr1 == Ptr2) return true;
7795193323Sed
7796193323Sed  // Gather base node and offset information.
7797193323Sed  SDValue Base1, Base2;
7798193323Sed  int64_t Offset1, Offset2;
7799207618Srdivacky  const GlobalValue *GV1, *GV2;
7800198090Srdivacky  void *CV1, *CV2;
7801198090Srdivacky  bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7802198090Srdivacky  bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7803193323Sed
7804198090Srdivacky  // If they have a same base address then check to see if they overlap.
7805198090Srdivacky  if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7806193323Sed    return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7807193323Sed
7808218893Sdim  // It is possible for different frame indices to alias each other, mostly
7809218893Sdim  // when tail call optimization reuses return address slots for arguments.
7810218893Sdim  // To catch this case, look up the actual index of frame indices to compute
7811218893Sdim  // the real alias relationship.
7812218893Sdim  if (isFrameIndex1 && isFrameIndex2) {
7813218893Sdim    MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7814218893Sdim    Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
7815218893Sdim    Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
7816218893Sdim    return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7817218893Sdim  }
7818218893Sdim
7819218893Sdim  // Otherwise, if we know what the bases are, and they aren't identical, then
7820218893Sdim  // we know they cannot alias.
7821198090Srdivacky  if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7822198090Srdivacky    return false;
7823193323Sed
7824198090Srdivacky  // If we know required SrcValue1 and SrcValue2 have relatively large alignment
7825198090Srdivacky  // compared to the size and offset of the access, we may be able to prove they
7826198090Srdivacky  // do not alias.  This check is conservative for now to catch cases created by
7827198090Srdivacky  // splitting vector types.
7828198090Srdivacky  if ((SrcValueAlign1 == SrcValueAlign2) &&
7829198090Srdivacky      (SrcValueOffset1 != SrcValueOffset2) &&
7830198090Srdivacky      (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7831198090Srdivacky    int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7832198090Srdivacky    int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7833218893Sdim
7834198090Srdivacky    // There is no overlap between these relatively aligned accesses of similar
7835198090Srdivacky    // size, return no alias.
7836198090Srdivacky    if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7837198090Srdivacky      return false;
7838198090Srdivacky  }
7839218893Sdim
7840193323Sed  if (CombinerGlobalAA) {
7841193323Sed    // Use alias analysis information.
7842193323Sed    int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7843193323Sed    int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7844193323Sed    int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7845193323Sed    AliasAnalysis::AliasResult AAResult =
7846218893Sdim      AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
7847218893Sdim               AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
7848193323Sed    if (AAResult == AliasAnalysis::NoAlias)
7849193323Sed      return false;
7850193323Sed  }
7851193323Sed
7852193323Sed  // Otherwise we have to assume they alias.
7853193323Sed  return true;
7854193323Sed}
7855193323Sed
7856193323Sed/// FindAliasInfo - Extracts the relevant alias information from the memory
7857193323Sed/// node.  Returns true if the operand was a load.
7858193323Sedbool DAGCombiner::FindAliasInfo(SDNode *N,
7859193323Sed                        SDValue &Ptr, int64_t &Size,
7860218893Sdim                        const Value *&SrcValue,
7861198090Srdivacky                        int &SrcValueOffset,
7862218893Sdim                        unsigned &SrcValueAlign,
7863218893Sdim                        const MDNode *&TBAAInfo) const {
7864193323Sed  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7865193323Sed    Ptr = LD->getBasePtr();
7866193323Sed    Size = LD->getMemoryVT().getSizeInBits() >> 3;
7867193323Sed    SrcValue = LD->getSrcValue();
7868193323Sed    SrcValueOffset = LD->getSrcValueOffset();
7869198090Srdivacky    SrcValueAlign = LD->getOriginalAlignment();
7870218893Sdim    TBAAInfo = LD->getTBAAInfo();
7871193323Sed    return true;
7872223017Sdim  }
7873223017Sdim  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7874193323Sed    Ptr = ST->getBasePtr();
7875193323Sed    Size = ST->getMemoryVT().getSizeInBits() >> 3;
7876193323Sed    SrcValue = ST->getSrcValue();
7877193323Sed    SrcValueOffset = ST->getSrcValueOffset();
7878198090Srdivacky    SrcValueAlign = ST->getOriginalAlignment();
7879218893Sdim    TBAAInfo = ST->getTBAAInfo();
7880223017Sdim    return false;
7881193323Sed  }
7882223017Sdim  llvm_unreachable("FindAliasInfo expected a memory operand");
7883193323Sed}
7884193323Sed
7885193323Sed/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7886193323Sed/// looking for aliasing nodes and adding them to the Aliases vector.
7887193323Sedvoid DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7888193323Sed                                   SmallVector<SDValue, 8> &Aliases) {
7889193323Sed  SmallVector<SDValue, 8> Chains;     // List of chains to visit.
7890198090Srdivacky  SmallPtrSet<SDNode *, 16> Visited;  // Visited node set.
7891193323Sed
7892193323Sed  // Get alias information for node.
7893193323Sed  SDValue Ptr;
7894198090Srdivacky  int64_t Size;
7895198090Srdivacky  const Value *SrcValue;
7896198090Srdivacky  int SrcValueOffset;
7897198090Srdivacky  unsigned SrcValueAlign;
7898218893Sdim  const MDNode *SrcTBAAInfo;
7899218893Sdim  bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7900218893Sdim                              SrcValueAlign, SrcTBAAInfo);
7901193323Sed
7902193323Sed  // Starting off.
7903193323Sed  Chains.push_back(OriginalChain);
7904198090Srdivacky  unsigned Depth = 0;
7905218893Sdim
7906193323Sed  // Look at each chain and determine if it is an alias.  If so, add it to the
7907193323Sed  // aliases list.  If not, then continue up the chain looking for the next
7908193323Sed  // candidate.
7909193323Sed  while (!Chains.empty()) {
7910193323Sed    SDValue Chain = Chains.back();
7911193323Sed    Chains.pop_back();
7912218893Sdim
7913218893Sdim    // For TokenFactor nodes, look at each operand and only continue up the
7914218893Sdim    // chain until we find two aliases.  If we've seen two aliases, assume we'll
7915198090Srdivacky    // find more and revert to original chain since the xform is unlikely to be
7916198090Srdivacky    // profitable.
7917218893Sdim    //
7918218893Sdim    // FIXME: The depth check could be made to return the last non-aliasing
7919198090Srdivacky    // chain we found before we hit a tokenfactor rather than the original
7920198090Srdivacky    // chain.
7921198090Srdivacky    if (Depth > 6 || Aliases.size() == 2) {
7922198090Srdivacky      Aliases.clear();
7923198090Srdivacky      Aliases.push_back(OriginalChain);
7924198090Srdivacky      break;
7925198090Srdivacky    }
7926193323Sed
7927198090Srdivacky    // Don't bother if we've been before.
7928198090Srdivacky    if (!Visited.insert(Chain.getNode()))
7929198090Srdivacky      continue;
7930193323Sed
7931193323Sed    switch (Chain.getOpcode()) {
7932193323Sed    case ISD::EntryToken:
7933193323Sed      // Entry token is ideal chain operand, but handled in FindBetterChain.
7934193323Sed      break;
7935193323Sed
7936193323Sed    case ISD::LOAD:
7937193323Sed    case ISD::STORE: {
7938193323Sed      // Get alias information for Chain.
7939193323Sed      SDValue OpPtr;
7940198090Srdivacky      int64_t OpSize;
7941198090Srdivacky      const Value *OpSrcValue;
7942198090Srdivacky      int OpSrcValueOffset;
7943198090Srdivacky      unsigned OpSrcValueAlign;
7944218893Sdim      const MDNode *OpSrcTBAAInfo;
7945193323Sed      bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7946198090Srdivacky                                    OpSrcValue, OpSrcValueOffset,
7947218893Sdim                                    OpSrcValueAlign,
7948218893Sdim                                    OpSrcTBAAInfo);
7949193323Sed
7950193323Sed      // If chain is alias then stop here.
7951193323Sed      if (!(IsLoad && IsOpLoad) &&
7952198090Srdivacky          isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7953218893Sdim                  SrcTBAAInfo,
7954198090Srdivacky                  OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7955218893Sdim                  OpSrcValueAlign, OpSrcTBAAInfo)) {
7956193323Sed        Aliases.push_back(Chain);
7957193323Sed      } else {
7958193323Sed        // Look further up the chain.
7959193323Sed        Chains.push_back(Chain.getOperand(0));
7960198090Srdivacky        ++Depth;
7961193323Sed      }
7962193323Sed      break;
7963193323Sed    }
7964193323Sed
7965193323Sed    case ISD::TokenFactor:
7966198090Srdivacky      // We have to check each of the operands of the token factor for "small"
7967198090Srdivacky      // token factors, so we queue them up.  Adding the operands to the queue
7968198090Srdivacky      // (stack) in reverse order maintains the original order and increases the
7969198090Srdivacky      // likelihood that getNode will find a matching token factor (CSE.)
7970198090Srdivacky      if (Chain.getNumOperands() > 16) {
7971198090Srdivacky        Aliases.push_back(Chain);
7972198090Srdivacky        break;
7973198090Srdivacky      }
7974193323Sed      for (unsigned n = Chain.getNumOperands(); n;)
7975193323Sed        Chains.push_back(Chain.getOperand(--n));
7976198090Srdivacky      ++Depth;
7977193323Sed      break;
7978193323Sed
7979193323Sed    default:
7980193323Sed      // For all other instructions we will just have to take what we can get.
7981193323Sed      Aliases.push_back(Chain);
7982193323Sed      break;
7983193323Sed    }
7984193323Sed  }
7985193323Sed}
7986193323Sed
7987193323Sed/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7988193323Sed/// for a better chain (aliasing node.)
7989193323SedSDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7990193323Sed  SmallVector<SDValue, 8> Aliases;  // Ops for replacing token factor.
7991193323Sed
7992193323Sed  // Accumulate all the aliases to this node.
7993193323Sed  GatherAllAliases(N, OldChain, Aliases);
7994193323Sed
7995223017Sdim  // If no operands then chain to entry token.
7996223017Sdim  if (Aliases.size() == 0)
7997193323Sed    return DAG.getEntryNode();
7998223017Sdim
7999223017Sdim  // If a single operand then chain to it.  We don't need to revisit it.
8000223017Sdim  if (Aliases.size() == 1)
8001193323Sed    return Aliases[0];
8002218893Sdim
8003193323Sed  // Construct a custom tailored token factor.
8004218893Sdim  return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8005198090Srdivacky                     &Aliases[0], Aliases.size());
8006193323Sed}
8007193323Sed
8008193323Sed// SelectionDAG::Combine - This is the entry point for the file.
8009193323Sed//
8010193323Sedvoid SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
8011193323Sed                           CodeGenOpt::Level OptLevel) {
8012193323Sed  /// run - This is the main entry point to this class.
8013193323Sed  ///
8014193323Sed  DAGCombiner(*this, AA, OptLevel).Run(Level);
8015193323Sed}
8016