DAGCombiner.cpp revision 219077
1193323Sed//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11193323Sed// both before and after the DAG is legalized. 12193323Sed// 13193323Sed// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14193323Sed// primarily intended to handle simplification opportunities that are implicit 15193323Sed// in the LLVM IR and exposed by the various codegen lowering phases. 16193323Sed// 17193323Sed//===----------------------------------------------------------------------===// 18193323Sed 19193323Sed#define DEBUG_TYPE "dagcombine" 20193323Sed#include "llvm/CodeGen/SelectionDAG.h" 21193323Sed#include "llvm/DerivedTypes.h" 22198090Srdivacky#include "llvm/LLVMContext.h" 23193323Sed#include "llvm/CodeGen/MachineFunction.h" 24193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 25193323Sed#include "llvm/CodeGen/PseudoSourceValue.h" 26193323Sed#include "llvm/Analysis/AliasAnalysis.h" 27193323Sed#include "llvm/Target/TargetData.h" 28193323Sed#include "llvm/Target/TargetLowering.h" 29193323Sed#include "llvm/Target/TargetMachine.h" 30193323Sed#include "llvm/Target/TargetOptions.h" 31193323Sed#include "llvm/ADT/SmallPtrSet.h" 32193323Sed#include "llvm/ADT/Statistic.h" 33193323Sed#include "llvm/Support/CommandLine.h" 34193323Sed#include "llvm/Support/Debug.h" 35198090Srdivacky#include "llvm/Support/ErrorHandling.h" 36193323Sed#include "llvm/Support/MathExtras.h" 37198090Srdivacky#include "llvm/Support/raw_ostream.h" 38193323Sed#include <algorithm> 39193323Sedusing namespace llvm; 40193323Sed 41193323SedSTATISTIC(NodesCombined , "Number of dag nodes combined"); 42193323SedSTATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43193323SedSTATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44193323SedSTATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45218893SdimSTATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46193323Sed 47193323Sednamespace { 48193323Sed static cl::opt<bool> 49193323Sed CombinerAA("combiner-alias-analysis", cl::Hidden, 50193323Sed cl::desc("Turn on alias analysis during testing")); 51193323Sed 52193323Sed static cl::opt<bool> 53193323Sed CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54193323Sed cl::desc("Include global information in alias analysis")); 55193323Sed 56193323Sed//------------------------------ DAGCombiner ---------------------------------// 57193323Sed 58198892Srdivacky class DAGCombiner { 59193323Sed SelectionDAG &DAG; 60193323Sed const TargetLowering &TLI; 61193323Sed CombineLevel Level; 62193323Sed CodeGenOpt::Level OptLevel; 63193323Sed bool LegalOperations; 64193323Sed bool LegalTypes; 65193323Sed 66193323Sed // Worklist of all of the nodes that need to be simplified. 67193323Sed std::vector<SDNode*> WorkList; 68193323Sed 69193323Sed // AA - Used for DAG load/store alias analysis. 70193323Sed AliasAnalysis &AA; 71193323Sed 72193323Sed /// AddUsersToWorkList - When an instruction is simplified, add all users of 73193323Sed /// the instruction to the work lists because they might get more simplified 74193323Sed /// now. 75193323Sed /// 76193323Sed void AddUsersToWorkList(SDNode *N) { 77193323Sed for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78193323Sed UI != UE; ++UI) 79193323Sed AddToWorkList(*UI); 80193323Sed } 81193323Sed 82193323Sed /// visit - call the node-specific routine that knows how to fold each 83193323Sed /// particular type of node. 84193323Sed SDValue visit(SDNode *N); 85193323Sed 86193323Sed public: 87193323Sed /// AddToWorkList - Add to the work list making sure it's instance is at the 88193323Sed /// the back (next to be processed.) 89193323Sed void AddToWorkList(SDNode *N) { 90193323Sed removeFromWorkList(N); 91193323Sed WorkList.push_back(N); 92193323Sed } 93193323Sed 94193323Sed /// removeFromWorkList - remove all instances of N from the worklist. 95193323Sed /// 96193323Sed void removeFromWorkList(SDNode *N) { 97193323Sed WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98193323Sed WorkList.end()); 99193323Sed } 100193323Sed 101193323Sed SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102193323Sed bool AddTo = true); 103193323Sed 104193323Sed SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105193323Sed return CombineTo(N, &Res, 1, AddTo); 106193323Sed } 107193323Sed 108193323Sed SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109193323Sed bool AddTo = true) { 110193323Sed SDValue To[] = { Res0, Res1 }; 111193323Sed return CombineTo(N, To, 2, AddTo); 112193323Sed } 113193323Sed 114193323Sed void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115193323Sed 116193323Sed private: 117193323Sed 118193323Sed /// SimplifyDemandedBits - Check the specified integer node value to see if 119193323Sed /// it can be simplified or if things it uses can be simplified by bit 120193323Sed /// propagation. If so, return true. 121193323Sed bool SimplifyDemandedBits(SDValue Op) { 122200581Srdivacky unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123200581Srdivacky APInt Demanded = APInt::getAllOnesValue(BitWidth); 124193323Sed return SimplifyDemandedBits(Op, Demanded); 125193323Sed } 126193323Sed 127193323Sed bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128193323Sed 129193323Sed bool CombineToPreIndexedLoadStore(SDNode *N); 130193323Sed bool CombineToPostIndexedLoadStore(SDNode *N); 131193323Sed 132207618Srdivacky void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133207618Srdivacky SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134207618Srdivacky SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135207618Srdivacky SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136207618Srdivacky SDValue PromoteIntBinOp(SDValue Op); 137207618Srdivacky SDValue PromoteIntShiftOp(SDValue Op); 138207618Srdivacky SDValue PromoteExtend(SDValue Op); 139207618Srdivacky bool PromoteLoad(SDValue Op); 140193323Sed 141193323Sed /// combine - call the node-specific routine that knows how to fold each 142193323Sed /// particular type of node. If that doesn't do anything, try the 143193323Sed /// target-specific DAG combines. 144193323Sed SDValue combine(SDNode *N); 145193323Sed 146193323Sed // Visitation implementation - Implement dag node combining for different 147193323Sed // node types. The semantics are as follows: 148193323Sed // Return Value: 149193323Sed // SDValue.getNode() == 0 - No change was made 150193323Sed // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151193323Sed // otherwise - N should be replaced by the returned Operand. 152193323Sed // 153193323Sed SDValue visitTokenFactor(SDNode *N); 154193323Sed SDValue visitMERGE_VALUES(SDNode *N); 155193323Sed SDValue visitADD(SDNode *N); 156193323Sed SDValue visitSUB(SDNode *N); 157193323Sed SDValue visitADDC(SDNode *N); 158193323Sed SDValue visitADDE(SDNode *N); 159193323Sed SDValue visitMUL(SDNode *N); 160193323Sed SDValue visitSDIV(SDNode *N); 161193323Sed SDValue visitUDIV(SDNode *N); 162193323Sed SDValue visitSREM(SDNode *N); 163193323Sed SDValue visitUREM(SDNode *N); 164193323Sed SDValue visitMULHU(SDNode *N); 165193323Sed SDValue visitMULHS(SDNode *N); 166193323Sed SDValue visitSMUL_LOHI(SDNode *N); 167193323Sed SDValue visitUMUL_LOHI(SDNode *N); 168193323Sed SDValue visitSDIVREM(SDNode *N); 169193323Sed SDValue visitUDIVREM(SDNode *N); 170193323Sed SDValue visitAND(SDNode *N); 171193323Sed SDValue visitOR(SDNode *N); 172193323Sed SDValue visitXOR(SDNode *N); 173193323Sed SDValue SimplifyVBinOp(SDNode *N); 174193323Sed SDValue visitSHL(SDNode *N); 175193323Sed SDValue visitSRA(SDNode *N); 176193323Sed SDValue visitSRL(SDNode *N); 177193323Sed SDValue visitCTLZ(SDNode *N); 178193323Sed SDValue visitCTTZ(SDNode *N); 179193323Sed SDValue visitCTPOP(SDNode *N); 180193323Sed SDValue visitSELECT(SDNode *N); 181193323Sed SDValue visitSELECT_CC(SDNode *N); 182193323Sed SDValue visitSETCC(SDNode *N); 183193323Sed SDValue visitSIGN_EXTEND(SDNode *N); 184193323Sed SDValue visitZERO_EXTEND(SDNode *N); 185193323Sed SDValue visitANY_EXTEND(SDNode *N); 186193323Sed SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187193323Sed SDValue visitTRUNCATE(SDNode *N); 188218893Sdim SDValue visitBITCAST(SDNode *N); 189193323Sed SDValue visitBUILD_PAIR(SDNode *N); 190193323Sed SDValue visitFADD(SDNode *N); 191193323Sed SDValue visitFSUB(SDNode *N); 192193323Sed SDValue visitFMUL(SDNode *N); 193193323Sed SDValue visitFDIV(SDNode *N); 194193323Sed SDValue visitFREM(SDNode *N); 195193323Sed SDValue visitFCOPYSIGN(SDNode *N); 196193323Sed SDValue visitSINT_TO_FP(SDNode *N); 197193323Sed SDValue visitUINT_TO_FP(SDNode *N); 198193323Sed SDValue visitFP_TO_SINT(SDNode *N); 199193323Sed SDValue visitFP_TO_UINT(SDNode *N); 200193323Sed SDValue visitFP_ROUND(SDNode *N); 201193323Sed SDValue visitFP_ROUND_INREG(SDNode *N); 202193323Sed SDValue visitFP_EXTEND(SDNode *N); 203193323Sed SDValue visitFNEG(SDNode *N); 204193323Sed SDValue visitFABS(SDNode *N); 205193323Sed SDValue visitBRCOND(SDNode *N); 206193323Sed SDValue visitBR_CC(SDNode *N); 207193323Sed SDValue visitLOAD(SDNode *N); 208193323Sed SDValue visitSTORE(SDNode *N); 209193323Sed SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210193323Sed SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211193323Sed SDValue visitBUILD_VECTOR(SDNode *N); 212193323Sed SDValue visitCONCAT_VECTORS(SDNode *N); 213193323Sed SDValue visitVECTOR_SHUFFLE(SDNode *N); 214210299Sed SDValue visitMEMBARRIER(SDNode *N); 215193323Sed 216193323Sed SDValue XformToShuffleWithZero(SDNode *N); 217193323Sed SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 218193323Sed 219193323Sed SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 220193323Sed 221193323Sed bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 222193323Sed SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 223193323Sed SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 224193323Sed SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 225193323Sed SDValue N3, ISD::CondCode CC, 226193323Sed bool NotExtCompare = false); 227198090Srdivacky SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 228193323Sed DebugLoc DL, bool foldBooleans = true); 229193323Sed SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 230193323Sed unsigned HiOp); 231198090Srdivacky SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 232218893Sdim SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 233193323Sed SDValue BuildSDIV(SDNode *N); 234193323Sed SDValue BuildUDIV(SDNode *N); 235193323Sed SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 236193323Sed SDValue ReduceLoadWidth(SDNode *N); 237193323Sed SDValue ReduceLoadOpStoreWidth(SDNode *N); 238218893Sdim SDValue TransformFPLoadStorePair(SDNode *N); 239193323Sed 240193323Sed SDValue GetDemandedBits(SDValue V, const APInt &Mask); 241193323Sed 242193323Sed /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 243193323Sed /// looking for aliasing nodes and adding them to the Aliases vector. 244193323Sed void GatherAllAliases(SDNode *N, SDValue OriginalChain, 245193323Sed SmallVector<SDValue, 8> &Aliases); 246193323Sed 247193323Sed /// isAlias - Return true if there is any possibility that the two addresses 248193323Sed /// overlap. 249193323Sed bool isAlias(SDValue Ptr1, int64_t Size1, 250193323Sed const Value *SrcValue1, int SrcValueOffset1, 251198090Srdivacky unsigned SrcValueAlign1, 252218893Sdim const MDNode *TBAAInfo1, 253193323Sed SDValue Ptr2, int64_t Size2, 254198090Srdivacky const Value *SrcValue2, int SrcValueOffset2, 255218893Sdim unsigned SrcValueAlign2, 256218893Sdim const MDNode *TBAAInfo2) const; 257193323Sed 258193323Sed /// FindAliasInfo - Extracts the relevant alias information from the memory 259193323Sed /// node. Returns true if the operand was a load. 260193323Sed bool FindAliasInfo(SDNode *N, 261193323Sed SDValue &Ptr, int64_t &Size, 262198090Srdivacky const Value *&SrcValue, int &SrcValueOffset, 263218893Sdim unsigned &SrcValueAlignment, 264218893Sdim const MDNode *&TBAAInfo) const; 265193323Sed 266193323Sed /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 267193323Sed /// looking for a better chain (aliasing node.) 268193323Sed SDValue FindBetterChain(SDNode *N, SDValue Chain); 269193323Sed 270207618Srdivacky public: 271207618Srdivacky DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 272207618Srdivacky : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 273207618Srdivacky OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 274207618Srdivacky 275207618Srdivacky /// Run - runs the dag combiner on all nodes in the work list 276207618Srdivacky void Run(CombineLevel AtLevel); 277218893Sdim 278207618Srdivacky SelectionDAG &getDAG() const { return DAG; } 279218893Sdim 280193323Sed /// getShiftAmountTy - Returns a type large enough to hold any valid 281193323Sed /// shift amount - before type legalization these can be huge. 282219077Sdim EVT getShiftAmountTy(EVT LHSTy) { 283219077Sdim return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 284193323Sed } 285218893Sdim 286207618Srdivacky /// isTypeLegal - This method returns true if we are running before type 287207618Srdivacky /// legalization or if the specified VT is legal. 288207618Srdivacky bool isTypeLegal(const EVT &VT) { 289207618Srdivacky if (!LegalTypes) return true; 290207618Srdivacky return TLI.isTypeLegal(VT); 291207618Srdivacky } 292193323Sed }; 293193323Sed} 294193323Sed 295193323Sed 296193323Sednamespace { 297193323Sed/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 298193323Sed/// nodes from the worklist. 299198892Srdivackyclass WorkListRemover : public SelectionDAG::DAGUpdateListener { 300193323Sed DAGCombiner &DC; 301193323Sedpublic: 302193323Sed explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 303193323Sed 304193323Sed virtual void NodeDeleted(SDNode *N, SDNode *E) { 305193323Sed DC.removeFromWorkList(N); 306193323Sed } 307193323Sed 308193323Sed virtual void NodeUpdated(SDNode *N) { 309193323Sed // Ignore updates. 310193323Sed } 311193323Sed}; 312193323Sed} 313193323Sed 314193323Sed//===----------------------------------------------------------------------===// 315193323Sed// TargetLowering::DAGCombinerInfo implementation 316193323Sed//===----------------------------------------------------------------------===// 317193323Sed 318193323Sedvoid TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 319193323Sed ((DAGCombiner*)DC)->AddToWorkList(N); 320193323Sed} 321193323Sed 322193323SedSDValue TargetLowering::DAGCombinerInfo:: 323193323SedCombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 324193323Sed return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 325193323Sed} 326193323Sed 327193323SedSDValue TargetLowering::DAGCombinerInfo:: 328193323SedCombineTo(SDNode *N, SDValue Res, bool AddTo) { 329193323Sed return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 330193323Sed} 331193323Sed 332193323Sed 333193323SedSDValue TargetLowering::DAGCombinerInfo:: 334193323SedCombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 335193323Sed return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 336193323Sed} 337193323Sed 338193323Sedvoid TargetLowering::DAGCombinerInfo:: 339193323SedCommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 340193323Sed return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 341193323Sed} 342193323Sed 343193323Sed//===----------------------------------------------------------------------===// 344193323Sed// Helper Functions 345193323Sed//===----------------------------------------------------------------------===// 346193323Sed 347193323Sed/// isNegatibleForFree - Return 1 if we can compute the negated form of the 348193323Sed/// specified expression for the same cost as the expression itself, or 2 if we 349193323Sed/// can compute the negated form more cheaply than the expression itself. 350193323Sedstatic char isNegatibleForFree(SDValue Op, bool LegalOperations, 351193323Sed unsigned Depth = 0) { 352193323Sed // No compile time optimizations on this type. 353193323Sed if (Op.getValueType() == MVT::ppcf128) 354193323Sed return 0; 355193323Sed 356193323Sed // fneg is removable even if it has multiple uses. 357193323Sed if (Op.getOpcode() == ISD::FNEG) return 2; 358193323Sed 359193323Sed // Don't allow anything with multiple uses. 360193323Sed if (!Op.hasOneUse()) return 0; 361193323Sed 362193323Sed // Don't recurse exponentially. 363193323Sed if (Depth > 6) return 0; 364193323Sed 365193323Sed switch (Op.getOpcode()) { 366193323Sed default: return false; 367193323Sed case ISD::ConstantFP: 368193323Sed // Don't invert constant FP values after legalize. The negated constant 369193323Sed // isn't necessarily legal. 370193323Sed return LegalOperations ? 0 : 1; 371193323Sed case ISD::FADD: 372193323Sed // FIXME: determine better conditions for this xform. 373193323Sed if (!UnsafeFPMath) return 0; 374193323Sed 375193323Sed // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 376193323Sed if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 377193323Sed return V; 378193323Sed // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 379193323Sed return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 380193323Sed case ISD::FSUB: 381193323Sed // We can't turn -(A-B) into B-A when we honor signed zeros. 382193323Sed if (!UnsafeFPMath) return 0; 383193323Sed 384193323Sed // fold (fneg (fsub A, B)) -> (fsub B, A) 385193323Sed return 1; 386193323Sed 387193323Sed case ISD::FMUL: 388193323Sed case ISD::FDIV: 389193323Sed if (HonorSignDependentRoundingFPMath()) return 0; 390193323Sed 391193323Sed // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 392193323Sed if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 393193323Sed return V; 394193323Sed 395193323Sed return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 396193323Sed 397193323Sed case ISD::FP_EXTEND: 398193323Sed case ISD::FP_ROUND: 399193323Sed case ISD::FSIN: 400193323Sed return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 401193323Sed } 402193323Sed} 403193323Sed 404193323Sed/// GetNegatedExpression - If isNegatibleForFree returns true, this function 405193323Sed/// returns the newly negated expression. 406193323Sedstatic SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 407193323Sed bool LegalOperations, unsigned Depth = 0) { 408193323Sed // fneg is removable even if it has multiple uses. 409193323Sed if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 410193323Sed 411193323Sed // Don't allow anything with multiple uses. 412193323Sed assert(Op.hasOneUse() && "Unknown reuse!"); 413193323Sed 414193323Sed assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 415193323Sed switch (Op.getOpcode()) { 416198090Srdivacky default: llvm_unreachable("Unknown code"); 417193323Sed case ISD::ConstantFP: { 418193323Sed APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 419193323Sed V.changeSign(); 420193323Sed return DAG.getConstantFP(V, Op.getValueType()); 421193323Sed } 422193323Sed case ISD::FADD: 423193323Sed // FIXME: determine better conditions for this xform. 424193323Sed assert(UnsafeFPMath); 425193323Sed 426193323Sed // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 427193323Sed if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 428193323Sed return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 429193323Sed GetNegatedExpression(Op.getOperand(0), DAG, 430193323Sed LegalOperations, Depth+1), 431193323Sed Op.getOperand(1)); 432193323Sed // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 433193323Sed return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 434193323Sed GetNegatedExpression(Op.getOperand(1), DAG, 435193323Sed LegalOperations, Depth+1), 436193323Sed Op.getOperand(0)); 437193323Sed case ISD::FSUB: 438193323Sed // We can't turn -(A-B) into B-A when we honor signed zeros. 439193323Sed assert(UnsafeFPMath); 440193323Sed 441193323Sed // fold (fneg (fsub 0, B)) -> B 442193323Sed if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 443193323Sed if (N0CFP->getValueAPF().isZero()) 444193323Sed return Op.getOperand(1); 445193323Sed 446193323Sed // fold (fneg (fsub A, B)) -> (fsub B, A) 447193323Sed return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 448193323Sed Op.getOperand(1), Op.getOperand(0)); 449193323Sed 450193323Sed case ISD::FMUL: 451193323Sed case ISD::FDIV: 452193323Sed assert(!HonorSignDependentRoundingFPMath()); 453193323Sed 454193323Sed // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 455193323Sed if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 456193323Sed return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 457193323Sed GetNegatedExpression(Op.getOperand(0), DAG, 458193323Sed LegalOperations, Depth+1), 459193323Sed Op.getOperand(1)); 460193323Sed 461193323Sed // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 462193323Sed return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 463193323Sed Op.getOperand(0), 464193323Sed GetNegatedExpression(Op.getOperand(1), DAG, 465193323Sed LegalOperations, Depth+1)); 466193323Sed 467193323Sed case ISD::FP_EXTEND: 468193323Sed case ISD::FSIN: 469193323Sed return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 470193323Sed GetNegatedExpression(Op.getOperand(0), DAG, 471193323Sed LegalOperations, Depth+1)); 472193323Sed case ISD::FP_ROUND: 473193323Sed return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 474193323Sed GetNegatedExpression(Op.getOperand(0), DAG, 475193323Sed LegalOperations, Depth+1), 476193323Sed Op.getOperand(1)); 477193323Sed } 478193323Sed} 479193323Sed 480193323Sed 481193323Sed// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 482193323Sed// that selects between the values 1 and 0, making it equivalent to a setcc. 483193323Sed// Also, set the incoming LHS, RHS, and CC references to the appropriate 484193323Sed// nodes based on the type of node we are checking. This simplifies life a 485193323Sed// bit for the callers. 486193323Sedstatic bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 487193323Sed SDValue &CC) { 488193323Sed if (N.getOpcode() == ISD::SETCC) { 489193323Sed LHS = N.getOperand(0); 490193323Sed RHS = N.getOperand(1); 491193323Sed CC = N.getOperand(2); 492193323Sed return true; 493193323Sed } 494193323Sed if (N.getOpcode() == ISD::SELECT_CC && 495193323Sed N.getOperand(2).getOpcode() == ISD::Constant && 496193323Sed N.getOperand(3).getOpcode() == ISD::Constant && 497193323Sed cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 498193323Sed cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 499193323Sed LHS = N.getOperand(0); 500193323Sed RHS = N.getOperand(1); 501193323Sed CC = N.getOperand(4); 502193323Sed return true; 503193323Sed } 504193323Sed return false; 505193323Sed} 506193323Sed 507193323Sed// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 508193323Sed// one use. If this is true, it allows the users to invert the operation for 509193323Sed// free when it is profitable to do so. 510193323Sedstatic bool isOneUseSetCC(SDValue N) { 511193323Sed SDValue N0, N1, N2; 512193323Sed if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 513193323Sed return true; 514193323Sed return false; 515193323Sed} 516193323Sed 517193323SedSDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 518193323Sed SDValue N0, SDValue N1) { 519198090Srdivacky EVT VT = N0.getValueType(); 520193323Sed if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 521193323Sed if (isa<ConstantSDNode>(N1)) { 522193323Sed // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 523193323Sed SDValue OpNode = 524193323Sed DAG.FoldConstantArithmetic(Opc, VT, 525193323Sed cast<ConstantSDNode>(N0.getOperand(1)), 526193323Sed cast<ConstantSDNode>(N1)); 527193323Sed return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 528193323Sed } else if (N0.hasOneUse()) { 529193323Sed // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 530193323Sed SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 531193323Sed N0.getOperand(0), N1); 532193323Sed AddToWorkList(OpNode.getNode()); 533193323Sed return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 534193323Sed } 535193323Sed } 536193323Sed 537193323Sed if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 538193323Sed if (isa<ConstantSDNode>(N0)) { 539193323Sed // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 540193323Sed SDValue OpNode = 541193323Sed DAG.FoldConstantArithmetic(Opc, VT, 542193323Sed cast<ConstantSDNode>(N1.getOperand(1)), 543193323Sed cast<ConstantSDNode>(N0)); 544193323Sed return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 545193323Sed } else if (N1.hasOneUse()) { 546193323Sed // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 547193323Sed SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 548193323Sed N1.getOperand(0), N0); 549193323Sed AddToWorkList(OpNode.getNode()); 550193323Sed return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 551193323Sed } 552193323Sed } 553193323Sed 554193323Sed return SDValue(); 555193323Sed} 556193323Sed 557193323SedSDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 558193323Sed bool AddTo) { 559193323Sed assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 560193323Sed ++NodesCombined; 561202375Srdivacky DEBUG(dbgs() << "\nReplacing.1 "; 562198090Srdivacky N->dump(&DAG); 563202375Srdivacky dbgs() << "\nWith: "; 564198090Srdivacky To[0].getNode()->dump(&DAG); 565202375Srdivacky dbgs() << " and " << NumTo-1 << " other values\n"; 566198090Srdivacky for (unsigned i = 0, e = NumTo; i != e; ++i) 567200581Srdivacky assert((!To[i].getNode() || 568200581Srdivacky N->getValueType(i) == To[i].getValueType()) && 569193323Sed "Cannot combine value to value of different type!")); 570193323Sed WorkListRemover DeadNodes(*this); 571193323Sed DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 572193323Sed 573193323Sed if (AddTo) { 574193323Sed // Push the new nodes and any users onto the worklist 575193323Sed for (unsigned i = 0, e = NumTo; i != e; ++i) { 576193323Sed if (To[i].getNode()) { 577193323Sed AddToWorkList(To[i].getNode()); 578193323Sed AddUsersToWorkList(To[i].getNode()); 579193323Sed } 580193323Sed } 581193323Sed } 582193323Sed 583193323Sed // Finally, if the node is now dead, remove it from the graph. The node 584193323Sed // may not be dead if the replacement process recursively simplified to 585193323Sed // something else needing this node. 586193323Sed if (N->use_empty()) { 587193323Sed // Nodes can be reintroduced into the worklist. Make sure we do not 588193323Sed // process a node that has been replaced. 589193323Sed removeFromWorkList(N); 590193323Sed 591193323Sed // Finally, since the node is now dead, remove it from the graph. 592193323Sed DAG.DeleteNode(N); 593193323Sed } 594193323Sed return SDValue(N, 0); 595193323Sed} 596193323Sed 597207618Srdivackyvoid DAGCombiner:: 598207618SrdivackyCommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 599193323Sed // Replace all uses. If any nodes become isomorphic to other nodes and 600193323Sed // are deleted, make sure to remove them from our worklist. 601193323Sed WorkListRemover DeadNodes(*this); 602193323Sed DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 603193323Sed 604193323Sed // Push the new node and any (possibly new) users onto the worklist. 605193323Sed AddToWorkList(TLO.New.getNode()); 606193323Sed AddUsersToWorkList(TLO.New.getNode()); 607193323Sed 608193323Sed // Finally, if the node is now dead, remove it from the graph. The node 609193323Sed // may not be dead if the replacement process recursively simplified to 610193323Sed // something else needing this node. 611193323Sed if (TLO.Old.getNode()->use_empty()) { 612193323Sed removeFromWorkList(TLO.Old.getNode()); 613193323Sed 614193323Sed // If the operands of this node are only used by the node, they will now 615193323Sed // be dead. Make sure to visit them first to delete dead nodes early. 616193323Sed for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 617193323Sed if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 618193323Sed AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 619193323Sed 620193323Sed DAG.DeleteNode(TLO.Old.getNode()); 621193323Sed } 622193323Sed} 623193323Sed 624193323Sed/// SimplifyDemandedBits - Check the specified integer node value to see if 625193323Sed/// it can be simplified or if things it uses can be simplified by bit 626193323Sed/// propagation. If so, return true. 627193323Sedbool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 628207618Srdivacky TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 629193323Sed APInt KnownZero, KnownOne; 630193323Sed if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 631193323Sed return false; 632193323Sed 633193323Sed // Revisit the node. 634193323Sed AddToWorkList(Op.getNode()); 635193323Sed 636193323Sed // Replace the old value with the new one. 637193323Sed ++NodesCombined; 638218893Sdim DEBUG(dbgs() << "\nReplacing.2 "; 639198090Srdivacky TLO.Old.getNode()->dump(&DAG); 640202375Srdivacky dbgs() << "\nWith: "; 641198090Srdivacky TLO.New.getNode()->dump(&DAG); 642202375Srdivacky dbgs() << '\n'); 643193323Sed 644193323Sed CommitTargetLoweringOpt(TLO); 645193323Sed return true; 646193323Sed} 647193323Sed 648207618Srdivackyvoid DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 649207618Srdivacky DebugLoc dl = Load->getDebugLoc(); 650207618Srdivacky EVT VT = Load->getValueType(0); 651207618Srdivacky SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 652207618Srdivacky 653207618Srdivacky DEBUG(dbgs() << "\nReplacing.9 "; 654207618Srdivacky Load->dump(&DAG); 655207618Srdivacky dbgs() << "\nWith: "; 656207618Srdivacky Trunc.getNode()->dump(&DAG); 657207618Srdivacky dbgs() << '\n'); 658207618Srdivacky WorkListRemover DeadNodes(*this); 659207618Srdivacky DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 660207618Srdivacky DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 661207618Srdivacky &DeadNodes); 662207618Srdivacky removeFromWorkList(Load); 663207618Srdivacky DAG.DeleteNode(Load); 664207618Srdivacky AddToWorkList(Trunc.getNode()); 665207618Srdivacky} 666207618Srdivacky 667207618SrdivackySDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 668207618Srdivacky Replace = false; 669207618Srdivacky DebugLoc dl = Op.getDebugLoc(); 670207618Srdivacky if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 671207618Srdivacky EVT MemVT = LD->getMemoryVT(); 672207618Srdivacky ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 673219077Sdim ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 674218893Sdim : ISD::EXTLOAD) 675207618Srdivacky : LD->getExtensionType(); 676207618Srdivacky Replace = true; 677218893Sdim return DAG.getExtLoad(ExtType, dl, PVT, 678207618Srdivacky LD->getChain(), LD->getBasePtr(), 679218893Sdim LD->getPointerInfo(), 680207618Srdivacky MemVT, LD->isVolatile(), 681207618Srdivacky LD->isNonTemporal(), LD->getAlignment()); 682207618Srdivacky } 683207618Srdivacky 684207618Srdivacky unsigned Opc = Op.getOpcode(); 685207618Srdivacky switch (Opc) { 686207618Srdivacky default: break; 687207618Srdivacky case ISD::AssertSext: 688207618Srdivacky return DAG.getNode(ISD::AssertSext, dl, PVT, 689207618Srdivacky SExtPromoteOperand(Op.getOperand(0), PVT), 690207618Srdivacky Op.getOperand(1)); 691207618Srdivacky case ISD::AssertZext: 692207618Srdivacky return DAG.getNode(ISD::AssertZext, dl, PVT, 693207618Srdivacky ZExtPromoteOperand(Op.getOperand(0), PVT), 694207618Srdivacky Op.getOperand(1)); 695207618Srdivacky case ISD::Constant: { 696207618Srdivacky unsigned ExtOpc = 697207618Srdivacky Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 698207618Srdivacky return DAG.getNode(ExtOpc, dl, PVT, Op); 699207618Srdivacky } 700218893Sdim } 701207618Srdivacky 702207618Srdivacky if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 703207618Srdivacky return SDValue(); 704207618Srdivacky return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 705207618Srdivacky} 706207618Srdivacky 707207618SrdivackySDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 708207618Srdivacky if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 709207618Srdivacky return SDValue(); 710207618Srdivacky EVT OldVT = Op.getValueType(); 711207618Srdivacky DebugLoc dl = Op.getDebugLoc(); 712207618Srdivacky bool Replace = false; 713207618Srdivacky SDValue NewOp = PromoteOperand(Op, PVT, Replace); 714207618Srdivacky if (NewOp.getNode() == 0) 715207618Srdivacky return SDValue(); 716207618Srdivacky AddToWorkList(NewOp.getNode()); 717207618Srdivacky 718207618Srdivacky if (Replace) 719207618Srdivacky ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 720207618Srdivacky return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 721207618Srdivacky DAG.getValueType(OldVT)); 722207618Srdivacky} 723207618Srdivacky 724207618SrdivackySDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 725207618Srdivacky EVT OldVT = Op.getValueType(); 726207618Srdivacky DebugLoc dl = Op.getDebugLoc(); 727207618Srdivacky bool Replace = false; 728207618Srdivacky SDValue NewOp = PromoteOperand(Op, PVT, Replace); 729207618Srdivacky if (NewOp.getNode() == 0) 730207618Srdivacky return SDValue(); 731207618Srdivacky AddToWorkList(NewOp.getNode()); 732207618Srdivacky 733207618Srdivacky if (Replace) 734207618Srdivacky ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 735207618Srdivacky return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 736207618Srdivacky} 737207618Srdivacky 738207618Srdivacky/// PromoteIntBinOp - Promote the specified integer binary operation if the 739207618Srdivacky/// target indicates it is beneficial. e.g. On x86, it's usually better to 740207618Srdivacky/// promote i16 operations to i32 since i16 instructions are longer. 741207618SrdivackySDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 742207618Srdivacky if (!LegalOperations) 743207618Srdivacky return SDValue(); 744207618Srdivacky 745207618Srdivacky EVT VT = Op.getValueType(); 746207618Srdivacky if (VT.isVector() || !VT.isInteger()) 747207618Srdivacky return SDValue(); 748207618Srdivacky 749207618Srdivacky // If operation type is 'undesirable', e.g. i16 on x86, consider 750207618Srdivacky // promoting it. 751207618Srdivacky unsigned Opc = Op.getOpcode(); 752207618Srdivacky if (TLI.isTypeDesirableForOp(Opc, VT)) 753207618Srdivacky return SDValue(); 754207618Srdivacky 755207618Srdivacky EVT PVT = VT; 756207618Srdivacky // Consult target whether it is a good idea to promote this operation and 757207618Srdivacky // what's the right type to promote it to. 758207618Srdivacky if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 759207618Srdivacky assert(PVT != VT && "Don't know what type to promote to!"); 760207618Srdivacky 761207618Srdivacky bool Replace0 = false; 762207618Srdivacky SDValue N0 = Op.getOperand(0); 763207618Srdivacky SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 764207618Srdivacky if (NN0.getNode() == 0) 765207618Srdivacky return SDValue(); 766207618Srdivacky 767207618Srdivacky bool Replace1 = false; 768207618Srdivacky SDValue N1 = Op.getOperand(1); 769208599Srdivacky SDValue NN1; 770208599Srdivacky if (N0 == N1) 771208599Srdivacky NN1 = NN0; 772208599Srdivacky else { 773208599Srdivacky NN1 = PromoteOperand(N1, PVT, Replace1); 774208599Srdivacky if (NN1.getNode() == 0) 775208599Srdivacky return SDValue(); 776208599Srdivacky } 777207618Srdivacky 778207618Srdivacky AddToWorkList(NN0.getNode()); 779208599Srdivacky if (NN1.getNode()) 780208599Srdivacky AddToWorkList(NN1.getNode()); 781207618Srdivacky 782207618Srdivacky if (Replace0) 783207618Srdivacky ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 784207618Srdivacky if (Replace1) 785207618Srdivacky ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 786207618Srdivacky 787207618Srdivacky DEBUG(dbgs() << "\nPromoting "; 788207618Srdivacky Op.getNode()->dump(&DAG)); 789207618Srdivacky DebugLoc dl = Op.getDebugLoc(); 790207618Srdivacky return DAG.getNode(ISD::TRUNCATE, dl, VT, 791207618Srdivacky DAG.getNode(Opc, dl, PVT, NN0, NN1)); 792207618Srdivacky } 793207618Srdivacky return SDValue(); 794207618Srdivacky} 795207618Srdivacky 796207618Srdivacky/// PromoteIntShiftOp - Promote the specified integer shift operation if the 797207618Srdivacky/// target indicates it is beneficial. e.g. On x86, it's usually better to 798207618Srdivacky/// promote i16 operations to i32 since i16 instructions are longer. 799207618SrdivackySDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 800207618Srdivacky if (!LegalOperations) 801207618Srdivacky return SDValue(); 802207618Srdivacky 803207618Srdivacky EVT VT = Op.getValueType(); 804207618Srdivacky if (VT.isVector() || !VT.isInteger()) 805207618Srdivacky return SDValue(); 806207618Srdivacky 807207618Srdivacky // If operation type is 'undesirable', e.g. i16 on x86, consider 808207618Srdivacky // promoting it. 809207618Srdivacky unsigned Opc = Op.getOpcode(); 810207618Srdivacky if (TLI.isTypeDesirableForOp(Opc, VT)) 811207618Srdivacky return SDValue(); 812207618Srdivacky 813207618Srdivacky EVT PVT = VT; 814207618Srdivacky // Consult target whether it is a good idea to promote this operation and 815207618Srdivacky // what's the right type to promote it to. 816207618Srdivacky if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 817207618Srdivacky assert(PVT != VT && "Don't know what type to promote to!"); 818207618Srdivacky 819207618Srdivacky bool Replace = false; 820207618Srdivacky SDValue N0 = Op.getOperand(0); 821207618Srdivacky if (Opc == ISD::SRA) 822207618Srdivacky N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 823207618Srdivacky else if (Opc == ISD::SRL) 824207618Srdivacky N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 825207618Srdivacky else 826207618Srdivacky N0 = PromoteOperand(N0, PVT, Replace); 827207618Srdivacky if (N0.getNode() == 0) 828207618Srdivacky return SDValue(); 829207618Srdivacky 830207618Srdivacky AddToWorkList(N0.getNode()); 831207618Srdivacky if (Replace) 832207618Srdivacky ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 833207618Srdivacky 834207618Srdivacky DEBUG(dbgs() << "\nPromoting "; 835207618Srdivacky Op.getNode()->dump(&DAG)); 836207618Srdivacky DebugLoc dl = Op.getDebugLoc(); 837207618Srdivacky return DAG.getNode(ISD::TRUNCATE, dl, VT, 838207618Srdivacky DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 839207618Srdivacky } 840207618Srdivacky return SDValue(); 841207618Srdivacky} 842207618Srdivacky 843207618SrdivackySDValue DAGCombiner::PromoteExtend(SDValue Op) { 844207618Srdivacky if (!LegalOperations) 845207618Srdivacky return SDValue(); 846207618Srdivacky 847207618Srdivacky EVT VT = Op.getValueType(); 848207618Srdivacky if (VT.isVector() || !VT.isInteger()) 849207618Srdivacky return SDValue(); 850207618Srdivacky 851207618Srdivacky // If operation type is 'undesirable', e.g. i16 on x86, consider 852207618Srdivacky // promoting it. 853207618Srdivacky unsigned Opc = Op.getOpcode(); 854207618Srdivacky if (TLI.isTypeDesirableForOp(Opc, VT)) 855207618Srdivacky return SDValue(); 856207618Srdivacky 857207618Srdivacky EVT PVT = VT; 858207618Srdivacky // Consult target whether it is a good idea to promote this operation and 859207618Srdivacky // what's the right type to promote it to. 860207618Srdivacky if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 861207618Srdivacky assert(PVT != VT && "Don't know what type to promote to!"); 862207618Srdivacky // fold (aext (aext x)) -> (aext x) 863207618Srdivacky // fold (aext (zext x)) -> (zext x) 864207618Srdivacky // fold (aext (sext x)) -> (sext x) 865207618Srdivacky DEBUG(dbgs() << "\nPromoting "; 866207618Srdivacky Op.getNode()->dump(&DAG)); 867207618Srdivacky return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 868207618Srdivacky } 869207618Srdivacky return SDValue(); 870207618Srdivacky} 871207618Srdivacky 872207618Srdivackybool DAGCombiner::PromoteLoad(SDValue Op) { 873207618Srdivacky if (!LegalOperations) 874207618Srdivacky return false; 875207618Srdivacky 876207618Srdivacky EVT VT = Op.getValueType(); 877207618Srdivacky if (VT.isVector() || !VT.isInteger()) 878207618Srdivacky return false; 879207618Srdivacky 880207618Srdivacky // If operation type is 'undesirable', e.g. i16 on x86, consider 881207618Srdivacky // promoting it. 882207618Srdivacky unsigned Opc = Op.getOpcode(); 883207618Srdivacky if (TLI.isTypeDesirableForOp(Opc, VT)) 884207618Srdivacky return false; 885207618Srdivacky 886207618Srdivacky EVT PVT = VT; 887207618Srdivacky // Consult target whether it is a good idea to promote this operation and 888207618Srdivacky // what's the right type to promote it to. 889207618Srdivacky if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 890207618Srdivacky assert(PVT != VT && "Don't know what type to promote to!"); 891207618Srdivacky 892207618Srdivacky DebugLoc dl = Op.getDebugLoc(); 893207618Srdivacky SDNode *N = Op.getNode(); 894207618Srdivacky LoadSDNode *LD = cast<LoadSDNode>(N); 895207618Srdivacky EVT MemVT = LD->getMemoryVT(); 896207618Srdivacky ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 897219077Sdim ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 898218893Sdim : ISD::EXTLOAD) 899207618Srdivacky : LD->getExtensionType(); 900218893Sdim SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 901207618Srdivacky LD->getChain(), LD->getBasePtr(), 902218893Sdim LD->getPointerInfo(), 903207618Srdivacky MemVT, LD->isVolatile(), 904207618Srdivacky LD->isNonTemporal(), LD->getAlignment()); 905207618Srdivacky SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 906207618Srdivacky 907207618Srdivacky DEBUG(dbgs() << "\nPromoting "; 908207618Srdivacky N->dump(&DAG); 909207618Srdivacky dbgs() << "\nTo: "; 910207618Srdivacky Result.getNode()->dump(&DAG); 911207618Srdivacky dbgs() << '\n'); 912207618Srdivacky WorkListRemover DeadNodes(*this); 913207618Srdivacky DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 914207618Srdivacky DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 915207618Srdivacky removeFromWorkList(N); 916207618Srdivacky DAG.DeleteNode(N); 917207618Srdivacky AddToWorkList(Result.getNode()); 918207618Srdivacky return true; 919207618Srdivacky } 920207618Srdivacky return false; 921207618Srdivacky} 922207618Srdivacky 923207618Srdivacky 924193323Sed//===----------------------------------------------------------------------===// 925193323Sed// Main DAG Combiner implementation 926193323Sed//===----------------------------------------------------------------------===// 927193323Sed 928193323Sedvoid DAGCombiner::Run(CombineLevel AtLevel) { 929193323Sed // set the instance variables, so that the various visit routines may use it. 930193323Sed Level = AtLevel; 931193323Sed LegalOperations = Level >= NoIllegalOperations; 932193323Sed LegalTypes = Level >= NoIllegalTypes; 933193323Sed 934193323Sed // Add all the dag nodes to the worklist. 935193323Sed WorkList.reserve(DAG.allnodes_size()); 936193323Sed for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 937193323Sed E = DAG.allnodes_end(); I != E; ++I) 938193323Sed WorkList.push_back(I); 939193323Sed 940193323Sed // Create a dummy node (which is not added to allnodes), that adds a reference 941193323Sed // to the root node, preventing it from being deleted, and tracking any 942193323Sed // changes of the root. 943193323Sed HandleSDNode Dummy(DAG.getRoot()); 944193323Sed 945193323Sed // The root of the dag may dangle to deleted nodes until the dag combiner is 946193323Sed // done. Set it to null to avoid confusion. 947193323Sed DAG.setRoot(SDValue()); 948193323Sed 949193323Sed // while the worklist isn't empty, inspect the node on the end of it and 950193323Sed // try and combine it. 951193323Sed while (!WorkList.empty()) { 952193323Sed SDNode *N = WorkList.back(); 953193323Sed WorkList.pop_back(); 954193323Sed 955193323Sed // If N has no uses, it is dead. Make sure to revisit all N's operands once 956193323Sed // N is deleted from the DAG, since they too may now be dead or may have a 957193323Sed // reduced number of uses, allowing other xforms. 958193323Sed if (N->use_empty() && N != &Dummy) { 959193323Sed for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 960193323Sed AddToWorkList(N->getOperand(i).getNode()); 961193323Sed 962193323Sed DAG.DeleteNode(N); 963193323Sed continue; 964193323Sed } 965193323Sed 966193323Sed SDValue RV = combine(N); 967193323Sed 968193323Sed if (RV.getNode() == 0) 969193323Sed continue; 970193323Sed 971193323Sed ++NodesCombined; 972193323Sed 973193323Sed // If we get back the same node we passed in, rather than a new node or 974193323Sed // zero, we know that the node must have defined multiple values and 975193323Sed // CombineTo was used. Since CombineTo takes care of the worklist 976193323Sed // mechanics for us, we have no work to do in this case. 977193323Sed if (RV.getNode() == N) 978193323Sed continue; 979193323Sed 980193323Sed assert(N->getOpcode() != ISD::DELETED_NODE && 981193323Sed RV.getNode()->getOpcode() != ISD::DELETED_NODE && 982193323Sed "Node was deleted but visit returned new node!"); 983193323Sed 984218893Sdim DEBUG(dbgs() << "\nReplacing.3 "; 985198090Srdivacky N->dump(&DAG); 986202375Srdivacky dbgs() << "\nWith: "; 987198090Srdivacky RV.getNode()->dump(&DAG); 988202375Srdivacky dbgs() << '\n'); 989193323Sed WorkListRemover DeadNodes(*this); 990193323Sed if (N->getNumValues() == RV.getNode()->getNumValues()) 991193323Sed DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 992193323Sed else { 993193323Sed assert(N->getValueType(0) == RV.getValueType() && 994193323Sed N->getNumValues() == 1 && "Type mismatch"); 995193323Sed SDValue OpV = RV; 996193323Sed DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 997193323Sed } 998193323Sed 999193323Sed // Push the new node and any users onto the worklist 1000193323Sed AddToWorkList(RV.getNode()); 1001193323Sed AddUsersToWorkList(RV.getNode()); 1002193323Sed 1003193323Sed // Add any uses of the old node to the worklist in case this node is the 1004193323Sed // last one that uses them. They may become dead after this node is 1005193323Sed // deleted. 1006193323Sed for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1007193323Sed AddToWorkList(N->getOperand(i).getNode()); 1008193323Sed 1009193323Sed // Finally, if the node is now dead, remove it from the graph. The node 1010193323Sed // may not be dead if the replacement process recursively simplified to 1011193323Sed // something else needing this node. 1012193323Sed if (N->use_empty()) { 1013193323Sed // Nodes can be reintroduced into the worklist. Make sure we do not 1014193323Sed // process a node that has been replaced. 1015193323Sed removeFromWorkList(N); 1016193323Sed 1017193323Sed // Finally, since the node is now dead, remove it from the graph. 1018193323Sed DAG.DeleteNode(N); 1019193323Sed } 1020193323Sed } 1021193323Sed 1022193323Sed // If the root changed (e.g. it was a dead load, update the root). 1023193323Sed DAG.setRoot(Dummy.getValue()); 1024193323Sed} 1025193323Sed 1026193323SedSDValue DAGCombiner::visit(SDNode *N) { 1027207618Srdivacky switch (N->getOpcode()) { 1028193323Sed default: break; 1029193323Sed case ISD::TokenFactor: return visitTokenFactor(N); 1030193323Sed case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1031193323Sed case ISD::ADD: return visitADD(N); 1032193323Sed case ISD::SUB: return visitSUB(N); 1033193323Sed case ISD::ADDC: return visitADDC(N); 1034193323Sed case ISD::ADDE: return visitADDE(N); 1035193323Sed case ISD::MUL: return visitMUL(N); 1036193323Sed case ISD::SDIV: return visitSDIV(N); 1037193323Sed case ISD::UDIV: return visitUDIV(N); 1038193323Sed case ISD::SREM: return visitSREM(N); 1039193323Sed case ISD::UREM: return visitUREM(N); 1040193323Sed case ISD::MULHU: return visitMULHU(N); 1041193323Sed case ISD::MULHS: return visitMULHS(N); 1042193323Sed case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1043193323Sed case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1044193323Sed case ISD::SDIVREM: return visitSDIVREM(N); 1045193323Sed case ISD::UDIVREM: return visitUDIVREM(N); 1046193323Sed case ISD::AND: return visitAND(N); 1047193323Sed case ISD::OR: return visitOR(N); 1048193323Sed case ISD::XOR: return visitXOR(N); 1049193323Sed case ISD::SHL: return visitSHL(N); 1050193323Sed case ISD::SRA: return visitSRA(N); 1051193323Sed case ISD::SRL: return visitSRL(N); 1052193323Sed case ISD::CTLZ: return visitCTLZ(N); 1053193323Sed case ISD::CTTZ: return visitCTTZ(N); 1054193323Sed case ISD::CTPOP: return visitCTPOP(N); 1055193323Sed case ISD::SELECT: return visitSELECT(N); 1056193323Sed case ISD::SELECT_CC: return visitSELECT_CC(N); 1057193323Sed case ISD::SETCC: return visitSETCC(N); 1058193323Sed case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1059193323Sed case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1060193323Sed case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1061193323Sed case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1062193323Sed case ISD::TRUNCATE: return visitTRUNCATE(N); 1063218893Sdim case ISD::BITCAST: return visitBITCAST(N); 1064193323Sed case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1065193323Sed case ISD::FADD: return visitFADD(N); 1066193323Sed case ISD::FSUB: return visitFSUB(N); 1067193323Sed case ISD::FMUL: return visitFMUL(N); 1068193323Sed case ISD::FDIV: return visitFDIV(N); 1069193323Sed case ISD::FREM: return visitFREM(N); 1070193323Sed case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1071193323Sed case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1072193323Sed case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1073193323Sed case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1074193323Sed case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1075193323Sed case ISD::FP_ROUND: return visitFP_ROUND(N); 1076193323Sed case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1077193323Sed case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1078193323Sed case ISD::FNEG: return visitFNEG(N); 1079193323Sed case ISD::FABS: return visitFABS(N); 1080193323Sed case ISD::BRCOND: return visitBRCOND(N); 1081193323Sed case ISD::BR_CC: return visitBR_CC(N); 1082193323Sed case ISD::LOAD: return visitLOAD(N); 1083193323Sed case ISD::STORE: return visitSTORE(N); 1084193323Sed case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1085193323Sed case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1086193323Sed case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1087193323Sed case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1088193323Sed case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1089210299Sed case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1090193323Sed } 1091193323Sed return SDValue(); 1092193323Sed} 1093193323Sed 1094193323SedSDValue DAGCombiner::combine(SDNode *N) { 1095193323Sed SDValue RV = visit(N); 1096193323Sed 1097193323Sed // If nothing happened, try a target-specific DAG combine. 1098193323Sed if (RV.getNode() == 0) { 1099193323Sed assert(N->getOpcode() != ISD::DELETED_NODE && 1100193323Sed "Node was deleted but visit returned NULL!"); 1101193323Sed 1102193323Sed if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1103193323Sed TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1104193323Sed 1105193323Sed // Expose the DAG combiner to the target combiner impls. 1106193323Sed TargetLowering::DAGCombinerInfo 1107198090Srdivacky DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1108193323Sed 1109193323Sed RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1110193323Sed } 1111193323Sed } 1112193323Sed 1113207618Srdivacky // If nothing happened still, try promoting the operation. 1114207618Srdivacky if (RV.getNode() == 0) { 1115207618Srdivacky switch (N->getOpcode()) { 1116207618Srdivacky default: break; 1117207618Srdivacky case ISD::ADD: 1118207618Srdivacky case ISD::SUB: 1119207618Srdivacky case ISD::MUL: 1120207618Srdivacky case ISD::AND: 1121207618Srdivacky case ISD::OR: 1122207618Srdivacky case ISD::XOR: 1123207618Srdivacky RV = PromoteIntBinOp(SDValue(N, 0)); 1124207618Srdivacky break; 1125207618Srdivacky case ISD::SHL: 1126207618Srdivacky case ISD::SRA: 1127207618Srdivacky case ISD::SRL: 1128207618Srdivacky RV = PromoteIntShiftOp(SDValue(N, 0)); 1129207618Srdivacky break; 1130207618Srdivacky case ISD::SIGN_EXTEND: 1131207618Srdivacky case ISD::ZERO_EXTEND: 1132207618Srdivacky case ISD::ANY_EXTEND: 1133207618Srdivacky RV = PromoteExtend(SDValue(N, 0)); 1134207618Srdivacky break; 1135207618Srdivacky case ISD::LOAD: 1136207618Srdivacky if (PromoteLoad(SDValue(N, 0))) 1137207618Srdivacky RV = SDValue(N, 0); 1138207618Srdivacky break; 1139207618Srdivacky } 1140207618Srdivacky } 1141207618Srdivacky 1142193323Sed // If N is a commutative binary node, try commuting it to enable more 1143193323Sed // sdisel CSE. 1144193323Sed if (RV.getNode() == 0 && 1145193323Sed SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1146193323Sed N->getNumValues() == 1) { 1147193323Sed SDValue N0 = N->getOperand(0); 1148193323Sed SDValue N1 = N->getOperand(1); 1149193323Sed 1150193323Sed // Constant operands are canonicalized to RHS. 1151193323Sed if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1152193323Sed SDValue Ops[] = { N1, N0 }; 1153193323Sed SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1154193323Sed Ops, 2); 1155193323Sed if (CSENode) 1156193323Sed return SDValue(CSENode, 0); 1157193323Sed } 1158193323Sed } 1159193323Sed 1160193323Sed return RV; 1161193323Sed} 1162193323Sed 1163193323Sed/// getInputChainForNode - Given a node, return its input chain if it has one, 1164193323Sed/// otherwise return a null sd operand. 1165193323Sedstatic SDValue getInputChainForNode(SDNode *N) { 1166193323Sed if (unsigned NumOps = N->getNumOperands()) { 1167193323Sed if (N->getOperand(0).getValueType() == MVT::Other) 1168193323Sed return N->getOperand(0); 1169193323Sed else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1170193323Sed return N->getOperand(NumOps-1); 1171193323Sed for (unsigned i = 1; i < NumOps-1; ++i) 1172193323Sed if (N->getOperand(i).getValueType() == MVT::Other) 1173193323Sed return N->getOperand(i); 1174193323Sed } 1175193323Sed return SDValue(); 1176193323Sed} 1177193323Sed 1178193323SedSDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1179193323Sed // If N has two operands, where one has an input chain equal to the other, 1180193323Sed // the 'other' chain is redundant. 1181193323Sed if (N->getNumOperands() == 2) { 1182193323Sed if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1183193323Sed return N->getOperand(0); 1184193323Sed if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1185193323Sed return N->getOperand(1); 1186193323Sed } 1187193323Sed 1188193323Sed SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1189193323Sed SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1190193323Sed SmallPtrSet<SDNode*, 16> SeenOps; 1191193323Sed bool Changed = false; // If we should replace this token factor. 1192193323Sed 1193193323Sed // Start out with this token factor. 1194193323Sed TFs.push_back(N); 1195193323Sed 1196193323Sed // Iterate through token factors. The TFs grows when new token factors are 1197193323Sed // encountered. 1198193323Sed for (unsigned i = 0; i < TFs.size(); ++i) { 1199193323Sed SDNode *TF = TFs[i]; 1200193323Sed 1201193323Sed // Check each of the operands. 1202193323Sed for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1203193323Sed SDValue Op = TF->getOperand(i); 1204193323Sed 1205193323Sed switch (Op.getOpcode()) { 1206193323Sed case ISD::EntryToken: 1207193323Sed // Entry tokens don't need to be added to the list. They are 1208193323Sed // rededundant. 1209193323Sed Changed = true; 1210193323Sed break; 1211193323Sed 1212193323Sed case ISD::TokenFactor: 1213198090Srdivacky if (Op.hasOneUse() && 1214193323Sed std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1215193323Sed // Queue up for processing. 1216193323Sed TFs.push_back(Op.getNode()); 1217193323Sed // Clean up in case the token factor is removed. 1218193323Sed AddToWorkList(Op.getNode()); 1219193323Sed Changed = true; 1220193323Sed break; 1221193323Sed } 1222193323Sed // Fall thru 1223193323Sed 1224193323Sed default: 1225193323Sed // Only add if it isn't already in the list. 1226193323Sed if (SeenOps.insert(Op.getNode())) 1227193323Sed Ops.push_back(Op); 1228193323Sed else 1229193323Sed Changed = true; 1230193323Sed break; 1231193323Sed } 1232193323Sed } 1233193323Sed } 1234218893Sdim 1235193323Sed SDValue Result; 1236193323Sed 1237193323Sed // If we've change things around then replace token factor. 1238193323Sed if (Changed) { 1239193323Sed if (Ops.empty()) { 1240193323Sed // The entry token is the only possible outcome. 1241193323Sed Result = DAG.getEntryNode(); 1242193323Sed } else { 1243193323Sed // New and improved token factor. 1244193323Sed Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1245193323Sed MVT::Other, &Ops[0], Ops.size()); 1246193323Sed } 1247193323Sed 1248193323Sed // Don't add users to work list. 1249193323Sed return CombineTo(N, Result, false); 1250193323Sed } 1251193323Sed 1252193323Sed return Result; 1253193323Sed} 1254193323Sed 1255193323Sed/// MERGE_VALUES can always be eliminated. 1256193323SedSDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1257193323Sed WorkListRemover DeadNodes(*this); 1258198090Srdivacky // Replacing results may cause a different MERGE_VALUES to suddenly 1259198090Srdivacky // be CSE'd with N, and carry its uses with it. Iterate until no 1260198090Srdivacky // uses remain, to ensure that the node can be safely deleted. 1261198090Srdivacky do { 1262198090Srdivacky for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1263198090Srdivacky DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1264198090Srdivacky &DeadNodes); 1265198090Srdivacky } while (!N->use_empty()); 1266193323Sed removeFromWorkList(N); 1267193323Sed DAG.DeleteNode(N); 1268193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 1269193323Sed} 1270193323Sed 1271193323Sedstatic 1272193323SedSDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1273193323Sed SelectionDAG &DAG) { 1274198090Srdivacky EVT VT = N0.getValueType(); 1275193323Sed SDValue N00 = N0.getOperand(0); 1276193323Sed SDValue N01 = N0.getOperand(1); 1277193323Sed ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1278193323Sed 1279193323Sed if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1280193323Sed isa<ConstantSDNode>(N00.getOperand(1))) { 1281193323Sed // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1282193323Sed N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1283193323Sed DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1284193323Sed N00.getOperand(0), N01), 1285193323Sed DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1286193323Sed N00.getOperand(1), N01)); 1287193323Sed return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1288193323Sed } 1289193323Sed 1290193323Sed return SDValue(); 1291193323Sed} 1292193323Sed 1293193323SedSDValue DAGCombiner::visitADD(SDNode *N) { 1294193323Sed SDValue N0 = N->getOperand(0); 1295193323Sed SDValue N1 = N->getOperand(1); 1296193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1297193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1298198090Srdivacky EVT VT = N0.getValueType(); 1299193323Sed 1300193323Sed // fold vector ops 1301193323Sed if (VT.isVector()) { 1302193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1303193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1304193323Sed } 1305193323Sed 1306193323Sed // fold (add x, undef) -> undef 1307193323Sed if (N0.getOpcode() == ISD::UNDEF) 1308193323Sed return N0; 1309193323Sed if (N1.getOpcode() == ISD::UNDEF) 1310193323Sed return N1; 1311193323Sed // fold (add c1, c2) -> c1+c2 1312193323Sed if (N0C && N1C) 1313193323Sed return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1314193323Sed // canonicalize constant to RHS 1315193323Sed if (N0C && !N1C) 1316193323Sed return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1317193323Sed // fold (add x, 0) -> x 1318193323Sed if (N1C && N1C->isNullValue()) 1319193323Sed return N0; 1320193323Sed // fold (add Sym, c) -> Sym+c 1321193323Sed if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1322193323Sed if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1323193323Sed GA->getOpcode() == ISD::GlobalAddress) 1324210299Sed return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1325193323Sed GA->getOffset() + 1326193323Sed (uint64_t)N1C->getSExtValue()); 1327193323Sed // fold ((c1-A)+c2) -> (c1+c2)-A 1328193323Sed if (N1C && N0.getOpcode() == ISD::SUB) 1329193323Sed if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1330193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1331193323Sed DAG.getConstant(N1C->getAPIntValue()+ 1332193323Sed N0C->getAPIntValue(), VT), 1333193323Sed N0.getOperand(1)); 1334193323Sed // reassociate add 1335193323Sed SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1336193323Sed if (RADD.getNode() != 0) 1337193323Sed return RADD; 1338193323Sed // fold ((0-A) + B) -> B-A 1339193323Sed if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1340193323Sed cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1341193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1342193323Sed // fold (A + (0-B)) -> A-B 1343193323Sed if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1344193323Sed cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1345193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1346193323Sed // fold (A+(B-A)) -> B 1347193323Sed if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1348193323Sed return N1.getOperand(0); 1349193323Sed // fold ((B-A)+A) -> B 1350193323Sed if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1351193323Sed return N0.getOperand(0); 1352193323Sed // fold (A+(B-(A+C))) to (B-C) 1353193323Sed if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1354193323Sed N0 == N1.getOperand(1).getOperand(0)) 1355193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1356193323Sed N1.getOperand(1).getOperand(1)); 1357193323Sed // fold (A+(B-(C+A))) to (B-C) 1358193323Sed if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1359193323Sed N0 == N1.getOperand(1).getOperand(1)) 1360193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1361193323Sed N1.getOperand(1).getOperand(0)); 1362193323Sed // fold (A+((B-A)+or-C)) to (B+or-C) 1363193323Sed if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1364193323Sed N1.getOperand(0).getOpcode() == ISD::SUB && 1365193323Sed N0 == N1.getOperand(0).getOperand(1)) 1366193323Sed return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1367193323Sed N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1368193323Sed 1369193323Sed // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1370193323Sed if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1371193323Sed SDValue N00 = N0.getOperand(0); 1372193323Sed SDValue N01 = N0.getOperand(1); 1373193323Sed SDValue N10 = N1.getOperand(0); 1374193323Sed SDValue N11 = N1.getOperand(1); 1375193323Sed 1376193323Sed if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1377193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1378193323Sed DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1379193323Sed DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1380193323Sed } 1381193323Sed 1382193323Sed if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1383193323Sed return SDValue(N, 0); 1384193323Sed 1385193323Sed // fold (a+b) -> (a|b) iff a and b share no bits. 1386193323Sed if (VT.isInteger() && !VT.isVector()) { 1387193323Sed APInt LHSZero, LHSOne; 1388193323Sed APInt RHSZero, RHSOne; 1389204642Srdivacky APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1390193323Sed DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1391193323Sed 1392193323Sed if (LHSZero.getBoolValue()) { 1393193323Sed DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1394193323Sed 1395193323Sed // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1396193323Sed // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1397193323Sed if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1398193323Sed (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1399193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1400193323Sed } 1401193323Sed } 1402193323Sed 1403193323Sed // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1404193323Sed if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1405193323Sed SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1406193323Sed if (Result.getNode()) return Result; 1407193323Sed } 1408193323Sed if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1409193323Sed SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1410193323Sed if (Result.getNode()) return Result; 1411193323Sed } 1412193323Sed 1413202878Srdivacky // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1414202878Srdivacky if (N1.getOpcode() == ISD::SHL && 1415202878Srdivacky N1.getOperand(0).getOpcode() == ISD::SUB) 1416202878Srdivacky if (ConstantSDNode *C = 1417202878Srdivacky dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1418202878Srdivacky if (C->getAPIntValue() == 0) 1419202878Srdivacky return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1420202878Srdivacky DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1421202878Srdivacky N1.getOperand(0).getOperand(1), 1422202878Srdivacky N1.getOperand(1))); 1423202878Srdivacky if (N0.getOpcode() == ISD::SHL && 1424202878Srdivacky N0.getOperand(0).getOpcode() == ISD::SUB) 1425202878Srdivacky if (ConstantSDNode *C = 1426202878Srdivacky dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1427202878Srdivacky if (C->getAPIntValue() == 0) 1428202878Srdivacky return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1429202878Srdivacky DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1430202878Srdivacky N0.getOperand(0).getOperand(1), 1431202878Srdivacky N0.getOperand(1))); 1432202878Srdivacky 1433218893Sdim if (N1.getOpcode() == ISD::AND) { 1434218893Sdim SDValue AndOp0 = N1.getOperand(0); 1435218893Sdim ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1436218893Sdim unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1437218893Sdim unsigned DestBits = VT.getScalarType().getSizeInBits(); 1438218893Sdim 1439218893Sdim // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1440218893Sdim // and similar xforms where the inner op is either ~0 or 0. 1441218893Sdim if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1442218893Sdim DebugLoc DL = N->getDebugLoc(); 1443218893Sdim return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1444218893Sdim } 1445218893Sdim } 1446218893Sdim 1447218893Sdim // add (sext i1), X -> sub X, (zext i1) 1448218893Sdim if (N0.getOpcode() == ISD::SIGN_EXTEND && 1449218893Sdim N0.getOperand(0).getValueType() == MVT::i1 && 1450218893Sdim !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1451218893Sdim DebugLoc DL = N->getDebugLoc(); 1452218893Sdim SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1453218893Sdim return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1454218893Sdim } 1455218893Sdim 1456193323Sed return SDValue(); 1457193323Sed} 1458193323Sed 1459193323SedSDValue DAGCombiner::visitADDC(SDNode *N) { 1460193323Sed SDValue N0 = N->getOperand(0); 1461193323Sed SDValue N1 = N->getOperand(1); 1462193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1463193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1464198090Srdivacky EVT VT = N0.getValueType(); 1465193323Sed 1466193323Sed // If the flag result is dead, turn this into an ADD. 1467193323Sed if (N->hasNUsesOfValue(0, 1)) 1468193323Sed return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1469193323Sed DAG.getNode(ISD::CARRY_FALSE, 1470218893Sdim N->getDebugLoc(), MVT::Glue)); 1471193323Sed 1472193323Sed // canonicalize constant to RHS. 1473193323Sed if (N0C && !N1C) 1474193323Sed return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1475193323Sed 1476193323Sed // fold (addc x, 0) -> x + no carry out 1477193323Sed if (N1C && N1C->isNullValue()) 1478193323Sed return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1479218893Sdim N->getDebugLoc(), MVT::Glue)); 1480193323Sed 1481193323Sed // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1482193323Sed APInt LHSZero, LHSOne; 1483193323Sed APInt RHSZero, RHSOne; 1484204642Srdivacky APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1485193323Sed DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1486193323Sed 1487193323Sed if (LHSZero.getBoolValue()) { 1488193323Sed DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1489193323Sed 1490193323Sed // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1491193323Sed // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1492193323Sed if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1493193323Sed (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1494193323Sed return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1495193323Sed DAG.getNode(ISD::CARRY_FALSE, 1496218893Sdim N->getDebugLoc(), MVT::Glue)); 1497193323Sed } 1498193323Sed 1499193323Sed return SDValue(); 1500193323Sed} 1501193323Sed 1502193323SedSDValue DAGCombiner::visitADDE(SDNode *N) { 1503193323Sed SDValue N0 = N->getOperand(0); 1504193323Sed SDValue N1 = N->getOperand(1); 1505193323Sed SDValue CarryIn = N->getOperand(2); 1506193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1507193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1508193323Sed 1509193323Sed // canonicalize constant to RHS 1510193323Sed if (N0C && !N1C) 1511193323Sed return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1512193323Sed N1, N0, CarryIn); 1513193323Sed 1514193323Sed // fold (adde x, y, false) -> (addc x, y) 1515193323Sed if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1516193323Sed return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1517193323Sed 1518193323Sed return SDValue(); 1519193323Sed} 1520193323Sed 1521218893Sdim// Since it may not be valid to emit a fold to zero for vector initializers 1522218893Sdim// check if we can before folding. 1523218893Sdimstatic SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1524219077Sdim SelectionDAG &DAG, bool LegalOperations) { 1525218893Sdim if (!VT.isVector()) { 1526218893Sdim return DAG.getConstant(0, VT); 1527218893Sdim } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1528218893Sdim // Produce a vector of zeros. 1529218893Sdim SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1530218893Sdim std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1531218893Sdim return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1532218893Sdim &Ops[0], Ops.size()); 1533218893Sdim } 1534218893Sdim return SDValue(); 1535218893Sdim} 1536218893Sdim 1537193323SedSDValue DAGCombiner::visitSUB(SDNode *N) { 1538193323Sed SDValue N0 = N->getOperand(0); 1539193323Sed SDValue N1 = N->getOperand(1); 1540193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1541193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1542198090Srdivacky EVT VT = N0.getValueType(); 1543193323Sed 1544193323Sed // fold vector ops 1545193323Sed if (VT.isVector()) { 1546193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1547193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1548193323Sed } 1549193323Sed 1550193323Sed // fold (sub x, x) -> 0 1551218893Sdim // FIXME: Refactor this and xor and other similar operations together. 1552193323Sed if (N0 == N1) 1553218893Sdim return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1554193323Sed // fold (sub c1, c2) -> c1-c2 1555193323Sed if (N0C && N1C) 1556193323Sed return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1557193323Sed // fold (sub x, c) -> (add x, -c) 1558193323Sed if (N1C) 1559193323Sed return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1560193323Sed DAG.getConstant(-N1C->getAPIntValue(), VT)); 1561202878Srdivacky // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1562202878Srdivacky if (N0C && N0C->isAllOnesValue()) 1563202878Srdivacky return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1564218893Sdim // fold A-(A-B) -> B 1565218893Sdim if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1566218893Sdim return N1.getOperand(1); 1567193323Sed // fold (A+B)-A -> B 1568193323Sed if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1569193323Sed return N0.getOperand(1); 1570193323Sed // fold (A+B)-B -> A 1571193323Sed if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1572193323Sed return N0.getOperand(0); 1573193323Sed // fold ((A+(B+or-C))-B) -> A+or-C 1574193323Sed if (N0.getOpcode() == ISD::ADD && 1575193323Sed (N0.getOperand(1).getOpcode() == ISD::SUB || 1576193323Sed N0.getOperand(1).getOpcode() == ISD::ADD) && 1577193323Sed N0.getOperand(1).getOperand(0) == N1) 1578193323Sed return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1579193323Sed N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1580193323Sed // fold ((A+(C+B))-B) -> A+C 1581193323Sed if (N0.getOpcode() == ISD::ADD && 1582193323Sed N0.getOperand(1).getOpcode() == ISD::ADD && 1583193323Sed N0.getOperand(1).getOperand(1) == N1) 1584193323Sed return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1585193323Sed N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1586193323Sed // fold ((A-(B-C))-C) -> A-B 1587193323Sed if (N0.getOpcode() == ISD::SUB && 1588193323Sed N0.getOperand(1).getOpcode() == ISD::SUB && 1589193323Sed N0.getOperand(1).getOperand(1) == N1) 1590193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1591193323Sed N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1592193323Sed 1593193323Sed // If either operand of a sub is undef, the result is undef 1594193323Sed if (N0.getOpcode() == ISD::UNDEF) 1595193323Sed return N0; 1596193323Sed if (N1.getOpcode() == ISD::UNDEF) 1597193323Sed return N1; 1598193323Sed 1599193323Sed // If the relocation model supports it, consider symbol offsets. 1600193323Sed if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1601193323Sed if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1602193323Sed // fold (sub Sym, c) -> Sym-c 1603193323Sed if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1604210299Sed return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1605193323Sed GA->getOffset() - 1606193323Sed (uint64_t)N1C->getSExtValue()); 1607193323Sed // fold (sub Sym+c1, Sym+c2) -> c1-c2 1608193323Sed if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1609193323Sed if (GA->getGlobal() == GB->getGlobal()) 1610193323Sed return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1611193323Sed VT); 1612193323Sed } 1613193323Sed 1614193323Sed return SDValue(); 1615193323Sed} 1616193323Sed 1617193323SedSDValue DAGCombiner::visitMUL(SDNode *N) { 1618193323Sed SDValue N0 = N->getOperand(0); 1619193323Sed SDValue N1 = N->getOperand(1); 1620193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1621193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1622198090Srdivacky EVT VT = N0.getValueType(); 1623193323Sed 1624193323Sed // fold vector ops 1625193323Sed if (VT.isVector()) { 1626193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1627193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1628193323Sed } 1629193323Sed 1630193323Sed // fold (mul x, undef) -> 0 1631193323Sed if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1632193323Sed return DAG.getConstant(0, VT); 1633193323Sed // fold (mul c1, c2) -> c1*c2 1634193323Sed if (N0C && N1C) 1635193323Sed return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1636193323Sed // canonicalize constant to RHS 1637193323Sed if (N0C && !N1C) 1638193323Sed return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1639193323Sed // fold (mul x, 0) -> 0 1640193323Sed if (N1C && N1C->isNullValue()) 1641193323Sed return N1; 1642193323Sed // fold (mul x, -1) -> 0-x 1643193323Sed if (N1C && N1C->isAllOnesValue()) 1644193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1645193323Sed DAG.getConstant(0, VT), N0); 1646193323Sed // fold (mul x, (1 << c)) -> x << c 1647193323Sed if (N1C && N1C->getAPIntValue().isPowerOf2()) 1648193323Sed return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1649193323Sed DAG.getConstant(N1C->getAPIntValue().logBase2(), 1650219077Sdim getShiftAmountTy(N0.getValueType()))); 1651193323Sed // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1652193323Sed if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1653193323Sed unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1654193323Sed // FIXME: If the input is something that is easily negated (e.g. a 1655193323Sed // single-use add), we should put the negate there. 1656193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1657193323Sed DAG.getConstant(0, VT), 1658193323Sed DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1659219077Sdim DAG.getConstant(Log2Val, 1660219077Sdim getShiftAmountTy(N0.getValueType())))); 1661193323Sed } 1662193323Sed // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1663193323Sed if (N1C && N0.getOpcode() == ISD::SHL && 1664193323Sed isa<ConstantSDNode>(N0.getOperand(1))) { 1665193323Sed SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1666193323Sed N1, N0.getOperand(1)); 1667193323Sed AddToWorkList(C3.getNode()); 1668193323Sed return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1669193323Sed N0.getOperand(0), C3); 1670193323Sed } 1671193323Sed 1672193323Sed // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1673193323Sed // use. 1674193323Sed { 1675193323Sed SDValue Sh(0,0), Y(0,0); 1676193323Sed // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1677193323Sed if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1678193323Sed N0.getNode()->hasOneUse()) { 1679193323Sed Sh = N0; Y = N1; 1680193323Sed } else if (N1.getOpcode() == ISD::SHL && 1681193323Sed isa<ConstantSDNode>(N1.getOperand(1)) && 1682193323Sed N1.getNode()->hasOneUse()) { 1683193323Sed Sh = N1; Y = N0; 1684193323Sed } 1685193323Sed 1686193323Sed if (Sh.getNode()) { 1687193323Sed SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1688193323Sed Sh.getOperand(0), Y); 1689193323Sed return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1690193323Sed Mul, Sh.getOperand(1)); 1691193323Sed } 1692193323Sed } 1693193323Sed 1694193323Sed // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1695193323Sed if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1696193323Sed isa<ConstantSDNode>(N0.getOperand(1))) 1697193323Sed return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1698193323Sed DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1699193323Sed N0.getOperand(0), N1), 1700193323Sed DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1701193323Sed N0.getOperand(1), N1)); 1702193323Sed 1703193323Sed // reassociate mul 1704193323Sed SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1705193323Sed if (RMUL.getNode() != 0) 1706193323Sed return RMUL; 1707193323Sed 1708193323Sed return SDValue(); 1709193323Sed} 1710193323Sed 1711193323SedSDValue DAGCombiner::visitSDIV(SDNode *N) { 1712193323Sed SDValue N0 = N->getOperand(0); 1713193323Sed SDValue N1 = N->getOperand(1); 1714193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1715193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1716198090Srdivacky EVT VT = N->getValueType(0); 1717193323Sed 1718193323Sed // fold vector ops 1719193323Sed if (VT.isVector()) { 1720193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1721193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1722193323Sed } 1723193323Sed 1724193323Sed // fold (sdiv c1, c2) -> c1/c2 1725193323Sed if (N0C && N1C && !N1C->isNullValue()) 1726193323Sed return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1727193323Sed // fold (sdiv X, 1) -> X 1728193323Sed if (N1C && N1C->getSExtValue() == 1LL) 1729193323Sed return N0; 1730193323Sed // fold (sdiv X, -1) -> 0-X 1731193323Sed if (N1C && N1C->isAllOnesValue()) 1732193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1733193323Sed DAG.getConstant(0, VT), N0); 1734193323Sed // If we know the sign bits of both operands are zero, strength reduce to a 1735193323Sed // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1736193323Sed if (!VT.isVector()) { 1737193323Sed if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1738193323Sed return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1739193323Sed N0, N1); 1740193323Sed } 1741193323Sed // fold (sdiv X, pow2) -> simple ops after legalize 1742193323Sed if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1743193323Sed (isPowerOf2_64(N1C->getSExtValue()) || 1744193323Sed isPowerOf2_64(-N1C->getSExtValue()))) { 1745193323Sed // If dividing by powers of two is cheap, then don't perform the following 1746193323Sed // fold. 1747193323Sed if (TLI.isPow2DivCheap()) 1748193323Sed return SDValue(); 1749193323Sed 1750193323Sed int64_t pow2 = N1C->getSExtValue(); 1751193323Sed int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1752193323Sed unsigned lg2 = Log2_64(abs2); 1753193323Sed 1754193323Sed // Splat the sign bit into the register 1755193323Sed SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1756193323Sed DAG.getConstant(VT.getSizeInBits()-1, 1757219077Sdim getShiftAmountTy(N0.getValueType()))); 1758193323Sed AddToWorkList(SGN.getNode()); 1759193323Sed 1760193323Sed // Add (N0 < 0) ? abs2 - 1 : 0; 1761193323Sed SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1762193323Sed DAG.getConstant(VT.getSizeInBits() - lg2, 1763219077Sdim getShiftAmountTy(SGN.getValueType()))); 1764193323Sed SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1765193323Sed AddToWorkList(SRL.getNode()); 1766193323Sed AddToWorkList(ADD.getNode()); // Divide by pow2 1767193323Sed SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1768219077Sdim DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1769193323Sed 1770193323Sed // If we're dividing by a positive value, we're done. Otherwise, we must 1771193323Sed // negate the result. 1772193323Sed if (pow2 > 0) 1773193323Sed return SRA; 1774193323Sed 1775193323Sed AddToWorkList(SRA.getNode()); 1776193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1777193323Sed DAG.getConstant(0, VT), SRA); 1778193323Sed } 1779193323Sed 1780193323Sed // if integer divide is expensive and we satisfy the requirements, emit an 1781193323Sed // alternate sequence. 1782193323Sed if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1783193323Sed !TLI.isIntDivCheap()) { 1784193323Sed SDValue Op = BuildSDIV(N); 1785193323Sed if (Op.getNode()) return Op; 1786193323Sed } 1787193323Sed 1788193323Sed // undef / X -> 0 1789193323Sed if (N0.getOpcode() == ISD::UNDEF) 1790193323Sed return DAG.getConstant(0, VT); 1791193323Sed // X / undef -> undef 1792193323Sed if (N1.getOpcode() == ISD::UNDEF) 1793193323Sed return N1; 1794193323Sed 1795193323Sed return SDValue(); 1796193323Sed} 1797193323Sed 1798193323SedSDValue DAGCombiner::visitUDIV(SDNode *N) { 1799193323Sed SDValue N0 = N->getOperand(0); 1800193323Sed SDValue N1 = N->getOperand(1); 1801193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1802193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1803198090Srdivacky EVT VT = N->getValueType(0); 1804193323Sed 1805193323Sed // fold vector ops 1806193323Sed if (VT.isVector()) { 1807193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1808193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1809193323Sed } 1810193323Sed 1811193323Sed // fold (udiv c1, c2) -> c1/c2 1812193323Sed if (N0C && N1C && !N1C->isNullValue()) 1813193323Sed return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1814193323Sed // fold (udiv x, (1 << c)) -> x >>u c 1815193323Sed if (N1C && N1C->getAPIntValue().isPowerOf2()) 1816193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1817193323Sed DAG.getConstant(N1C->getAPIntValue().logBase2(), 1818219077Sdim getShiftAmountTy(N0.getValueType()))); 1819193323Sed // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1820193323Sed if (N1.getOpcode() == ISD::SHL) { 1821193323Sed if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1822193323Sed if (SHC->getAPIntValue().isPowerOf2()) { 1823198090Srdivacky EVT ADDVT = N1.getOperand(1).getValueType(); 1824193323Sed SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1825193323Sed N1.getOperand(1), 1826193323Sed DAG.getConstant(SHC->getAPIntValue() 1827193323Sed .logBase2(), 1828193323Sed ADDVT)); 1829193323Sed AddToWorkList(Add.getNode()); 1830193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1831193323Sed } 1832193323Sed } 1833193323Sed } 1834193323Sed // fold (udiv x, c) -> alternate 1835193323Sed if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1836193323Sed SDValue Op = BuildUDIV(N); 1837193323Sed if (Op.getNode()) return Op; 1838193323Sed } 1839193323Sed 1840193323Sed // undef / X -> 0 1841193323Sed if (N0.getOpcode() == ISD::UNDEF) 1842193323Sed return DAG.getConstant(0, VT); 1843193323Sed // X / undef -> undef 1844193323Sed if (N1.getOpcode() == ISD::UNDEF) 1845193323Sed return N1; 1846193323Sed 1847193323Sed return SDValue(); 1848193323Sed} 1849193323Sed 1850193323SedSDValue DAGCombiner::visitSREM(SDNode *N) { 1851193323Sed SDValue N0 = N->getOperand(0); 1852193323Sed SDValue N1 = N->getOperand(1); 1853193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1854193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1855198090Srdivacky EVT VT = N->getValueType(0); 1856193323Sed 1857193323Sed // fold (srem c1, c2) -> c1%c2 1858193323Sed if (N0C && N1C && !N1C->isNullValue()) 1859193323Sed return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1860193323Sed // If we know the sign bits of both operands are zero, strength reduce to a 1861193323Sed // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1862193323Sed if (!VT.isVector()) { 1863193323Sed if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1864193323Sed return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1865193323Sed } 1866193323Sed 1867193323Sed // If X/C can be simplified by the division-by-constant logic, lower 1868193323Sed // X%C to the equivalent of X-X/C*C. 1869193323Sed if (N1C && !N1C->isNullValue()) { 1870193323Sed SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1871193323Sed AddToWorkList(Div.getNode()); 1872193323Sed SDValue OptimizedDiv = combine(Div.getNode()); 1873193323Sed if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1874193323Sed SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1875193323Sed OptimizedDiv, N1); 1876193323Sed SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1877193323Sed AddToWorkList(Mul.getNode()); 1878193323Sed return Sub; 1879193323Sed } 1880193323Sed } 1881193323Sed 1882193323Sed // undef % X -> 0 1883193323Sed if (N0.getOpcode() == ISD::UNDEF) 1884193323Sed return DAG.getConstant(0, VT); 1885193323Sed // X % undef -> undef 1886193323Sed if (N1.getOpcode() == ISD::UNDEF) 1887193323Sed return N1; 1888193323Sed 1889193323Sed return SDValue(); 1890193323Sed} 1891193323Sed 1892193323SedSDValue DAGCombiner::visitUREM(SDNode *N) { 1893193323Sed SDValue N0 = N->getOperand(0); 1894193323Sed SDValue N1 = N->getOperand(1); 1895193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1896193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1897198090Srdivacky EVT VT = N->getValueType(0); 1898193323Sed 1899193323Sed // fold (urem c1, c2) -> c1%c2 1900193323Sed if (N0C && N1C && !N1C->isNullValue()) 1901193323Sed return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1902193323Sed // fold (urem x, pow2) -> (and x, pow2-1) 1903193323Sed if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1904193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1905193323Sed DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1906193323Sed // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1907193323Sed if (N1.getOpcode() == ISD::SHL) { 1908193323Sed if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1909193323Sed if (SHC->getAPIntValue().isPowerOf2()) { 1910193323Sed SDValue Add = 1911193323Sed DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1912193323Sed DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1913193323Sed VT)); 1914193323Sed AddToWorkList(Add.getNode()); 1915193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1916193323Sed } 1917193323Sed } 1918193323Sed } 1919193323Sed 1920193323Sed // If X/C can be simplified by the division-by-constant logic, lower 1921193323Sed // X%C to the equivalent of X-X/C*C. 1922193323Sed if (N1C && !N1C->isNullValue()) { 1923193323Sed SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1924193323Sed AddToWorkList(Div.getNode()); 1925193323Sed SDValue OptimizedDiv = combine(Div.getNode()); 1926193323Sed if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1927193323Sed SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1928193323Sed OptimizedDiv, N1); 1929193323Sed SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1930193323Sed AddToWorkList(Mul.getNode()); 1931193323Sed return Sub; 1932193323Sed } 1933193323Sed } 1934193323Sed 1935193323Sed // undef % X -> 0 1936193323Sed if (N0.getOpcode() == ISD::UNDEF) 1937193323Sed return DAG.getConstant(0, VT); 1938193323Sed // X % undef -> undef 1939193323Sed if (N1.getOpcode() == ISD::UNDEF) 1940193323Sed return N1; 1941193323Sed 1942193323Sed return SDValue(); 1943193323Sed} 1944193323Sed 1945193323SedSDValue DAGCombiner::visitMULHS(SDNode *N) { 1946193323Sed SDValue N0 = N->getOperand(0); 1947193323Sed SDValue N1 = N->getOperand(1); 1948193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1949198090Srdivacky EVT VT = N->getValueType(0); 1950218893Sdim DebugLoc DL = N->getDebugLoc(); 1951193323Sed 1952193323Sed // fold (mulhs x, 0) -> 0 1953193323Sed if (N1C && N1C->isNullValue()) 1954193323Sed return N1; 1955193323Sed // fold (mulhs x, 1) -> (sra x, size(x)-1) 1956193323Sed if (N1C && N1C->getAPIntValue() == 1) 1957193323Sed return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1958193323Sed DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1959219077Sdim getShiftAmountTy(N0.getValueType()))); 1960193323Sed // fold (mulhs x, undef) -> 0 1961193323Sed if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1962193323Sed return DAG.getConstant(0, VT); 1963193323Sed 1964218893Sdim // If the type twice as wide is legal, transform the mulhs to a wider multiply 1965218893Sdim // plus a shift. 1966218893Sdim if (VT.isSimple() && !VT.isVector()) { 1967218893Sdim MVT Simple = VT.getSimpleVT(); 1968218893Sdim unsigned SimpleSize = Simple.getSizeInBits(); 1969218893Sdim EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 1970218893Sdim if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 1971218893Sdim N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 1972218893Sdim N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 1973218893Sdim N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 1974218893Sdim N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 1975219077Sdim DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 1976218893Sdim return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 1977218893Sdim } 1978218893Sdim } 1979219077Sdim 1980193323Sed return SDValue(); 1981193323Sed} 1982193323Sed 1983193323SedSDValue DAGCombiner::visitMULHU(SDNode *N) { 1984193323Sed SDValue N0 = N->getOperand(0); 1985193323Sed SDValue N1 = N->getOperand(1); 1986193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1987198090Srdivacky EVT VT = N->getValueType(0); 1988218893Sdim DebugLoc DL = N->getDebugLoc(); 1989193323Sed 1990193323Sed // fold (mulhu x, 0) -> 0 1991193323Sed if (N1C && N1C->isNullValue()) 1992193323Sed return N1; 1993193323Sed // fold (mulhu x, 1) -> 0 1994193323Sed if (N1C && N1C->getAPIntValue() == 1) 1995193323Sed return DAG.getConstant(0, N0.getValueType()); 1996193323Sed // fold (mulhu x, undef) -> 0 1997193323Sed if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1998193323Sed return DAG.getConstant(0, VT); 1999193323Sed 2000218893Sdim // If the type twice as wide is legal, transform the mulhu to a wider multiply 2001218893Sdim // plus a shift. 2002218893Sdim if (VT.isSimple() && !VT.isVector()) { 2003218893Sdim MVT Simple = VT.getSimpleVT(); 2004218893Sdim unsigned SimpleSize = Simple.getSizeInBits(); 2005218893Sdim EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2006218893Sdim if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2007218893Sdim N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2008218893Sdim N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2009218893Sdim N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2010218893Sdim N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2011219077Sdim DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2012218893Sdim return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2013218893Sdim } 2014218893Sdim } 2015219077Sdim 2016193323Sed return SDValue(); 2017193323Sed} 2018193323Sed 2019193323Sed/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2020193323Sed/// compute two values. LoOp and HiOp give the opcodes for the two computations 2021193323Sed/// that are being performed. Return true if a simplification was made. 2022193323Sed/// 2023193323SedSDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2024193323Sed unsigned HiOp) { 2025193323Sed // If the high half is not needed, just compute the low half. 2026193323Sed bool HiExists = N->hasAnyUseOfValue(1); 2027193323Sed if (!HiExists && 2028193323Sed (!LegalOperations || 2029193323Sed TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2030193323Sed SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2031193323Sed N->op_begin(), N->getNumOperands()); 2032193323Sed return CombineTo(N, Res, Res); 2033193323Sed } 2034193323Sed 2035193323Sed // If the low half is not needed, just compute the high half. 2036193323Sed bool LoExists = N->hasAnyUseOfValue(0); 2037193323Sed if (!LoExists && 2038193323Sed (!LegalOperations || 2039193323Sed TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2040193323Sed SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2041193323Sed N->op_begin(), N->getNumOperands()); 2042193323Sed return CombineTo(N, Res, Res); 2043193323Sed } 2044193323Sed 2045193323Sed // If both halves are used, return as it is. 2046193323Sed if (LoExists && HiExists) 2047193323Sed return SDValue(); 2048193323Sed 2049193323Sed // If the two computed results can be simplified separately, separate them. 2050193323Sed if (LoExists) { 2051193323Sed SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2052193323Sed N->op_begin(), N->getNumOperands()); 2053193323Sed AddToWorkList(Lo.getNode()); 2054193323Sed SDValue LoOpt = combine(Lo.getNode()); 2055193323Sed if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2056193323Sed (!LegalOperations || 2057193323Sed TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2058193323Sed return CombineTo(N, LoOpt, LoOpt); 2059193323Sed } 2060193323Sed 2061193323Sed if (HiExists) { 2062193323Sed SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2063193323Sed N->op_begin(), N->getNumOperands()); 2064193323Sed AddToWorkList(Hi.getNode()); 2065193323Sed SDValue HiOpt = combine(Hi.getNode()); 2066193323Sed if (HiOpt.getNode() && HiOpt != Hi && 2067193323Sed (!LegalOperations || 2068193323Sed TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2069193323Sed return CombineTo(N, HiOpt, HiOpt); 2070193323Sed } 2071193323Sed 2072193323Sed return SDValue(); 2073193323Sed} 2074193323Sed 2075193323SedSDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2076193323Sed SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2077193323Sed if (Res.getNode()) return Res; 2078193323Sed 2079218893Sdim EVT VT = N->getValueType(0); 2080218893Sdim DebugLoc DL = N->getDebugLoc(); 2081218893Sdim 2082218893Sdim // If the type twice as wide is legal, transform the mulhu to a wider multiply 2083218893Sdim // plus a shift. 2084218893Sdim if (VT.isSimple() && !VT.isVector()) { 2085218893Sdim MVT Simple = VT.getSimpleVT(); 2086218893Sdim unsigned SimpleSize = Simple.getSizeInBits(); 2087218893Sdim EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2088218893Sdim if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2089218893Sdim SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2090218893Sdim SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2091218893Sdim Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2092218893Sdim // Compute the high part as N1. 2093218893Sdim Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2094219077Sdim DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2095218893Sdim Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2096218893Sdim // Compute the low part as N0. 2097218893Sdim Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2098218893Sdim return CombineTo(N, Lo, Hi); 2099218893Sdim } 2100218893Sdim } 2101219077Sdim 2102193323Sed return SDValue(); 2103193323Sed} 2104193323Sed 2105193323SedSDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2106193323Sed SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2107193323Sed if (Res.getNode()) return Res; 2108193323Sed 2109218893Sdim EVT VT = N->getValueType(0); 2110218893Sdim DebugLoc DL = N->getDebugLoc(); 2111219077Sdim 2112218893Sdim // If the type twice as wide is legal, transform the mulhu to a wider multiply 2113218893Sdim // plus a shift. 2114218893Sdim if (VT.isSimple() && !VT.isVector()) { 2115218893Sdim MVT Simple = VT.getSimpleVT(); 2116218893Sdim unsigned SimpleSize = Simple.getSizeInBits(); 2117218893Sdim EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2118218893Sdim if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2119218893Sdim SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2120218893Sdim SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2121218893Sdim Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2122218893Sdim // Compute the high part as N1. 2123218893Sdim Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2124219077Sdim DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2125218893Sdim Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2126218893Sdim // Compute the low part as N0. 2127218893Sdim Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2128218893Sdim return CombineTo(N, Lo, Hi); 2129218893Sdim } 2130218893Sdim } 2131219077Sdim 2132193323Sed return SDValue(); 2133193323Sed} 2134193323Sed 2135193323SedSDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2136193323Sed SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2137193323Sed if (Res.getNode()) return Res; 2138193323Sed 2139193323Sed return SDValue(); 2140193323Sed} 2141193323Sed 2142193323SedSDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2143193323Sed SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2144193323Sed if (Res.getNode()) return Res; 2145193323Sed 2146193323Sed return SDValue(); 2147193323Sed} 2148193323Sed 2149193323Sed/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2150193323Sed/// two operands of the same opcode, try to simplify it. 2151193323SedSDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2152193323Sed SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2153198090Srdivacky EVT VT = N0.getValueType(); 2154193323Sed assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2155193323Sed 2156202375Srdivacky // Bail early if none of these transforms apply. 2157202375Srdivacky if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2158202375Srdivacky 2159193323Sed // For each of OP in AND/OR/XOR: 2160193323Sed // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2161193323Sed // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2162193323Sed // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2163210299Sed // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2164200581Srdivacky // 2165200581Srdivacky // do not sink logical op inside of a vector extend, since it may combine 2166200581Srdivacky // into a vsetcc. 2167202375Srdivacky EVT Op0VT = N0.getOperand(0).getValueType(); 2168202375Srdivacky if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2169193323Sed N0.getOpcode() == ISD::SIGN_EXTEND || 2170207618Srdivacky // Avoid infinite looping with PromoteIntBinOp. 2171207618Srdivacky (N0.getOpcode() == ISD::ANY_EXTEND && 2172207618Srdivacky (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2173210299Sed (N0.getOpcode() == ISD::TRUNCATE && 2174210299Sed (!TLI.isZExtFree(VT, Op0VT) || 2175210299Sed !TLI.isTruncateFree(Op0VT, VT)) && 2176210299Sed TLI.isTypeLegal(Op0VT))) && 2177200581Srdivacky !VT.isVector() && 2178202375Srdivacky Op0VT == N1.getOperand(0).getValueType() && 2179202375Srdivacky (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2180193323Sed SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2181193323Sed N0.getOperand(0).getValueType(), 2182193323Sed N0.getOperand(0), N1.getOperand(0)); 2183193323Sed AddToWorkList(ORNode.getNode()); 2184193323Sed return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2185193323Sed } 2186193323Sed 2187193323Sed // For each of OP in SHL/SRL/SRA/AND... 2188193323Sed // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2189193323Sed // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2190193323Sed // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2191193323Sed if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2192193323Sed N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2193193323Sed N0.getOperand(1) == N1.getOperand(1)) { 2194193323Sed SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2195193323Sed N0.getOperand(0).getValueType(), 2196193323Sed N0.getOperand(0), N1.getOperand(0)); 2197193323Sed AddToWorkList(ORNode.getNode()); 2198193323Sed return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2199193323Sed ORNode, N0.getOperand(1)); 2200193323Sed } 2201193323Sed 2202193323Sed return SDValue(); 2203193323Sed} 2204193323Sed 2205193323SedSDValue DAGCombiner::visitAND(SDNode *N) { 2206193323Sed SDValue N0 = N->getOperand(0); 2207193323Sed SDValue N1 = N->getOperand(1); 2208193323Sed SDValue LL, LR, RL, RR, CC0, CC1; 2209193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2210193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2211198090Srdivacky EVT VT = N1.getValueType(); 2212204792Srdivacky unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2213193323Sed 2214193323Sed // fold vector ops 2215193323Sed if (VT.isVector()) { 2216193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 2217193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 2218193323Sed } 2219193323Sed 2220193323Sed // fold (and x, undef) -> 0 2221193323Sed if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2222193323Sed return DAG.getConstant(0, VT); 2223193323Sed // fold (and c1, c2) -> c1&c2 2224193323Sed if (N0C && N1C) 2225193323Sed return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2226193323Sed // canonicalize constant to RHS 2227193323Sed if (N0C && !N1C) 2228193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2229193323Sed // fold (and x, -1) -> x 2230193323Sed if (N1C && N1C->isAllOnesValue()) 2231193323Sed return N0; 2232193323Sed // if (and x, c) is known to be zero, return 0 2233193323Sed if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2234193323Sed APInt::getAllOnesValue(BitWidth))) 2235193323Sed return DAG.getConstant(0, VT); 2236193323Sed // reassociate and 2237193323Sed SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2238193323Sed if (RAND.getNode() != 0) 2239193323Sed return RAND; 2240204642Srdivacky // fold (and (or x, C), D) -> D if (C & D) == D 2241193323Sed if (N1C && N0.getOpcode() == ISD::OR) 2242193323Sed if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2243193323Sed if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2244193323Sed return N1; 2245193323Sed // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2246193323Sed if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2247193323Sed SDValue N0Op0 = N0.getOperand(0); 2248193323Sed APInt Mask = ~N1C->getAPIntValue(); 2249218893Sdim Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2250193323Sed if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2251193323Sed SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2252193323Sed N0.getValueType(), N0Op0); 2253193323Sed 2254193323Sed // Replace uses of the AND with uses of the Zero extend node. 2255193323Sed CombineTo(N, Zext); 2256193323Sed 2257193323Sed // We actually want to replace all uses of the any_extend with the 2258193323Sed // zero_extend, to avoid duplicating things. This will later cause this 2259193323Sed // AND to be folded. 2260193323Sed CombineTo(N0.getNode(), Zext); 2261193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 2262193323Sed } 2263193323Sed } 2264193323Sed // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2265193323Sed if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2266193323Sed ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2267193323Sed ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2268193323Sed 2269193323Sed if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2270193323Sed LL.getValueType().isInteger()) { 2271193323Sed // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2272193323Sed if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2273193323Sed SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2274193323Sed LR.getValueType(), LL, RL); 2275193323Sed AddToWorkList(ORNode.getNode()); 2276193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2277193323Sed } 2278193323Sed // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2279193323Sed if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2280193323Sed SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2281193323Sed LR.getValueType(), LL, RL); 2282193323Sed AddToWorkList(ANDNode.getNode()); 2283193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2284193323Sed } 2285193323Sed // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2286193323Sed if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2287193323Sed SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2288193323Sed LR.getValueType(), LL, RL); 2289193323Sed AddToWorkList(ORNode.getNode()); 2290193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2291193323Sed } 2292193323Sed } 2293193323Sed // canonicalize equivalent to ll == rl 2294193323Sed if (LL == RR && LR == RL) { 2295193323Sed Op1 = ISD::getSetCCSwappedOperands(Op1); 2296193323Sed std::swap(RL, RR); 2297193323Sed } 2298193323Sed if (LL == RL && LR == RR) { 2299193323Sed bool isInteger = LL.getValueType().isInteger(); 2300193323Sed ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2301193323Sed if (Result != ISD::SETCC_INVALID && 2302193323Sed (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2303193323Sed return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2304193323Sed LL, LR, Result); 2305193323Sed } 2306193323Sed } 2307193323Sed 2308193323Sed // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2309193323Sed if (N0.getOpcode() == N1.getOpcode()) { 2310193323Sed SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2311193323Sed if (Tmp.getNode()) return Tmp; 2312193323Sed } 2313193323Sed 2314193323Sed // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2315193323Sed // fold (and (sra)) -> (and (srl)) when possible. 2316193323Sed if (!VT.isVector() && 2317193323Sed SimplifyDemandedBits(SDValue(N, 0))) 2318193323Sed return SDValue(N, 0); 2319202375Srdivacky 2320193323Sed // fold (zext_inreg (extload x)) -> (zextload x) 2321193323Sed if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2322193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2323198090Srdivacky EVT MemVT = LN0->getMemoryVT(); 2324193323Sed // If we zero all the possible extended bits, then we can turn this into 2325193323Sed // a zextload if we are running before legalize or the operation is legal. 2326204792Srdivacky unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2327193323Sed if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2328204792Srdivacky BitWidth - MemVT.getScalarType().getSizeInBits())) && 2329193323Sed ((!LegalOperations && !LN0->isVolatile()) || 2330198090Srdivacky TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2331218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2332193323Sed LN0->getChain(), LN0->getBasePtr(), 2333218893Sdim LN0->getPointerInfo(), MemVT, 2334203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 2335203954Srdivacky LN0->getAlignment()); 2336193323Sed AddToWorkList(N); 2337193323Sed CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2338193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 2339193323Sed } 2340193323Sed } 2341193323Sed // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2342193323Sed if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2343193323Sed N0.hasOneUse()) { 2344193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2345198090Srdivacky EVT MemVT = LN0->getMemoryVT(); 2346193323Sed // If we zero all the possible extended bits, then we can turn this into 2347193323Sed // a zextload if we are running before legalize or the operation is legal. 2348204792Srdivacky unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2349193323Sed if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2350204792Srdivacky BitWidth - MemVT.getScalarType().getSizeInBits())) && 2351193323Sed ((!LegalOperations && !LN0->isVolatile()) || 2352198090Srdivacky TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2353218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2354193323Sed LN0->getChain(), 2355218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 2356218893Sdim MemVT, 2357203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 2358203954Srdivacky LN0->getAlignment()); 2359193323Sed AddToWorkList(N); 2360193323Sed CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2361193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 2362193323Sed } 2363193323Sed } 2364193323Sed 2365193323Sed // fold (and (load x), 255) -> (zextload x, i8) 2366193323Sed // fold (and (extload x, i16), 255) -> (zextload x, i8) 2367202375Srdivacky // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2368202375Srdivacky if (N1C && (N0.getOpcode() == ISD::LOAD || 2369202375Srdivacky (N0.getOpcode() == ISD::ANY_EXTEND && 2370202375Srdivacky N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2371202375Srdivacky bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2372202375Srdivacky LoadSDNode *LN0 = HasAnyExt 2373202375Srdivacky ? cast<LoadSDNode>(N0.getOperand(0)) 2374202375Srdivacky : cast<LoadSDNode>(N0); 2375193323Sed if (LN0->getExtensionType() != ISD::SEXTLOAD && 2376202375Srdivacky LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2377193323Sed uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2378202375Srdivacky if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2379202375Srdivacky EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2380202375Srdivacky EVT LoadedVT = LN0->getMemoryVT(); 2381193323Sed 2382202375Srdivacky if (ExtVT == LoadedVT && 2383202375Srdivacky (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2384202375Srdivacky EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2385218893Sdim 2386218893Sdim SDValue NewLoad = 2387218893Sdim DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2388202375Srdivacky LN0->getChain(), LN0->getBasePtr(), 2389218893Sdim LN0->getPointerInfo(), 2390203954Srdivacky ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2391203954Srdivacky LN0->getAlignment()); 2392202375Srdivacky AddToWorkList(N); 2393202375Srdivacky CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2394202375Srdivacky return SDValue(N, 0); // Return N so it doesn't get rechecked! 2395202375Srdivacky } 2396218893Sdim 2397202375Srdivacky // Do not change the width of a volatile load. 2398202375Srdivacky // Do not generate loads of non-round integer types since these can 2399202375Srdivacky // be expensive (and would be wrong if the type is not byte sized). 2400202375Srdivacky if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2401202375Srdivacky (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2402202375Srdivacky EVT PtrType = LN0->getOperand(1).getValueType(); 2403193323Sed 2404202375Srdivacky unsigned Alignment = LN0->getAlignment(); 2405202375Srdivacky SDValue NewPtr = LN0->getBasePtr(); 2406193323Sed 2407202375Srdivacky // For big endian targets, we need to add an offset to the pointer 2408202375Srdivacky // to load the correct bytes. For little endian systems, we merely 2409202375Srdivacky // need to read fewer bytes from the same pointer. 2410202375Srdivacky if (TLI.isBigEndian()) { 2411202375Srdivacky unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2412202375Srdivacky unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2413202375Srdivacky unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2414202375Srdivacky NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2415202375Srdivacky NewPtr, DAG.getConstant(PtrOff, PtrType)); 2416202375Srdivacky Alignment = MinAlign(Alignment, PtrOff); 2417202375Srdivacky } 2418193323Sed 2419202375Srdivacky AddToWorkList(NewPtr.getNode()); 2420218893Sdim 2421202375Srdivacky EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2422202375Srdivacky SDValue Load = 2423218893Sdim DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2424202375Srdivacky LN0->getChain(), NewPtr, 2425218893Sdim LN0->getPointerInfo(), 2426203954Srdivacky ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2427203954Srdivacky Alignment); 2428202375Srdivacky AddToWorkList(N); 2429202375Srdivacky CombineTo(LN0, Load, Load.getValue(1)); 2430202375Srdivacky return SDValue(N, 0); // Return N so it doesn't get rechecked! 2431193323Sed } 2432193323Sed } 2433193323Sed } 2434193323Sed } 2435193323Sed 2436193323Sed return SDValue(); 2437193323Sed} 2438193323Sed 2439193323SedSDValue DAGCombiner::visitOR(SDNode *N) { 2440193323Sed SDValue N0 = N->getOperand(0); 2441193323Sed SDValue N1 = N->getOperand(1); 2442193323Sed SDValue LL, LR, RL, RR, CC0, CC1; 2443193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2444193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2445198090Srdivacky EVT VT = N1.getValueType(); 2446193323Sed 2447193323Sed // fold vector ops 2448193323Sed if (VT.isVector()) { 2449193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 2450193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 2451193323Sed } 2452193323Sed 2453193323Sed // fold (or x, undef) -> -1 2454210299Sed if (!LegalOperations && 2455210299Sed (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2456200581Srdivacky EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2457200581Srdivacky return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2458200581Srdivacky } 2459193323Sed // fold (or c1, c2) -> c1|c2 2460193323Sed if (N0C && N1C) 2461193323Sed return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2462193323Sed // canonicalize constant to RHS 2463193323Sed if (N0C && !N1C) 2464193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2465193323Sed // fold (or x, 0) -> x 2466193323Sed if (N1C && N1C->isNullValue()) 2467193323Sed return N0; 2468193323Sed // fold (or x, -1) -> -1 2469193323Sed if (N1C && N1C->isAllOnesValue()) 2470193323Sed return N1; 2471193323Sed // fold (or x, c) -> c iff (x & ~c) == 0 2472193323Sed if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2473193323Sed return N1; 2474193323Sed // reassociate or 2475193323Sed SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2476193323Sed if (ROR.getNode() != 0) 2477193323Sed return ROR; 2478193323Sed // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2479204642Srdivacky // iff (c1 & c2) == 0. 2480193323Sed if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2481193323Sed isa<ConstantSDNode>(N0.getOperand(1))) { 2482193323Sed ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2483204642Srdivacky if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2484204642Srdivacky return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2485204642Srdivacky DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2486204642Srdivacky N0.getOperand(0), N1), 2487204642Srdivacky DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2488193323Sed } 2489193323Sed // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2490193323Sed if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2491193323Sed ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2492193323Sed ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2493193323Sed 2494193323Sed if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2495193323Sed LL.getValueType().isInteger()) { 2496193323Sed // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2497193323Sed // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2498193323Sed if (cast<ConstantSDNode>(LR)->isNullValue() && 2499193323Sed (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2500193323Sed SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2501193323Sed LR.getValueType(), LL, RL); 2502193323Sed AddToWorkList(ORNode.getNode()); 2503193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2504193323Sed } 2505193323Sed // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2506193323Sed // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2507193323Sed if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2508193323Sed (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2509193323Sed SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2510193323Sed LR.getValueType(), LL, RL); 2511193323Sed AddToWorkList(ANDNode.getNode()); 2512193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2513193323Sed } 2514193323Sed } 2515193323Sed // canonicalize equivalent to ll == rl 2516193323Sed if (LL == RR && LR == RL) { 2517193323Sed Op1 = ISD::getSetCCSwappedOperands(Op1); 2518193323Sed std::swap(RL, RR); 2519193323Sed } 2520193323Sed if (LL == RL && LR == RR) { 2521193323Sed bool isInteger = LL.getValueType().isInteger(); 2522193323Sed ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2523193323Sed if (Result != ISD::SETCC_INVALID && 2524193323Sed (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2525193323Sed return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2526193323Sed LL, LR, Result); 2527193323Sed } 2528193323Sed } 2529193323Sed 2530193323Sed // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2531193323Sed if (N0.getOpcode() == N1.getOpcode()) { 2532193323Sed SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2533193323Sed if (Tmp.getNode()) return Tmp; 2534193323Sed } 2535193323Sed 2536193323Sed // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2537193323Sed if (N0.getOpcode() == ISD::AND && 2538193323Sed N1.getOpcode() == ISD::AND && 2539193323Sed N0.getOperand(1).getOpcode() == ISD::Constant && 2540193323Sed N1.getOperand(1).getOpcode() == ISD::Constant && 2541193323Sed // Don't increase # computations. 2542193323Sed (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2543193323Sed // We can only do this xform if we know that bits from X that are set in C2 2544193323Sed // but not in C1 are already zero. Likewise for Y. 2545193323Sed const APInt &LHSMask = 2546193323Sed cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2547193323Sed const APInt &RHSMask = 2548193323Sed cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2549193323Sed 2550193323Sed if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2551193323Sed DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2552193323Sed SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2553193323Sed N0.getOperand(0), N1.getOperand(0)); 2554193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2555193323Sed DAG.getConstant(LHSMask | RHSMask, VT)); 2556193323Sed } 2557193323Sed } 2558193323Sed 2559193323Sed // See if this is some rotate idiom. 2560193323Sed if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2561193323Sed return SDValue(Rot, 0); 2562193323Sed 2563210299Sed // Simplify the operands using demanded-bits information. 2564210299Sed if (!VT.isVector() && 2565210299Sed SimplifyDemandedBits(SDValue(N, 0))) 2566210299Sed return SDValue(N, 0); 2567210299Sed 2568193323Sed return SDValue(); 2569193323Sed} 2570193323Sed 2571193323Sed/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2572193323Sedstatic bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2573193323Sed if (Op.getOpcode() == ISD::AND) { 2574193323Sed if (isa<ConstantSDNode>(Op.getOperand(1))) { 2575193323Sed Mask = Op.getOperand(1); 2576193323Sed Op = Op.getOperand(0); 2577193323Sed } else { 2578193323Sed return false; 2579193323Sed } 2580193323Sed } 2581193323Sed 2582193323Sed if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2583193323Sed Shift = Op; 2584193323Sed return true; 2585193323Sed } 2586193323Sed 2587193323Sed return false; 2588193323Sed} 2589193323Sed 2590193323Sed// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2591193323Sed// idioms for rotate, and if the target supports rotation instructions, generate 2592193323Sed// a rot[lr]. 2593193323SedSDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2594193323Sed // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2595198090Srdivacky EVT VT = LHS.getValueType(); 2596193323Sed if (!TLI.isTypeLegal(VT)) return 0; 2597193323Sed 2598193323Sed // The target must have at least one rotate flavor. 2599193323Sed bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2600193323Sed bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2601193323Sed if (!HasROTL && !HasROTR) return 0; 2602193323Sed 2603193323Sed // Match "(X shl/srl V1) & V2" where V2 may not be present. 2604193323Sed SDValue LHSShift; // The shift. 2605193323Sed SDValue LHSMask; // AND value if any. 2606193323Sed if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2607193323Sed return 0; // Not part of a rotate. 2608193323Sed 2609193323Sed SDValue RHSShift; // The shift. 2610193323Sed SDValue RHSMask; // AND value if any. 2611193323Sed if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2612193323Sed return 0; // Not part of a rotate. 2613193323Sed 2614193323Sed if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2615193323Sed return 0; // Not shifting the same value. 2616193323Sed 2617193323Sed if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2618193323Sed return 0; // Shifts must disagree. 2619193323Sed 2620193323Sed // Canonicalize shl to left side in a shl/srl pair. 2621193323Sed if (RHSShift.getOpcode() == ISD::SHL) { 2622193323Sed std::swap(LHS, RHS); 2623193323Sed std::swap(LHSShift, RHSShift); 2624193323Sed std::swap(LHSMask , RHSMask ); 2625193323Sed } 2626193323Sed 2627193323Sed unsigned OpSizeInBits = VT.getSizeInBits(); 2628193323Sed SDValue LHSShiftArg = LHSShift.getOperand(0); 2629193323Sed SDValue LHSShiftAmt = LHSShift.getOperand(1); 2630193323Sed SDValue RHSShiftAmt = RHSShift.getOperand(1); 2631193323Sed 2632193323Sed // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2633193323Sed // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2634193323Sed if (LHSShiftAmt.getOpcode() == ISD::Constant && 2635193323Sed RHSShiftAmt.getOpcode() == ISD::Constant) { 2636193323Sed uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2637193323Sed uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2638193323Sed if ((LShVal + RShVal) != OpSizeInBits) 2639193323Sed return 0; 2640193323Sed 2641193323Sed SDValue Rot; 2642193323Sed if (HasROTL) 2643193323Sed Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2644193323Sed else 2645193323Sed Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2646193323Sed 2647193323Sed // If there is an AND of either shifted operand, apply it to the result. 2648193323Sed if (LHSMask.getNode() || RHSMask.getNode()) { 2649193323Sed APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2650193323Sed 2651193323Sed if (LHSMask.getNode()) { 2652193323Sed APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2653193323Sed Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2654193323Sed } 2655193323Sed if (RHSMask.getNode()) { 2656193323Sed APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2657193323Sed Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2658193323Sed } 2659193323Sed 2660193323Sed Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2661193323Sed } 2662193323Sed 2663193323Sed return Rot.getNode(); 2664193323Sed } 2665193323Sed 2666193323Sed // If there is a mask here, and we have a variable shift, we can't be sure 2667193323Sed // that we're masking out the right stuff. 2668193323Sed if (LHSMask.getNode() || RHSMask.getNode()) 2669193323Sed return 0; 2670193323Sed 2671193323Sed // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2672193323Sed // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2673193323Sed if (RHSShiftAmt.getOpcode() == ISD::SUB && 2674193323Sed LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2675193323Sed if (ConstantSDNode *SUBC = 2676193323Sed dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2677193323Sed if (SUBC->getAPIntValue() == OpSizeInBits) { 2678193323Sed if (HasROTL) 2679193323Sed return DAG.getNode(ISD::ROTL, DL, VT, 2680193323Sed LHSShiftArg, LHSShiftAmt).getNode(); 2681193323Sed else 2682193323Sed return DAG.getNode(ISD::ROTR, DL, VT, 2683193323Sed LHSShiftArg, RHSShiftAmt).getNode(); 2684193323Sed } 2685193323Sed } 2686193323Sed } 2687193323Sed 2688193323Sed // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2689193323Sed // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2690193323Sed if (LHSShiftAmt.getOpcode() == ISD::SUB && 2691193323Sed RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2692193323Sed if (ConstantSDNode *SUBC = 2693193323Sed dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2694193323Sed if (SUBC->getAPIntValue() == OpSizeInBits) { 2695193323Sed if (HasROTR) 2696193323Sed return DAG.getNode(ISD::ROTR, DL, VT, 2697193323Sed LHSShiftArg, RHSShiftAmt).getNode(); 2698193323Sed else 2699193323Sed return DAG.getNode(ISD::ROTL, DL, VT, 2700193323Sed LHSShiftArg, LHSShiftAmt).getNode(); 2701193323Sed } 2702193323Sed } 2703193323Sed } 2704193323Sed 2705193323Sed // Look for sign/zext/any-extended or truncate cases: 2706193323Sed if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2707193323Sed || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2708193323Sed || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2709193323Sed || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2710193323Sed (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2711193323Sed || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2712193323Sed || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2713193323Sed || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2714193323Sed SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2715193323Sed SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2716193323Sed if (RExtOp0.getOpcode() == ISD::SUB && 2717193323Sed RExtOp0.getOperand(1) == LExtOp0) { 2718193323Sed // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2719193323Sed // (rotl x, y) 2720193323Sed // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2721193323Sed // (rotr x, (sub 32, y)) 2722193323Sed if (ConstantSDNode *SUBC = 2723193323Sed dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2724193323Sed if (SUBC->getAPIntValue() == OpSizeInBits) { 2725193323Sed return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2726193323Sed LHSShiftArg, 2727193323Sed HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2728193323Sed } 2729193323Sed } 2730193323Sed } else if (LExtOp0.getOpcode() == ISD::SUB && 2731193323Sed RExtOp0 == LExtOp0.getOperand(1)) { 2732193323Sed // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2733193323Sed // (rotr x, y) 2734193323Sed // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2735193323Sed // (rotl x, (sub 32, y)) 2736193323Sed if (ConstantSDNode *SUBC = 2737193323Sed dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2738193323Sed if (SUBC->getAPIntValue() == OpSizeInBits) { 2739193323Sed return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2740193323Sed LHSShiftArg, 2741193323Sed HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2742193323Sed } 2743193323Sed } 2744193323Sed } 2745193323Sed } 2746193323Sed 2747193323Sed return 0; 2748193323Sed} 2749193323Sed 2750193323SedSDValue DAGCombiner::visitXOR(SDNode *N) { 2751193323Sed SDValue N0 = N->getOperand(0); 2752193323Sed SDValue N1 = N->getOperand(1); 2753193323Sed SDValue LHS, RHS, CC; 2754193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2755193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2756198090Srdivacky EVT VT = N0.getValueType(); 2757193323Sed 2758193323Sed // fold vector ops 2759193323Sed if (VT.isVector()) { 2760193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 2761193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 2762193323Sed } 2763193323Sed 2764193323Sed // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2765193323Sed if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2766193323Sed return DAG.getConstant(0, VT); 2767193323Sed // fold (xor x, undef) -> undef 2768193323Sed if (N0.getOpcode() == ISD::UNDEF) 2769193323Sed return N0; 2770193323Sed if (N1.getOpcode() == ISD::UNDEF) 2771193323Sed return N1; 2772193323Sed // fold (xor c1, c2) -> c1^c2 2773193323Sed if (N0C && N1C) 2774193323Sed return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2775193323Sed // canonicalize constant to RHS 2776193323Sed if (N0C && !N1C) 2777193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2778193323Sed // fold (xor x, 0) -> x 2779193323Sed if (N1C && N1C->isNullValue()) 2780193323Sed return N0; 2781193323Sed // reassociate xor 2782193323Sed SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2783193323Sed if (RXOR.getNode() != 0) 2784193323Sed return RXOR; 2785193323Sed 2786193323Sed // fold !(x cc y) -> (x !cc y) 2787193323Sed if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2788193323Sed bool isInt = LHS.getValueType().isInteger(); 2789193323Sed ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2790193323Sed isInt); 2791193323Sed 2792193323Sed if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2793193323Sed switch (N0.getOpcode()) { 2794193323Sed default: 2795198090Srdivacky llvm_unreachable("Unhandled SetCC Equivalent!"); 2796193323Sed case ISD::SETCC: 2797193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2798193323Sed case ISD::SELECT_CC: 2799193323Sed return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2800193323Sed N0.getOperand(3), NotCC); 2801193323Sed } 2802193323Sed } 2803193323Sed } 2804193323Sed 2805193323Sed // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2806193323Sed if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2807193323Sed N0.getNode()->hasOneUse() && 2808193323Sed isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2809193323Sed SDValue V = N0.getOperand(0); 2810193323Sed V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2811193323Sed DAG.getConstant(1, V.getValueType())); 2812193323Sed AddToWorkList(V.getNode()); 2813193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2814193323Sed } 2815193323Sed 2816193323Sed // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2817193323Sed if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2818193323Sed (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2819193323Sed SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2820193323Sed if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2821193323Sed unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2822193323Sed LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2823193323Sed RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2824193323Sed AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2825193323Sed return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2826193323Sed } 2827193323Sed } 2828193323Sed // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2829193323Sed if (N1C && N1C->isAllOnesValue() && 2830193323Sed (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2831193323Sed SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2832193323Sed if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2833193323Sed unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2834193323Sed LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2835193323Sed RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2836193323Sed AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2837193323Sed return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2838193323Sed } 2839193323Sed } 2840193323Sed // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2841193323Sed if (N1C && N0.getOpcode() == ISD::XOR) { 2842193323Sed ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2843193323Sed ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2844193323Sed if (N00C) 2845193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2846193323Sed DAG.getConstant(N1C->getAPIntValue() ^ 2847193323Sed N00C->getAPIntValue(), VT)); 2848193323Sed if (N01C) 2849193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2850193323Sed DAG.getConstant(N1C->getAPIntValue() ^ 2851193323Sed N01C->getAPIntValue(), VT)); 2852193323Sed } 2853193323Sed // fold (xor x, x) -> 0 2854218893Sdim if (N0 == N1) 2855218893Sdim return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 2856193323Sed 2857193323Sed // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2858193323Sed if (N0.getOpcode() == N1.getOpcode()) { 2859193323Sed SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2860193323Sed if (Tmp.getNode()) return Tmp; 2861193323Sed } 2862193323Sed 2863193323Sed // Simplify the expression using non-local knowledge. 2864193323Sed if (!VT.isVector() && 2865193323Sed SimplifyDemandedBits(SDValue(N, 0))) 2866193323Sed return SDValue(N, 0); 2867193323Sed 2868193323Sed return SDValue(); 2869193323Sed} 2870193323Sed 2871193323Sed/// visitShiftByConstant - Handle transforms common to the three shifts, when 2872193323Sed/// the shift amount is a constant. 2873193323SedSDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2874193323Sed SDNode *LHS = N->getOperand(0).getNode(); 2875193323Sed if (!LHS->hasOneUse()) return SDValue(); 2876193323Sed 2877193323Sed // We want to pull some binops through shifts, so that we have (and (shift)) 2878193323Sed // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2879193323Sed // thing happens with address calculations, so it's important to canonicalize 2880193323Sed // it. 2881193323Sed bool HighBitSet = false; // Can we transform this if the high bit is set? 2882193323Sed 2883193323Sed switch (LHS->getOpcode()) { 2884193323Sed default: return SDValue(); 2885193323Sed case ISD::OR: 2886193323Sed case ISD::XOR: 2887193323Sed HighBitSet = false; // We can only transform sra if the high bit is clear. 2888193323Sed break; 2889193323Sed case ISD::AND: 2890193323Sed HighBitSet = true; // We can only transform sra if the high bit is set. 2891193323Sed break; 2892193323Sed case ISD::ADD: 2893193323Sed if (N->getOpcode() != ISD::SHL) 2894193323Sed return SDValue(); // only shl(add) not sr[al](add). 2895193323Sed HighBitSet = false; // We can only transform sra if the high bit is clear. 2896193323Sed break; 2897193323Sed } 2898193323Sed 2899193323Sed // We require the RHS of the binop to be a constant as well. 2900193323Sed ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2901193323Sed if (!BinOpCst) return SDValue(); 2902193323Sed 2903193323Sed // FIXME: disable this unless the input to the binop is a shift by a constant. 2904193323Sed // If it is not a shift, it pessimizes some common cases like: 2905193323Sed // 2906193323Sed // void foo(int *X, int i) { X[i & 1235] = 1; } 2907193323Sed // int bar(int *X, int i) { return X[i & 255]; } 2908193323Sed SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2909193323Sed if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2910193323Sed BinOpLHSVal->getOpcode() != ISD::SRA && 2911193323Sed BinOpLHSVal->getOpcode() != ISD::SRL) || 2912193323Sed !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2913193323Sed return SDValue(); 2914193323Sed 2915198090Srdivacky EVT VT = N->getValueType(0); 2916193323Sed 2917193323Sed // If this is a signed shift right, and the high bit is modified by the 2918193323Sed // logical operation, do not perform the transformation. The highBitSet 2919193323Sed // boolean indicates the value of the high bit of the constant which would 2920193323Sed // cause it to be modified for this operation. 2921193323Sed if (N->getOpcode() == ISD::SRA) { 2922193323Sed bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2923193323Sed if (BinOpRHSSignSet != HighBitSet) 2924193323Sed return SDValue(); 2925193323Sed } 2926193323Sed 2927193323Sed // Fold the constants, shifting the binop RHS by the shift amount. 2928193323Sed SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2929193323Sed N->getValueType(0), 2930193323Sed LHS->getOperand(1), N->getOperand(1)); 2931193323Sed 2932193323Sed // Create the new shift. 2933218893Sdim SDValue NewShift = DAG.getNode(N->getOpcode(), 2934218893Sdim LHS->getOperand(0).getDebugLoc(), 2935193323Sed VT, LHS->getOperand(0), N->getOperand(1)); 2936193323Sed 2937193323Sed // Create the new binop. 2938193323Sed return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2939193323Sed} 2940193323Sed 2941193323SedSDValue DAGCombiner::visitSHL(SDNode *N) { 2942193323Sed SDValue N0 = N->getOperand(0); 2943193323Sed SDValue N1 = N->getOperand(1); 2944193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2945193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2946198090Srdivacky EVT VT = N0.getValueType(); 2947200581Srdivacky unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2948193323Sed 2949193323Sed // fold (shl c1, c2) -> c1<<c2 2950193323Sed if (N0C && N1C) 2951193323Sed return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2952193323Sed // fold (shl 0, x) -> 0 2953193323Sed if (N0C && N0C->isNullValue()) 2954193323Sed return N0; 2955193323Sed // fold (shl x, c >= size(x)) -> undef 2956193323Sed if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2957193323Sed return DAG.getUNDEF(VT); 2958193323Sed // fold (shl x, 0) -> x 2959193323Sed if (N1C && N1C->isNullValue()) 2960193323Sed return N0; 2961193323Sed // if (shl x, c) is known to be zero, return 0 2962193323Sed if (DAG.MaskedValueIsZero(SDValue(N, 0), 2963200581Srdivacky APInt::getAllOnesValue(OpSizeInBits))) 2964193323Sed return DAG.getConstant(0, VT); 2965193323Sed // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2966193323Sed if (N1.getOpcode() == ISD::TRUNCATE && 2967193323Sed N1.getOperand(0).getOpcode() == ISD::AND && 2968193323Sed N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2969193323Sed SDValue N101 = N1.getOperand(0).getOperand(1); 2970193323Sed if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2971198090Srdivacky EVT TruncVT = N1.getValueType(); 2972193323Sed SDValue N100 = N1.getOperand(0).getOperand(0); 2973193323Sed APInt TruncC = N101C->getAPIntValue(); 2974218893Sdim TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 2975193323Sed return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2976193323Sed DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2977193323Sed DAG.getNode(ISD::TRUNCATE, 2978193323Sed N->getDebugLoc(), 2979193323Sed TruncVT, N100), 2980193323Sed DAG.getConstant(TruncC, TruncVT))); 2981193323Sed } 2982193323Sed } 2983193323Sed 2984193323Sed if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2985193323Sed return SDValue(N, 0); 2986193323Sed 2987193323Sed // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2988193323Sed if (N1C && N0.getOpcode() == ISD::SHL && 2989193323Sed N0.getOperand(1).getOpcode() == ISD::Constant) { 2990193323Sed uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2991193323Sed uint64_t c2 = N1C->getZExtValue(); 2992218893Sdim if (c1 + c2 >= OpSizeInBits) 2993193323Sed return DAG.getConstant(0, VT); 2994193323Sed return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2995193323Sed DAG.getConstant(c1 + c2, N1.getValueType())); 2996193323Sed } 2997218893Sdim 2998218893Sdim // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 2999218893Sdim // For this to be valid, the second form must not preserve any of the bits 3000218893Sdim // that are shifted out by the inner shift in the first form. This means 3001218893Sdim // the outer shift size must be >= the number of bits added by the ext. 3002218893Sdim // As a corollary, we don't care what kind of ext it is. 3003218893Sdim if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3004218893Sdim N0.getOpcode() == ISD::ANY_EXTEND || 3005218893Sdim N0.getOpcode() == ISD::SIGN_EXTEND) && 3006218893Sdim N0.getOperand(0).getOpcode() == ISD::SHL && 3007218893Sdim isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3008219077Sdim uint64_t c1 = 3009218893Sdim cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3010218893Sdim uint64_t c2 = N1C->getZExtValue(); 3011218893Sdim EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3012218893Sdim uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3013218893Sdim if (c2 >= OpSizeInBits - InnerShiftSize) { 3014218893Sdim if (c1 + c2 >= OpSizeInBits) 3015218893Sdim return DAG.getConstant(0, VT); 3016218893Sdim return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3017218893Sdim DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3018218893Sdim N0.getOperand(0)->getOperand(0)), 3019218893Sdim DAG.getConstant(c1 + c2, N1.getValueType())); 3020218893Sdim } 3021218893Sdim } 3022218893Sdim 3023193323Sed // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 3024193323Sed // (srl (and x, (shl -1, c1)), (sub c1, c2)) 3025193323Sed if (N1C && N0.getOpcode() == ISD::SRL && 3026193323Sed N0.getOperand(1).getOpcode() == ISD::Constant) { 3027193323Sed uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3028198090Srdivacky if (c1 < VT.getSizeInBits()) { 3029198090Srdivacky uint64_t c2 = N1C->getZExtValue(); 3030198090Srdivacky SDValue HiBitsMask = 3031198090Srdivacky DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3032198090Srdivacky VT.getSizeInBits() - c1), 3033198090Srdivacky VT); 3034198090Srdivacky SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 3035198090Srdivacky N0.getOperand(0), 3036198090Srdivacky HiBitsMask); 3037198090Srdivacky if (c2 > c1) 3038198090Srdivacky return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 3039198090Srdivacky DAG.getConstant(c2-c1, N1.getValueType())); 3040198090Srdivacky else 3041198090Srdivacky return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 3042198090Srdivacky DAG.getConstant(c1-c2, N1.getValueType())); 3043198090Srdivacky } 3044193323Sed } 3045193323Sed // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3046198090Srdivacky if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3047198090Srdivacky SDValue HiBitsMask = 3048198090Srdivacky DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3049198090Srdivacky VT.getSizeInBits() - 3050198090Srdivacky N1C->getZExtValue()), 3051198090Srdivacky VT); 3052193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3053198090Srdivacky HiBitsMask); 3054198090Srdivacky } 3055193323Sed 3056207618Srdivacky if (N1C) { 3057207618Srdivacky SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3058207618Srdivacky if (NewSHL.getNode()) 3059207618Srdivacky return NewSHL; 3060207618Srdivacky } 3061207618Srdivacky 3062207618Srdivacky return SDValue(); 3063193323Sed} 3064193323Sed 3065193323SedSDValue DAGCombiner::visitSRA(SDNode *N) { 3066193323Sed SDValue N0 = N->getOperand(0); 3067193323Sed SDValue N1 = N->getOperand(1); 3068193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3069193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3070198090Srdivacky EVT VT = N0.getValueType(); 3071200581Srdivacky unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3072193323Sed 3073193323Sed // fold (sra c1, c2) -> (sra c1, c2) 3074193323Sed if (N0C && N1C) 3075193323Sed return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3076193323Sed // fold (sra 0, x) -> 0 3077193323Sed if (N0C && N0C->isNullValue()) 3078193323Sed return N0; 3079193323Sed // fold (sra -1, x) -> -1 3080193323Sed if (N0C && N0C->isAllOnesValue()) 3081193323Sed return N0; 3082193323Sed // fold (sra x, (setge c, size(x))) -> undef 3083200581Srdivacky if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3084193323Sed return DAG.getUNDEF(VT); 3085193323Sed // fold (sra x, 0) -> x 3086193323Sed if (N1C && N1C->isNullValue()) 3087193323Sed return N0; 3088193323Sed // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3089193323Sed // sext_inreg. 3090193323Sed if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3091200581Srdivacky unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3092202375Srdivacky EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3093202375Srdivacky if (VT.isVector()) 3094202375Srdivacky ExtVT = EVT::getVectorVT(*DAG.getContext(), 3095202375Srdivacky ExtVT, VT.getVectorNumElements()); 3096202375Srdivacky if ((!LegalOperations || 3097202375Srdivacky TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3098193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3099202375Srdivacky N0.getOperand(0), DAG.getValueType(ExtVT)); 3100193323Sed } 3101193323Sed 3102193323Sed // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3103193323Sed if (N1C && N0.getOpcode() == ISD::SRA) { 3104193323Sed if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3105193323Sed unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3106200581Srdivacky if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3107193323Sed return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3108193323Sed DAG.getConstant(Sum, N1C->getValueType(0))); 3109193323Sed } 3110193323Sed } 3111193323Sed 3112193323Sed // fold (sra (shl X, m), (sub result_size, n)) 3113193323Sed // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3114193323Sed // result_size - n != m. 3115193323Sed // If truncate is free for the target sext(shl) is likely to result in better 3116193323Sed // code. 3117193323Sed if (N0.getOpcode() == ISD::SHL) { 3118193323Sed // Get the two constanst of the shifts, CN0 = m, CN = n. 3119193323Sed const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3120193323Sed if (N01C && N1C) { 3121193323Sed // Determine what the truncate's result bitsize and type would be. 3122198090Srdivacky EVT TruncVT = 3123218893Sdim EVT::getIntegerVT(*DAG.getContext(), 3124218893Sdim OpSizeInBits - N1C->getZExtValue()); 3125193323Sed // Determine the residual right-shift amount. 3126193323Sed signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3127193323Sed 3128193323Sed // If the shift is not a no-op (in which case this should be just a sign 3129193323Sed // extend already), the truncated to type is legal, sign_extend is legal 3130203954Srdivacky // on that type, and the truncate to that type is both legal and free, 3131193323Sed // perform the transform. 3132193323Sed if ((ShiftAmt > 0) && 3133193323Sed TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3134193323Sed TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3135193323Sed TLI.isTruncateFree(VT, TruncVT)) { 3136193323Sed 3137219077Sdim SDValue Amt = DAG.getConstant(ShiftAmt, 3138219077Sdim getShiftAmountTy(N0.getOperand(0).getValueType())); 3139193323Sed SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3140193323Sed N0.getOperand(0), Amt); 3141193323Sed SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3142193323Sed Shift); 3143193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3144193323Sed N->getValueType(0), Trunc); 3145193323Sed } 3146193323Sed } 3147193323Sed } 3148193323Sed 3149193323Sed // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3150193323Sed if (N1.getOpcode() == ISD::TRUNCATE && 3151193323Sed N1.getOperand(0).getOpcode() == ISD::AND && 3152193323Sed N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3153193323Sed SDValue N101 = N1.getOperand(0).getOperand(1); 3154193323Sed if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3155198090Srdivacky EVT TruncVT = N1.getValueType(); 3156193323Sed SDValue N100 = N1.getOperand(0).getOperand(0); 3157193323Sed APInt TruncC = N101C->getAPIntValue(); 3158218893Sdim TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3159193323Sed return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3160193323Sed DAG.getNode(ISD::AND, N->getDebugLoc(), 3161193323Sed TruncVT, 3162193323Sed DAG.getNode(ISD::TRUNCATE, 3163193323Sed N->getDebugLoc(), 3164193323Sed TruncVT, N100), 3165193323Sed DAG.getConstant(TruncC, TruncVT))); 3166193323Sed } 3167193323Sed } 3168193323Sed 3169218893Sdim // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3170218893Sdim // if c1 is equal to the number of bits the trunc removes 3171218893Sdim if (N0.getOpcode() == ISD::TRUNCATE && 3172218893Sdim (N0.getOperand(0).getOpcode() == ISD::SRL || 3173218893Sdim N0.getOperand(0).getOpcode() == ISD::SRA) && 3174218893Sdim N0.getOperand(0).hasOneUse() && 3175218893Sdim N0.getOperand(0).getOperand(1).hasOneUse() && 3176218893Sdim N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3177218893Sdim EVT LargeVT = N0.getOperand(0).getValueType(); 3178218893Sdim ConstantSDNode *LargeShiftAmt = 3179218893Sdim cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3180218893Sdim 3181218893Sdim if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3182218893Sdim LargeShiftAmt->getZExtValue()) { 3183218893Sdim SDValue Amt = 3184218893Sdim DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3185219077Sdim getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3186218893Sdim SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3187218893Sdim N0.getOperand(0).getOperand(0), Amt); 3188218893Sdim return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3189218893Sdim } 3190218893Sdim } 3191218893Sdim 3192193323Sed // Simplify, based on bits shifted out of the LHS. 3193193323Sed if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3194193323Sed return SDValue(N, 0); 3195193323Sed 3196193323Sed 3197193323Sed // If the sign bit is known to be zero, switch this to a SRL. 3198193323Sed if (DAG.SignBitIsZero(N0)) 3199193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3200193323Sed 3201207618Srdivacky if (N1C) { 3202207618Srdivacky SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3203207618Srdivacky if (NewSRA.getNode()) 3204207618Srdivacky return NewSRA; 3205207618Srdivacky } 3206207618Srdivacky 3207207618Srdivacky return SDValue(); 3208193323Sed} 3209193323Sed 3210193323SedSDValue DAGCombiner::visitSRL(SDNode *N) { 3211193323Sed SDValue N0 = N->getOperand(0); 3212193323Sed SDValue N1 = N->getOperand(1); 3213193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3214193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3215198090Srdivacky EVT VT = N0.getValueType(); 3216200581Srdivacky unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3217193323Sed 3218193323Sed // fold (srl c1, c2) -> c1 >>u c2 3219193323Sed if (N0C && N1C) 3220193323Sed return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3221193323Sed // fold (srl 0, x) -> 0 3222193323Sed if (N0C && N0C->isNullValue()) 3223193323Sed return N0; 3224193323Sed // fold (srl x, c >= size(x)) -> undef 3225193323Sed if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3226193323Sed return DAG.getUNDEF(VT); 3227193323Sed // fold (srl x, 0) -> x 3228193323Sed if (N1C && N1C->isNullValue()) 3229193323Sed return N0; 3230193323Sed // if (srl x, c) is known to be zero, return 0 3231193323Sed if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3232193323Sed APInt::getAllOnesValue(OpSizeInBits))) 3233193323Sed return DAG.getConstant(0, VT); 3234193323Sed 3235193323Sed // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3236193323Sed if (N1C && N0.getOpcode() == ISD::SRL && 3237193323Sed N0.getOperand(1).getOpcode() == ISD::Constant) { 3238193323Sed uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3239193323Sed uint64_t c2 = N1C->getZExtValue(); 3240218893Sdim if (c1 + c2 >= OpSizeInBits) 3241193323Sed return DAG.getConstant(0, VT); 3242193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3243193323Sed DAG.getConstant(c1 + c2, N1.getValueType())); 3244193323Sed } 3245218893Sdim 3246218893Sdim // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3247218893Sdim if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3248218893Sdim N0.getOperand(0).getOpcode() == ISD::SRL && 3249218893Sdim isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3250219077Sdim uint64_t c1 = 3251218893Sdim cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3252218893Sdim uint64_t c2 = N1C->getZExtValue(); 3253218893Sdim EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3254218893Sdim EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3255218893Sdim uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3256218893Sdim // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3257218893Sdim if (c1 + OpSizeInBits == InnerShiftSize) { 3258218893Sdim if (c1 + c2 >= InnerShiftSize) 3259218893Sdim return DAG.getConstant(0, VT); 3260218893Sdim return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3261219077Sdim DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3262218893Sdim N0.getOperand(0)->getOperand(0), 3263218893Sdim DAG.getConstant(c1 + c2, ShiftCountVT))); 3264218893Sdim } 3265218893Sdim } 3266218893Sdim 3267207618Srdivacky // fold (srl (shl x, c), c) -> (and x, cst2) 3268207618Srdivacky if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3269207618Srdivacky N0.getValueSizeInBits() <= 64) { 3270207618Srdivacky uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3271207618Srdivacky return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3272207618Srdivacky DAG.getConstant(~0ULL >> ShAmt, VT)); 3273207618Srdivacky } 3274193323Sed 3275218893Sdim 3276193323Sed // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3277193323Sed if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3278193323Sed // Shifting in all undef bits? 3279198090Srdivacky EVT SmallVT = N0.getOperand(0).getValueType(); 3280193323Sed if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3281193323Sed return DAG.getUNDEF(VT); 3282193323Sed 3283207618Srdivacky if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3284207618Srdivacky SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3285207618Srdivacky N0.getOperand(0), N1); 3286207618Srdivacky AddToWorkList(SmallShift.getNode()); 3287207618Srdivacky return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3288207618Srdivacky } 3289193323Sed } 3290193323Sed 3291193323Sed // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3292193323Sed // bit, which is unmodified by sra. 3293193323Sed if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3294193323Sed if (N0.getOpcode() == ISD::SRA) 3295193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3296193323Sed } 3297193323Sed 3298193323Sed // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3299193323Sed if (N1C && N0.getOpcode() == ISD::CTLZ && 3300193323Sed N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3301193323Sed APInt KnownZero, KnownOne; 3302204642Srdivacky APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3303193323Sed DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3304193323Sed 3305193323Sed // If any of the input bits are KnownOne, then the input couldn't be all 3306193323Sed // zeros, thus the result of the srl will always be zero. 3307193323Sed if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3308193323Sed 3309193323Sed // If all of the bits input the to ctlz node are known to be zero, then 3310193323Sed // the result of the ctlz is "32" and the result of the shift is one. 3311193323Sed APInt UnknownBits = ~KnownZero & Mask; 3312193323Sed if (UnknownBits == 0) return DAG.getConstant(1, VT); 3313193323Sed 3314193323Sed // Otherwise, check to see if there is exactly one bit input to the ctlz. 3315193323Sed if ((UnknownBits & (UnknownBits - 1)) == 0) { 3316193323Sed // Okay, we know that only that the single bit specified by UnknownBits 3317193323Sed // could be set on input to the CTLZ node. If this bit is set, the SRL 3318193323Sed // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3319193323Sed // to an SRL/XOR pair, which is likely to simplify more. 3320193323Sed unsigned ShAmt = UnknownBits.countTrailingZeros(); 3321193323Sed SDValue Op = N0.getOperand(0); 3322193323Sed 3323193323Sed if (ShAmt) { 3324193323Sed Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3325219077Sdim DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3326193323Sed AddToWorkList(Op.getNode()); 3327193323Sed } 3328193323Sed 3329193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3330193323Sed Op, DAG.getConstant(1, VT)); 3331193323Sed } 3332193323Sed } 3333193323Sed 3334193323Sed // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3335193323Sed if (N1.getOpcode() == ISD::TRUNCATE && 3336193323Sed N1.getOperand(0).getOpcode() == ISD::AND && 3337193323Sed N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3338193323Sed SDValue N101 = N1.getOperand(0).getOperand(1); 3339193323Sed if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3340198090Srdivacky EVT TruncVT = N1.getValueType(); 3341193323Sed SDValue N100 = N1.getOperand(0).getOperand(0); 3342193323Sed APInt TruncC = N101C->getAPIntValue(); 3343218893Sdim TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3344193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3345193323Sed DAG.getNode(ISD::AND, N->getDebugLoc(), 3346193323Sed TruncVT, 3347193323Sed DAG.getNode(ISD::TRUNCATE, 3348193323Sed N->getDebugLoc(), 3349193323Sed TruncVT, N100), 3350193323Sed DAG.getConstant(TruncC, TruncVT))); 3351193323Sed } 3352193323Sed } 3353193323Sed 3354193323Sed // fold operands of srl based on knowledge that the low bits are not 3355193323Sed // demanded. 3356193323Sed if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3357193323Sed return SDValue(N, 0); 3358193323Sed 3359201360Srdivacky if (N1C) { 3360201360Srdivacky SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3361201360Srdivacky if (NewSRL.getNode()) 3362201360Srdivacky return NewSRL; 3363201360Srdivacky } 3364201360Srdivacky 3365210299Sed // Attempt to convert a srl of a load into a narrower zero-extending load. 3366210299Sed SDValue NarrowLoad = ReduceLoadWidth(N); 3367210299Sed if (NarrowLoad.getNode()) 3368210299Sed return NarrowLoad; 3369210299Sed 3370201360Srdivacky // Here is a common situation. We want to optimize: 3371201360Srdivacky // 3372201360Srdivacky // %a = ... 3373201360Srdivacky // %b = and i32 %a, 2 3374201360Srdivacky // %c = srl i32 %b, 1 3375201360Srdivacky // brcond i32 %c ... 3376201360Srdivacky // 3377201360Srdivacky // into 3378218893Sdim // 3379201360Srdivacky // %a = ... 3380201360Srdivacky // %b = and %a, 2 3381201360Srdivacky // %c = setcc eq %b, 0 3382201360Srdivacky // brcond %c ... 3383201360Srdivacky // 3384201360Srdivacky // However when after the source operand of SRL is optimized into AND, the SRL 3385201360Srdivacky // itself may not be optimized further. Look for it and add the BRCOND into 3386201360Srdivacky // the worklist. 3387202375Srdivacky if (N->hasOneUse()) { 3388202375Srdivacky SDNode *Use = *N->use_begin(); 3389202375Srdivacky if (Use->getOpcode() == ISD::BRCOND) 3390202375Srdivacky AddToWorkList(Use); 3391202375Srdivacky else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3392202375Srdivacky // Also look pass the truncate. 3393202375Srdivacky Use = *Use->use_begin(); 3394202375Srdivacky if (Use->getOpcode() == ISD::BRCOND) 3395202375Srdivacky AddToWorkList(Use); 3396202375Srdivacky } 3397202375Srdivacky } 3398201360Srdivacky 3399201360Srdivacky return SDValue(); 3400193323Sed} 3401193323Sed 3402193323SedSDValue DAGCombiner::visitCTLZ(SDNode *N) { 3403193323Sed SDValue N0 = N->getOperand(0); 3404198090Srdivacky EVT VT = N->getValueType(0); 3405193323Sed 3406193323Sed // fold (ctlz c1) -> c2 3407193323Sed if (isa<ConstantSDNode>(N0)) 3408193323Sed return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3409193323Sed return SDValue(); 3410193323Sed} 3411193323Sed 3412193323SedSDValue DAGCombiner::visitCTTZ(SDNode *N) { 3413193323Sed SDValue N0 = N->getOperand(0); 3414198090Srdivacky EVT VT = N->getValueType(0); 3415193323Sed 3416193323Sed // fold (cttz c1) -> c2 3417193323Sed if (isa<ConstantSDNode>(N0)) 3418193323Sed return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3419193323Sed return SDValue(); 3420193323Sed} 3421193323Sed 3422193323SedSDValue DAGCombiner::visitCTPOP(SDNode *N) { 3423193323Sed SDValue N0 = N->getOperand(0); 3424198090Srdivacky EVT VT = N->getValueType(0); 3425193323Sed 3426193323Sed // fold (ctpop c1) -> c2 3427193323Sed if (isa<ConstantSDNode>(N0)) 3428193323Sed return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3429193323Sed return SDValue(); 3430193323Sed} 3431193323Sed 3432193323SedSDValue DAGCombiner::visitSELECT(SDNode *N) { 3433193323Sed SDValue N0 = N->getOperand(0); 3434193323Sed SDValue N1 = N->getOperand(1); 3435193323Sed SDValue N2 = N->getOperand(2); 3436193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3437193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3438193323Sed ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3439198090Srdivacky EVT VT = N->getValueType(0); 3440198090Srdivacky EVT VT0 = N0.getValueType(); 3441193323Sed 3442193323Sed // fold (select C, X, X) -> X 3443193323Sed if (N1 == N2) 3444193323Sed return N1; 3445193323Sed // fold (select true, X, Y) -> X 3446193323Sed if (N0C && !N0C->isNullValue()) 3447193323Sed return N1; 3448193323Sed // fold (select false, X, Y) -> Y 3449193323Sed if (N0C && N0C->isNullValue()) 3450193323Sed return N2; 3451193323Sed // fold (select C, 1, X) -> (or C, X) 3452193323Sed if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3453193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3454193323Sed // fold (select C, 0, 1) -> (xor C, 1) 3455193323Sed if (VT.isInteger() && 3456193323Sed (VT0 == MVT::i1 || 3457193323Sed (VT0.isInteger() && 3458193323Sed TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3459193323Sed N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3460193323Sed SDValue XORNode; 3461193323Sed if (VT == VT0) 3462193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3463193323Sed N0, DAG.getConstant(1, VT0)); 3464193323Sed XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3465193323Sed N0, DAG.getConstant(1, VT0)); 3466193323Sed AddToWorkList(XORNode.getNode()); 3467193323Sed if (VT.bitsGT(VT0)) 3468193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3469193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3470193323Sed } 3471193323Sed // fold (select C, 0, X) -> (and (not C), X) 3472193323Sed if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3473193323Sed SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3474193323Sed AddToWorkList(NOTNode.getNode()); 3475193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3476193323Sed } 3477193323Sed // fold (select C, X, 1) -> (or (not C), X) 3478193323Sed if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3479193323Sed SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3480193323Sed AddToWorkList(NOTNode.getNode()); 3481193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3482193323Sed } 3483193323Sed // fold (select C, X, 0) -> (and C, X) 3484193323Sed if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3485193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3486193323Sed // fold (select X, X, Y) -> (or X, Y) 3487193323Sed // fold (select X, 1, Y) -> (or X, Y) 3488193323Sed if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3489193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3490193323Sed // fold (select X, Y, X) -> (and X, Y) 3491193323Sed // fold (select X, Y, 0) -> (and X, Y) 3492193323Sed if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3493193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3494193323Sed 3495193323Sed // If we can fold this based on the true/false value, do so. 3496193323Sed if (SimplifySelectOps(N, N1, N2)) 3497193323Sed return SDValue(N, 0); // Don't revisit N. 3498193323Sed 3499193323Sed // fold selects based on a setcc into other things, such as min/max/abs 3500193323Sed if (N0.getOpcode() == ISD::SETCC) { 3501193323Sed // FIXME: 3502193323Sed // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3503193323Sed // having to say they don't support SELECT_CC on every type the DAG knows 3504193323Sed // about, since there is no way to mark an opcode illegal at all value types 3505198090Srdivacky if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3506198090Srdivacky TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3507193323Sed return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3508193323Sed N0.getOperand(0), N0.getOperand(1), 3509193323Sed N1, N2, N0.getOperand(2)); 3510193323Sed return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3511193323Sed } 3512193323Sed 3513193323Sed return SDValue(); 3514193323Sed} 3515193323Sed 3516193323SedSDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3517193323Sed SDValue N0 = N->getOperand(0); 3518193323Sed SDValue N1 = N->getOperand(1); 3519193323Sed SDValue N2 = N->getOperand(2); 3520193323Sed SDValue N3 = N->getOperand(3); 3521193323Sed SDValue N4 = N->getOperand(4); 3522193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3523193323Sed 3524193323Sed // fold select_cc lhs, rhs, x, x, cc -> x 3525193323Sed if (N2 == N3) 3526193323Sed return N2; 3527193323Sed 3528193323Sed // Determine if the condition we're dealing with is constant 3529193323Sed SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3530193323Sed N0, N1, CC, N->getDebugLoc(), false); 3531193323Sed if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3532193323Sed 3533193323Sed if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3534193323Sed if (!SCCC->isNullValue()) 3535193323Sed return N2; // cond always true -> true val 3536193323Sed else 3537193323Sed return N3; // cond always false -> false val 3538193323Sed } 3539193323Sed 3540193323Sed // Fold to a simpler select_cc 3541193323Sed if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3542193323Sed return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3543193323Sed SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3544193323Sed SCC.getOperand(2)); 3545193323Sed 3546193323Sed // If we can fold this based on the true/false value, do so. 3547193323Sed if (SimplifySelectOps(N, N2, N3)) 3548193323Sed return SDValue(N, 0); // Don't revisit N. 3549193323Sed 3550193323Sed // fold select_cc into other things, such as min/max/abs 3551193323Sed return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3552193323Sed} 3553193323Sed 3554193323SedSDValue DAGCombiner::visitSETCC(SDNode *N) { 3555193323Sed return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3556193323Sed cast<CondCodeSDNode>(N->getOperand(2))->get(), 3557193323Sed N->getDebugLoc()); 3558193323Sed} 3559193323Sed 3560193323Sed// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3561193323Sed// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3562193323Sed// transformation. Returns true if extension are possible and the above 3563193323Sed// mentioned transformation is profitable. 3564193323Sedstatic bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3565193323Sed unsigned ExtOpc, 3566193323Sed SmallVector<SDNode*, 4> &ExtendNodes, 3567193323Sed const TargetLowering &TLI) { 3568193323Sed bool HasCopyToRegUses = false; 3569193323Sed bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3570193323Sed for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3571193323Sed UE = N0.getNode()->use_end(); 3572193323Sed UI != UE; ++UI) { 3573193323Sed SDNode *User = *UI; 3574193323Sed if (User == N) 3575193323Sed continue; 3576193323Sed if (UI.getUse().getResNo() != N0.getResNo()) 3577193323Sed continue; 3578193323Sed // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3579193323Sed if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3580193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3581193323Sed if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3582193323Sed // Sign bits will be lost after a zext. 3583193323Sed return false; 3584193323Sed bool Add = false; 3585193323Sed for (unsigned i = 0; i != 2; ++i) { 3586193323Sed SDValue UseOp = User->getOperand(i); 3587193323Sed if (UseOp == N0) 3588193323Sed continue; 3589193323Sed if (!isa<ConstantSDNode>(UseOp)) 3590193323Sed return false; 3591193323Sed Add = true; 3592193323Sed } 3593193323Sed if (Add) 3594193323Sed ExtendNodes.push_back(User); 3595193323Sed continue; 3596193323Sed } 3597193323Sed // If truncates aren't free and there are users we can't 3598193323Sed // extend, it isn't worthwhile. 3599193323Sed if (!isTruncFree) 3600193323Sed return false; 3601193323Sed // Remember if this value is live-out. 3602193323Sed if (User->getOpcode() == ISD::CopyToReg) 3603193323Sed HasCopyToRegUses = true; 3604193323Sed } 3605193323Sed 3606193323Sed if (HasCopyToRegUses) { 3607193323Sed bool BothLiveOut = false; 3608193323Sed for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3609193323Sed UI != UE; ++UI) { 3610193323Sed SDUse &Use = UI.getUse(); 3611193323Sed if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3612193323Sed BothLiveOut = true; 3613193323Sed break; 3614193323Sed } 3615193323Sed } 3616193323Sed if (BothLiveOut) 3617193323Sed // Both unextended and extended values are live out. There had better be 3618218893Sdim // a good reason for the transformation. 3619193323Sed return ExtendNodes.size(); 3620193323Sed } 3621193323Sed return true; 3622193323Sed} 3623193323Sed 3624193323SedSDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3625193323Sed SDValue N0 = N->getOperand(0); 3626198090Srdivacky EVT VT = N->getValueType(0); 3627193323Sed 3628193323Sed // fold (sext c1) -> c1 3629193323Sed if (isa<ConstantSDNode>(N0)) 3630193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3631193323Sed 3632193323Sed // fold (sext (sext x)) -> (sext x) 3633193323Sed // fold (sext (aext x)) -> (sext x) 3634193323Sed if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3635193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3636193323Sed N0.getOperand(0)); 3637193323Sed 3638193323Sed if (N0.getOpcode() == ISD::TRUNCATE) { 3639193323Sed // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3640193323Sed // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3641193323Sed SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3642193323Sed if (NarrowLoad.getNode()) { 3643208599Srdivacky SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3644208599Srdivacky if (NarrowLoad.getNode() != N0.getNode()) { 3645193323Sed CombineTo(N0.getNode(), NarrowLoad); 3646208599Srdivacky // CombineTo deleted the truncate, if needed, but not what's under it. 3647208599Srdivacky AddToWorkList(oye); 3648208599Srdivacky } 3649193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3650193323Sed } 3651193323Sed 3652193323Sed // See if the value being truncated is already sign extended. If so, just 3653193323Sed // eliminate the trunc/sext pair. 3654193323Sed SDValue Op = N0.getOperand(0); 3655202375Srdivacky unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3656202375Srdivacky unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3657202375Srdivacky unsigned DestBits = VT.getScalarType().getSizeInBits(); 3658193323Sed unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3659193323Sed 3660193323Sed if (OpBits == DestBits) { 3661193323Sed // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3662193323Sed // bits, it is already ready. 3663193323Sed if (NumSignBits > DestBits-MidBits) 3664193323Sed return Op; 3665193323Sed } else if (OpBits < DestBits) { 3666193323Sed // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3667193323Sed // bits, just sext from i32. 3668193323Sed if (NumSignBits > OpBits-MidBits) 3669193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3670193323Sed } else { 3671193323Sed // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3672193323Sed // bits, just truncate to i32. 3673193323Sed if (NumSignBits > OpBits-MidBits) 3674193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3675193323Sed } 3676193323Sed 3677193323Sed // fold (sext (truncate x)) -> (sextinreg x). 3678193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3679193323Sed N0.getValueType())) { 3680202375Srdivacky if (OpBits < DestBits) 3681193323Sed Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3682202375Srdivacky else if (OpBits > DestBits) 3683193323Sed Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3684193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3685202375Srdivacky DAG.getValueType(N0.getValueType())); 3686193323Sed } 3687193323Sed } 3688193323Sed 3689193323Sed // fold (sext (load x)) -> (sext (truncate (sextload x))) 3690219077Sdim // None of the supported targets knows how to perform load and sign extend 3691219077Sdim // in one instruction. We only perform this transformation on scalars. 3692219077Sdim if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3693193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3694193323Sed TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3695193323Sed bool DoXform = true; 3696193323Sed SmallVector<SDNode*, 4> SetCCs; 3697193323Sed if (!N0.hasOneUse()) 3698193323Sed DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3699193323Sed if (DoXform) { 3700193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3701218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3702193323Sed LN0->getChain(), 3703218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 3704193323Sed N0.getValueType(), 3705203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 3706203954Srdivacky LN0->getAlignment()); 3707193323Sed CombineTo(N, ExtLoad); 3708193323Sed SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3709193323Sed N0.getValueType(), ExtLoad); 3710193323Sed CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3711193323Sed 3712193323Sed // Extend SetCC uses if necessary. 3713193323Sed for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3714193323Sed SDNode *SetCC = SetCCs[i]; 3715193323Sed SmallVector<SDValue, 4> Ops; 3716193323Sed 3717193323Sed for (unsigned j = 0; j != 2; ++j) { 3718193323Sed SDValue SOp = SetCC->getOperand(j); 3719193323Sed if (SOp == Trunc) 3720193323Sed Ops.push_back(ExtLoad); 3721193323Sed else 3722193323Sed Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3723193323Sed N->getDebugLoc(), VT, SOp)); 3724193323Sed } 3725193323Sed 3726193323Sed Ops.push_back(SetCC->getOperand(2)); 3727193323Sed CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3728193323Sed SetCC->getValueType(0), 3729193323Sed &Ops[0], Ops.size())); 3730193323Sed } 3731193323Sed 3732193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3733193323Sed } 3734193323Sed } 3735193323Sed 3736193323Sed // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3737193323Sed // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3738193323Sed if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3739193323Sed ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3740193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3741198090Srdivacky EVT MemVT = LN0->getMemoryVT(); 3742193323Sed if ((!LegalOperations && !LN0->isVolatile()) || 3743198090Srdivacky TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3744218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3745193323Sed LN0->getChain(), 3746218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 3747218893Sdim MemVT, 3748203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 3749203954Srdivacky LN0->getAlignment()); 3750193323Sed CombineTo(N, ExtLoad); 3751193323Sed CombineTo(N0.getNode(), 3752193323Sed DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3753193323Sed N0.getValueType(), ExtLoad), 3754193323Sed ExtLoad.getValue(1)); 3755193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3756193323Sed } 3757193323Sed } 3758193323Sed 3759193323Sed if (N0.getOpcode() == ISD::SETCC) { 3760198090Srdivacky // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3761207618Srdivacky // Only do this before legalize for now. 3762207618Srdivacky if (VT.isVector() && !LegalOperations) { 3763207618Srdivacky EVT N0VT = N0.getOperand(0).getValueType(); 3764198090Srdivacky // We know that the # elements of the results is the same as the 3765198090Srdivacky // # elements of the compare (and the # elements of the compare result 3766198090Srdivacky // for that matter). Check to see that they are the same size. If so, 3767198090Srdivacky // we know that the element size of the sext'd result matches the 3768198090Srdivacky // element size of the compare operands. 3769207618Srdivacky if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3770210299Sed return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3771210299Sed N0.getOperand(1), 3772210299Sed cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3773207618Srdivacky // If the desired elements are smaller or larger than the source 3774207618Srdivacky // elements we can use a matching integer vector type and then 3775207618Srdivacky // truncate/sign extend 3776207618Srdivacky else { 3777210299Sed EVT MatchingElementType = 3778210299Sed EVT::getIntegerVT(*DAG.getContext(), 3779210299Sed N0VT.getScalarType().getSizeInBits()); 3780210299Sed EVT MatchingVectorType = 3781210299Sed EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3782210299Sed N0VT.getVectorNumElements()); 3783210299Sed SDValue VsetCC = 3784210299Sed DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3785210299Sed N0.getOperand(1), 3786210299Sed cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3787210299Sed return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3788207618Srdivacky } 3789198090Srdivacky } 3790207618Srdivacky 3791198090Srdivacky // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3792207618Srdivacky unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3793198090Srdivacky SDValue NegOne = 3794207618Srdivacky DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3795193323Sed SDValue SCC = 3796193323Sed SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3797198090Srdivacky NegOne, DAG.getConstant(0, VT), 3798193323Sed cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3799193323Sed if (SCC.getNode()) return SCC; 3800203954Srdivacky if (!LegalOperations || 3801203954Srdivacky TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3802203954Srdivacky return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3803203954Srdivacky DAG.getSetCC(N->getDebugLoc(), 3804203954Srdivacky TLI.getSetCCResultType(VT), 3805203954Srdivacky N0.getOperand(0), N0.getOperand(1), 3806203954Srdivacky cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3807203954Srdivacky NegOne, DAG.getConstant(0, VT)); 3808218893Sdim } 3809193323Sed 3810193323Sed // fold (sext x) -> (zext x) if the sign bit is known zero. 3811193323Sed if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3812193323Sed DAG.SignBitIsZero(N0)) 3813193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3814193323Sed 3815193323Sed return SDValue(); 3816193323Sed} 3817193323Sed 3818193323SedSDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3819193323Sed SDValue N0 = N->getOperand(0); 3820198090Srdivacky EVT VT = N->getValueType(0); 3821193323Sed 3822193323Sed // fold (zext c1) -> c1 3823193323Sed if (isa<ConstantSDNode>(N0)) 3824193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3825193323Sed // fold (zext (zext x)) -> (zext x) 3826193323Sed // fold (zext (aext x)) -> (zext x) 3827193323Sed if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3828193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3829193323Sed N0.getOperand(0)); 3830193323Sed 3831193323Sed // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3832193323Sed // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3833193323Sed if (N0.getOpcode() == ISD::TRUNCATE) { 3834193323Sed SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3835193323Sed if (NarrowLoad.getNode()) { 3836208599Srdivacky SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3837208599Srdivacky if (NarrowLoad.getNode() != N0.getNode()) { 3838193323Sed CombineTo(N0.getNode(), NarrowLoad); 3839208599Srdivacky // CombineTo deleted the truncate, if needed, but not what's under it. 3840208599Srdivacky AddToWorkList(oye); 3841208599Srdivacky } 3842193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3843193323Sed } 3844193323Sed } 3845193323Sed 3846193323Sed // fold (zext (truncate x)) -> (and x, mask) 3847193323Sed if (N0.getOpcode() == ISD::TRUNCATE && 3848210299Sed (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3849218893Sdim 3850218893Sdim // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3851218893Sdim // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 3852218893Sdim SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3853218893Sdim if (NarrowLoad.getNode()) { 3854218893Sdim SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3855218893Sdim if (NarrowLoad.getNode() != N0.getNode()) { 3856218893Sdim CombineTo(N0.getNode(), NarrowLoad); 3857218893Sdim // CombineTo deleted the truncate, if needed, but not what's under it. 3858218893Sdim AddToWorkList(oye); 3859218893Sdim } 3860218893Sdim return SDValue(N, 0); // Return N so it doesn't get rechecked! 3861218893Sdim } 3862218893Sdim 3863193323Sed SDValue Op = N0.getOperand(0); 3864193323Sed if (Op.getValueType().bitsLT(VT)) { 3865193323Sed Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3866193323Sed } else if (Op.getValueType().bitsGT(VT)) { 3867193323Sed Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3868193323Sed } 3869200581Srdivacky return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3870200581Srdivacky N0.getValueType().getScalarType()); 3871193323Sed } 3872193323Sed 3873193323Sed // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3874193323Sed // if either of the casts is not free. 3875193323Sed if (N0.getOpcode() == ISD::AND && 3876193323Sed N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3877193323Sed N0.getOperand(1).getOpcode() == ISD::Constant && 3878193323Sed (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3879193323Sed N0.getValueType()) || 3880193323Sed !TLI.isZExtFree(N0.getValueType(), VT))) { 3881193323Sed SDValue X = N0.getOperand(0).getOperand(0); 3882193323Sed if (X.getValueType().bitsLT(VT)) { 3883193323Sed X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3884193323Sed } else if (X.getValueType().bitsGT(VT)) { 3885193323Sed X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3886193323Sed } 3887193323Sed APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3888218893Sdim Mask = Mask.zext(VT.getSizeInBits()); 3889193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3890193323Sed X, DAG.getConstant(Mask, VT)); 3891193323Sed } 3892193323Sed 3893193323Sed // fold (zext (load x)) -> (zext (truncate (zextload x))) 3894219077Sdim // None of the supported targets knows how to perform load and vector_zext 3895219077Sdim // in one instruction. We only perform this transformation on scalar zext. 3896219077Sdim if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3897193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3898193323Sed TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3899193323Sed bool DoXform = true; 3900193323Sed SmallVector<SDNode*, 4> SetCCs; 3901193323Sed if (!N0.hasOneUse()) 3902193323Sed DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3903193323Sed if (DoXform) { 3904193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3905218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3906193323Sed LN0->getChain(), 3907218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 3908193323Sed N0.getValueType(), 3909203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 3910203954Srdivacky LN0->getAlignment()); 3911193323Sed CombineTo(N, ExtLoad); 3912193323Sed SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3913193323Sed N0.getValueType(), ExtLoad); 3914193323Sed CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3915193323Sed 3916193323Sed // Extend SetCC uses if necessary. 3917193323Sed for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3918193323Sed SDNode *SetCC = SetCCs[i]; 3919193323Sed SmallVector<SDValue, 4> Ops; 3920193323Sed 3921193323Sed for (unsigned j = 0; j != 2; ++j) { 3922193323Sed SDValue SOp = SetCC->getOperand(j); 3923193323Sed if (SOp == Trunc) 3924193323Sed Ops.push_back(ExtLoad); 3925193323Sed else 3926193323Sed Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3927193323Sed N->getDebugLoc(), VT, SOp)); 3928193323Sed } 3929193323Sed 3930193323Sed Ops.push_back(SetCC->getOperand(2)); 3931193323Sed CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3932193323Sed SetCC->getValueType(0), 3933193323Sed &Ops[0], Ops.size())); 3934193323Sed } 3935193323Sed 3936193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3937193323Sed } 3938193323Sed } 3939193323Sed 3940193323Sed // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3941193323Sed // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3942193323Sed if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3943193323Sed ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3944193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3945198090Srdivacky EVT MemVT = LN0->getMemoryVT(); 3946193323Sed if ((!LegalOperations && !LN0->isVolatile()) || 3947198090Srdivacky TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3948218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3949193323Sed LN0->getChain(), 3950218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 3951218893Sdim MemVT, 3952203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 3953203954Srdivacky LN0->getAlignment()); 3954193323Sed CombineTo(N, ExtLoad); 3955193323Sed CombineTo(N0.getNode(), 3956193323Sed DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3957193323Sed ExtLoad), 3958193323Sed ExtLoad.getValue(1)); 3959193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3960193323Sed } 3961193323Sed } 3962193323Sed 3963193323Sed if (N0.getOpcode() == ISD::SETCC) { 3964208599Srdivacky if (!LegalOperations && VT.isVector()) { 3965208599Srdivacky // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 3966208599Srdivacky // Only do this before legalize for now. 3967208599Srdivacky EVT N0VT = N0.getOperand(0).getValueType(); 3968208599Srdivacky EVT EltVT = VT.getVectorElementType(); 3969208599Srdivacky SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 3970208599Srdivacky DAG.getConstant(1, EltVT)); 3971208599Srdivacky if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 3972208599Srdivacky // We know that the # elements of the results is the same as the 3973208599Srdivacky // # elements of the compare (and the # elements of the compare result 3974208599Srdivacky // for that matter). Check to see that they are the same size. If so, 3975208599Srdivacky // we know that the element size of the sext'd result matches the 3976208599Srdivacky // element size of the compare operands. 3977208599Srdivacky return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3978208599Srdivacky DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3979208599Srdivacky N0.getOperand(1), 3980208599Srdivacky cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3981208599Srdivacky DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3982208599Srdivacky &OneOps[0], OneOps.size())); 3983208599Srdivacky } else { 3984208599Srdivacky // If the desired elements are smaller or larger than the source 3985208599Srdivacky // elements we can use a matching integer vector type and then 3986208599Srdivacky // truncate/sign extend 3987208599Srdivacky EVT MatchingElementType = 3988208599Srdivacky EVT::getIntegerVT(*DAG.getContext(), 3989208599Srdivacky N0VT.getScalarType().getSizeInBits()); 3990208599Srdivacky EVT MatchingVectorType = 3991208599Srdivacky EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3992208599Srdivacky N0VT.getVectorNumElements()); 3993208599Srdivacky SDValue VsetCC = 3994208599Srdivacky DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3995208599Srdivacky N0.getOperand(1), 3996208599Srdivacky cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3997208599Srdivacky return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3998208599Srdivacky DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 3999208599Srdivacky DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4000208599Srdivacky &OneOps[0], OneOps.size())); 4001208599Srdivacky } 4002208599Srdivacky } 4003208599Srdivacky 4004208599Srdivacky // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4005193323Sed SDValue SCC = 4006193323Sed SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4007193323Sed DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4008193323Sed cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4009193323Sed if (SCC.getNode()) return SCC; 4010193323Sed } 4011193323Sed 4012200581Srdivacky // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4013200581Srdivacky if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4014200581Srdivacky isa<ConstantSDNode>(N0.getOperand(1)) && 4015200581Srdivacky N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4016200581Srdivacky N0.hasOneUse()) { 4017218893Sdim SDValue ShAmt = N0.getOperand(1); 4018218893Sdim unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4019200581Srdivacky if (N0.getOpcode() == ISD::SHL) { 4020218893Sdim SDValue InnerZExt = N0.getOperand(0); 4021200581Srdivacky // If the original shl may be shifting out bits, do not perform this 4022200581Srdivacky // transformation. 4023218893Sdim unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4024218893Sdim InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4025218893Sdim if (ShAmtVal > KnownZeroBits) 4026200581Srdivacky return SDValue(); 4027200581Srdivacky } 4028218893Sdim 4029218893Sdim DebugLoc DL = N->getDebugLoc(); 4030219077Sdim 4031219077Sdim // Ensure that the shift amount is wide enough for the shifted value. 4032218893Sdim if (VT.getSizeInBits() >= 256) 4033218893Sdim ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4034219077Sdim 4035218893Sdim return DAG.getNode(N0.getOpcode(), DL, VT, 4036218893Sdim DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4037218893Sdim ShAmt); 4038200581Srdivacky } 4039200581Srdivacky 4040193323Sed return SDValue(); 4041193323Sed} 4042193323Sed 4043193323SedSDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4044193323Sed SDValue N0 = N->getOperand(0); 4045198090Srdivacky EVT VT = N->getValueType(0); 4046193323Sed 4047193323Sed // fold (aext c1) -> c1 4048193323Sed if (isa<ConstantSDNode>(N0)) 4049193323Sed return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4050193323Sed // fold (aext (aext x)) -> (aext x) 4051193323Sed // fold (aext (zext x)) -> (zext x) 4052193323Sed // fold (aext (sext x)) -> (sext x) 4053193323Sed if (N0.getOpcode() == ISD::ANY_EXTEND || 4054193323Sed N0.getOpcode() == ISD::ZERO_EXTEND || 4055193323Sed N0.getOpcode() == ISD::SIGN_EXTEND) 4056193323Sed return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4057193323Sed 4058193323Sed // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4059193323Sed // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4060193323Sed if (N0.getOpcode() == ISD::TRUNCATE) { 4061193323Sed SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4062193323Sed if (NarrowLoad.getNode()) { 4063208599Srdivacky SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4064208599Srdivacky if (NarrowLoad.getNode() != N0.getNode()) { 4065193323Sed CombineTo(N0.getNode(), NarrowLoad); 4066208599Srdivacky // CombineTo deleted the truncate, if needed, but not what's under it. 4067208599Srdivacky AddToWorkList(oye); 4068208599Srdivacky } 4069193323Sed return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 4070193323Sed } 4071193323Sed } 4072193323Sed 4073193323Sed // fold (aext (truncate x)) 4074193323Sed if (N0.getOpcode() == ISD::TRUNCATE) { 4075193323Sed SDValue TruncOp = N0.getOperand(0); 4076193323Sed if (TruncOp.getValueType() == VT) 4077193323Sed return TruncOp; // x iff x size == zext size. 4078193323Sed if (TruncOp.getValueType().bitsGT(VT)) 4079193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4080193323Sed return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4081193323Sed } 4082193323Sed 4083193323Sed // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4084193323Sed // if the trunc is not free. 4085193323Sed if (N0.getOpcode() == ISD::AND && 4086193323Sed N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4087193323Sed N0.getOperand(1).getOpcode() == ISD::Constant && 4088193323Sed !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4089193323Sed N0.getValueType())) { 4090193323Sed SDValue X = N0.getOperand(0).getOperand(0); 4091193323Sed if (X.getValueType().bitsLT(VT)) { 4092193323Sed X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4093193323Sed } else if (X.getValueType().bitsGT(VT)) { 4094193323Sed X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4095193323Sed } 4096193323Sed APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4097218893Sdim Mask = Mask.zext(VT.getSizeInBits()); 4098193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4099193323Sed X, DAG.getConstant(Mask, VT)); 4100193323Sed } 4101193323Sed 4102193323Sed // fold (aext (load x)) -> (aext (truncate (extload x))) 4103219077Sdim // None of the supported targets knows how to perform load and any_ext 4104219077Sdim // in one instruction. We only perform this transformation on scalars. 4105219077Sdim if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4106193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4107193323Sed TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4108193323Sed bool DoXform = true; 4109193323Sed SmallVector<SDNode*, 4> SetCCs; 4110193323Sed if (!N0.hasOneUse()) 4111193323Sed DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4112193323Sed if (DoXform) { 4113193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4114218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4115193323Sed LN0->getChain(), 4116218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 4117193323Sed N0.getValueType(), 4118203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 4119203954Srdivacky LN0->getAlignment()); 4120193323Sed CombineTo(N, ExtLoad); 4121193323Sed SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4122193323Sed N0.getValueType(), ExtLoad); 4123193323Sed CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4124193323Sed 4125193323Sed // Extend SetCC uses if necessary. 4126193323Sed for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4127193323Sed SDNode *SetCC = SetCCs[i]; 4128193323Sed SmallVector<SDValue, 4> Ops; 4129193323Sed 4130193323Sed for (unsigned j = 0; j != 2; ++j) { 4131193323Sed SDValue SOp = SetCC->getOperand(j); 4132193323Sed if (SOp == Trunc) 4133193323Sed Ops.push_back(ExtLoad); 4134193323Sed else 4135193323Sed Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 4136193323Sed N->getDebugLoc(), VT, SOp)); 4137193323Sed } 4138193323Sed 4139193323Sed Ops.push_back(SetCC->getOperand(2)); 4140193323Sed CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 4141193323Sed SetCC->getValueType(0), 4142193323Sed &Ops[0], Ops.size())); 4143193323Sed } 4144193323Sed 4145193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 4146193323Sed } 4147193323Sed } 4148193323Sed 4149193323Sed // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4150193323Sed // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4151193323Sed // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4152193323Sed if (N0.getOpcode() == ISD::LOAD && 4153193323Sed !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4154193323Sed N0.hasOneUse()) { 4155193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4156198090Srdivacky EVT MemVT = LN0->getMemoryVT(); 4157218893Sdim SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4158218893Sdim VT, LN0->getChain(), LN0->getBasePtr(), 4159218893Sdim LN0->getPointerInfo(), MemVT, 4160203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 4161203954Srdivacky LN0->getAlignment()); 4162193323Sed CombineTo(N, ExtLoad); 4163193323Sed CombineTo(N0.getNode(), 4164193323Sed DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4165193323Sed N0.getValueType(), ExtLoad), 4166193323Sed ExtLoad.getValue(1)); 4167193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 4168193323Sed } 4169193323Sed 4170193323Sed if (N0.getOpcode() == ISD::SETCC) { 4171208599Srdivacky // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4172208599Srdivacky // Only do this before legalize for now. 4173208599Srdivacky if (VT.isVector() && !LegalOperations) { 4174208599Srdivacky EVT N0VT = N0.getOperand(0).getValueType(); 4175208599Srdivacky // We know that the # elements of the results is the same as the 4176208599Srdivacky // # elements of the compare (and the # elements of the compare result 4177208599Srdivacky // for that matter). Check to see that they are the same size. If so, 4178208599Srdivacky // we know that the element size of the sext'd result matches the 4179208599Srdivacky // element size of the compare operands. 4180208599Srdivacky if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4181210299Sed return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4182210299Sed N0.getOperand(1), 4183210299Sed cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4184208599Srdivacky // If the desired elements are smaller or larger than the source 4185208599Srdivacky // elements we can use a matching integer vector type and then 4186208599Srdivacky // truncate/sign extend 4187208599Srdivacky else { 4188210299Sed EVT MatchingElementType = 4189210299Sed EVT::getIntegerVT(*DAG.getContext(), 4190210299Sed N0VT.getScalarType().getSizeInBits()); 4191210299Sed EVT MatchingVectorType = 4192210299Sed EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4193210299Sed N0VT.getVectorNumElements()); 4194210299Sed SDValue VsetCC = 4195210299Sed DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4196210299Sed N0.getOperand(1), 4197210299Sed cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4198210299Sed return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4199208599Srdivacky } 4200208599Srdivacky } 4201208599Srdivacky 4202208599Srdivacky // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4203193323Sed SDValue SCC = 4204193323Sed SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4205193323Sed DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4206193323Sed cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4207193323Sed if (SCC.getNode()) 4208193323Sed return SCC; 4209193323Sed } 4210193323Sed 4211193323Sed return SDValue(); 4212193323Sed} 4213193323Sed 4214193323Sed/// GetDemandedBits - See if the specified operand can be simplified with the 4215193323Sed/// knowledge that only the bits specified by Mask are used. If so, return the 4216193323Sed/// simpler operand, otherwise return a null SDValue. 4217193323SedSDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4218193323Sed switch (V.getOpcode()) { 4219193323Sed default: break; 4220193323Sed case ISD::OR: 4221193323Sed case ISD::XOR: 4222193323Sed // If the LHS or RHS don't contribute bits to the or, drop them. 4223193323Sed if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4224193323Sed return V.getOperand(1); 4225193323Sed if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4226193323Sed return V.getOperand(0); 4227193323Sed break; 4228193323Sed case ISD::SRL: 4229193323Sed // Only look at single-use SRLs. 4230193323Sed if (!V.getNode()->hasOneUse()) 4231193323Sed break; 4232193323Sed if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4233193323Sed // See if we can recursively simplify the LHS. 4234193323Sed unsigned Amt = RHSC->getZExtValue(); 4235193323Sed 4236193323Sed // Watch out for shift count overflow though. 4237193323Sed if (Amt >= Mask.getBitWidth()) break; 4238193323Sed APInt NewMask = Mask << Amt; 4239193323Sed SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4240193323Sed if (SimplifyLHS.getNode()) 4241193323Sed return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4242193323Sed SimplifyLHS, V.getOperand(1)); 4243193323Sed } 4244193323Sed } 4245193323Sed return SDValue(); 4246193323Sed} 4247193323Sed 4248193323Sed/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4249193323Sed/// bits and then truncated to a narrower type and where N is a multiple 4250193323Sed/// of number of bits of the narrower type, transform it to a narrower load 4251193323Sed/// from address + N / num of bits of new type. If the result is to be 4252193323Sed/// extended, also fold the extension to form a extending load. 4253193323SedSDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4254193323Sed unsigned Opc = N->getOpcode(); 4255210299Sed 4256193323Sed ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4257193323Sed SDValue N0 = N->getOperand(0); 4258198090Srdivacky EVT VT = N->getValueType(0); 4259198090Srdivacky EVT ExtVT = VT; 4260193323Sed 4261193323Sed // This transformation isn't valid for vector loads. 4262193323Sed if (VT.isVector()) 4263193323Sed return SDValue(); 4264193323Sed 4265202375Srdivacky // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4266193323Sed // extended to VT. 4267193323Sed if (Opc == ISD::SIGN_EXTEND_INREG) { 4268193323Sed ExtType = ISD::SEXTLOAD; 4269198090Srdivacky ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4270210299Sed } else if (Opc == ISD::SRL) { 4271218893Sdim // Another special-case: SRL is basically zero-extending a narrower value. 4272210299Sed ExtType = ISD::ZEXTLOAD; 4273210299Sed N0 = SDValue(N, 0); 4274210299Sed ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4275210299Sed if (!N01) return SDValue(); 4276210299Sed ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4277210299Sed VT.getSizeInBits() - N01->getZExtValue()); 4278193323Sed } 4279218893Sdim if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4280218893Sdim return SDValue(); 4281193323Sed 4282198090Srdivacky unsigned EVTBits = ExtVT.getSizeInBits(); 4283219077Sdim 4284218893Sdim // Do not generate loads of non-round integer types since these can 4285218893Sdim // be expensive (and would be wrong if the type is not byte sized). 4286218893Sdim if (!ExtVT.isRound()) 4287218893Sdim return SDValue(); 4288219077Sdim 4289193323Sed unsigned ShAmt = 0; 4290218893Sdim if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4291193323Sed if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4292193323Sed ShAmt = N01->getZExtValue(); 4293193323Sed // Is the shift amount a multiple of size of VT? 4294193323Sed if ((ShAmt & (EVTBits-1)) == 0) { 4295193323Sed N0 = N0.getOperand(0); 4296198090Srdivacky // Is the load width a multiple of size of VT? 4297198090Srdivacky if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4298193323Sed return SDValue(); 4299193323Sed } 4300218893Sdim 4301218893Sdim // At this point, we must have a load or else we can't do the transform. 4302218893Sdim if (!isa<LoadSDNode>(N0)) return SDValue(); 4303219077Sdim 4304218893Sdim // If the shift amount is larger than the input type then we're not 4305218893Sdim // accessing any of the loaded bytes. If the load was a zextload/extload 4306218893Sdim // then the result of the shift+trunc is zero/undef (handled elsewhere). 4307218893Sdim // If the load was a sextload then the result is a splat of the sign bit 4308218893Sdim // of the extended byte. This is not worth optimizing for. 4309218893Sdim if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4310218893Sdim return SDValue(); 4311193323Sed } 4312193323Sed } 4313193323Sed 4314218893Sdim // If the load is shifted left (and the result isn't shifted back right), 4315218893Sdim // we can fold the truncate through the shift. 4316218893Sdim unsigned ShLeftAmt = 0; 4317218893Sdim if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4318218893Sdim ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4319218893Sdim if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4320218893Sdim ShLeftAmt = N01->getZExtValue(); 4321218893Sdim N0 = N0.getOperand(0); 4322193323Sed } 4323218893Sdim } 4324219077Sdim 4325218893Sdim // If we haven't found a load, we can't narrow it. Don't transform one with 4326218893Sdim // multiple uses, this would require adding a new load. 4327218893Sdim if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4328218893Sdim // Don't change the width of a volatile load. 4329218893Sdim cast<LoadSDNode>(N0)->isVolatile()) 4330218893Sdim return SDValue(); 4331219077Sdim 4332218893Sdim // Verify that we are actually reducing a load width here. 4333218893Sdim if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4334218893Sdim return SDValue(); 4335219077Sdim 4336218893Sdim LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4337218893Sdim EVT PtrType = N0.getOperand(1).getValueType(); 4338193323Sed 4339218893Sdim // For big endian targets, we need to adjust the offset to the pointer to 4340218893Sdim // load the correct bytes. 4341218893Sdim if (TLI.isBigEndian()) { 4342218893Sdim unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4343218893Sdim unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4344218893Sdim ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4345218893Sdim } 4346193323Sed 4347218893Sdim uint64_t PtrOff = ShAmt / 8; 4348218893Sdim unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4349218893Sdim SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4350218893Sdim PtrType, LN0->getBasePtr(), 4351218893Sdim DAG.getConstant(PtrOff, PtrType)); 4352218893Sdim AddToWorkList(NewPtr.getNode()); 4353193323Sed 4354218893Sdim SDValue Load; 4355218893Sdim if (ExtType == ISD::NON_EXTLOAD) 4356218893Sdim Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4357218893Sdim LN0->getPointerInfo().getWithOffset(PtrOff), 4358218893Sdim LN0->isVolatile(), LN0->isNonTemporal(), NewAlign); 4359218893Sdim else 4360218893Sdim Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4361218893Sdim LN0->getPointerInfo().getWithOffset(PtrOff), 4362218893Sdim ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4363218893Sdim NewAlign); 4364193323Sed 4365218893Sdim // Replace the old load's chain with the new load's chain. 4366218893Sdim WorkListRemover DeadNodes(*this); 4367218893Sdim DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4368218893Sdim &DeadNodes); 4369218893Sdim 4370218893Sdim // Shift the result left, if we've swallowed a left shift. 4371218893Sdim SDValue Result = Load; 4372218893Sdim if (ShLeftAmt != 0) { 4373219077Sdim EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4374218893Sdim if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4375218893Sdim ShImmTy = VT; 4376218893Sdim Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4377218893Sdim Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4378193323Sed } 4379193323Sed 4380218893Sdim // Return the new loaded value. 4381218893Sdim return Result; 4382193323Sed} 4383193323Sed 4384193323SedSDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4385193323Sed SDValue N0 = N->getOperand(0); 4386193323Sed SDValue N1 = N->getOperand(1); 4387198090Srdivacky EVT VT = N->getValueType(0); 4388198090Srdivacky EVT EVT = cast<VTSDNode>(N1)->getVT(); 4389200581Srdivacky unsigned VTBits = VT.getScalarType().getSizeInBits(); 4390202375Srdivacky unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4391193323Sed 4392193323Sed // fold (sext_in_reg c1) -> c1 4393193323Sed if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4394193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4395193323Sed 4396193323Sed // If the input is already sign extended, just drop the extension. 4397200581Srdivacky if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4398193323Sed return N0; 4399193323Sed 4400193323Sed // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4401193323Sed if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4402193323Sed EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4403193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4404193323Sed N0.getOperand(0), N1); 4405193323Sed } 4406193323Sed 4407193323Sed // fold (sext_in_reg (sext x)) -> (sext x) 4408193323Sed // fold (sext_in_reg (aext x)) -> (sext x) 4409193323Sed // if x is small enough. 4410193323Sed if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4411193323Sed SDValue N00 = N0.getOperand(0); 4412207618Srdivacky if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4413207618Srdivacky (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4414193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4415193323Sed } 4416193323Sed 4417193323Sed // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4418193323Sed if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4419193323Sed return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4420193323Sed 4421193323Sed // fold operands of sext_in_reg based on knowledge that the top bits are not 4422193323Sed // demanded. 4423193323Sed if (SimplifyDemandedBits(SDValue(N, 0))) 4424193323Sed return SDValue(N, 0); 4425193323Sed 4426193323Sed // fold (sext_in_reg (load x)) -> (smaller sextload x) 4427193323Sed // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4428193323Sed SDValue NarrowLoad = ReduceLoadWidth(N); 4429193323Sed if (NarrowLoad.getNode()) 4430193323Sed return NarrowLoad; 4431193323Sed 4432193323Sed // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4433193323Sed // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4434193323Sed // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4435193323Sed if (N0.getOpcode() == ISD::SRL) { 4436193323Sed if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4437200581Srdivacky if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4438193323Sed // We can turn this into an SRA iff the input to the SRL is already sign 4439193323Sed // extended enough. 4440193323Sed unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4441200581Srdivacky if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4442193323Sed return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4443193323Sed N0.getOperand(0), N0.getOperand(1)); 4444193323Sed } 4445193323Sed } 4446193323Sed 4447193323Sed // fold (sext_inreg (extload x)) -> (sextload x) 4448193323Sed if (ISD::isEXTLoad(N0.getNode()) && 4449193323Sed ISD::isUNINDEXEDLoad(N0.getNode()) && 4450193323Sed EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4451193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4452193323Sed TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4453193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4454218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4455193323Sed LN0->getChain(), 4456218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 4457218893Sdim EVT, 4458203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 4459203954Srdivacky LN0->getAlignment()); 4460193323Sed CombineTo(N, ExtLoad); 4461193323Sed CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4462193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 4463193323Sed } 4464193323Sed // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4465193323Sed if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4466193323Sed N0.hasOneUse() && 4467193323Sed EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4468193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4469193323Sed TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4470193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4471218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4472193323Sed LN0->getChain(), 4473218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 4474218893Sdim EVT, 4475203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 4476203954Srdivacky LN0->getAlignment()); 4477193323Sed CombineTo(N, ExtLoad); 4478193323Sed CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4479193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 4480193323Sed } 4481193323Sed return SDValue(); 4482193323Sed} 4483193323Sed 4484193323SedSDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4485193323Sed SDValue N0 = N->getOperand(0); 4486198090Srdivacky EVT VT = N->getValueType(0); 4487193323Sed 4488193323Sed // noop truncate 4489193323Sed if (N0.getValueType() == N->getValueType(0)) 4490193323Sed return N0; 4491193323Sed // fold (truncate c1) -> c1 4492193323Sed if (isa<ConstantSDNode>(N0)) 4493193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4494193323Sed // fold (truncate (truncate x)) -> (truncate x) 4495193323Sed if (N0.getOpcode() == ISD::TRUNCATE) 4496193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4497193323Sed // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4498207618Srdivacky if (N0.getOpcode() == ISD::ZERO_EXTEND || 4499207618Srdivacky N0.getOpcode() == ISD::SIGN_EXTEND || 4500193323Sed N0.getOpcode() == ISD::ANY_EXTEND) { 4501193323Sed if (N0.getOperand(0).getValueType().bitsLT(VT)) 4502193323Sed // if the source is smaller than the dest, we still need an extend 4503193323Sed return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4504193323Sed N0.getOperand(0)); 4505193323Sed else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4506193323Sed // if the source is larger than the dest, than we just need the truncate 4507193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4508193323Sed else 4509193323Sed // if the source and dest are the same type, we can drop both the extend 4510202375Srdivacky // and the truncate. 4511193323Sed return N0.getOperand(0); 4512193323Sed } 4513193323Sed 4514193323Sed // See if we can simplify the input to this truncate through knowledge that 4515219077Sdim // only the low bits are being used. 4516219077Sdim // For example "trunc (or (shl x, 8), y)" // -> trunc y 4517219077Sdim // Currenly we only perform this optimization on scalars because vectors 4518219077Sdim // may have different active low bits. 4519219077Sdim if (!VT.isVector()) { 4520219077Sdim SDValue Shorter = 4521219077Sdim GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4522219077Sdim VT.getSizeInBits())); 4523219077Sdim if (Shorter.getNode()) 4524219077Sdim return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4525219077Sdim } 4526193323Sed // fold (truncate (load x)) -> (smaller load x) 4527193323Sed // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4528210299Sed if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4529210299Sed SDValue Reduced = ReduceLoadWidth(N); 4530210299Sed if (Reduced.getNode()) 4531210299Sed return Reduced; 4532210299Sed } 4533210299Sed 4534210299Sed // Simplify the operands using demanded-bits information. 4535210299Sed if (!VT.isVector() && 4536210299Sed SimplifyDemandedBits(SDValue(N, 0))) 4537210299Sed return SDValue(N, 0); 4538210299Sed 4539207618Srdivacky return SDValue(); 4540193323Sed} 4541193323Sed 4542193323Sedstatic SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4543193323Sed SDValue Elt = N->getOperand(i); 4544193323Sed if (Elt.getOpcode() != ISD::MERGE_VALUES) 4545193323Sed return Elt.getNode(); 4546193323Sed return Elt.getOperand(Elt.getResNo()).getNode(); 4547193323Sed} 4548193323Sed 4549193323Sed/// CombineConsecutiveLoads - build_pair (load, load) -> load 4550193323Sed/// if load locations are consecutive. 4551198090SrdivackySDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4552193323Sed assert(N->getOpcode() == ISD::BUILD_PAIR); 4553193323Sed 4554193574Sed LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4555193574Sed LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4556218893Sdim if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4557218893Sdim LD1->getPointerInfo().getAddrSpace() != 4558218893Sdim LD2->getPointerInfo().getAddrSpace()) 4559193323Sed return SDValue(); 4560198090Srdivacky EVT LD1VT = LD1->getValueType(0); 4561193323Sed 4562193323Sed if (ISD::isNON_EXTLoad(LD2) && 4563193323Sed LD2->hasOneUse() && 4564193323Sed // If both are volatile this would reduce the number of volatile loads. 4565193323Sed // If one is volatile it might be ok, but play conservative and bail out. 4566193574Sed !LD1->isVolatile() && 4567193574Sed !LD2->isVolatile() && 4568200581Srdivacky DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4569193574Sed unsigned Align = LD1->getAlignment(); 4570193323Sed unsigned NewAlign = TLI.getTargetData()-> 4571198090Srdivacky getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4572193323Sed 4573193323Sed if (NewAlign <= Align && 4574193323Sed (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4575193574Sed return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4576218893Sdim LD1->getBasePtr(), LD1->getPointerInfo(), 4577218893Sdim false, false, Align); 4578193323Sed } 4579193323Sed 4580193323Sed return SDValue(); 4581193323Sed} 4582193323Sed 4583218893SdimSDValue DAGCombiner::visitBITCAST(SDNode *N) { 4584193323Sed SDValue N0 = N->getOperand(0); 4585198090Srdivacky EVT VT = N->getValueType(0); 4586193323Sed 4587193323Sed // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4588193323Sed // Only do this before legalize, since afterward the target may be depending 4589193323Sed // on the bitconvert. 4590193323Sed // First check to see if this is all constant. 4591193323Sed if (!LegalTypes && 4592193323Sed N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4593193323Sed VT.isVector()) { 4594193323Sed bool isSimple = true; 4595193323Sed for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4596193323Sed if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4597193323Sed N0.getOperand(i).getOpcode() != ISD::Constant && 4598193323Sed N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4599193323Sed isSimple = false; 4600193323Sed break; 4601193323Sed } 4602193323Sed 4603198090Srdivacky EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4604193323Sed assert(!DestEltVT.isVector() && 4605193323Sed "Element type of vector ValueType must not be vector!"); 4606193323Sed if (isSimple) 4607218893Sdim return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4608193323Sed } 4609193323Sed 4610193323Sed // If the input is a constant, let getNode fold it. 4611193323Sed if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4612218893Sdim SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 4613198090Srdivacky if (Res.getNode() != N) { 4614198090Srdivacky if (!LegalOperations || 4615198090Srdivacky TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4616198090Srdivacky return Res; 4617198090Srdivacky 4618198090Srdivacky // Folding it resulted in an illegal node, and it's too late to 4619198090Srdivacky // do that. Clean up the old node and forego the transformation. 4620198090Srdivacky // Ideally this won't happen very often, because instcombine 4621198090Srdivacky // and the earlier dagcombine runs (where illegal nodes are 4622198090Srdivacky // permitted) should have folded most of them already. 4623198090Srdivacky DAG.DeleteNode(Res.getNode()); 4624198090Srdivacky } 4625193323Sed } 4626193323Sed 4627193323Sed // (conv (conv x, t1), t2) -> (conv x, t2) 4628218893Sdim if (N0.getOpcode() == ISD::BITCAST) 4629218893Sdim return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 4630193323Sed N0.getOperand(0)); 4631193323Sed 4632193323Sed // fold (conv (load x)) -> (load (conv*)x) 4633193323Sed // If the resultant load doesn't need a higher alignment than the original! 4634193323Sed if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4635193323Sed // Do not change the width of a volatile load. 4636193323Sed !cast<LoadSDNode>(N0)->isVolatile() && 4637193323Sed (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4638193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4639193323Sed unsigned Align = TLI.getTargetData()-> 4640198090Srdivacky getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4641193323Sed unsigned OrigAlign = LN0->getAlignment(); 4642193323Sed 4643193323Sed if (Align <= OrigAlign) { 4644193323Sed SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4645218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 4646203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 4647203954Srdivacky OrigAlign); 4648193323Sed AddToWorkList(N); 4649193323Sed CombineTo(N0.getNode(), 4650218893Sdim DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4651193323Sed N0.getValueType(), Load), 4652193323Sed Load.getValue(1)); 4653193323Sed return Load; 4654193323Sed } 4655193323Sed } 4656193323Sed 4657193323Sed // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4658193323Sed // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4659193323Sed // This often reduces constant pool loads. 4660193323Sed if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4661193323Sed N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4662218893Sdim SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 4663193323Sed N0.getOperand(0)); 4664193323Sed AddToWorkList(NewConv.getNode()); 4665193323Sed 4666193323Sed APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4667193323Sed if (N0.getOpcode() == ISD::FNEG) 4668193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4669193323Sed NewConv, DAG.getConstant(SignBit, VT)); 4670193323Sed assert(N0.getOpcode() == ISD::FABS); 4671193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4672193323Sed NewConv, DAG.getConstant(~SignBit, VT)); 4673193323Sed } 4674193323Sed 4675193323Sed // fold (bitconvert (fcopysign cst, x)) -> 4676193323Sed // (or (and (bitconvert x), sign), (and cst, (not sign))) 4677193323Sed // Note that we don't handle (copysign x, cst) because this can always be 4678193323Sed // folded to an fneg or fabs. 4679193323Sed if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4680193323Sed isa<ConstantFPSDNode>(N0.getOperand(0)) && 4681193323Sed VT.isInteger() && !VT.isVector()) { 4682193323Sed unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4683198090Srdivacky EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4684207618Srdivacky if (isTypeLegal(IntXVT)) { 4685218893Sdim SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4686193323Sed IntXVT, N0.getOperand(1)); 4687193323Sed AddToWorkList(X.getNode()); 4688193323Sed 4689193323Sed // If X has a different width than the result/lhs, sext it or truncate it. 4690193323Sed unsigned VTWidth = VT.getSizeInBits(); 4691193323Sed if (OrigXWidth < VTWidth) { 4692193323Sed X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4693193323Sed AddToWorkList(X.getNode()); 4694193323Sed } else if (OrigXWidth > VTWidth) { 4695193323Sed // To get the sign bit in the right place, we have to shift it right 4696193323Sed // before truncating. 4697193323Sed X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4698193323Sed X.getValueType(), X, 4699193323Sed DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4700193323Sed AddToWorkList(X.getNode()); 4701193323Sed X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4702193323Sed AddToWorkList(X.getNode()); 4703193323Sed } 4704193323Sed 4705193323Sed APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4706193323Sed X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4707193323Sed X, DAG.getConstant(SignBit, VT)); 4708193323Sed AddToWorkList(X.getNode()); 4709193323Sed 4710218893Sdim SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4711193323Sed VT, N0.getOperand(0)); 4712193323Sed Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4713193323Sed Cst, DAG.getConstant(~SignBit, VT)); 4714193323Sed AddToWorkList(Cst.getNode()); 4715193323Sed 4716193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4717193323Sed } 4718193323Sed } 4719193323Sed 4720193323Sed // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4721193323Sed if (N0.getOpcode() == ISD::BUILD_PAIR) { 4722193323Sed SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4723193323Sed if (CombineLD.getNode()) 4724193323Sed return CombineLD; 4725193323Sed } 4726193323Sed 4727193323Sed return SDValue(); 4728193323Sed} 4729193323Sed 4730193323SedSDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4731198090Srdivacky EVT VT = N->getValueType(0); 4732193323Sed return CombineConsecutiveLoads(N, VT); 4733193323Sed} 4734193323Sed 4735218893Sdim/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 4736193323Sed/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4737193323Sed/// destination element value type. 4738193323SedSDValue DAGCombiner:: 4739218893SdimConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4740198090Srdivacky EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4741193323Sed 4742193323Sed // If this is already the right type, we're done. 4743193323Sed if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4744193323Sed 4745193323Sed unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4746193323Sed unsigned DstBitSize = DstEltVT.getSizeInBits(); 4747193323Sed 4748193323Sed // If this is a conversion of N elements of one type to N elements of another 4749193323Sed // type, convert each element. This handles FP<->INT cases. 4750193323Sed if (SrcBitSize == DstBitSize) { 4751212904Sdim EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4752212904Sdim BV->getValueType(0).getVectorNumElements()); 4753212904Sdim 4754212904Sdim // Due to the FP element handling below calling this routine recursively, 4755212904Sdim // we can end up with a scalar-to-vector node here. 4756212904Sdim if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 4757218893Sdim return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4758218893Sdim DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4759212904Sdim DstEltVT, BV->getOperand(0))); 4760218893Sdim 4761193323Sed SmallVector<SDValue, 8> Ops; 4762193323Sed for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4763193323Sed SDValue Op = BV->getOperand(i); 4764193323Sed // If the vector element type is not legal, the BUILD_VECTOR operands 4765193323Sed // are promoted and implicitly truncated. Make that explicit here. 4766193323Sed if (Op.getValueType() != SrcEltVT) 4767193323Sed Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4768218893Sdim Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4769193323Sed DstEltVT, Op)); 4770193323Sed AddToWorkList(Ops.back().getNode()); 4771193323Sed } 4772193323Sed return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4773193323Sed &Ops[0], Ops.size()); 4774193323Sed } 4775193323Sed 4776193323Sed // Otherwise, we're growing or shrinking the elements. To avoid having to 4777193323Sed // handle annoying details of growing/shrinking FP values, we convert them to 4778193323Sed // int first. 4779193323Sed if (SrcEltVT.isFloatingPoint()) { 4780193323Sed // Convert the input float vector to a int vector where the elements are the 4781193323Sed // same sizes. 4782193323Sed assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4783198090Srdivacky EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4784218893Sdim BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 4785193323Sed SrcEltVT = IntVT; 4786193323Sed } 4787193323Sed 4788193323Sed // Now we know the input is an integer vector. If the output is a FP type, 4789193323Sed // convert to integer first, then to FP of the right size. 4790193323Sed if (DstEltVT.isFloatingPoint()) { 4791193323Sed assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4792198090Srdivacky EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4793218893Sdim SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 4794193323Sed 4795193323Sed // Next, convert to FP elements of the same size. 4796218893Sdim return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 4797193323Sed } 4798193323Sed 4799193323Sed // Okay, we know the src/dst types are both integers of differing types. 4800193323Sed // Handling growing first. 4801193323Sed assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4802193323Sed if (SrcBitSize < DstBitSize) { 4803193323Sed unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4804193323Sed 4805193323Sed SmallVector<SDValue, 8> Ops; 4806193323Sed for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4807193323Sed i += NumInputsPerOutput) { 4808193323Sed bool isLE = TLI.isLittleEndian(); 4809193323Sed APInt NewBits = APInt(DstBitSize, 0); 4810193323Sed bool EltIsUndef = true; 4811193323Sed for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4812193323Sed // Shift the previously computed bits over. 4813193323Sed NewBits <<= SrcBitSize; 4814193323Sed SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4815193323Sed if (Op.getOpcode() == ISD::UNDEF) continue; 4816193323Sed EltIsUndef = false; 4817193323Sed 4818218893Sdim NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 4819207618Srdivacky zextOrTrunc(SrcBitSize).zext(DstBitSize); 4820193323Sed } 4821193323Sed 4822193323Sed if (EltIsUndef) 4823193323Sed Ops.push_back(DAG.getUNDEF(DstEltVT)); 4824193323Sed else 4825193323Sed Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4826193323Sed } 4827193323Sed 4828198090Srdivacky EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4829193323Sed return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4830193323Sed &Ops[0], Ops.size()); 4831193323Sed } 4832193323Sed 4833193323Sed // Finally, this must be the case where we are shrinking elements: each input 4834193323Sed // turns into multiple outputs. 4835193323Sed bool isS2V = ISD::isScalarToVector(BV); 4836193323Sed unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4837198090Srdivacky EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4838198090Srdivacky NumOutputsPerInput*BV->getNumOperands()); 4839193323Sed SmallVector<SDValue, 8> Ops; 4840193323Sed 4841193323Sed for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4842193323Sed if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4843193323Sed for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4844193323Sed Ops.push_back(DAG.getUNDEF(DstEltVT)); 4845193323Sed continue; 4846193323Sed } 4847193323Sed 4848218893Sdim APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 4849218893Sdim getAPIntValue().zextOrTrunc(SrcBitSize); 4850193323Sed 4851193323Sed for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4852218893Sdim APInt ThisVal = OpVal.trunc(DstBitSize); 4853193323Sed Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4854218893Sdim if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 4855193323Sed // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4856193323Sed return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4857193323Sed Ops[0]); 4858193323Sed OpVal = OpVal.lshr(DstBitSize); 4859193323Sed } 4860193323Sed 4861193323Sed // For big endian targets, swap the order of the pieces of each element. 4862193323Sed if (TLI.isBigEndian()) 4863193323Sed std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4864193323Sed } 4865193323Sed 4866193323Sed return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4867193323Sed &Ops[0], Ops.size()); 4868193323Sed} 4869193323Sed 4870193323SedSDValue DAGCombiner::visitFADD(SDNode *N) { 4871193323Sed SDValue N0 = N->getOperand(0); 4872193323Sed SDValue N1 = N->getOperand(1); 4873193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4874193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4875198090Srdivacky EVT VT = N->getValueType(0); 4876193323Sed 4877193323Sed // fold vector ops 4878193323Sed if (VT.isVector()) { 4879193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 4880193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 4881193323Sed } 4882193323Sed 4883193323Sed // fold (fadd c1, c2) -> (fadd c1, c2) 4884193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 4885193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4886193323Sed // canonicalize constant to RHS 4887193323Sed if (N0CFP && !N1CFP) 4888193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4889193323Sed // fold (fadd A, 0) -> A 4890193323Sed if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4891193323Sed return N0; 4892193323Sed // fold (fadd A, (fneg B)) -> (fsub A, B) 4893193323Sed if (isNegatibleForFree(N1, LegalOperations) == 2) 4894193323Sed return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4895193323Sed GetNegatedExpression(N1, DAG, LegalOperations)); 4896193323Sed // fold (fadd (fneg A), B) -> (fsub B, A) 4897193323Sed if (isNegatibleForFree(N0, LegalOperations) == 2) 4898193323Sed return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4899193323Sed GetNegatedExpression(N0, DAG, LegalOperations)); 4900193323Sed 4901193323Sed // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4902193323Sed if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4903193323Sed N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4904193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4905193323Sed DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4906193323Sed N0.getOperand(1), N1)); 4907193323Sed 4908193323Sed return SDValue(); 4909193323Sed} 4910193323Sed 4911193323SedSDValue DAGCombiner::visitFSUB(SDNode *N) { 4912193323Sed SDValue N0 = N->getOperand(0); 4913193323Sed SDValue N1 = N->getOperand(1); 4914193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4915193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4916198090Srdivacky EVT VT = N->getValueType(0); 4917193323Sed 4918193323Sed // fold vector ops 4919193323Sed if (VT.isVector()) { 4920193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 4921193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 4922193323Sed } 4923193323Sed 4924193323Sed // fold (fsub c1, c2) -> c1-c2 4925193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 4926193323Sed return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4927193323Sed // fold (fsub A, 0) -> A 4928193323Sed if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4929193323Sed return N0; 4930193323Sed // fold (fsub 0, B) -> -B 4931193323Sed if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4932193323Sed if (isNegatibleForFree(N1, LegalOperations)) 4933193323Sed return GetNegatedExpression(N1, DAG, LegalOperations); 4934193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4935193323Sed return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4936193323Sed } 4937193323Sed // fold (fsub A, (fneg B)) -> (fadd A, B) 4938193323Sed if (isNegatibleForFree(N1, LegalOperations)) 4939193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4940193323Sed GetNegatedExpression(N1, DAG, LegalOperations)); 4941193323Sed 4942193323Sed return SDValue(); 4943193323Sed} 4944193323Sed 4945193323SedSDValue DAGCombiner::visitFMUL(SDNode *N) { 4946193323Sed SDValue N0 = N->getOperand(0); 4947193323Sed SDValue N1 = N->getOperand(1); 4948193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4949193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4950198090Srdivacky EVT VT = N->getValueType(0); 4951193323Sed 4952193323Sed // fold vector ops 4953193323Sed if (VT.isVector()) { 4954193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 4955193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 4956193323Sed } 4957193323Sed 4958193323Sed // fold (fmul c1, c2) -> c1*c2 4959193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 4960193323Sed return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4961193323Sed // canonicalize constant to RHS 4962193323Sed if (N0CFP && !N1CFP) 4963193323Sed return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4964193323Sed // fold (fmul A, 0) -> 0 4965193323Sed if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4966193323Sed return N1; 4967193574Sed // fold (fmul A, 0) -> 0, vector edition. 4968193574Sed if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4969193574Sed return N1; 4970193323Sed // fold (fmul X, 2.0) -> (fadd X, X) 4971193323Sed if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4972193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4973198090Srdivacky // fold (fmul X, -1.0) -> (fneg X) 4974193323Sed if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4975193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4976193323Sed return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4977193323Sed 4978193323Sed // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4979193323Sed if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4980193323Sed if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4981193323Sed // Both can be negated for free, check to see if at least one is cheaper 4982193323Sed // negated. 4983193323Sed if (LHSNeg == 2 || RHSNeg == 2) 4984193323Sed return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4985193323Sed GetNegatedExpression(N0, DAG, LegalOperations), 4986193323Sed GetNegatedExpression(N1, DAG, LegalOperations)); 4987193323Sed } 4988193323Sed } 4989193323Sed 4990193323Sed // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4991193323Sed if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4992193323Sed N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4993193323Sed return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4994193323Sed DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4995193323Sed N0.getOperand(1), N1)); 4996193323Sed 4997193323Sed return SDValue(); 4998193323Sed} 4999193323Sed 5000193323SedSDValue DAGCombiner::visitFDIV(SDNode *N) { 5001193323Sed SDValue N0 = N->getOperand(0); 5002193323Sed SDValue N1 = N->getOperand(1); 5003193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5004193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5005198090Srdivacky EVT VT = N->getValueType(0); 5006193323Sed 5007193323Sed // fold vector ops 5008193323Sed if (VT.isVector()) { 5009193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 5010193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 5011193323Sed } 5012193323Sed 5013193323Sed // fold (fdiv c1, c2) -> c1/c2 5014193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 5015193323Sed return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5016193323Sed 5017193323Sed 5018193323Sed // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5019193323Sed if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5020193323Sed if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5021193323Sed // Both can be negated for free, check to see if at least one is cheaper 5022193323Sed // negated. 5023193323Sed if (LHSNeg == 2 || RHSNeg == 2) 5024193323Sed return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5025193323Sed GetNegatedExpression(N0, DAG, LegalOperations), 5026193323Sed GetNegatedExpression(N1, DAG, LegalOperations)); 5027193323Sed } 5028193323Sed } 5029193323Sed 5030193323Sed return SDValue(); 5031193323Sed} 5032193323Sed 5033193323SedSDValue DAGCombiner::visitFREM(SDNode *N) { 5034193323Sed SDValue N0 = N->getOperand(0); 5035193323Sed SDValue N1 = N->getOperand(1); 5036193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5037193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5038198090Srdivacky EVT VT = N->getValueType(0); 5039193323Sed 5040193323Sed // fold (frem c1, c2) -> fmod(c1,c2) 5041193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 5042193323Sed return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5043193323Sed 5044193323Sed return SDValue(); 5045193323Sed} 5046193323Sed 5047193323SedSDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5048193323Sed SDValue N0 = N->getOperand(0); 5049193323Sed SDValue N1 = N->getOperand(1); 5050193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5051193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5052198090Srdivacky EVT VT = N->getValueType(0); 5053193323Sed 5054193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5055193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5056193323Sed 5057193323Sed if (N1CFP) { 5058193323Sed const APFloat& V = N1CFP->getValueAPF(); 5059193323Sed // copysign(x, c1) -> fabs(x) iff ispos(c1) 5060193323Sed // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5061193323Sed if (!V.isNegative()) { 5062193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5063193323Sed return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5064193323Sed } else { 5065193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5066193323Sed return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5067193323Sed DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5068193323Sed } 5069193323Sed } 5070193323Sed 5071193323Sed // copysign(fabs(x), y) -> copysign(x, y) 5072193323Sed // copysign(fneg(x), y) -> copysign(x, y) 5073193323Sed // copysign(copysign(x,z), y) -> copysign(x, y) 5074193323Sed if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5075193323Sed N0.getOpcode() == ISD::FCOPYSIGN) 5076193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5077193323Sed N0.getOperand(0), N1); 5078193323Sed 5079193323Sed // copysign(x, abs(y)) -> abs(x) 5080193323Sed if (N1.getOpcode() == ISD::FABS) 5081193323Sed return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5082193323Sed 5083193323Sed // copysign(x, copysign(y,z)) -> copysign(x, z) 5084193323Sed if (N1.getOpcode() == ISD::FCOPYSIGN) 5085193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5086193323Sed N0, N1.getOperand(1)); 5087193323Sed 5088193323Sed // copysign(x, fp_extend(y)) -> copysign(x, y) 5089193323Sed // copysign(x, fp_round(y)) -> copysign(x, y) 5090193323Sed if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5091193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5092193323Sed N0, N1.getOperand(0)); 5093193323Sed 5094193323Sed return SDValue(); 5095193323Sed} 5096193323Sed 5097193323SedSDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5098193323Sed SDValue N0 = N->getOperand(0); 5099193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5100198090Srdivacky EVT VT = N->getValueType(0); 5101198090Srdivacky EVT OpVT = N0.getValueType(); 5102193323Sed 5103193323Sed // fold (sint_to_fp c1) -> c1fp 5104193323Sed if (N0C && OpVT != MVT::ppcf128) 5105193323Sed return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5106193323Sed 5107193323Sed // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5108193323Sed // but UINT_TO_FP is legal on this target, try to convert. 5109193323Sed if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5110193323Sed TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5111193323Sed // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5112193323Sed if (DAG.SignBitIsZero(N0)) 5113193323Sed return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5114193323Sed } 5115193323Sed 5116193323Sed return SDValue(); 5117193323Sed} 5118193323Sed 5119193323SedSDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5120193323Sed SDValue N0 = N->getOperand(0); 5121193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5122198090Srdivacky EVT VT = N->getValueType(0); 5123198090Srdivacky EVT OpVT = N0.getValueType(); 5124193323Sed 5125193323Sed // fold (uint_to_fp c1) -> c1fp 5126193323Sed if (N0C && OpVT != MVT::ppcf128) 5127193323Sed return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5128193323Sed 5129193323Sed // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5130193323Sed // but SINT_TO_FP is legal on this target, try to convert. 5131193323Sed if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5132193323Sed TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5133193323Sed // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5134193323Sed if (DAG.SignBitIsZero(N0)) 5135193323Sed return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5136193323Sed } 5137193323Sed 5138193323Sed return SDValue(); 5139193323Sed} 5140193323Sed 5141193323SedSDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5142193323Sed SDValue N0 = N->getOperand(0); 5143193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5144198090Srdivacky EVT VT = N->getValueType(0); 5145193323Sed 5146193323Sed // fold (fp_to_sint c1fp) -> c1 5147193323Sed if (N0CFP) 5148193323Sed return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5149193323Sed 5150193323Sed return SDValue(); 5151193323Sed} 5152193323Sed 5153193323SedSDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5154193323Sed SDValue N0 = N->getOperand(0); 5155193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5156198090Srdivacky EVT VT = N->getValueType(0); 5157193323Sed 5158193323Sed // fold (fp_to_uint c1fp) -> c1 5159193323Sed if (N0CFP && VT != MVT::ppcf128) 5160193323Sed return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5161193323Sed 5162193323Sed return SDValue(); 5163193323Sed} 5164193323Sed 5165193323SedSDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5166193323Sed SDValue N0 = N->getOperand(0); 5167193323Sed SDValue N1 = N->getOperand(1); 5168193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5169198090Srdivacky EVT VT = N->getValueType(0); 5170193323Sed 5171193323Sed // fold (fp_round c1fp) -> c1fp 5172193323Sed if (N0CFP && N0.getValueType() != MVT::ppcf128) 5173193323Sed return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5174193323Sed 5175193323Sed // fold (fp_round (fp_extend x)) -> x 5176193323Sed if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5177193323Sed return N0.getOperand(0); 5178193323Sed 5179193323Sed // fold (fp_round (fp_round x)) -> (fp_round x) 5180193323Sed if (N0.getOpcode() == ISD::FP_ROUND) { 5181193323Sed // This is a value preserving truncation if both round's are. 5182193323Sed bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5183193323Sed N0.getNode()->getConstantOperandVal(1) == 1; 5184193323Sed return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5185193323Sed DAG.getIntPtrConstant(IsTrunc)); 5186193323Sed } 5187193323Sed 5188193323Sed // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5189193323Sed if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5190193323Sed SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5191193323Sed N0.getOperand(0), N1); 5192193323Sed AddToWorkList(Tmp.getNode()); 5193193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5194193323Sed Tmp, N0.getOperand(1)); 5195193323Sed } 5196193323Sed 5197193323Sed return SDValue(); 5198193323Sed} 5199193323Sed 5200193323SedSDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5201193323Sed SDValue N0 = N->getOperand(0); 5202198090Srdivacky EVT VT = N->getValueType(0); 5203198090Srdivacky EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5204193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5205193323Sed 5206193323Sed // fold (fp_round_inreg c1fp) -> c1fp 5207207618Srdivacky if (N0CFP && isTypeLegal(EVT)) { 5208193323Sed SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5209193323Sed return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5210193323Sed } 5211193323Sed 5212193323Sed return SDValue(); 5213193323Sed} 5214193323Sed 5215193323SedSDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5216193323Sed SDValue N0 = N->getOperand(0); 5217193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5218198090Srdivacky EVT VT = N->getValueType(0); 5219193323Sed 5220193323Sed // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5221193323Sed if (N->hasOneUse() && 5222193323Sed N->use_begin()->getOpcode() == ISD::FP_ROUND) 5223193323Sed return SDValue(); 5224193323Sed 5225193323Sed // fold (fp_extend c1fp) -> c1fp 5226193323Sed if (N0CFP && VT != MVT::ppcf128) 5227193323Sed return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5228193323Sed 5229193323Sed // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5230193323Sed // value of X. 5231193323Sed if (N0.getOpcode() == ISD::FP_ROUND 5232193323Sed && N0.getNode()->getConstantOperandVal(1) == 1) { 5233193323Sed SDValue In = N0.getOperand(0); 5234193323Sed if (In.getValueType() == VT) return In; 5235193323Sed if (VT.bitsLT(In.getValueType())) 5236193323Sed return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5237193323Sed In, N0.getOperand(1)); 5238193323Sed return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5239193323Sed } 5240193323Sed 5241193323Sed // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5242193323Sed if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5243193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5244193323Sed TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5245193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5246218893Sdim SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5247193323Sed LN0->getChain(), 5248218893Sdim LN0->getBasePtr(), LN0->getPointerInfo(), 5249193323Sed N0.getValueType(), 5250203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), 5251203954Srdivacky LN0->getAlignment()); 5252193323Sed CombineTo(N, ExtLoad); 5253193323Sed CombineTo(N0.getNode(), 5254193323Sed DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5255193323Sed N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5256193323Sed ExtLoad.getValue(1)); 5257193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 5258193323Sed } 5259193323Sed 5260193323Sed return SDValue(); 5261193323Sed} 5262193323Sed 5263193323SedSDValue DAGCombiner::visitFNEG(SDNode *N) { 5264193323Sed SDValue N0 = N->getOperand(0); 5265198396Srdivacky EVT VT = N->getValueType(0); 5266193323Sed 5267193323Sed if (isNegatibleForFree(N0, LegalOperations)) 5268193323Sed return GetNegatedExpression(N0, DAG, LegalOperations); 5269193323Sed 5270193323Sed // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5271193323Sed // constant pool values. 5272218893Sdim if (N0.getOpcode() == ISD::BITCAST && 5273198396Srdivacky !VT.isVector() && 5274198396Srdivacky N0.getNode()->hasOneUse() && 5275198396Srdivacky N0.getOperand(0).getValueType().isInteger()) { 5276193323Sed SDValue Int = N0.getOperand(0); 5277198090Srdivacky EVT IntVT = Int.getValueType(); 5278193323Sed if (IntVT.isInteger() && !IntVT.isVector()) { 5279193323Sed Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5280193323Sed DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5281193323Sed AddToWorkList(Int.getNode()); 5282218893Sdim return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5283198396Srdivacky VT, Int); 5284193323Sed } 5285193323Sed } 5286193323Sed 5287193323Sed return SDValue(); 5288193323Sed} 5289193323Sed 5290193323SedSDValue DAGCombiner::visitFABS(SDNode *N) { 5291193323Sed SDValue N0 = N->getOperand(0); 5292193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5293198090Srdivacky EVT VT = N->getValueType(0); 5294193323Sed 5295193323Sed // fold (fabs c1) -> fabs(c1) 5296193323Sed if (N0CFP && VT != MVT::ppcf128) 5297193323Sed return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5298193323Sed // fold (fabs (fabs x)) -> (fabs x) 5299193323Sed if (N0.getOpcode() == ISD::FABS) 5300193323Sed return N->getOperand(0); 5301193323Sed // fold (fabs (fneg x)) -> (fabs x) 5302193323Sed // fold (fabs (fcopysign x, y)) -> (fabs x) 5303193323Sed if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5304193323Sed return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5305193323Sed 5306193323Sed // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5307193323Sed // constant pool values. 5308218893Sdim if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5309193323Sed N0.getOperand(0).getValueType().isInteger() && 5310193323Sed !N0.getOperand(0).getValueType().isVector()) { 5311193323Sed SDValue Int = N0.getOperand(0); 5312198090Srdivacky EVT IntVT = Int.getValueType(); 5313193323Sed if (IntVT.isInteger() && !IntVT.isVector()) { 5314193323Sed Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5315193323Sed DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5316193323Sed AddToWorkList(Int.getNode()); 5317218893Sdim return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5318193323Sed N->getValueType(0), Int); 5319193323Sed } 5320193323Sed } 5321193323Sed 5322193323Sed return SDValue(); 5323193323Sed} 5324193323Sed 5325193323SedSDValue DAGCombiner::visitBRCOND(SDNode *N) { 5326193323Sed SDValue Chain = N->getOperand(0); 5327193323Sed SDValue N1 = N->getOperand(1); 5328193323Sed SDValue N2 = N->getOperand(2); 5329193323Sed 5330199481Srdivacky // If N is a constant we could fold this into a fallthrough or unconditional 5331199481Srdivacky // branch. However that doesn't happen very often in normal code, because 5332199481Srdivacky // Instcombine/SimplifyCFG should have handled the available opportunities. 5333199481Srdivacky // If we did this folding here, it would be necessary to update the 5334199481Srdivacky // MachineBasicBlock CFG, which is awkward. 5335199481Srdivacky 5336193323Sed // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5337193323Sed // on the target. 5338193323Sed if (N1.getOpcode() == ISD::SETCC && 5339193323Sed TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5340193323Sed return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5341193323Sed Chain, N1.getOperand(2), 5342193323Sed N1.getOperand(0), N1.getOperand(1), N2); 5343193323Sed } 5344193323Sed 5345218893Sdim if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5346218893Sdim ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5347218893Sdim (N1.getOperand(0).hasOneUse() && 5348218893Sdim N1.getOperand(0).getOpcode() == ISD::SRL))) { 5349218893Sdim SDNode *Trunc = 0; 5350218893Sdim if (N1.getOpcode() == ISD::TRUNCATE) { 5351218893Sdim // Look pass the truncate. 5352218893Sdim Trunc = N1.getNode(); 5353218893Sdim N1 = N1.getOperand(0); 5354218893Sdim } 5355202375Srdivacky 5356193323Sed // Match this pattern so that we can generate simpler code: 5357193323Sed // 5358193323Sed // %a = ... 5359193323Sed // %b = and i32 %a, 2 5360193323Sed // %c = srl i32 %b, 1 5361193323Sed // brcond i32 %c ... 5362193323Sed // 5363193323Sed // into 5364218893Sdim // 5365193323Sed // %a = ... 5366202375Srdivacky // %b = and i32 %a, 2 5367193323Sed // %c = setcc eq %b, 0 5368193323Sed // brcond %c ... 5369193323Sed // 5370193323Sed // This applies only when the AND constant value has one bit set and the 5371193323Sed // SRL constant is equal to the log2 of the AND constant. The back-end is 5372193323Sed // smart enough to convert the result into a TEST/JMP sequence. 5373193323Sed SDValue Op0 = N1.getOperand(0); 5374193323Sed SDValue Op1 = N1.getOperand(1); 5375193323Sed 5376193323Sed if (Op0.getOpcode() == ISD::AND && 5377193323Sed Op1.getOpcode() == ISD::Constant) { 5378193323Sed SDValue AndOp1 = Op0.getOperand(1); 5379193323Sed 5380193323Sed if (AndOp1.getOpcode() == ISD::Constant) { 5381193323Sed const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5382193323Sed 5383193323Sed if (AndConst.isPowerOf2() && 5384193323Sed cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5385193323Sed SDValue SetCC = 5386193323Sed DAG.getSetCC(N->getDebugLoc(), 5387193323Sed TLI.getSetCCResultType(Op0.getValueType()), 5388193323Sed Op0, DAG.getConstant(0, Op0.getValueType()), 5389193323Sed ISD::SETNE); 5390193323Sed 5391202375Srdivacky SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5392202375Srdivacky MVT::Other, Chain, SetCC, N2); 5393202375Srdivacky // Don't add the new BRCond into the worklist or else SimplifySelectCC 5394202375Srdivacky // will convert it back to (X & C1) >> C2. 5395202375Srdivacky CombineTo(N, NewBRCond, false); 5396202375Srdivacky // Truncate is dead. 5397202375Srdivacky if (Trunc) { 5398202375Srdivacky removeFromWorkList(Trunc); 5399202375Srdivacky DAG.DeleteNode(Trunc); 5400202375Srdivacky } 5401193323Sed // Replace the uses of SRL with SETCC 5402204642Srdivacky WorkListRemover DeadNodes(*this); 5403204642Srdivacky DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5404193323Sed removeFromWorkList(N1.getNode()); 5405193323Sed DAG.DeleteNode(N1.getNode()); 5406202375Srdivacky return SDValue(N, 0); // Return N so it doesn't get rechecked! 5407193323Sed } 5408193323Sed } 5409193323Sed } 5410218893Sdim 5411218893Sdim if (Trunc) 5412218893Sdim // Restore N1 if the above transformation doesn't match. 5413218893Sdim N1 = N->getOperand(1); 5414193323Sed } 5415218893Sdim 5416204642Srdivacky // Transform br(xor(x, y)) -> br(x != y) 5417204642Srdivacky // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5418204642Srdivacky if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5419204642Srdivacky SDNode *TheXor = N1.getNode(); 5420204642Srdivacky SDValue Op0 = TheXor->getOperand(0); 5421204642Srdivacky SDValue Op1 = TheXor->getOperand(1); 5422204642Srdivacky if (Op0.getOpcode() == Op1.getOpcode()) { 5423204642Srdivacky // Avoid missing important xor optimizations. 5424204642Srdivacky SDValue Tmp = visitXOR(TheXor); 5425207618Srdivacky if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5426204642Srdivacky DEBUG(dbgs() << "\nReplacing.8 "; 5427204642Srdivacky TheXor->dump(&DAG); 5428204642Srdivacky dbgs() << "\nWith: "; 5429204642Srdivacky Tmp.getNode()->dump(&DAG); 5430204642Srdivacky dbgs() << '\n'); 5431204642Srdivacky WorkListRemover DeadNodes(*this); 5432204642Srdivacky DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5433204642Srdivacky removeFromWorkList(TheXor); 5434204642Srdivacky DAG.DeleteNode(TheXor); 5435204642Srdivacky return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5436204642Srdivacky MVT::Other, Chain, Tmp, N2); 5437204642Srdivacky } 5438204642Srdivacky } 5439193323Sed 5440204642Srdivacky if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5441204642Srdivacky bool Equal = false; 5442204642Srdivacky if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5443204642Srdivacky if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5444204642Srdivacky Op0.getOpcode() == ISD::XOR) { 5445204642Srdivacky TheXor = Op0.getNode(); 5446204642Srdivacky Equal = true; 5447204642Srdivacky } 5448204642Srdivacky 5449218893Sdim EVT SetCCVT = N1.getValueType(); 5450204642Srdivacky if (LegalTypes) 5451204642Srdivacky SetCCVT = TLI.getSetCCResultType(SetCCVT); 5452204642Srdivacky SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5453204642Srdivacky SetCCVT, 5454204642Srdivacky Op0, Op1, 5455204642Srdivacky Equal ? ISD::SETEQ : ISD::SETNE); 5456204642Srdivacky // Replace the uses of XOR with SETCC 5457204642Srdivacky WorkListRemover DeadNodes(*this); 5458218893Sdim DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5459218893Sdim removeFromWorkList(N1.getNode()); 5460218893Sdim DAG.DeleteNode(N1.getNode()); 5461204642Srdivacky return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5462204642Srdivacky MVT::Other, Chain, SetCC, N2); 5463204642Srdivacky } 5464204642Srdivacky } 5465204642Srdivacky 5466193323Sed return SDValue(); 5467193323Sed} 5468193323Sed 5469193323Sed// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5470193323Sed// 5471193323SedSDValue DAGCombiner::visitBR_CC(SDNode *N) { 5472193323Sed CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5473193323Sed SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5474193323Sed 5475199481Srdivacky // If N is a constant we could fold this into a fallthrough or unconditional 5476199481Srdivacky // branch. However that doesn't happen very often in normal code, because 5477199481Srdivacky // Instcombine/SimplifyCFG should have handled the available opportunities. 5478199481Srdivacky // If we did this folding here, it would be necessary to update the 5479199481Srdivacky // MachineBasicBlock CFG, which is awkward. 5480199481Srdivacky 5481193323Sed // Use SimplifySetCC to simplify SETCC's. 5482193323Sed SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5483193323Sed CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5484193323Sed false); 5485193323Sed if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5486193323Sed 5487193323Sed // fold to a simpler setcc 5488193323Sed if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5489193323Sed return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5490193323Sed N->getOperand(0), Simp.getOperand(2), 5491193323Sed Simp.getOperand(0), Simp.getOperand(1), 5492193323Sed N->getOperand(4)); 5493193323Sed 5494193323Sed return SDValue(); 5495193323Sed} 5496193323Sed 5497193323Sed/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5498193323Sed/// pre-indexed load / store when the base pointer is an add or subtract 5499193323Sed/// and it has other uses besides the load / store. After the 5500193323Sed/// transformation, the new indexed load / store has effectively folded 5501193323Sed/// the add / subtract in and all of its other uses are redirected to the 5502193323Sed/// new load / store. 5503193323Sedbool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5504193323Sed if (!LegalOperations) 5505193323Sed return false; 5506193323Sed 5507193323Sed bool isLoad = true; 5508193323Sed SDValue Ptr; 5509198090Srdivacky EVT VT; 5510193323Sed if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5511193323Sed if (LD->isIndexed()) 5512193323Sed return false; 5513193323Sed VT = LD->getMemoryVT(); 5514193323Sed if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5515193323Sed !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5516193323Sed return false; 5517193323Sed Ptr = LD->getBasePtr(); 5518193323Sed } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5519193323Sed if (ST->isIndexed()) 5520193323Sed return false; 5521193323Sed VT = ST->getMemoryVT(); 5522193323Sed if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5523193323Sed !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5524193323Sed return false; 5525193323Sed Ptr = ST->getBasePtr(); 5526193323Sed isLoad = false; 5527193323Sed } else { 5528193323Sed return false; 5529193323Sed } 5530193323Sed 5531193323Sed // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5532193323Sed // out. There is no reason to make this a preinc/predec. 5533193323Sed if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5534193323Sed Ptr.getNode()->hasOneUse()) 5535193323Sed return false; 5536193323Sed 5537193323Sed // Ask the target to do addressing mode selection. 5538193323Sed SDValue BasePtr; 5539193323Sed SDValue Offset; 5540193323Sed ISD::MemIndexedMode AM = ISD::UNINDEXED; 5541193323Sed if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5542193323Sed return false; 5543193323Sed // Don't create a indexed load / store with zero offset. 5544193323Sed if (isa<ConstantSDNode>(Offset) && 5545193323Sed cast<ConstantSDNode>(Offset)->isNullValue()) 5546193323Sed return false; 5547193323Sed 5548193323Sed // Try turning it into a pre-indexed load / store except when: 5549193323Sed // 1) The new base ptr is a frame index. 5550193323Sed // 2) If N is a store and the new base ptr is either the same as or is a 5551193323Sed // predecessor of the value being stored. 5552193323Sed // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5553193323Sed // that would create a cycle. 5554193323Sed // 4) All uses are load / store ops that use it as old base ptr. 5555193323Sed 5556193323Sed // Check #1. Preinc'ing a frame index would require copying the stack pointer 5557193323Sed // (plus the implicit offset) to a register to preinc anyway. 5558193323Sed if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5559193323Sed return false; 5560193323Sed 5561193323Sed // Check #2. 5562193323Sed if (!isLoad) { 5563193323Sed SDValue Val = cast<StoreSDNode>(N)->getValue(); 5564193323Sed if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5565193323Sed return false; 5566193323Sed } 5567193323Sed 5568193323Sed // Now check for #3 and #4. 5569193323Sed bool RealUse = false; 5570193323Sed for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5571193323Sed E = Ptr.getNode()->use_end(); I != E; ++I) { 5572193323Sed SDNode *Use = *I; 5573193323Sed if (Use == N) 5574193323Sed continue; 5575193323Sed if (Use->isPredecessorOf(N)) 5576193323Sed return false; 5577193323Sed 5578193323Sed if (!((Use->getOpcode() == ISD::LOAD && 5579193323Sed cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5580193323Sed (Use->getOpcode() == ISD::STORE && 5581193323Sed cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5582193323Sed RealUse = true; 5583193323Sed } 5584193323Sed 5585193323Sed if (!RealUse) 5586193323Sed return false; 5587193323Sed 5588193323Sed SDValue Result; 5589193323Sed if (isLoad) 5590193323Sed Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5591193323Sed BasePtr, Offset, AM); 5592193323Sed else 5593193323Sed Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5594193323Sed BasePtr, Offset, AM); 5595193323Sed ++PreIndexedNodes; 5596193323Sed ++NodesCombined; 5597202375Srdivacky DEBUG(dbgs() << "\nReplacing.4 "; 5598198090Srdivacky N->dump(&DAG); 5599202375Srdivacky dbgs() << "\nWith: "; 5600198090Srdivacky Result.getNode()->dump(&DAG); 5601202375Srdivacky dbgs() << '\n'); 5602193323Sed WorkListRemover DeadNodes(*this); 5603193323Sed if (isLoad) { 5604193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5605193323Sed &DeadNodes); 5606193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5607193323Sed &DeadNodes); 5608193323Sed } else { 5609193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5610193323Sed &DeadNodes); 5611193323Sed } 5612193323Sed 5613193323Sed // Finally, since the node is now dead, remove it from the graph. 5614193323Sed DAG.DeleteNode(N); 5615193323Sed 5616193323Sed // Replace the uses of Ptr with uses of the updated base value. 5617193323Sed DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5618193323Sed &DeadNodes); 5619193323Sed removeFromWorkList(Ptr.getNode()); 5620193323Sed DAG.DeleteNode(Ptr.getNode()); 5621193323Sed 5622193323Sed return true; 5623193323Sed} 5624193323Sed 5625193323Sed/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5626193323Sed/// add / sub of the base pointer node into a post-indexed load / store. 5627193323Sed/// The transformation folded the add / subtract into the new indexed 5628193323Sed/// load / store effectively and all of its uses are redirected to the 5629193323Sed/// new load / store. 5630193323Sedbool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5631193323Sed if (!LegalOperations) 5632193323Sed return false; 5633193323Sed 5634193323Sed bool isLoad = true; 5635193323Sed SDValue Ptr; 5636198090Srdivacky EVT VT; 5637193323Sed if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5638193323Sed if (LD->isIndexed()) 5639193323Sed return false; 5640193323Sed VT = LD->getMemoryVT(); 5641193323Sed if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5642193323Sed !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5643193323Sed return false; 5644193323Sed Ptr = LD->getBasePtr(); 5645193323Sed } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5646193323Sed if (ST->isIndexed()) 5647193323Sed return false; 5648193323Sed VT = ST->getMemoryVT(); 5649193323Sed if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5650193323Sed !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5651193323Sed return false; 5652193323Sed Ptr = ST->getBasePtr(); 5653193323Sed isLoad = false; 5654193323Sed } else { 5655193323Sed return false; 5656193323Sed } 5657193323Sed 5658193323Sed if (Ptr.getNode()->hasOneUse()) 5659193323Sed return false; 5660193323Sed 5661193323Sed for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5662193323Sed E = Ptr.getNode()->use_end(); I != E; ++I) { 5663193323Sed SDNode *Op = *I; 5664193323Sed if (Op == N || 5665193323Sed (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5666193323Sed continue; 5667193323Sed 5668193323Sed SDValue BasePtr; 5669193323Sed SDValue Offset; 5670193323Sed ISD::MemIndexedMode AM = ISD::UNINDEXED; 5671193323Sed if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5672193323Sed // Don't create a indexed load / store with zero offset. 5673193323Sed if (isa<ConstantSDNode>(Offset) && 5674193323Sed cast<ConstantSDNode>(Offset)->isNullValue()) 5675193323Sed continue; 5676193323Sed 5677193323Sed // Try turning it into a post-indexed load / store except when 5678193323Sed // 1) All uses are load / store ops that use it as base ptr. 5679193323Sed // 2) Op must be independent of N, i.e. Op is neither a predecessor 5680193323Sed // nor a successor of N. Otherwise, if Op is folded that would 5681193323Sed // create a cycle. 5682193323Sed 5683193323Sed if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5684193323Sed continue; 5685193323Sed 5686193323Sed // Check for #1. 5687193323Sed bool TryNext = false; 5688193323Sed for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5689193323Sed EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5690193323Sed SDNode *Use = *II; 5691193323Sed if (Use == Ptr.getNode()) 5692193323Sed continue; 5693193323Sed 5694193323Sed // If all the uses are load / store addresses, then don't do the 5695193323Sed // transformation. 5696193323Sed if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5697193323Sed bool RealUse = false; 5698193323Sed for (SDNode::use_iterator III = Use->use_begin(), 5699193323Sed EEE = Use->use_end(); III != EEE; ++III) { 5700193323Sed SDNode *UseUse = *III; 5701193323Sed if (!((UseUse->getOpcode() == ISD::LOAD && 5702193323Sed cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5703193323Sed (UseUse->getOpcode() == ISD::STORE && 5704193323Sed cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5705193323Sed RealUse = true; 5706193323Sed } 5707193323Sed 5708193323Sed if (!RealUse) { 5709193323Sed TryNext = true; 5710193323Sed break; 5711193323Sed } 5712193323Sed } 5713193323Sed } 5714193323Sed 5715193323Sed if (TryNext) 5716193323Sed continue; 5717193323Sed 5718193323Sed // Check for #2 5719193323Sed if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5720193323Sed SDValue Result = isLoad 5721193323Sed ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5722193323Sed BasePtr, Offset, AM) 5723193323Sed : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5724193323Sed BasePtr, Offset, AM); 5725193323Sed ++PostIndexedNodes; 5726193323Sed ++NodesCombined; 5727202375Srdivacky DEBUG(dbgs() << "\nReplacing.5 "; 5728198090Srdivacky N->dump(&DAG); 5729202375Srdivacky dbgs() << "\nWith: "; 5730198090Srdivacky Result.getNode()->dump(&DAG); 5731202375Srdivacky dbgs() << '\n'); 5732193323Sed WorkListRemover DeadNodes(*this); 5733193323Sed if (isLoad) { 5734193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5735193323Sed &DeadNodes); 5736193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5737193323Sed &DeadNodes); 5738193323Sed } else { 5739193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5740193323Sed &DeadNodes); 5741193323Sed } 5742193323Sed 5743193323Sed // Finally, since the node is now dead, remove it from the graph. 5744193323Sed DAG.DeleteNode(N); 5745193323Sed 5746193323Sed // Replace the uses of Use with uses of the updated base value. 5747193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5748193323Sed Result.getValue(isLoad ? 1 : 0), 5749193323Sed &DeadNodes); 5750193323Sed removeFromWorkList(Op); 5751193323Sed DAG.DeleteNode(Op); 5752193323Sed return true; 5753193323Sed } 5754193323Sed } 5755193323Sed } 5756193323Sed 5757193323Sed return false; 5758193323Sed} 5759193323Sed 5760193323SedSDValue DAGCombiner::visitLOAD(SDNode *N) { 5761193323Sed LoadSDNode *LD = cast<LoadSDNode>(N); 5762193323Sed SDValue Chain = LD->getChain(); 5763193323Sed SDValue Ptr = LD->getBasePtr(); 5764193323Sed 5765193323Sed // If load is not volatile and there are no uses of the loaded value (and 5766193323Sed // the updated indexed value in case of indexed loads), change uses of the 5767193323Sed // chain value into uses of the chain input (i.e. delete the dead load). 5768193323Sed if (!LD->isVolatile()) { 5769193323Sed if (N->getValueType(1) == MVT::Other) { 5770193323Sed // Unindexed loads. 5771193323Sed if (N->hasNUsesOfValue(0, 0)) { 5772193323Sed // It's not safe to use the two value CombineTo variant here. e.g. 5773193323Sed // v1, chain2 = load chain1, loc 5774193323Sed // v2, chain3 = load chain2, loc 5775193323Sed // v3 = add v2, c 5776193323Sed // Now we replace use of chain2 with chain1. This makes the second load 5777193323Sed // isomorphic to the one we are deleting, and thus makes this load live. 5778202375Srdivacky DEBUG(dbgs() << "\nReplacing.6 "; 5779198090Srdivacky N->dump(&DAG); 5780202375Srdivacky dbgs() << "\nWith chain: "; 5781198090Srdivacky Chain.getNode()->dump(&DAG); 5782202375Srdivacky dbgs() << "\n"); 5783193323Sed WorkListRemover DeadNodes(*this); 5784193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5785193323Sed 5786193323Sed if (N->use_empty()) { 5787193323Sed removeFromWorkList(N); 5788193323Sed DAG.DeleteNode(N); 5789193323Sed } 5790193323Sed 5791193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 5792193323Sed } 5793193323Sed } else { 5794193323Sed // Indexed loads. 5795193323Sed assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5796193323Sed if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5797193323Sed SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5798204642Srdivacky DEBUG(dbgs() << "\nReplacing.7 "; 5799198090Srdivacky N->dump(&DAG); 5800202375Srdivacky dbgs() << "\nWith: "; 5801198090Srdivacky Undef.getNode()->dump(&DAG); 5802202375Srdivacky dbgs() << " and 2 other values\n"); 5803193323Sed WorkListRemover DeadNodes(*this); 5804193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5805193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5806193323Sed DAG.getUNDEF(N->getValueType(1)), 5807193323Sed &DeadNodes); 5808193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5809193323Sed removeFromWorkList(N); 5810193323Sed DAG.DeleteNode(N); 5811193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 5812193323Sed } 5813193323Sed } 5814193323Sed } 5815193323Sed 5816193323Sed // If this load is directly stored, replace the load value with the stored 5817193323Sed // value. 5818193323Sed // TODO: Handle store large -> read small portion. 5819193323Sed // TODO: Handle TRUNCSTORE/LOADEXT 5820193323Sed if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5821193323Sed !LD->isVolatile()) { 5822193323Sed if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5823193323Sed StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5824193323Sed if (PrevST->getBasePtr() == Ptr && 5825193323Sed PrevST->getValue().getValueType() == N->getValueType(0)) 5826193323Sed return CombineTo(N, Chain.getOperand(1), Chain); 5827193323Sed } 5828193323Sed } 5829193323Sed 5830206083Srdivacky // Try to infer better alignment information than the load already has. 5831206083Srdivacky if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5832206083Srdivacky if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5833206083Srdivacky if (Align > LD->getAlignment()) 5834218893Sdim return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5835218893Sdim LD->getValueType(0), 5836218893Sdim Chain, Ptr, LD->getPointerInfo(), 5837218893Sdim LD->getMemoryVT(), 5838206083Srdivacky LD->isVolatile(), LD->isNonTemporal(), Align); 5839206083Srdivacky } 5840206083Srdivacky } 5841206083Srdivacky 5842193323Sed if (CombinerAA) { 5843193323Sed // Walk up chain skipping non-aliasing memory nodes. 5844193323Sed SDValue BetterChain = FindBetterChain(N, Chain); 5845193323Sed 5846193323Sed // If there is a better chain. 5847193323Sed if (Chain != BetterChain) { 5848193323Sed SDValue ReplLoad; 5849193323Sed 5850193323Sed // Replace the chain to void dependency. 5851193323Sed if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5852193323Sed ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5853218893Sdim BetterChain, Ptr, LD->getPointerInfo(), 5854203954Srdivacky LD->isVolatile(), LD->isNonTemporal(), 5855203954Srdivacky LD->getAlignment()); 5856193323Sed } else { 5857218893Sdim ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5858218893Sdim LD->getValueType(0), 5859218893Sdim BetterChain, Ptr, LD->getPointerInfo(), 5860193323Sed LD->getMemoryVT(), 5861193323Sed LD->isVolatile(), 5862203954Srdivacky LD->isNonTemporal(), 5863193323Sed LD->getAlignment()); 5864193323Sed } 5865193323Sed 5866193323Sed // Create token factor to keep old chain connected. 5867193323Sed SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5868193323Sed MVT::Other, Chain, ReplLoad.getValue(1)); 5869218893Sdim 5870198090Srdivacky // Make sure the new and old chains are cleaned up. 5871198090Srdivacky AddToWorkList(Token.getNode()); 5872218893Sdim 5873193323Sed // Replace uses with load result and token factor. Don't add users 5874193323Sed // to work list. 5875193323Sed return CombineTo(N, ReplLoad.getValue(0), Token, false); 5876193323Sed } 5877193323Sed } 5878193323Sed 5879193323Sed // Try transforming N to an indexed load. 5880193323Sed if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5881193323Sed return SDValue(N, 0); 5882193323Sed 5883193323Sed return SDValue(); 5884193323Sed} 5885193323Sed 5886207618Srdivacky/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5887207618Srdivacky/// load is having specific bytes cleared out. If so, return the byte size 5888207618Srdivacky/// being masked out and the shift amount. 5889207618Srdivackystatic std::pair<unsigned, unsigned> 5890207618SrdivackyCheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5891207618Srdivacky std::pair<unsigned, unsigned> Result(0, 0); 5892218893Sdim 5893207618Srdivacky // Check for the structure we're looking for. 5894207618Srdivacky if (V->getOpcode() != ISD::AND || 5895207618Srdivacky !isa<ConstantSDNode>(V->getOperand(1)) || 5896207618Srdivacky !ISD::isNormalLoad(V->getOperand(0).getNode())) 5897207618Srdivacky return Result; 5898218893Sdim 5899207618Srdivacky // Check the chain and pointer. 5900207618Srdivacky LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5901207618Srdivacky if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5902218893Sdim 5903207618Srdivacky // The store should be chained directly to the load or be an operand of a 5904207618Srdivacky // tokenfactor. 5905207618Srdivacky if (LD == Chain.getNode()) 5906207618Srdivacky ; // ok. 5907207618Srdivacky else if (Chain->getOpcode() != ISD::TokenFactor) 5908207618Srdivacky return Result; // Fail. 5909207618Srdivacky else { 5910207618Srdivacky bool isOk = false; 5911207618Srdivacky for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5912207618Srdivacky if (Chain->getOperand(i).getNode() == LD) { 5913207618Srdivacky isOk = true; 5914207618Srdivacky break; 5915207618Srdivacky } 5916207618Srdivacky if (!isOk) return Result; 5917207618Srdivacky } 5918218893Sdim 5919207618Srdivacky // This only handles simple types. 5920207618Srdivacky if (V.getValueType() != MVT::i16 && 5921207618Srdivacky V.getValueType() != MVT::i32 && 5922207618Srdivacky V.getValueType() != MVT::i64) 5923207618Srdivacky return Result; 5924193323Sed 5925207618Srdivacky // Check the constant mask. Invert it so that the bits being masked out are 5926207618Srdivacky // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5927207618Srdivacky // follow the sign bit for uniformity. 5928207618Srdivacky uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5929207618Srdivacky unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5930207618Srdivacky if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5931207618Srdivacky unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5932207618Srdivacky if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5933207618Srdivacky if (NotMaskLZ == 64) return Result; // All zero mask. 5934218893Sdim 5935207618Srdivacky // See if we have a continuous run of bits. If so, we have 0*1+0* 5936207618Srdivacky if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5937207618Srdivacky return Result; 5938207618Srdivacky 5939207618Srdivacky // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5940207618Srdivacky if (V.getValueType() != MVT::i64 && NotMaskLZ) 5941207618Srdivacky NotMaskLZ -= 64-V.getValueSizeInBits(); 5942218893Sdim 5943207618Srdivacky unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5944207618Srdivacky switch (MaskedBytes) { 5945218893Sdim case 1: 5946218893Sdim case 2: 5947207618Srdivacky case 4: break; 5948207618Srdivacky default: return Result; // All one mask, or 5-byte mask. 5949207618Srdivacky } 5950218893Sdim 5951207618Srdivacky // Verify that the first bit starts at a multiple of mask so that the access 5952207618Srdivacky // is aligned the same as the access width. 5953207618Srdivacky if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5954218893Sdim 5955207618Srdivacky Result.first = MaskedBytes; 5956207618Srdivacky Result.second = NotMaskTZ/8; 5957207618Srdivacky return Result; 5958207618Srdivacky} 5959207618Srdivacky 5960207618Srdivacky 5961207618Srdivacky/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5962207618Srdivacky/// provides a value as specified by MaskInfo. If so, replace the specified 5963207618Srdivacky/// store with a narrower store of truncated IVal. 5964207618Srdivackystatic SDNode * 5965207618SrdivackyShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5966207618Srdivacky SDValue IVal, StoreSDNode *St, 5967207618Srdivacky DAGCombiner *DC) { 5968207618Srdivacky unsigned NumBytes = MaskInfo.first; 5969207618Srdivacky unsigned ByteShift = MaskInfo.second; 5970207618Srdivacky SelectionDAG &DAG = DC->getDAG(); 5971218893Sdim 5972207618Srdivacky // Check to see if IVal is all zeros in the part being masked in by the 'or' 5973207618Srdivacky // that uses this. If not, this is not a replacement. 5974207618Srdivacky APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5975207618Srdivacky ByteShift*8, (ByteShift+NumBytes)*8); 5976207618Srdivacky if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5977218893Sdim 5978207618Srdivacky // Check that it is legal on the target to do this. It is legal if the new 5979207618Srdivacky // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5980207618Srdivacky // legalization. 5981207618Srdivacky MVT VT = MVT::getIntegerVT(NumBytes*8); 5982207618Srdivacky if (!DC->isTypeLegal(VT)) 5983207618Srdivacky return 0; 5984218893Sdim 5985207618Srdivacky // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5986207618Srdivacky // shifted by ByteShift and truncated down to NumBytes. 5987207618Srdivacky if (ByteShift) 5988207618Srdivacky IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5989219077Sdim DAG.getConstant(ByteShift*8, 5990219077Sdim DC->getShiftAmountTy(IVal.getValueType()))); 5991207618Srdivacky 5992207618Srdivacky // Figure out the offset for the store and the alignment of the access. 5993207618Srdivacky unsigned StOffset; 5994207618Srdivacky unsigned NewAlign = St->getAlignment(); 5995207618Srdivacky 5996207618Srdivacky if (DAG.getTargetLoweringInfo().isLittleEndian()) 5997207618Srdivacky StOffset = ByteShift; 5998207618Srdivacky else 5999207618Srdivacky StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6000218893Sdim 6001207618Srdivacky SDValue Ptr = St->getBasePtr(); 6002207618Srdivacky if (StOffset) { 6003207618Srdivacky Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6004207618Srdivacky Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6005207618Srdivacky NewAlign = MinAlign(NewAlign, StOffset); 6006207618Srdivacky } 6007218893Sdim 6008207618Srdivacky // Truncate down to the new size. 6009207618Srdivacky IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6010218893Sdim 6011207618Srdivacky ++OpsNarrowed; 6012218893Sdim return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6013218893Sdim St->getPointerInfo().getWithOffset(StOffset), 6014207618Srdivacky false, false, NewAlign).getNode(); 6015207618Srdivacky} 6016207618Srdivacky 6017207618Srdivacky 6018193323Sed/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6019193323Sed/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6020193323Sed/// of the loaded bits, try narrowing the load and store if it would end up 6021193323Sed/// being a win for performance or code size. 6022193323SedSDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6023193323Sed StoreSDNode *ST = cast<StoreSDNode>(N); 6024193323Sed if (ST->isVolatile()) 6025193323Sed return SDValue(); 6026193323Sed 6027193323Sed SDValue Chain = ST->getChain(); 6028193323Sed SDValue Value = ST->getValue(); 6029193323Sed SDValue Ptr = ST->getBasePtr(); 6030198090Srdivacky EVT VT = Value.getValueType(); 6031193323Sed 6032193323Sed if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6033193323Sed return SDValue(); 6034193323Sed 6035193323Sed unsigned Opc = Value.getOpcode(); 6036218893Sdim 6037207618Srdivacky // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6038207618Srdivacky // is a byte mask indicating a consecutive number of bytes, check to see if 6039207618Srdivacky // Y is known to provide just those bytes. If so, we try to replace the 6040207618Srdivacky // load + replace + store sequence with a single (narrower) store, which makes 6041207618Srdivacky // the load dead. 6042207618Srdivacky if (Opc == ISD::OR) { 6043207618Srdivacky std::pair<unsigned, unsigned> MaskedLoad; 6044207618Srdivacky MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6045207618Srdivacky if (MaskedLoad.first) 6046207618Srdivacky if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6047207618Srdivacky Value.getOperand(1), ST,this)) 6048207618Srdivacky return SDValue(NewST, 0); 6049218893Sdim 6050207618Srdivacky // Or is commutative, so try swapping X and Y. 6051207618Srdivacky MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6052207618Srdivacky if (MaskedLoad.first) 6053207618Srdivacky if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6054207618Srdivacky Value.getOperand(0), ST,this)) 6055207618Srdivacky return SDValue(NewST, 0); 6056207618Srdivacky } 6057218893Sdim 6058193323Sed if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6059193323Sed Value.getOperand(1).getOpcode() != ISD::Constant) 6060193323Sed return SDValue(); 6061193323Sed 6062193323Sed SDValue N0 = Value.getOperand(0); 6063212904Sdim if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6064212904Sdim Chain == SDValue(N0.getNode(), 1)) { 6065193323Sed LoadSDNode *LD = cast<LoadSDNode>(N0); 6066218893Sdim if (LD->getBasePtr() != Ptr || 6067218893Sdim LD->getPointerInfo().getAddrSpace() != 6068218893Sdim ST->getPointerInfo().getAddrSpace()) 6069193323Sed return SDValue(); 6070193323Sed 6071193323Sed // Find the type to narrow it the load / op / store to. 6072193323Sed SDValue N1 = Value.getOperand(1); 6073193323Sed unsigned BitWidth = N1.getValueSizeInBits(); 6074193323Sed APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6075193323Sed if (Opc == ISD::AND) 6076193323Sed Imm ^= APInt::getAllOnesValue(BitWidth); 6077193323Sed if (Imm == 0 || Imm.isAllOnesValue()) 6078193323Sed return SDValue(); 6079193323Sed unsigned ShAmt = Imm.countTrailingZeros(); 6080193323Sed unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6081193323Sed unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6082198090Srdivacky EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6083193323Sed while (NewBW < BitWidth && 6084193323Sed !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6085193323Sed TLI.isNarrowingProfitable(VT, NewVT))) { 6086193323Sed NewBW = NextPowerOf2(NewBW); 6087198090Srdivacky NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6088193323Sed } 6089193323Sed if (NewBW >= BitWidth) 6090193323Sed return SDValue(); 6091193323Sed 6092193323Sed // If the lsb changed does not start at the type bitwidth boundary, 6093193323Sed // start at the previous one. 6094193323Sed if (ShAmt % NewBW) 6095193323Sed ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6096193323Sed APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6097193323Sed if ((Imm & Mask) == Imm) { 6098193323Sed APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6099193323Sed if (Opc == ISD::AND) 6100193323Sed NewImm ^= APInt::getAllOnesValue(NewBW); 6101193323Sed uint64_t PtrOff = ShAmt / 8; 6102193323Sed // For big endian targets, we need to adjust the offset to the pointer to 6103193323Sed // load the correct bytes. 6104193323Sed if (TLI.isBigEndian()) 6105193323Sed PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6106193323Sed 6107193323Sed unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6108207618Srdivacky const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6109207618Srdivacky if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6110193323Sed return SDValue(); 6111193323Sed 6112193323Sed SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6113193323Sed Ptr.getValueType(), Ptr, 6114193323Sed DAG.getConstant(PtrOff, Ptr.getValueType())); 6115193323Sed SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6116193323Sed LD->getChain(), NewPtr, 6117218893Sdim LD->getPointerInfo().getWithOffset(PtrOff), 6118203954Srdivacky LD->isVolatile(), LD->isNonTemporal(), 6119203954Srdivacky NewAlign); 6120193323Sed SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6121193323Sed DAG.getConstant(NewImm, NewVT)); 6122193323Sed SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6123193323Sed NewVal, NewPtr, 6124218893Sdim ST->getPointerInfo().getWithOffset(PtrOff), 6125203954Srdivacky false, false, NewAlign); 6126193323Sed 6127193323Sed AddToWorkList(NewPtr.getNode()); 6128193323Sed AddToWorkList(NewLD.getNode()); 6129193323Sed AddToWorkList(NewVal.getNode()); 6130193323Sed WorkListRemover DeadNodes(*this); 6131193323Sed DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6132193323Sed &DeadNodes); 6133193323Sed ++OpsNarrowed; 6134193323Sed return NewST; 6135193323Sed } 6136193323Sed } 6137193323Sed 6138193323Sed return SDValue(); 6139193323Sed} 6140193323Sed 6141218893Sdim/// TransformFPLoadStorePair - For a given floating point load / store pair, 6142218893Sdim/// if the load value isn't used by any other operations, then consider 6143218893Sdim/// transforming the pair to integer load / store operations if the target 6144218893Sdim/// deems the transformation profitable. 6145218893SdimSDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6146218893Sdim StoreSDNode *ST = cast<StoreSDNode>(N); 6147218893Sdim SDValue Chain = ST->getChain(); 6148218893Sdim SDValue Value = ST->getValue(); 6149218893Sdim if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6150218893Sdim Value.hasOneUse() && 6151218893Sdim Chain == SDValue(Value.getNode(), 1)) { 6152218893Sdim LoadSDNode *LD = cast<LoadSDNode>(Value); 6153218893Sdim EVT VT = LD->getMemoryVT(); 6154218893Sdim if (!VT.isFloatingPoint() || 6155218893Sdim VT != ST->getMemoryVT() || 6156218893Sdim LD->isNonTemporal() || 6157218893Sdim ST->isNonTemporal() || 6158218893Sdim LD->getPointerInfo().getAddrSpace() != 0 || 6159218893Sdim ST->getPointerInfo().getAddrSpace() != 0) 6160218893Sdim return SDValue(); 6161218893Sdim 6162218893Sdim EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6163218893Sdim if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6164218893Sdim !TLI.isOperationLegal(ISD::STORE, IntVT) || 6165218893Sdim !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6166218893Sdim !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6167218893Sdim return SDValue(); 6168218893Sdim 6169218893Sdim unsigned LDAlign = LD->getAlignment(); 6170218893Sdim unsigned STAlign = ST->getAlignment(); 6171218893Sdim const Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6172218893Sdim unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6173218893Sdim if (LDAlign < ABIAlign || STAlign < ABIAlign) 6174218893Sdim return SDValue(); 6175218893Sdim 6176218893Sdim SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6177218893Sdim LD->getChain(), LD->getBasePtr(), 6178218893Sdim LD->getPointerInfo(), 6179218893Sdim false, false, LDAlign); 6180218893Sdim 6181218893Sdim SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6182218893Sdim NewLD, ST->getBasePtr(), 6183218893Sdim ST->getPointerInfo(), 6184218893Sdim false, false, STAlign); 6185218893Sdim 6186218893Sdim AddToWorkList(NewLD.getNode()); 6187218893Sdim AddToWorkList(NewST.getNode()); 6188218893Sdim WorkListRemover DeadNodes(*this); 6189218893Sdim DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6190218893Sdim &DeadNodes); 6191218893Sdim ++LdStFP2Int; 6192218893Sdim return NewST; 6193218893Sdim } 6194218893Sdim 6195218893Sdim return SDValue(); 6196218893Sdim} 6197218893Sdim 6198193323SedSDValue DAGCombiner::visitSTORE(SDNode *N) { 6199193323Sed StoreSDNode *ST = cast<StoreSDNode>(N); 6200193323Sed SDValue Chain = ST->getChain(); 6201193323Sed SDValue Value = ST->getValue(); 6202193323Sed SDValue Ptr = ST->getBasePtr(); 6203193323Sed 6204193323Sed // If this is a store of a bit convert, store the input value if the 6205193323Sed // resultant store does not need a higher alignment than the original. 6206218893Sdim if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6207193323Sed ST->isUnindexed()) { 6208193323Sed unsigned OrigAlign = ST->getAlignment(); 6209198090Srdivacky EVT SVT = Value.getOperand(0).getValueType(); 6210193323Sed unsigned Align = TLI.getTargetData()-> 6211198090Srdivacky getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6212193323Sed if (Align <= OrigAlign && 6213193323Sed ((!LegalOperations && !ST->isVolatile()) || 6214193323Sed TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6215193323Sed return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6216218893Sdim Ptr, ST->getPointerInfo(), ST->isVolatile(), 6217203954Srdivacky ST->isNonTemporal(), OrigAlign); 6218193323Sed } 6219193323Sed 6220193323Sed // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6221193323Sed if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6222193323Sed // NOTE: If the original store is volatile, this transform must not increase 6223193323Sed // the number of stores. For example, on x86-32 an f64 can be stored in one 6224193323Sed // processor operation but an i64 (which is not legal) requires two. So the 6225193323Sed // transform should not be done in this case. 6226193323Sed if (Value.getOpcode() != ISD::TargetConstantFP) { 6227193323Sed SDValue Tmp; 6228198090Srdivacky switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6229198090Srdivacky default: llvm_unreachable("Unknown FP type"); 6230193323Sed case MVT::f80: // We don't do this for these yet. 6231193323Sed case MVT::f128: 6232193323Sed case MVT::ppcf128: 6233193323Sed break; 6234193323Sed case MVT::f32: 6235207618Srdivacky if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6236193323Sed TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6237193323Sed Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6238193323Sed bitcastToAPInt().getZExtValue(), MVT::i32); 6239193323Sed return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6240218893Sdim Ptr, ST->getPointerInfo(), ST->isVolatile(), 6241203954Srdivacky ST->isNonTemporal(), ST->getAlignment()); 6242193323Sed } 6243193323Sed break; 6244193323Sed case MVT::f64: 6245207618Srdivacky if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6246193323Sed !ST->isVolatile()) || 6247193323Sed TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6248193323Sed Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6249193323Sed getZExtValue(), MVT::i64); 6250193323Sed return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6251218893Sdim Ptr, ST->getPointerInfo(), ST->isVolatile(), 6252203954Srdivacky ST->isNonTemporal(), ST->getAlignment()); 6253193323Sed } else if (!ST->isVolatile() && 6254193323Sed TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6255193323Sed // Many FP stores are not made apparent until after legalize, e.g. for 6256193323Sed // argument passing. Since this is so common, custom legalize the 6257193323Sed // 64-bit integer store into two 32-bit stores. 6258193323Sed uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6259193323Sed SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6260193323Sed SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6261193323Sed if (TLI.isBigEndian()) std::swap(Lo, Hi); 6262193323Sed 6263193323Sed unsigned Alignment = ST->getAlignment(); 6264193323Sed bool isVolatile = ST->isVolatile(); 6265203954Srdivacky bool isNonTemporal = ST->isNonTemporal(); 6266193323Sed 6267193323Sed SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6268218893Sdim Ptr, ST->getPointerInfo(), 6269203954Srdivacky isVolatile, isNonTemporal, 6270203954Srdivacky ST->getAlignment()); 6271193323Sed Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6272193323Sed DAG.getConstant(4, Ptr.getValueType())); 6273193323Sed Alignment = MinAlign(Alignment, 4U); 6274193323Sed SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6275218893Sdim Ptr, ST->getPointerInfo().getWithOffset(4), 6276218893Sdim isVolatile, isNonTemporal, 6277203954Srdivacky Alignment); 6278193323Sed return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6279193323Sed St0, St1); 6280193323Sed } 6281193323Sed 6282193323Sed break; 6283193323Sed } 6284193323Sed } 6285193323Sed } 6286193323Sed 6287206083Srdivacky // Try to infer better alignment information than the store already has. 6288206083Srdivacky if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6289206083Srdivacky if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6290206083Srdivacky if (Align > ST->getAlignment()) 6291206083Srdivacky return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6292218893Sdim Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6293206083Srdivacky ST->isVolatile(), ST->isNonTemporal(), Align); 6294206083Srdivacky } 6295206083Srdivacky } 6296206083Srdivacky 6297218893Sdim // Try transforming a pair floating point load / store ops to integer 6298218893Sdim // load / store ops. 6299218893Sdim SDValue NewST = TransformFPLoadStorePair(N); 6300218893Sdim if (NewST.getNode()) 6301218893Sdim return NewST; 6302218893Sdim 6303193323Sed if (CombinerAA) { 6304193323Sed // Walk up chain skipping non-aliasing memory nodes. 6305193323Sed SDValue BetterChain = FindBetterChain(N, Chain); 6306193323Sed 6307193323Sed // If there is a better chain. 6308193323Sed if (Chain != BetterChain) { 6309198090Srdivacky SDValue ReplStore; 6310198090Srdivacky 6311193323Sed // Replace the chain to avoid dependency. 6312193323Sed if (ST->isTruncatingStore()) { 6313193323Sed ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6314218893Sdim ST->getPointerInfo(), 6315203954Srdivacky ST->getMemoryVT(), ST->isVolatile(), 6316203954Srdivacky ST->isNonTemporal(), ST->getAlignment()); 6317193323Sed } else { 6318193323Sed ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6319218893Sdim ST->getPointerInfo(), 6320203954Srdivacky ST->isVolatile(), ST->isNonTemporal(), 6321203954Srdivacky ST->getAlignment()); 6322193323Sed } 6323193323Sed 6324193323Sed // Create token to keep both nodes around. 6325193323Sed SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6326193323Sed MVT::Other, Chain, ReplStore); 6327193323Sed 6328198090Srdivacky // Make sure the new and old chains are cleaned up. 6329198090Srdivacky AddToWorkList(Token.getNode()); 6330198090Srdivacky 6331193323Sed // Don't add users to work list. 6332193323Sed return CombineTo(N, Token, false); 6333193323Sed } 6334193323Sed } 6335193323Sed 6336193323Sed // Try transforming N to an indexed store. 6337193323Sed if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6338193323Sed return SDValue(N, 0); 6339193323Sed 6340193323Sed // FIXME: is there such a thing as a truncating indexed store? 6341193323Sed if (ST->isTruncatingStore() && ST->isUnindexed() && 6342193323Sed Value.getValueType().isInteger()) { 6343193323Sed // See if we can simplify the input to this truncstore with knowledge that 6344193323Sed // only the low bits are being used. For example: 6345193323Sed // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6346193323Sed SDValue Shorter = 6347193323Sed GetDemandedBits(Value, 6348193323Sed APInt::getLowBitsSet(Value.getValueSizeInBits(), 6349193323Sed ST->getMemoryVT().getSizeInBits())); 6350193323Sed AddToWorkList(Value.getNode()); 6351193323Sed if (Shorter.getNode()) 6352193323Sed return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6353218893Sdim Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6354203954Srdivacky ST->isVolatile(), ST->isNonTemporal(), 6355203954Srdivacky ST->getAlignment()); 6356193323Sed 6357193323Sed // Otherwise, see if we can simplify the operation with 6358193323Sed // SimplifyDemandedBits, which only works if the value has a single use. 6359193323Sed if (SimplifyDemandedBits(Value, 6360218893Sdim APInt::getLowBitsSet( 6361218893Sdim Value.getValueType().getScalarType().getSizeInBits(), 6362218893Sdim ST->getMemoryVT().getScalarType().getSizeInBits()))) 6363193323Sed return SDValue(N, 0); 6364193323Sed } 6365193323Sed 6366193323Sed // If this is a load followed by a store to the same location, then the store 6367193323Sed // is dead/noop. 6368193323Sed if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6369193323Sed if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6370193323Sed ST->isUnindexed() && !ST->isVolatile() && 6371193323Sed // There can't be any side effects between the load and store, such as 6372193323Sed // a call or store. 6373193323Sed Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6374193323Sed // The store is dead, remove it. 6375193323Sed return Chain; 6376193323Sed } 6377193323Sed } 6378193323Sed 6379193323Sed // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6380193323Sed // truncating store. We can do this even if this is already a truncstore. 6381193323Sed if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6382193323Sed && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6383193323Sed TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6384193323Sed ST->getMemoryVT())) { 6385193323Sed return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6386218893Sdim Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6387203954Srdivacky ST->isVolatile(), ST->isNonTemporal(), 6388203954Srdivacky ST->getAlignment()); 6389193323Sed } 6390193323Sed 6391193323Sed return ReduceLoadOpStoreWidth(N); 6392193323Sed} 6393193323Sed 6394193323SedSDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6395193323Sed SDValue InVec = N->getOperand(0); 6396193323Sed SDValue InVal = N->getOperand(1); 6397193323Sed SDValue EltNo = N->getOperand(2); 6398193323Sed 6399208599Srdivacky // If the inserted element is an UNDEF, just use the input vector. 6400208599Srdivacky if (InVal.getOpcode() == ISD::UNDEF) 6401208599Srdivacky return InVec; 6402208599Srdivacky 6403218893Sdim EVT VT = InVec.getValueType(); 6404218893Sdim 6405219077Sdim // If we can't generate a legal BUILD_VECTOR, exit 6406218893Sdim if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 6407218893Sdim return SDValue(); 6408218893Sdim 6409193323Sed // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6410193323Sed // vector with the inserted element. 6411193323Sed if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6412193323Sed unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6413193323Sed SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6414193323Sed InVec.getNode()->op_end()); 6415193323Sed if (Elt < Ops.size()) 6416193323Sed Ops[Elt] = InVal; 6417193323Sed return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6418218893Sdim VT, &Ops[0], Ops.size()); 6419193323Sed } 6420218893Sdim // If the invec is an UNDEF and if EltNo is a constant, create a new 6421193323Sed // BUILD_VECTOR with undef elements and the inserted element. 6422218893Sdim if (InVec.getOpcode() == ISD::UNDEF && 6423193323Sed isa<ConstantSDNode>(EltNo)) { 6424198090Srdivacky EVT EltVT = VT.getVectorElementType(); 6425193323Sed unsigned NElts = VT.getVectorNumElements(); 6426198090Srdivacky SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6427193323Sed 6428193323Sed unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6429193323Sed if (Elt < Ops.size()) 6430193323Sed Ops[Elt] = InVal; 6431193323Sed return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6432218893Sdim VT, &Ops[0], Ops.size()); 6433193323Sed } 6434193323Sed return SDValue(); 6435193323Sed} 6436193323Sed 6437193323SedSDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6438193323Sed // (vextract (scalar_to_vector val, 0) -> val 6439193323Sed SDValue InVec = N->getOperand(0); 6440193323Sed 6441193323Sed if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6442203954Srdivacky // Check if the result type doesn't match the inserted element type. A 6443203954Srdivacky // SCALAR_TO_VECTOR may truncate the inserted element and the 6444203954Srdivacky // EXTRACT_VECTOR_ELT may widen the extracted vector. 6445193323Sed SDValue InOp = InVec.getOperand(0); 6446203954Srdivacky EVT NVT = N->getValueType(0); 6447203954Srdivacky if (InOp.getValueType() != NVT) { 6448203954Srdivacky assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6449203954Srdivacky return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6450203954Srdivacky } 6451193323Sed return InOp; 6452193323Sed } 6453193323Sed 6454193323Sed // Perform only after legalization to ensure build_vector / vector_shuffle 6455193323Sed // optimizations have already been done. 6456193323Sed if (!LegalOperations) return SDValue(); 6457193323Sed 6458193323Sed // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6459193323Sed // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6460193323Sed // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6461193323Sed SDValue EltNo = N->getOperand(1); 6462193323Sed 6463193323Sed if (isa<ConstantSDNode>(EltNo)) { 6464218893Sdim int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6465193323Sed bool NewLoad = false; 6466193323Sed bool BCNumEltsChanged = false; 6467198090Srdivacky EVT VT = InVec.getValueType(); 6468198090Srdivacky EVT ExtVT = VT.getVectorElementType(); 6469198090Srdivacky EVT LVT = ExtVT; 6470193323Sed 6471218893Sdim if (InVec.getOpcode() == ISD::BITCAST) { 6472198090Srdivacky EVT BCVT = InVec.getOperand(0).getValueType(); 6473198090Srdivacky if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6474193323Sed return SDValue(); 6475193323Sed if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6476193323Sed BCNumEltsChanged = true; 6477193323Sed InVec = InVec.getOperand(0); 6478198090Srdivacky ExtVT = BCVT.getVectorElementType(); 6479193323Sed NewLoad = true; 6480193323Sed } 6481193323Sed 6482193323Sed LoadSDNode *LN0 = NULL; 6483193323Sed const ShuffleVectorSDNode *SVN = NULL; 6484193323Sed if (ISD::isNormalLoad(InVec.getNode())) { 6485193323Sed LN0 = cast<LoadSDNode>(InVec); 6486193323Sed } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6487198090Srdivacky InVec.getOperand(0).getValueType() == ExtVT && 6488193323Sed ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6489193323Sed LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6490193323Sed } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6491193323Sed // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6492193323Sed // => 6493193323Sed // (load $addr+1*size) 6494193323Sed 6495193323Sed // If the bit convert changed the number of elements, it is unsafe 6496193323Sed // to examine the mask. 6497193323Sed if (BCNumEltsChanged) 6498193323Sed return SDValue(); 6499193323Sed 6500193323Sed // Select the input vector, guarding against out of range extract vector. 6501193323Sed unsigned NumElems = VT.getVectorNumElements(); 6502218893Sdim int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6503193323Sed InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6504193323Sed 6505218893Sdim if (InVec.getOpcode() == ISD::BITCAST) 6506193323Sed InVec = InVec.getOperand(0); 6507193323Sed if (ISD::isNormalLoad(InVec.getNode())) { 6508193323Sed LN0 = cast<LoadSDNode>(InVec); 6509207618Srdivacky Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6510193323Sed } 6511193323Sed } 6512193323Sed 6513193323Sed if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 6514193323Sed return SDValue(); 6515193323Sed 6516218893Sdim // If Idx was -1 above, Elt is going to be -1, so just return undef. 6517218893Sdim if (Elt == -1) 6518218893Sdim return DAG.getUNDEF(LN0->getBasePtr().getValueType()); 6519218893Sdim 6520193323Sed unsigned Align = LN0->getAlignment(); 6521193323Sed if (NewLoad) { 6522193323Sed // Check the resultant load doesn't need a higher alignment than the 6523193323Sed // original load. 6524193323Sed unsigned NewAlign = 6525218893Sdim TLI.getTargetData() 6526218893Sdim ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6527193323Sed 6528193323Sed if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6529193323Sed return SDValue(); 6530193323Sed 6531193323Sed Align = NewAlign; 6532193323Sed } 6533193323Sed 6534193323Sed SDValue NewPtr = LN0->getBasePtr(); 6535218893Sdim unsigned PtrOff = 0; 6536218893Sdim 6537193323Sed if (Elt) { 6538218893Sdim PtrOff = LVT.getSizeInBits() * Elt / 8; 6539198090Srdivacky EVT PtrType = NewPtr.getValueType(); 6540193323Sed if (TLI.isBigEndian()) 6541193323Sed PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6542193323Sed NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6543193323Sed DAG.getConstant(PtrOff, PtrType)); 6544193323Sed } 6545193323Sed 6546193323Sed return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6547218893Sdim LN0->getPointerInfo().getWithOffset(PtrOff), 6548203954Srdivacky LN0->isVolatile(), LN0->isNonTemporal(), Align); 6549193323Sed } 6550193323Sed 6551193323Sed return SDValue(); 6552193323Sed} 6553193323Sed 6554193323SedSDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6555193323Sed unsigned NumInScalars = N->getNumOperands(); 6556198090Srdivacky EVT VT = N->getValueType(0); 6557193323Sed 6558193323Sed // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6559193323Sed // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6560193323Sed // at most two distinct vectors, turn this into a shuffle node. 6561193323Sed SDValue VecIn1, VecIn2; 6562193323Sed for (unsigned i = 0; i != NumInScalars; ++i) { 6563193323Sed // Ignore undef inputs. 6564193323Sed if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6565193323Sed 6566193323Sed // If this input is something other than a EXTRACT_VECTOR_ELT with a 6567193323Sed // constant index, bail out. 6568193323Sed if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6569193323Sed !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6570193323Sed VecIn1 = VecIn2 = SDValue(0, 0); 6571193323Sed break; 6572193323Sed } 6573193323Sed 6574193323Sed // If the input vector type disagrees with the result of the build_vector, 6575193323Sed // we can't make a shuffle. 6576193323Sed SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6577193323Sed if (ExtractedFromVec.getValueType() != VT) { 6578193323Sed VecIn1 = VecIn2 = SDValue(0, 0); 6579193323Sed break; 6580193323Sed } 6581193323Sed 6582193323Sed // Otherwise, remember this. We allow up to two distinct input vectors. 6583193323Sed if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6584193323Sed continue; 6585193323Sed 6586193323Sed if (VecIn1.getNode() == 0) { 6587193323Sed VecIn1 = ExtractedFromVec; 6588193323Sed } else if (VecIn2.getNode() == 0) { 6589193323Sed VecIn2 = ExtractedFromVec; 6590193323Sed } else { 6591193323Sed // Too many inputs. 6592193323Sed VecIn1 = VecIn2 = SDValue(0, 0); 6593193323Sed break; 6594193323Sed } 6595193323Sed } 6596193323Sed 6597193323Sed // If everything is good, we can make a shuffle operation. 6598193323Sed if (VecIn1.getNode()) { 6599193323Sed SmallVector<int, 8> Mask; 6600193323Sed for (unsigned i = 0; i != NumInScalars; ++i) { 6601193323Sed if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6602193323Sed Mask.push_back(-1); 6603193323Sed continue; 6604193323Sed } 6605193323Sed 6606193323Sed // If extracting from the first vector, just use the index directly. 6607193323Sed SDValue Extract = N->getOperand(i); 6608193323Sed SDValue ExtVal = Extract.getOperand(1); 6609193323Sed if (Extract.getOperand(0) == VecIn1) { 6610193323Sed unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6611193323Sed if (ExtIndex > VT.getVectorNumElements()) 6612193323Sed return SDValue(); 6613218893Sdim 6614193323Sed Mask.push_back(ExtIndex); 6615193323Sed continue; 6616193323Sed } 6617193323Sed 6618193323Sed // Otherwise, use InIdx + VecSize 6619193323Sed unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6620193323Sed Mask.push_back(Idx+NumInScalars); 6621193323Sed } 6622193323Sed 6623193323Sed // Add count and size info. 6624207618Srdivacky if (!isTypeLegal(VT)) 6625193323Sed return SDValue(); 6626193323Sed 6627193323Sed // Return the new VECTOR_SHUFFLE node. 6628193323Sed SDValue Ops[2]; 6629193323Sed Ops[0] = VecIn1; 6630193323Sed Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6631193323Sed return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6632193323Sed } 6633193323Sed 6634193323Sed return SDValue(); 6635193323Sed} 6636193323Sed 6637193323SedSDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6638193323Sed // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6639193323Sed // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6640193323Sed // inputs come from at most two distinct vectors, turn this into a shuffle 6641193323Sed // node. 6642193323Sed 6643193323Sed // If we only have one input vector, we don't need to do any concatenation. 6644193323Sed if (N->getNumOperands() == 1) 6645193323Sed return N->getOperand(0); 6646193323Sed 6647193323Sed return SDValue(); 6648193323Sed} 6649193323Sed 6650193323SedSDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6651198090Srdivacky EVT VT = N->getValueType(0); 6652193323Sed unsigned NumElts = VT.getVectorNumElements(); 6653193323Sed 6654193323Sed SDValue N0 = N->getOperand(0); 6655193323Sed 6656193323Sed assert(N0.getValueType().getVectorNumElements() == NumElts && 6657193323Sed "Vector shuffle must be normalized in DAG"); 6658193323Sed 6659193323Sed // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6660193323Sed 6661218893Sdim // If it is a splat, check if the argument vector is another splat or a 6662218893Sdim // build_vector with all scalar elements the same. 6663218893Sdim ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 6664218893Sdim if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 6665193323Sed SDNode *V = N0.getNode(); 6666193323Sed 6667193323Sed // If this is a bit convert that changes the element type of the vector but 6668193323Sed // not the number of vector elements, look through it. Be careful not to 6669193323Sed // look though conversions that change things like v4f32 to v2f64. 6670218893Sdim if (V->getOpcode() == ISD::BITCAST) { 6671193323Sed SDValue ConvInput = V->getOperand(0); 6672193323Sed if (ConvInput.getValueType().isVector() && 6673193323Sed ConvInput.getValueType().getVectorNumElements() == NumElts) 6674193323Sed V = ConvInput.getNode(); 6675193323Sed } 6676193323Sed 6677193323Sed if (V->getOpcode() == ISD::BUILD_VECTOR) { 6678218893Sdim assert(V->getNumOperands() == NumElts && 6679218893Sdim "BUILD_VECTOR has wrong number of operands"); 6680218893Sdim SDValue Base; 6681218893Sdim bool AllSame = true; 6682218893Sdim for (unsigned i = 0; i != NumElts; ++i) { 6683218893Sdim if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6684218893Sdim Base = V->getOperand(i); 6685218893Sdim break; 6686193323Sed } 6687218893Sdim } 6688218893Sdim // Splat of <u, u, u, u>, return <u, u, u, u> 6689218893Sdim if (!Base.getNode()) 6690218893Sdim return N0; 6691218893Sdim for (unsigned i = 0; i != NumElts; ++i) { 6692218893Sdim if (V->getOperand(i) != Base) { 6693218893Sdim AllSame = false; 6694218893Sdim break; 6695193323Sed } 6696193323Sed } 6697218893Sdim // Splat of <x, x, x, x>, return <x, x, x, x> 6698218893Sdim if (AllSame) 6699218893Sdim return N0; 6700193323Sed } 6701193323Sed } 6702193323Sed return SDValue(); 6703193323Sed} 6704193323Sed 6705210299SedSDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6706210299Sed if (!TLI.getShouldFoldAtomicFences()) 6707210299Sed return SDValue(); 6708210299Sed 6709210299Sed SDValue atomic = N->getOperand(0); 6710210299Sed switch (atomic.getOpcode()) { 6711210299Sed case ISD::ATOMIC_CMP_SWAP: 6712210299Sed case ISD::ATOMIC_SWAP: 6713210299Sed case ISD::ATOMIC_LOAD_ADD: 6714210299Sed case ISD::ATOMIC_LOAD_SUB: 6715210299Sed case ISD::ATOMIC_LOAD_AND: 6716210299Sed case ISD::ATOMIC_LOAD_OR: 6717210299Sed case ISD::ATOMIC_LOAD_XOR: 6718210299Sed case ISD::ATOMIC_LOAD_NAND: 6719210299Sed case ISD::ATOMIC_LOAD_MIN: 6720210299Sed case ISD::ATOMIC_LOAD_MAX: 6721210299Sed case ISD::ATOMIC_LOAD_UMIN: 6722210299Sed case ISD::ATOMIC_LOAD_UMAX: 6723210299Sed break; 6724210299Sed default: 6725210299Sed return SDValue(); 6726210299Sed } 6727210299Sed 6728210299Sed SDValue fence = atomic.getOperand(0); 6729210299Sed if (fence.getOpcode() != ISD::MEMBARRIER) 6730210299Sed return SDValue(); 6731210299Sed 6732210299Sed switch (atomic.getOpcode()) { 6733210299Sed case ISD::ATOMIC_CMP_SWAP: 6734210299Sed return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6735210299Sed fence.getOperand(0), 6736210299Sed atomic.getOperand(1), atomic.getOperand(2), 6737210299Sed atomic.getOperand(3)), atomic.getResNo()); 6738210299Sed case ISD::ATOMIC_SWAP: 6739210299Sed case ISD::ATOMIC_LOAD_ADD: 6740210299Sed case ISD::ATOMIC_LOAD_SUB: 6741210299Sed case ISD::ATOMIC_LOAD_AND: 6742210299Sed case ISD::ATOMIC_LOAD_OR: 6743210299Sed case ISD::ATOMIC_LOAD_XOR: 6744210299Sed case ISD::ATOMIC_LOAD_NAND: 6745210299Sed case ISD::ATOMIC_LOAD_MIN: 6746210299Sed case ISD::ATOMIC_LOAD_MAX: 6747210299Sed case ISD::ATOMIC_LOAD_UMIN: 6748210299Sed case ISD::ATOMIC_LOAD_UMAX: 6749210299Sed return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6750210299Sed fence.getOperand(0), 6751210299Sed atomic.getOperand(1), atomic.getOperand(2)), 6752210299Sed atomic.getResNo()); 6753210299Sed default: 6754210299Sed return SDValue(); 6755210299Sed } 6756210299Sed} 6757210299Sed 6758193323Sed/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6759193323Sed/// an AND to a vector_shuffle with the destination vector and a zero vector. 6760193323Sed/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6761193323Sed/// vector_shuffle V, Zero, <0, 4, 2, 4> 6762193323SedSDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6763198090Srdivacky EVT VT = N->getValueType(0); 6764193323Sed DebugLoc dl = N->getDebugLoc(); 6765193323Sed SDValue LHS = N->getOperand(0); 6766193323Sed SDValue RHS = N->getOperand(1); 6767193323Sed if (N->getOpcode() == ISD::AND) { 6768218893Sdim if (RHS.getOpcode() == ISD::BITCAST) 6769193323Sed RHS = RHS.getOperand(0); 6770193323Sed if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6771193323Sed SmallVector<int, 8> Indices; 6772193323Sed unsigned NumElts = RHS.getNumOperands(); 6773193323Sed for (unsigned i = 0; i != NumElts; ++i) { 6774193323Sed SDValue Elt = RHS.getOperand(i); 6775193323Sed if (!isa<ConstantSDNode>(Elt)) 6776193323Sed return SDValue(); 6777193323Sed else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6778193323Sed Indices.push_back(i); 6779193323Sed else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6780193323Sed Indices.push_back(NumElts); 6781193323Sed else 6782193323Sed return SDValue(); 6783193323Sed } 6784193323Sed 6785193323Sed // Let's see if the target supports this vector_shuffle. 6786198090Srdivacky EVT RVT = RHS.getValueType(); 6787193323Sed if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6788193323Sed return SDValue(); 6789193323Sed 6790193323Sed // Return the new VECTOR_SHUFFLE node. 6791198090Srdivacky EVT EltVT = RVT.getVectorElementType(); 6792193323Sed SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6793198090Srdivacky DAG.getConstant(0, EltVT)); 6794193323Sed SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6795193323Sed RVT, &ZeroOps[0], ZeroOps.size()); 6796218893Sdim LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 6797193323Sed SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6798218893Sdim return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 6799193323Sed } 6800193323Sed } 6801193323Sed 6802193323Sed return SDValue(); 6803193323Sed} 6804193323Sed 6805193323Sed/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6806193323SedSDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6807193323Sed // After legalize, the target may be depending on adds and other 6808193323Sed // binary ops to provide legal ways to construct constants or other 6809193323Sed // things. Simplifying them may result in a loss of legality. 6810193323Sed if (LegalOperations) return SDValue(); 6811193323Sed 6812218893Sdim assert(N->getValueType(0).isVector() && 6813218893Sdim "SimplifyVBinOp only works on vectors!"); 6814193323Sed 6815193323Sed SDValue LHS = N->getOperand(0); 6816193323Sed SDValue RHS = N->getOperand(1); 6817193323Sed SDValue Shuffle = XformToShuffleWithZero(N); 6818193323Sed if (Shuffle.getNode()) return Shuffle; 6819193323Sed 6820193323Sed // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6821193323Sed // this operation. 6822193323Sed if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6823193323Sed RHS.getOpcode() == ISD::BUILD_VECTOR) { 6824193323Sed SmallVector<SDValue, 8> Ops; 6825193323Sed for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6826193323Sed SDValue LHSOp = LHS.getOperand(i); 6827193323Sed SDValue RHSOp = RHS.getOperand(i); 6828193323Sed // If these two elements can't be folded, bail out. 6829193323Sed if ((LHSOp.getOpcode() != ISD::UNDEF && 6830193323Sed LHSOp.getOpcode() != ISD::Constant && 6831193323Sed LHSOp.getOpcode() != ISD::ConstantFP) || 6832193323Sed (RHSOp.getOpcode() != ISD::UNDEF && 6833193323Sed RHSOp.getOpcode() != ISD::Constant && 6834193323Sed RHSOp.getOpcode() != ISD::ConstantFP)) 6835193323Sed break; 6836193323Sed 6837193323Sed // Can't fold divide by zero. 6838193323Sed if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6839193323Sed N->getOpcode() == ISD::FDIV) { 6840193323Sed if ((RHSOp.getOpcode() == ISD::Constant && 6841193323Sed cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6842193323Sed (RHSOp.getOpcode() == ISD::ConstantFP && 6843193323Sed cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6844193323Sed break; 6845193323Sed } 6846193323Sed 6847218893Sdim EVT VT = LHSOp.getValueType(); 6848218893Sdim assert(RHSOp.getValueType() == VT && 6849218893Sdim "SimplifyVBinOp with different BUILD_VECTOR element types"); 6850218893Sdim SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 6851208599Srdivacky LHSOp, RHSOp); 6852208599Srdivacky if (FoldOp.getOpcode() != ISD::UNDEF && 6853208599Srdivacky FoldOp.getOpcode() != ISD::Constant && 6854208599Srdivacky FoldOp.getOpcode() != ISD::ConstantFP) 6855208599Srdivacky break; 6856208599Srdivacky Ops.push_back(FoldOp); 6857208599Srdivacky AddToWorkList(FoldOp.getNode()); 6858193323Sed } 6859193323Sed 6860218893Sdim if (Ops.size() == LHS.getNumOperands()) 6861218893Sdim return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6862218893Sdim LHS.getValueType(), &Ops[0], Ops.size()); 6863193323Sed } 6864193323Sed 6865193323Sed return SDValue(); 6866193323Sed} 6867193323Sed 6868193323SedSDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6869193323Sed SDValue N1, SDValue N2){ 6870193323Sed assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6871193323Sed 6872193323Sed SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6873193323Sed cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6874193323Sed 6875193323Sed // If we got a simplified select_cc node back from SimplifySelectCC, then 6876193323Sed // break it down into a new SETCC node, and a new SELECT node, and then return 6877193323Sed // the SELECT node, since we were called with a SELECT node. 6878193323Sed if (SCC.getNode()) { 6879193323Sed // Check to see if we got a select_cc back (to turn into setcc/select). 6880193323Sed // Otherwise, just return whatever node we got back, like fabs. 6881193323Sed if (SCC.getOpcode() == ISD::SELECT_CC) { 6882193323Sed SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6883193323Sed N0.getValueType(), 6884193323Sed SCC.getOperand(0), SCC.getOperand(1), 6885193323Sed SCC.getOperand(4)); 6886193323Sed AddToWorkList(SETCC.getNode()); 6887193323Sed return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6888193323Sed SCC.getOperand(2), SCC.getOperand(3), SETCC); 6889193323Sed } 6890193323Sed 6891193323Sed return SCC; 6892193323Sed } 6893193323Sed return SDValue(); 6894193323Sed} 6895193323Sed 6896193323Sed/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6897193323Sed/// are the two values being selected between, see if we can simplify the 6898193323Sed/// select. Callers of this should assume that TheSelect is deleted if this 6899193323Sed/// returns true. As such, they should return the appropriate thing (e.g. the 6900193323Sed/// node) back to the top-level of the DAG combiner loop to avoid it being 6901193323Sed/// looked at. 6902193323Sedbool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6903193323Sed SDValue RHS) { 6904193323Sed 6905218893Sdim // Cannot simplify select with vector condition 6906218893Sdim if (TheSelect->getOperand(0).getValueType().isVector()) return false; 6907218893Sdim 6908193323Sed // If this is a select from two identical things, try to pull the operation 6909193323Sed // through the select. 6910218893Sdim if (LHS.getOpcode() != RHS.getOpcode() || 6911218893Sdim !LHS.hasOneUse() || !RHS.hasOneUse()) 6912218893Sdim return false; 6913218893Sdim 6914218893Sdim // If this is a load and the token chain is identical, replace the select 6915218893Sdim // of two loads with a load through a select of the address to load from. 6916218893Sdim // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6917218893Sdim // constants have been dropped into the constant pool. 6918218893Sdim if (LHS.getOpcode() == ISD::LOAD) { 6919218893Sdim LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6920218893Sdim LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6921218893Sdim 6922218893Sdim // Token chains must be identical. 6923218893Sdim if (LHS.getOperand(0) != RHS.getOperand(0) || 6924193323Sed // Do not let this transformation reduce the number of volatile loads. 6925218893Sdim LLD->isVolatile() || RLD->isVolatile() || 6926218893Sdim // If this is an EXTLOAD, the VT's must match. 6927218893Sdim LLD->getMemoryVT() != RLD->getMemoryVT() || 6928218893Sdim // If this is an EXTLOAD, the kind of extension must match. 6929218893Sdim (LLD->getExtensionType() != RLD->getExtensionType() && 6930218893Sdim // The only exception is if one of the extensions is anyext. 6931218893Sdim LLD->getExtensionType() != ISD::EXTLOAD && 6932218893Sdim RLD->getExtensionType() != ISD::EXTLOAD) || 6933198892Srdivacky // FIXME: this discards src value information. This is 6934198892Srdivacky // over-conservative. It would be beneficial to be able to remember 6935202375Srdivacky // both potential memory locations. Since we are discarding 6936202375Srdivacky // src value info, don't do the transformation if the memory 6937202375Srdivacky // locations are not in the default address space. 6938218893Sdim LLD->getPointerInfo().getAddrSpace() != 0 || 6939218893Sdim RLD->getPointerInfo().getAddrSpace() != 0) 6940218893Sdim return false; 6941193323Sed 6942218893Sdim // Check that the select condition doesn't reach either load. If so, 6943218893Sdim // folding this will induce a cycle into the DAG. If not, this is safe to 6944218893Sdim // xform, so create a select of the addresses. 6945218893Sdim SDValue Addr; 6946218893Sdim if (TheSelect->getOpcode() == ISD::SELECT) { 6947218893Sdim SDNode *CondNode = TheSelect->getOperand(0).getNode(); 6948218893Sdim if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 6949218893Sdim (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 6950218893Sdim return false; 6951218893Sdim Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6952218893Sdim LLD->getBasePtr().getValueType(), 6953218893Sdim TheSelect->getOperand(0), LLD->getBasePtr(), 6954218893Sdim RLD->getBasePtr()); 6955218893Sdim } else { // Otherwise SELECT_CC 6956218893Sdim SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 6957218893Sdim SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 6958193323Sed 6959218893Sdim if ((LLD->hasAnyUseOfValue(1) && 6960218893Sdim (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 6961218893Sdim (LLD->hasAnyUseOfValue(1) && 6962218893Sdim (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 6963218893Sdim return false; 6964193323Sed 6965218893Sdim Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6966218893Sdim LLD->getBasePtr().getValueType(), 6967218893Sdim TheSelect->getOperand(0), 6968218893Sdim TheSelect->getOperand(1), 6969218893Sdim LLD->getBasePtr(), RLD->getBasePtr(), 6970218893Sdim TheSelect->getOperand(4)); 6971193323Sed } 6972218893Sdim 6973218893Sdim SDValue Load; 6974218893Sdim if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6975218893Sdim Load = DAG.getLoad(TheSelect->getValueType(0), 6976218893Sdim TheSelect->getDebugLoc(), 6977218893Sdim // FIXME: Discards pointer info. 6978218893Sdim LLD->getChain(), Addr, MachinePointerInfo(), 6979218893Sdim LLD->isVolatile(), LLD->isNonTemporal(), 6980218893Sdim LLD->getAlignment()); 6981218893Sdim } else { 6982218893Sdim Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 6983218893Sdim RLD->getExtensionType() : LLD->getExtensionType(), 6984218893Sdim TheSelect->getDebugLoc(), 6985218893Sdim TheSelect->getValueType(0), 6986218893Sdim // FIXME: Discards pointer info. 6987218893Sdim LLD->getChain(), Addr, MachinePointerInfo(), 6988218893Sdim LLD->getMemoryVT(), LLD->isVolatile(), 6989218893Sdim LLD->isNonTemporal(), LLD->getAlignment()); 6990218893Sdim } 6991218893Sdim 6992218893Sdim // Users of the select now use the result of the load. 6993218893Sdim CombineTo(TheSelect, Load); 6994218893Sdim 6995218893Sdim // Users of the old loads now use the new load's chain. We know the 6996218893Sdim // old-load value is dead now. 6997218893Sdim CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6998218893Sdim CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6999218893Sdim return true; 7000193323Sed } 7001193323Sed 7002193323Sed return false; 7003193323Sed} 7004193323Sed 7005193323Sed/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 7006193323Sed/// where 'cond' is the comparison specified by CC. 7007193323SedSDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 7008193323Sed SDValue N2, SDValue N3, 7009193323Sed ISD::CondCode CC, bool NotExtCompare) { 7010193323Sed // (x ? y : y) -> y. 7011193323Sed if (N2 == N3) return N2; 7012218893Sdim 7013198090Srdivacky EVT VT = N2.getValueType(); 7014193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 7015193323Sed ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 7016193323Sed ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 7017193323Sed 7018193323Sed // Determine if the condition we're dealing with is constant 7019193323Sed SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 7020193323Sed N0, N1, CC, DL, false); 7021193323Sed if (SCC.getNode()) AddToWorkList(SCC.getNode()); 7022193323Sed ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 7023193323Sed 7024193323Sed // fold select_cc true, x, y -> x 7025193323Sed if (SCCC && !SCCC->isNullValue()) 7026193323Sed return N2; 7027193323Sed // fold select_cc false, x, y -> y 7028193323Sed if (SCCC && SCCC->isNullValue()) 7029193323Sed return N3; 7030193323Sed 7031193323Sed // Check to see if we can simplify the select into an fabs node 7032193323Sed if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 7033193323Sed // Allow either -0.0 or 0.0 7034193323Sed if (CFP->getValueAPF().isZero()) { 7035193323Sed // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 7036193323Sed if ((CC == ISD::SETGE || CC == ISD::SETGT) && 7037193323Sed N0 == N2 && N3.getOpcode() == ISD::FNEG && 7038193323Sed N2 == N3.getOperand(0)) 7039193323Sed return DAG.getNode(ISD::FABS, DL, VT, N0); 7040193323Sed 7041193323Sed // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 7042193323Sed if ((CC == ISD::SETLT || CC == ISD::SETLE) && 7043193323Sed N0 == N3 && N2.getOpcode() == ISD::FNEG && 7044193323Sed N2.getOperand(0) == N3) 7045193323Sed return DAG.getNode(ISD::FABS, DL, VT, N3); 7046193323Sed } 7047193323Sed } 7048218893Sdim 7049193323Sed // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 7050193323Sed // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 7051193323Sed // in it. This is a win when the constant is not otherwise available because 7052193323Sed // it replaces two constant pool loads with one. We only do this if the FP 7053193323Sed // type is known to be legal, because if it isn't, then we are before legalize 7054193323Sed // types an we want the other legalization to happen first (e.g. to avoid 7055193323Sed // messing with soft float) and if the ConstantFP is not legal, because if 7056193323Sed // it is legal, we may not need to store the FP constant in a constant pool. 7057193323Sed if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 7058193323Sed if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 7059193323Sed if (TLI.isTypeLegal(N2.getValueType()) && 7060193323Sed (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 7061193323Sed TargetLowering::Legal) && 7062193323Sed // If both constants have multiple uses, then we won't need to do an 7063193323Sed // extra load, they are likely around in registers for other users. 7064193323Sed (TV->hasOneUse() || FV->hasOneUse())) { 7065193323Sed Constant *Elts[] = { 7066193323Sed const_cast<ConstantFP*>(FV->getConstantFPValue()), 7067193323Sed const_cast<ConstantFP*>(TV->getConstantFPValue()) 7068193323Sed }; 7069193323Sed const Type *FPTy = Elts[0]->getType(); 7070193323Sed const TargetData &TD = *TLI.getTargetData(); 7071218893Sdim 7072193323Sed // Create a ConstantArray of the two constants. 7073193323Sed Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 7074193323Sed SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 7075193323Sed TD.getPrefTypeAlignment(FPTy)); 7076193323Sed unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 7077193323Sed 7078193323Sed // Get the offsets to the 0 and 1 element of the array so that we can 7079193323Sed // select between them. 7080193323Sed SDValue Zero = DAG.getIntPtrConstant(0); 7081193323Sed unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 7082193323Sed SDValue One = DAG.getIntPtrConstant(EltSize); 7083218893Sdim 7084193323Sed SDValue Cond = DAG.getSetCC(DL, 7085193323Sed TLI.getSetCCResultType(N0.getValueType()), 7086193323Sed N0, N1, CC); 7087193323Sed SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 7088193323Sed Cond, One, Zero); 7089193323Sed CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 7090193323Sed CstOffset); 7091193323Sed return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 7092218893Sdim MachinePointerInfo::getConstantPool(), false, 7093203954Srdivacky false, Alignment); 7094193323Sed 7095193323Sed } 7096218893Sdim } 7097193323Sed 7098193323Sed // Check to see if we can perform the "gzip trick", transforming 7099193323Sed // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 7100193323Sed if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 7101193323Sed N0.getValueType().isInteger() && 7102193323Sed N2.getValueType().isInteger() && 7103193323Sed (N1C->isNullValue() || // (a < 0) ? b : 0 7104193323Sed (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 7105198090Srdivacky EVT XType = N0.getValueType(); 7106198090Srdivacky EVT AType = N2.getValueType(); 7107193323Sed if (XType.bitsGE(AType)) { 7108193323Sed // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 7109193323Sed // single-bit constant. 7110193323Sed if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 7111193323Sed unsigned ShCtV = N2C->getAPIntValue().logBase2(); 7112193323Sed ShCtV = XType.getSizeInBits()-ShCtV-1; 7113219077Sdim SDValue ShCt = DAG.getConstant(ShCtV, 7114219077Sdim getShiftAmountTy(N0.getValueType())); 7115193323Sed SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 7116193323Sed XType, N0, ShCt); 7117193323Sed AddToWorkList(Shift.getNode()); 7118193323Sed 7119193323Sed if (XType.bitsGT(AType)) { 7120193323Sed Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7121193323Sed AddToWorkList(Shift.getNode()); 7122193323Sed } 7123193323Sed 7124193323Sed return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7125193323Sed } 7126193323Sed 7127193323Sed SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 7128193323Sed XType, N0, 7129193323Sed DAG.getConstant(XType.getSizeInBits()-1, 7130219077Sdim getShiftAmountTy(N0.getValueType()))); 7131193323Sed AddToWorkList(Shift.getNode()); 7132193323Sed 7133193323Sed if (XType.bitsGT(AType)) { 7134193323Sed Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7135193323Sed AddToWorkList(Shift.getNode()); 7136193323Sed } 7137193323Sed 7138193323Sed return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7139193323Sed } 7140193323Sed } 7141193323Sed 7142218893Sdim // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 7143218893Sdim // where y is has a single bit set. 7144218893Sdim // A plaintext description would be, we can turn the SELECT_CC into an AND 7145218893Sdim // when the condition can be materialized as an all-ones register. Any 7146218893Sdim // single bit-test can be materialized as an all-ones register with 7147218893Sdim // shift-left and shift-right-arith. 7148218893Sdim if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 7149218893Sdim N0->getValueType(0) == VT && 7150218893Sdim N1C && N1C->isNullValue() && 7151218893Sdim N2C && N2C->isNullValue()) { 7152218893Sdim SDValue AndLHS = N0->getOperand(0); 7153218893Sdim ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 7154218893Sdim if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 7155218893Sdim // Shift the tested bit over the sign bit. 7156218893Sdim APInt AndMask = ConstAndRHS->getAPIntValue(); 7157218893Sdim SDValue ShlAmt = 7158219077Sdim DAG.getConstant(AndMask.countLeadingZeros(), 7159219077Sdim getShiftAmountTy(AndLHS.getValueType())); 7160218893Sdim SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 7161218893Sdim 7162218893Sdim // Now arithmetic right shift it all the way over, so the result is either 7163218893Sdim // all-ones, or zero. 7164218893Sdim SDValue ShrAmt = 7165219077Sdim DAG.getConstant(AndMask.getBitWidth()-1, 7166219077Sdim getShiftAmountTy(Shl.getValueType())); 7167218893Sdim SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 7168218893Sdim 7169218893Sdim return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 7170218893Sdim } 7171218893Sdim } 7172218893Sdim 7173193323Sed // fold select C, 16, 0 -> shl C, 4 7174193323Sed if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7175193323Sed TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 7176193323Sed 7177193323Sed // If the caller doesn't want us to simplify this into a zext of a compare, 7178193323Sed // don't do it. 7179193323Sed if (NotExtCompare && N2C->getAPIntValue() == 1) 7180193323Sed return SDValue(); 7181193323Sed 7182193323Sed // Get a SetCC of the condition 7183193323Sed // FIXME: Should probably make sure that setcc is legal if we ever have a 7184193323Sed // target where it isn't. 7185193323Sed SDValue Temp, SCC; 7186193323Sed // cast from setcc result type to select result type 7187193323Sed if (LegalTypes) { 7188193323Sed SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7189193323Sed N0, N1, CC); 7190193323Sed if (N2.getValueType().bitsLT(SCC.getValueType())) 7191193323Sed Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7192193323Sed else 7193193323Sed Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7194193323Sed N2.getValueType(), SCC); 7195193323Sed } else { 7196193323Sed SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7197193323Sed Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7198193323Sed N2.getValueType(), SCC); 7199193323Sed } 7200193323Sed 7201193323Sed AddToWorkList(SCC.getNode()); 7202193323Sed AddToWorkList(Temp.getNode()); 7203193323Sed 7204193323Sed if (N2C->getAPIntValue() == 1) 7205193323Sed return Temp; 7206193323Sed 7207193323Sed // shl setcc result by log2 n2c 7208193323Sed return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7209193323Sed DAG.getConstant(N2C->getAPIntValue().logBase2(), 7210219077Sdim getShiftAmountTy(Temp.getValueType()))); 7211193323Sed } 7212193323Sed 7213193323Sed // Check to see if this is the equivalent of setcc 7214193323Sed // FIXME: Turn all of these into setcc if setcc if setcc is legal 7215193323Sed // otherwise, go ahead with the folds. 7216193323Sed if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7217198090Srdivacky EVT XType = N0.getValueType(); 7218193323Sed if (!LegalOperations || 7219193323Sed TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7220193323Sed SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7221193323Sed if (Res.getValueType() != VT) 7222193323Sed Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7223193323Sed return Res; 7224193323Sed } 7225193323Sed 7226193323Sed // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7227193323Sed if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7228193323Sed (!LegalOperations || 7229193323Sed TLI.isOperationLegal(ISD::CTLZ, XType))) { 7230193323Sed SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7231193323Sed return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7232193323Sed DAG.getConstant(Log2_32(XType.getSizeInBits()), 7233219077Sdim getShiftAmountTy(Ctlz.getValueType()))); 7234193323Sed } 7235193323Sed // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7236193323Sed if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7237193323Sed SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7238193323Sed XType, DAG.getConstant(0, XType), N0); 7239193323Sed SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7240193323Sed return DAG.getNode(ISD::SRL, DL, XType, 7241193323Sed DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7242193323Sed DAG.getConstant(XType.getSizeInBits()-1, 7243219077Sdim getShiftAmountTy(XType))); 7244193323Sed } 7245193323Sed // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7246193323Sed if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7247193323Sed SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7248193323Sed DAG.getConstant(XType.getSizeInBits()-1, 7249219077Sdim getShiftAmountTy(N0.getValueType()))); 7250193323Sed return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7251193323Sed } 7252193323Sed } 7253193323Sed 7254210299Sed // Check to see if this is an integer abs. 7255210299Sed // select_cc setg[te] X, 0, X, -X -> 7256210299Sed // select_cc setgt X, -1, X, -X -> 7257210299Sed // select_cc setl[te] X, 0, -X, X -> 7258210299Sed // select_cc setlt X, 1, -X, X -> 7259193323Sed // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7260210299Sed if (N1C) { 7261210299Sed ConstantSDNode *SubC = NULL; 7262210299Sed if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7263210299Sed (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7264210299Sed N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7265210299Sed SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7266210299Sed else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7267210299Sed (N1C->isOne() && CC == ISD::SETLT)) && 7268210299Sed N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7269210299Sed SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7270210299Sed 7271198090Srdivacky EVT XType = N0.getValueType(); 7272210299Sed if (SubC && SubC->isNullValue() && XType.isInteger()) { 7273210299Sed SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7274210299Sed N0, 7275210299Sed DAG.getConstant(XType.getSizeInBits()-1, 7276219077Sdim getShiftAmountTy(N0.getValueType()))); 7277210299Sed SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7278210299Sed XType, N0, Shift); 7279210299Sed AddToWorkList(Shift.getNode()); 7280210299Sed AddToWorkList(Add.getNode()); 7281210299Sed return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7282193323Sed } 7283193323Sed } 7284193323Sed 7285193323Sed return SDValue(); 7286193323Sed} 7287193323Sed 7288193323Sed/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7289198090SrdivackySDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7290193323Sed SDValue N1, ISD::CondCode Cond, 7291193323Sed DebugLoc DL, bool foldBooleans) { 7292193323Sed TargetLowering::DAGCombinerInfo 7293198090Srdivacky DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7294193323Sed return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7295193323Sed} 7296193323Sed 7297193323Sed/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7298193323Sed/// return a DAG expression to select that will generate the same value by 7299193323Sed/// multiplying by a magic number. See: 7300193323Sed/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7301193323SedSDValue DAGCombiner::BuildSDIV(SDNode *N) { 7302193323Sed std::vector<SDNode*> Built; 7303193323Sed SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7304193323Sed 7305193323Sed for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7306193323Sed ii != ee; ++ii) 7307193323Sed AddToWorkList(*ii); 7308193323Sed return S; 7309193323Sed} 7310193323Sed 7311193323Sed/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7312193323Sed/// return a DAG expression to select that will generate the same value by 7313193323Sed/// multiplying by a magic number. See: 7314193323Sed/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7315193323SedSDValue DAGCombiner::BuildUDIV(SDNode *N) { 7316193323Sed std::vector<SDNode*> Built; 7317193323Sed SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7318193323Sed 7319193323Sed for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7320193323Sed ii != ee; ++ii) 7321193323Sed AddToWorkList(*ii); 7322193323Sed return S; 7323193323Sed} 7324193323Sed 7325198090Srdivacky/// FindBaseOffset - Return true if base is a frame index, which is known not 7326218893Sdim// to alias with anything but itself. Provides base object and offset as 7327218893Sdim// results. 7328198090Srdivackystatic bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7329207618Srdivacky const GlobalValue *&GV, void *&CV) { 7330193323Sed // Assume it is a primitive operation. 7331198090Srdivacky Base = Ptr; Offset = 0; GV = 0; CV = 0; 7332193323Sed 7333193323Sed // If it's an adding a simple constant then integrate the offset. 7334193323Sed if (Base.getOpcode() == ISD::ADD) { 7335193323Sed if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7336193323Sed Base = Base.getOperand(0); 7337193323Sed Offset += C->getZExtValue(); 7338193323Sed } 7339193323Sed } 7340218893Sdim 7341198090Srdivacky // Return the underlying GlobalValue, and update the Offset. Return false 7342198090Srdivacky // for GlobalAddressSDNode since the same GlobalAddress may be represented 7343198090Srdivacky // by multiple nodes with different offsets. 7344198090Srdivacky if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7345198090Srdivacky GV = G->getGlobal(); 7346198090Srdivacky Offset += G->getOffset(); 7347198090Srdivacky return false; 7348198090Srdivacky } 7349193323Sed 7350198090Srdivacky // Return the underlying Constant value, and update the Offset. Return false 7351198090Srdivacky // for ConstantSDNodes since the same constant pool entry may be represented 7352198090Srdivacky // by multiple nodes with different offsets. 7353198090Srdivacky if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7354198090Srdivacky CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7355198090Srdivacky : (void *)C->getConstVal(); 7356198090Srdivacky Offset += C->getOffset(); 7357198090Srdivacky return false; 7358198090Srdivacky } 7359193323Sed // If it's any of the following then it can't alias with anything but itself. 7360198090Srdivacky return isa<FrameIndexSDNode>(Base); 7361193323Sed} 7362193323Sed 7363193323Sed/// isAlias - Return true if there is any possibility that the two addresses 7364193323Sed/// overlap. 7365193323Sedbool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7366193323Sed const Value *SrcValue1, int SrcValueOffset1, 7367198090Srdivacky unsigned SrcValueAlign1, 7368218893Sdim const MDNode *TBAAInfo1, 7369193323Sed SDValue Ptr2, int64_t Size2, 7370198090Srdivacky const Value *SrcValue2, int SrcValueOffset2, 7371218893Sdim unsigned SrcValueAlign2, 7372218893Sdim const MDNode *TBAAInfo2) const { 7373193323Sed // If they are the same then they must be aliases. 7374193323Sed if (Ptr1 == Ptr2) return true; 7375193323Sed 7376193323Sed // Gather base node and offset information. 7377193323Sed SDValue Base1, Base2; 7378193323Sed int64_t Offset1, Offset2; 7379207618Srdivacky const GlobalValue *GV1, *GV2; 7380198090Srdivacky void *CV1, *CV2; 7381198090Srdivacky bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7382198090Srdivacky bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7383193323Sed 7384198090Srdivacky // If they have a same base address then check to see if they overlap. 7385198090Srdivacky if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7386193323Sed return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7387193323Sed 7388218893Sdim // It is possible for different frame indices to alias each other, mostly 7389218893Sdim // when tail call optimization reuses return address slots for arguments. 7390218893Sdim // To catch this case, look up the actual index of frame indices to compute 7391218893Sdim // the real alias relationship. 7392218893Sdim if (isFrameIndex1 && isFrameIndex2) { 7393218893Sdim MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7394218893Sdim Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7395218893Sdim Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7396218893Sdim return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7397218893Sdim } 7398218893Sdim 7399218893Sdim // Otherwise, if we know what the bases are, and they aren't identical, then 7400218893Sdim // we know they cannot alias. 7401198090Srdivacky if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7402198090Srdivacky return false; 7403193323Sed 7404198090Srdivacky // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7405198090Srdivacky // compared to the size and offset of the access, we may be able to prove they 7406198090Srdivacky // do not alias. This check is conservative for now to catch cases created by 7407198090Srdivacky // splitting vector types. 7408198090Srdivacky if ((SrcValueAlign1 == SrcValueAlign2) && 7409198090Srdivacky (SrcValueOffset1 != SrcValueOffset2) && 7410198090Srdivacky (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7411198090Srdivacky int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7412198090Srdivacky int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7413218893Sdim 7414198090Srdivacky // There is no overlap between these relatively aligned accesses of similar 7415198090Srdivacky // size, return no alias. 7416198090Srdivacky if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7417198090Srdivacky return false; 7418198090Srdivacky } 7419218893Sdim 7420193323Sed if (CombinerGlobalAA) { 7421193323Sed // Use alias analysis information. 7422193323Sed int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7423193323Sed int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7424193323Sed int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7425193323Sed AliasAnalysis::AliasResult AAResult = 7426218893Sdim AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7427218893Sdim AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7428193323Sed if (AAResult == AliasAnalysis::NoAlias) 7429193323Sed return false; 7430193323Sed } 7431193323Sed 7432193323Sed // Otherwise we have to assume they alias. 7433193323Sed return true; 7434193323Sed} 7435193323Sed 7436193323Sed/// FindAliasInfo - Extracts the relevant alias information from the memory 7437193323Sed/// node. Returns true if the operand was a load. 7438193323Sedbool DAGCombiner::FindAliasInfo(SDNode *N, 7439193323Sed SDValue &Ptr, int64_t &Size, 7440218893Sdim const Value *&SrcValue, 7441198090Srdivacky int &SrcValueOffset, 7442218893Sdim unsigned &SrcValueAlign, 7443218893Sdim const MDNode *&TBAAInfo) const { 7444193323Sed if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7445193323Sed Ptr = LD->getBasePtr(); 7446193323Sed Size = LD->getMemoryVT().getSizeInBits() >> 3; 7447193323Sed SrcValue = LD->getSrcValue(); 7448193323Sed SrcValueOffset = LD->getSrcValueOffset(); 7449198090Srdivacky SrcValueAlign = LD->getOriginalAlignment(); 7450218893Sdim TBAAInfo = LD->getTBAAInfo(); 7451193323Sed return true; 7452193323Sed } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7453193323Sed Ptr = ST->getBasePtr(); 7454193323Sed Size = ST->getMemoryVT().getSizeInBits() >> 3; 7455193323Sed SrcValue = ST->getSrcValue(); 7456193323Sed SrcValueOffset = ST->getSrcValueOffset(); 7457198090Srdivacky SrcValueAlign = ST->getOriginalAlignment(); 7458218893Sdim TBAAInfo = ST->getTBAAInfo(); 7459193323Sed } else { 7460198090Srdivacky llvm_unreachable("FindAliasInfo expected a memory operand"); 7461193323Sed } 7462193323Sed 7463193323Sed return false; 7464193323Sed} 7465193323Sed 7466193323Sed/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7467193323Sed/// looking for aliasing nodes and adding them to the Aliases vector. 7468193323Sedvoid DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7469193323Sed SmallVector<SDValue, 8> &Aliases) { 7470193323Sed SmallVector<SDValue, 8> Chains; // List of chains to visit. 7471198090Srdivacky SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7472193323Sed 7473193323Sed // Get alias information for node. 7474193323Sed SDValue Ptr; 7475198090Srdivacky int64_t Size; 7476198090Srdivacky const Value *SrcValue; 7477198090Srdivacky int SrcValueOffset; 7478198090Srdivacky unsigned SrcValueAlign; 7479218893Sdim const MDNode *SrcTBAAInfo; 7480218893Sdim bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7481218893Sdim SrcValueAlign, SrcTBAAInfo); 7482193323Sed 7483193323Sed // Starting off. 7484193323Sed Chains.push_back(OriginalChain); 7485198090Srdivacky unsigned Depth = 0; 7486218893Sdim 7487193323Sed // Look at each chain and determine if it is an alias. If so, add it to the 7488193323Sed // aliases list. If not, then continue up the chain looking for the next 7489193323Sed // candidate. 7490193323Sed while (!Chains.empty()) { 7491193323Sed SDValue Chain = Chains.back(); 7492193323Sed Chains.pop_back(); 7493218893Sdim 7494218893Sdim // For TokenFactor nodes, look at each operand and only continue up the 7495218893Sdim // chain until we find two aliases. If we've seen two aliases, assume we'll 7496198090Srdivacky // find more and revert to original chain since the xform is unlikely to be 7497198090Srdivacky // profitable. 7498218893Sdim // 7499218893Sdim // FIXME: The depth check could be made to return the last non-aliasing 7500198090Srdivacky // chain we found before we hit a tokenfactor rather than the original 7501198090Srdivacky // chain. 7502198090Srdivacky if (Depth > 6 || Aliases.size() == 2) { 7503198090Srdivacky Aliases.clear(); 7504198090Srdivacky Aliases.push_back(OriginalChain); 7505198090Srdivacky break; 7506198090Srdivacky } 7507193323Sed 7508198090Srdivacky // Don't bother if we've been before. 7509198090Srdivacky if (!Visited.insert(Chain.getNode())) 7510198090Srdivacky continue; 7511193323Sed 7512193323Sed switch (Chain.getOpcode()) { 7513193323Sed case ISD::EntryToken: 7514193323Sed // Entry token is ideal chain operand, but handled in FindBetterChain. 7515193323Sed break; 7516193323Sed 7517193323Sed case ISD::LOAD: 7518193323Sed case ISD::STORE: { 7519193323Sed // Get alias information for Chain. 7520193323Sed SDValue OpPtr; 7521198090Srdivacky int64_t OpSize; 7522198090Srdivacky const Value *OpSrcValue; 7523198090Srdivacky int OpSrcValueOffset; 7524198090Srdivacky unsigned OpSrcValueAlign; 7525218893Sdim const MDNode *OpSrcTBAAInfo; 7526193323Sed bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7527198090Srdivacky OpSrcValue, OpSrcValueOffset, 7528218893Sdim OpSrcValueAlign, 7529218893Sdim OpSrcTBAAInfo); 7530193323Sed 7531193323Sed // If chain is alias then stop here. 7532193323Sed if (!(IsLoad && IsOpLoad) && 7533198090Srdivacky isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7534218893Sdim SrcTBAAInfo, 7535198090Srdivacky OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7536218893Sdim OpSrcValueAlign, OpSrcTBAAInfo)) { 7537193323Sed Aliases.push_back(Chain); 7538193323Sed } else { 7539193323Sed // Look further up the chain. 7540193323Sed Chains.push_back(Chain.getOperand(0)); 7541198090Srdivacky ++Depth; 7542193323Sed } 7543193323Sed break; 7544193323Sed } 7545193323Sed 7546193323Sed case ISD::TokenFactor: 7547198090Srdivacky // We have to check each of the operands of the token factor for "small" 7548198090Srdivacky // token factors, so we queue them up. Adding the operands to the queue 7549198090Srdivacky // (stack) in reverse order maintains the original order and increases the 7550198090Srdivacky // likelihood that getNode will find a matching token factor (CSE.) 7551198090Srdivacky if (Chain.getNumOperands() > 16) { 7552198090Srdivacky Aliases.push_back(Chain); 7553198090Srdivacky break; 7554198090Srdivacky } 7555193323Sed for (unsigned n = Chain.getNumOperands(); n;) 7556193323Sed Chains.push_back(Chain.getOperand(--n)); 7557198090Srdivacky ++Depth; 7558193323Sed break; 7559193323Sed 7560193323Sed default: 7561193323Sed // For all other instructions we will just have to take what we can get. 7562193323Sed Aliases.push_back(Chain); 7563193323Sed break; 7564193323Sed } 7565193323Sed } 7566193323Sed} 7567193323Sed 7568193323Sed/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7569193323Sed/// for a better chain (aliasing node.) 7570193323SedSDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7571193323Sed SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7572193323Sed 7573193323Sed // Accumulate all the aliases to this node. 7574193323Sed GatherAllAliases(N, OldChain, Aliases); 7575193323Sed 7576193323Sed if (Aliases.size() == 0) { 7577193323Sed // If no operands then chain to entry token. 7578193323Sed return DAG.getEntryNode(); 7579193323Sed } else if (Aliases.size() == 1) { 7580193323Sed // If a single operand then chain to it. We don't need to revisit it. 7581193323Sed return Aliases[0]; 7582193323Sed } 7583218893Sdim 7584193323Sed // Construct a custom tailored token factor. 7585218893Sdim return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7586198090Srdivacky &Aliases[0], Aliases.size()); 7587193323Sed} 7588193323Sed 7589193323Sed// SelectionDAG::Combine - This is the entry point for the file. 7590193323Sed// 7591193323Sedvoid SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7592193323Sed CodeGenOpt::Level OptLevel) { 7593193323Sed /// run - This is the main entry point to this class. 7594193323Sed /// 7595193323Sed DAGCombiner(*this, AA, OptLevel).Run(Level); 7596193323Sed} 7597