DAGCombiner.cpp revision 193323
1193323Sed//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11193323Sed// both before and after the DAG is legalized. 12193323Sed// 13193323Sed// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14193323Sed// primarily intended to handle simplification opportunities that are implicit 15193323Sed// in the LLVM IR and exposed by the various codegen lowering phases. 16193323Sed// 17193323Sed//===----------------------------------------------------------------------===// 18193323Sed 19193323Sed#define DEBUG_TYPE "dagcombine" 20193323Sed#include "llvm/CodeGen/SelectionDAG.h" 21193323Sed#include "llvm/DerivedTypes.h" 22193323Sed#include "llvm/CodeGen/MachineFunction.h" 23193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 24193323Sed#include "llvm/CodeGen/PseudoSourceValue.h" 25193323Sed#include "llvm/Analysis/AliasAnalysis.h" 26193323Sed#include "llvm/Target/TargetData.h" 27193323Sed#include "llvm/Target/TargetFrameInfo.h" 28193323Sed#include "llvm/Target/TargetLowering.h" 29193323Sed#include "llvm/Target/TargetMachine.h" 30193323Sed#include "llvm/Target/TargetOptions.h" 31193323Sed#include "llvm/ADT/SmallPtrSet.h" 32193323Sed#include "llvm/ADT/Statistic.h" 33193323Sed#include "llvm/Support/Compiler.h" 34193323Sed#include "llvm/Support/CommandLine.h" 35193323Sed#include "llvm/Support/Debug.h" 36193323Sed#include "llvm/Support/MathExtras.h" 37193323Sed#include <algorithm> 38193323Sed#include <set> 39193323Sedusing namespace llvm; 40193323Sed 41193323SedSTATISTIC(NodesCombined , "Number of dag nodes combined"); 42193323SedSTATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43193323SedSTATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44193323SedSTATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45193323Sed 46193323Sednamespace { 47193323Sed static cl::opt<bool> 48193323Sed CombinerAA("combiner-alias-analysis", cl::Hidden, 49193323Sed cl::desc("Turn on alias analysis during testing")); 50193323Sed 51193323Sed static cl::opt<bool> 52193323Sed CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53193323Sed cl::desc("Include global information in alias analysis")); 54193323Sed 55193323Sed//------------------------------ DAGCombiner ---------------------------------// 56193323Sed 57193323Sed class VISIBILITY_HIDDEN DAGCombiner { 58193323Sed SelectionDAG &DAG; 59193323Sed const TargetLowering &TLI; 60193323Sed CombineLevel Level; 61193323Sed CodeGenOpt::Level OptLevel; 62193323Sed bool LegalOperations; 63193323Sed bool LegalTypes; 64193323Sed 65193323Sed // Worklist of all of the nodes that need to be simplified. 66193323Sed std::vector<SDNode*> WorkList; 67193323Sed 68193323Sed // AA - Used for DAG load/store alias analysis. 69193323Sed AliasAnalysis &AA; 70193323Sed 71193323Sed /// AddUsersToWorkList - When an instruction is simplified, add all users of 72193323Sed /// the instruction to the work lists because they might get more simplified 73193323Sed /// now. 74193323Sed /// 75193323Sed void AddUsersToWorkList(SDNode *N) { 76193323Sed for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 77193323Sed UI != UE; ++UI) 78193323Sed AddToWorkList(*UI); 79193323Sed } 80193323Sed 81193323Sed /// visit - call the node-specific routine that knows how to fold each 82193323Sed /// particular type of node. 83193323Sed SDValue visit(SDNode *N); 84193323Sed 85193323Sed public: 86193323Sed /// AddToWorkList - Add to the work list making sure it's instance is at the 87193323Sed /// the back (next to be processed.) 88193323Sed void AddToWorkList(SDNode *N) { 89193323Sed removeFromWorkList(N); 90193323Sed WorkList.push_back(N); 91193323Sed } 92193323Sed 93193323Sed /// removeFromWorkList - remove all instances of N from the worklist. 94193323Sed /// 95193323Sed void removeFromWorkList(SDNode *N) { 96193323Sed WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 97193323Sed WorkList.end()); 98193323Sed } 99193323Sed 100193323Sed SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 101193323Sed bool AddTo = true); 102193323Sed 103193323Sed SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 104193323Sed return CombineTo(N, &Res, 1, AddTo); 105193323Sed } 106193323Sed 107193323Sed SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 108193323Sed bool AddTo = true) { 109193323Sed SDValue To[] = { Res0, Res1 }; 110193323Sed return CombineTo(N, To, 2, AddTo); 111193323Sed } 112193323Sed 113193323Sed void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 114193323Sed 115193323Sed private: 116193323Sed 117193323Sed /// SimplifyDemandedBits - Check the specified integer node value to see if 118193323Sed /// it can be simplified or if things it uses can be simplified by bit 119193323Sed /// propagation. If so, return true. 120193323Sed bool SimplifyDemandedBits(SDValue Op) { 121193323Sed APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 122193323Sed return SimplifyDemandedBits(Op, Demanded); 123193323Sed } 124193323Sed 125193323Sed bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 126193323Sed 127193323Sed bool CombineToPreIndexedLoadStore(SDNode *N); 128193323Sed bool CombineToPostIndexedLoadStore(SDNode *N); 129193323Sed 130193323Sed 131193323Sed /// combine - call the node-specific routine that knows how to fold each 132193323Sed /// particular type of node. If that doesn't do anything, try the 133193323Sed /// target-specific DAG combines. 134193323Sed SDValue combine(SDNode *N); 135193323Sed 136193323Sed // Visitation implementation - Implement dag node combining for different 137193323Sed // node types. The semantics are as follows: 138193323Sed // Return Value: 139193323Sed // SDValue.getNode() == 0 - No change was made 140193323Sed // SDValue.getNode() == N - N was replaced, is dead and has been handled. 141193323Sed // otherwise - N should be replaced by the returned Operand. 142193323Sed // 143193323Sed SDValue visitTokenFactor(SDNode *N); 144193323Sed SDValue visitMERGE_VALUES(SDNode *N); 145193323Sed SDValue visitADD(SDNode *N); 146193323Sed SDValue visitSUB(SDNode *N); 147193323Sed SDValue visitADDC(SDNode *N); 148193323Sed SDValue visitADDE(SDNode *N); 149193323Sed SDValue visitMUL(SDNode *N); 150193323Sed SDValue visitSDIV(SDNode *N); 151193323Sed SDValue visitUDIV(SDNode *N); 152193323Sed SDValue visitSREM(SDNode *N); 153193323Sed SDValue visitUREM(SDNode *N); 154193323Sed SDValue visitMULHU(SDNode *N); 155193323Sed SDValue visitMULHS(SDNode *N); 156193323Sed SDValue visitSMUL_LOHI(SDNode *N); 157193323Sed SDValue visitUMUL_LOHI(SDNode *N); 158193323Sed SDValue visitSDIVREM(SDNode *N); 159193323Sed SDValue visitUDIVREM(SDNode *N); 160193323Sed SDValue visitAND(SDNode *N); 161193323Sed SDValue visitOR(SDNode *N); 162193323Sed SDValue visitXOR(SDNode *N); 163193323Sed SDValue SimplifyVBinOp(SDNode *N); 164193323Sed SDValue visitSHL(SDNode *N); 165193323Sed SDValue visitSRA(SDNode *N); 166193323Sed SDValue visitSRL(SDNode *N); 167193323Sed SDValue visitCTLZ(SDNode *N); 168193323Sed SDValue visitCTTZ(SDNode *N); 169193323Sed SDValue visitCTPOP(SDNode *N); 170193323Sed SDValue visitSELECT(SDNode *N); 171193323Sed SDValue visitSELECT_CC(SDNode *N); 172193323Sed SDValue visitSETCC(SDNode *N); 173193323Sed SDValue visitSIGN_EXTEND(SDNode *N); 174193323Sed SDValue visitZERO_EXTEND(SDNode *N); 175193323Sed SDValue visitANY_EXTEND(SDNode *N); 176193323Sed SDValue visitSIGN_EXTEND_INREG(SDNode *N); 177193323Sed SDValue visitTRUNCATE(SDNode *N); 178193323Sed SDValue visitBIT_CONVERT(SDNode *N); 179193323Sed SDValue visitBUILD_PAIR(SDNode *N); 180193323Sed SDValue visitFADD(SDNode *N); 181193323Sed SDValue visitFSUB(SDNode *N); 182193323Sed SDValue visitFMUL(SDNode *N); 183193323Sed SDValue visitFDIV(SDNode *N); 184193323Sed SDValue visitFREM(SDNode *N); 185193323Sed SDValue visitFCOPYSIGN(SDNode *N); 186193323Sed SDValue visitSINT_TO_FP(SDNode *N); 187193323Sed SDValue visitUINT_TO_FP(SDNode *N); 188193323Sed SDValue visitFP_TO_SINT(SDNode *N); 189193323Sed SDValue visitFP_TO_UINT(SDNode *N); 190193323Sed SDValue visitFP_ROUND(SDNode *N); 191193323Sed SDValue visitFP_ROUND_INREG(SDNode *N); 192193323Sed SDValue visitFP_EXTEND(SDNode *N); 193193323Sed SDValue visitFNEG(SDNode *N); 194193323Sed SDValue visitFABS(SDNode *N); 195193323Sed SDValue visitBRCOND(SDNode *N); 196193323Sed SDValue visitBR_CC(SDNode *N); 197193323Sed SDValue visitLOAD(SDNode *N); 198193323Sed SDValue visitSTORE(SDNode *N); 199193323Sed SDValue visitINSERT_VECTOR_ELT(SDNode *N); 200193323Sed SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 201193323Sed SDValue visitBUILD_VECTOR(SDNode *N); 202193323Sed SDValue visitCONCAT_VECTORS(SDNode *N); 203193323Sed SDValue visitVECTOR_SHUFFLE(SDNode *N); 204193323Sed 205193323Sed SDValue XformToShuffleWithZero(SDNode *N); 206193323Sed SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 207193323Sed 208193323Sed SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 209193323Sed 210193323Sed bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 211193323Sed SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 212193323Sed SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 213193323Sed SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 214193323Sed SDValue N3, ISD::CondCode CC, 215193323Sed bool NotExtCompare = false); 216193323Sed SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 217193323Sed DebugLoc DL, bool foldBooleans = true); 218193323Sed SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 219193323Sed unsigned HiOp); 220193323Sed SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 221193323Sed SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 222193323Sed SDValue BuildSDIV(SDNode *N); 223193323Sed SDValue BuildUDIV(SDNode *N); 224193323Sed SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 225193323Sed SDValue ReduceLoadWidth(SDNode *N); 226193323Sed SDValue ReduceLoadOpStoreWidth(SDNode *N); 227193323Sed 228193323Sed SDValue GetDemandedBits(SDValue V, const APInt &Mask); 229193323Sed 230193323Sed /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 231193323Sed /// looking for aliasing nodes and adding them to the Aliases vector. 232193323Sed void GatherAllAliases(SDNode *N, SDValue OriginalChain, 233193323Sed SmallVector<SDValue, 8> &Aliases); 234193323Sed 235193323Sed /// isAlias - Return true if there is any possibility that the two addresses 236193323Sed /// overlap. 237193323Sed bool isAlias(SDValue Ptr1, int64_t Size1, 238193323Sed const Value *SrcValue1, int SrcValueOffset1, 239193323Sed SDValue Ptr2, int64_t Size2, 240193323Sed const Value *SrcValue2, int SrcValueOffset2) const; 241193323Sed 242193323Sed /// FindAliasInfo - Extracts the relevant alias information from the memory 243193323Sed /// node. Returns true if the operand was a load. 244193323Sed bool FindAliasInfo(SDNode *N, 245193323Sed SDValue &Ptr, int64_t &Size, 246193323Sed const Value *&SrcValue, int &SrcValueOffset) const; 247193323Sed 248193323Sed /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 249193323Sed /// looking for a better chain (aliasing node.) 250193323Sed SDValue FindBetterChain(SDNode *N, SDValue Chain); 251193323Sed 252193323Sed /// getShiftAmountTy - Returns a type large enough to hold any valid 253193323Sed /// shift amount - before type legalization these can be huge. 254193323Sed MVT getShiftAmountTy() { 255193323Sed return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 256193323Sed } 257193323Sed 258193323Sedpublic: 259193323Sed DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 260193323Sed : DAG(D), 261193323Sed TLI(D.getTargetLoweringInfo()), 262193323Sed Level(Unrestricted), 263193323Sed OptLevel(OL), 264193323Sed LegalOperations(false), 265193323Sed LegalTypes(false), 266193323Sed AA(A) {} 267193323Sed 268193323Sed /// Run - runs the dag combiner on all nodes in the work list 269193323Sed void Run(CombineLevel AtLevel); 270193323Sed }; 271193323Sed} 272193323Sed 273193323Sed 274193323Sednamespace { 275193323Sed/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 276193323Sed/// nodes from the worklist. 277193323Sedclass VISIBILITY_HIDDEN WorkListRemover : 278193323Sed public SelectionDAG::DAGUpdateListener { 279193323Sed DAGCombiner &DC; 280193323Sedpublic: 281193323Sed explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 282193323Sed 283193323Sed virtual void NodeDeleted(SDNode *N, SDNode *E) { 284193323Sed DC.removeFromWorkList(N); 285193323Sed } 286193323Sed 287193323Sed virtual void NodeUpdated(SDNode *N) { 288193323Sed // Ignore updates. 289193323Sed } 290193323Sed}; 291193323Sed} 292193323Sed 293193323Sed//===----------------------------------------------------------------------===// 294193323Sed// TargetLowering::DAGCombinerInfo implementation 295193323Sed//===----------------------------------------------------------------------===// 296193323Sed 297193323Sedvoid TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 298193323Sed ((DAGCombiner*)DC)->AddToWorkList(N); 299193323Sed} 300193323Sed 301193323SedSDValue TargetLowering::DAGCombinerInfo:: 302193323SedCombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 303193323Sed return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 304193323Sed} 305193323Sed 306193323SedSDValue TargetLowering::DAGCombinerInfo:: 307193323SedCombineTo(SDNode *N, SDValue Res, bool AddTo) { 308193323Sed return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 309193323Sed} 310193323Sed 311193323Sed 312193323SedSDValue TargetLowering::DAGCombinerInfo:: 313193323SedCombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 314193323Sed return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 315193323Sed} 316193323Sed 317193323Sedvoid TargetLowering::DAGCombinerInfo:: 318193323SedCommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 319193323Sed return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 320193323Sed} 321193323Sed 322193323Sed//===----------------------------------------------------------------------===// 323193323Sed// Helper Functions 324193323Sed//===----------------------------------------------------------------------===// 325193323Sed 326193323Sed/// isNegatibleForFree - Return 1 if we can compute the negated form of the 327193323Sed/// specified expression for the same cost as the expression itself, or 2 if we 328193323Sed/// can compute the negated form more cheaply than the expression itself. 329193323Sedstatic char isNegatibleForFree(SDValue Op, bool LegalOperations, 330193323Sed unsigned Depth = 0) { 331193323Sed // No compile time optimizations on this type. 332193323Sed if (Op.getValueType() == MVT::ppcf128) 333193323Sed return 0; 334193323Sed 335193323Sed // fneg is removable even if it has multiple uses. 336193323Sed if (Op.getOpcode() == ISD::FNEG) return 2; 337193323Sed 338193323Sed // Don't allow anything with multiple uses. 339193323Sed if (!Op.hasOneUse()) return 0; 340193323Sed 341193323Sed // Don't recurse exponentially. 342193323Sed if (Depth > 6) return 0; 343193323Sed 344193323Sed switch (Op.getOpcode()) { 345193323Sed default: return false; 346193323Sed case ISD::ConstantFP: 347193323Sed // Don't invert constant FP values after legalize. The negated constant 348193323Sed // isn't necessarily legal. 349193323Sed return LegalOperations ? 0 : 1; 350193323Sed case ISD::FADD: 351193323Sed // FIXME: determine better conditions for this xform. 352193323Sed if (!UnsafeFPMath) return 0; 353193323Sed 354193323Sed // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 355193323Sed if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 356193323Sed return V; 357193323Sed // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 358193323Sed return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 359193323Sed case ISD::FSUB: 360193323Sed // We can't turn -(A-B) into B-A when we honor signed zeros. 361193323Sed if (!UnsafeFPMath) return 0; 362193323Sed 363193323Sed // fold (fneg (fsub A, B)) -> (fsub B, A) 364193323Sed return 1; 365193323Sed 366193323Sed case ISD::FMUL: 367193323Sed case ISD::FDIV: 368193323Sed if (HonorSignDependentRoundingFPMath()) return 0; 369193323Sed 370193323Sed // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 371193323Sed if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 372193323Sed return V; 373193323Sed 374193323Sed return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 375193323Sed 376193323Sed case ISD::FP_EXTEND: 377193323Sed case ISD::FP_ROUND: 378193323Sed case ISD::FSIN: 379193323Sed return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 380193323Sed } 381193323Sed} 382193323Sed 383193323Sed/// GetNegatedExpression - If isNegatibleForFree returns true, this function 384193323Sed/// returns the newly negated expression. 385193323Sedstatic SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 386193323Sed bool LegalOperations, unsigned Depth = 0) { 387193323Sed // fneg is removable even if it has multiple uses. 388193323Sed if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 389193323Sed 390193323Sed // Don't allow anything with multiple uses. 391193323Sed assert(Op.hasOneUse() && "Unknown reuse!"); 392193323Sed 393193323Sed assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 394193323Sed switch (Op.getOpcode()) { 395193323Sed default: assert(0 && "Unknown code"); 396193323Sed case ISD::ConstantFP: { 397193323Sed APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 398193323Sed V.changeSign(); 399193323Sed return DAG.getConstantFP(V, Op.getValueType()); 400193323Sed } 401193323Sed case ISD::FADD: 402193323Sed // FIXME: determine better conditions for this xform. 403193323Sed assert(UnsafeFPMath); 404193323Sed 405193323Sed // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 406193323Sed if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 407193323Sed return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 408193323Sed GetNegatedExpression(Op.getOperand(0), DAG, 409193323Sed LegalOperations, Depth+1), 410193323Sed Op.getOperand(1)); 411193323Sed // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 412193323Sed return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 413193323Sed GetNegatedExpression(Op.getOperand(1), DAG, 414193323Sed LegalOperations, Depth+1), 415193323Sed Op.getOperand(0)); 416193323Sed case ISD::FSUB: 417193323Sed // We can't turn -(A-B) into B-A when we honor signed zeros. 418193323Sed assert(UnsafeFPMath); 419193323Sed 420193323Sed // fold (fneg (fsub 0, B)) -> B 421193323Sed if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 422193323Sed if (N0CFP->getValueAPF().isZero()) 423193323Sed return Op.getOperand(1); 424193323Sed 425193323Sed // fold (fneg (fsub A, B)) -> (fsub B, A) 426193323Sed return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 427193323Sed Op.getOperand(1), Op.getOperand(0)); 428193323Sed 429193323Sed case ISD::FMUL: 430193323Sed case ISD::FDIV: 431193323Sed assert(!HonorSignDependentRoundingFPMath()); 432193323Sed 433193323Sed // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 434193323Sed if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 435193323Sed return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 436193323Sed GetNegatedExpression(Op.getOperand(0), DAG, 437193323Sed LegalOperations, Depth+1), 438193323Sed Op.getOperand(1)); 439193323Sed 440193323Sed // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 441193323Sed return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 442193323Sed Op.getOperand(0), 443193323Sed GetNegatedExpression(Op.getOperand(1), DAG, 444193323Sed LegalOperations, Depth+1)); 445193323Sed 446193323Sed case ISD::FP_EXTEND: 447193323Sed case ISD::FSIN: 448193323Sed return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 449193323Sed GetNegatedExpression(Op.getOperand(0), DAG, 450193323Sed LegalOperations, Depth+1)); 451193323Sed case ISD::FP_ROUND: 452193323Sed return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 453193323Sed GetNegatedExpression(Op.getOperand(0), DAG, 454193323Sed LegalOperations, Depth+1), 455193323Sed Op.getOperand(1)); 456193323Sed } 457193323Sed} 458193323Sed 459193323Sed 460193323Sed// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 461193323Sed// that selects between the values 1 and 0, making it equivalent to a setcc. 462193323Sed// Also, set the incoming LHS, RHS, and CC references to the appropriate 463193323Sed// nodes based on the type of node we are checking. This simplifies life a 464193323Sed// bit for the callers. 465193323Sedstatic bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 466193323Sed SDValue &CC) { 467193323Sed if (N.getOpcode() == ISD::SETCC) { 468193323Sed LHS = N.getOperand(0); 469193323Sed RHS = N.getOperand(1); 470193323Sed CC = N.getOperand(2); 471193323Sed return true; 472193323Sed } 473193323Sed if (N.getOpcode() == ISD::SELECT_CC && 474193323Sed N.getOperand(2).getOpcode() == ISD::Constant && 475193323Sed N.getOperand(3).getOpcode() == ISD::Constant && 476193323Sed cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 477193323Sed cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 478193323Sed LHS = N.getOperand(0); 479193323Sed RHS = N.getOperand(1); 480193323Sed CC = N.getOperand(4); 481193323Sed return true; 482193323Sed } 483193323Sed return false; 484193323Sed} 485193323Sed 486193323Sed// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 487193323Sed// one use. If this is true, it allows the users to invert the operation for 488193323Sed// free when it is profitable to do so. 489193323Sedstatic bool isOneUseSetCC(SDValue N) { 490193323Sed SDValue N0, N1, N2; 491193323Sed if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 492193323Sed return true; 493193323Sed return false; 494193323Sed} 495193323Sed 496193323SedSDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 497193323Sed SDValue N0, SDValue N1) { 498193323Sed MVT VT = N0.getValueType(); 499193323Sed if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 500193323Sed if (isa<ConstantSDNode>(N1)) { 501193323Sed // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 502193323Sed SDValue OpNode = 503193323Sed DAG.FoldConstantArithmetic(Opc, VT, 504193323Sed cast<ConstantSDNode>(N0.getOperand(1)), 505193323Sed cast<ConstantSDNode>(N1)); 506193323Sed return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 507193323Sed } else if (N0.hasOneUse()) { 508193323Sed // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 509193323Sed SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 510193323Sed N0.getOperand(0), N1); 511193323Sed AddToWorkList(OpNode.getNode()); 512193323Sed return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 513193323Sed } 514193323Sed } 515193323Sed 516193323Sed if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 517193323Sed if (isa<ConstantSDNode>(N0)) { 518193323Sed // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 519193323Sed SDValue OpNode = 520193323Sed DAG.FoldConstantArithmetic(Opc, VT, 521193323Sed cast<ConstantSDNode>(N1.getOperand(1)), 522193323Sed cast<ConstantSDNode>(N0)); 523193323Sed return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 524193323Sed } else if (N1.hasOneUse()) { 525193323Sed // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 526193323Sed SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 527193323Sed N1.getOperand(0), N0); 528193323Sed AddToWorkList(OpNode.getNode()); 529193323Sed return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 530193323Sed } 531193323Sed } 532193323Sed 533193323Sed return SDValue(); 534193323Sed} 535193323Sed 536193323SedSDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 537193323Sed bool AddTo) { 538193323Sed assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 539193323Sed ++NodesCombined; 540193323Sed DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 541193323Sed DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 542193323Sed DOUT << " and " << NumTo-1 << " other values\n"; 543193323Sed DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 544193323Sed assert(N->getValueType(i) == To[i].getValueType() && 545193323Sed "Cannot combine value to value of different type!")); 546193323Sed WorkListRemover DeadNodes(*this); 547193323Sed DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 548193323Sed 549193323Sed if (AddTo) { 550193323Sed // Push the new nodes and any users onto the worklist 551193323Sed for (unsigned i = 0, e = NumTo; i != e; ++i) { 552193323Sed if (To[i].getNode()) { 553193323Sed AddToWorkList(To[i].getNode()); 554193323Sed AddUsersToWorkList(To[i].getNode()); 555193323Sed } 556193323Sed } 557193323Sed } 558193323Sed 559193323Sed // Finally, if the node is now dead, remove it from the graph. The node 560193323Sed // may not be dead if the replacement process recursively simplified to 561193323Sed // something else needing this node. 562193323Sed if (N->use_empty()) { 563193323Sed // Nodes can be reintroduced into the worklist. Make sure we do not 564193323Sed // process a node that has been replaced. 565193323Sed removeFromWorkList(N); 566193323Sed 567193323Sed // Finally, since the node is now dead, remove it from the graph. 568193323Sed DAG.DeleteNode(N); 569193323Sed } 570193323Sed return SDValue(N, 0); 571193323Sed} 572193323Sed 573193323Sedvoid 574193323SedDAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 575193323Sed TLO) { 576193323Sed // Replace all uses. If any nodes become isomorphic to other nodes and 577193323Sed // are deleted, make sure to remove them from our worklist. 578193323Sed WorkListRemover DeadNodes(*this); 579193323Sed DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 580193323Sed 581193323Sed // Push the new node and any (possibly new) users onto the worklist. 582193323Sed AddToWorkList(TLO.New.getNode()); 583193323Sed AddUsersToWorkList(TLO.New.getNode()); 584193323Sed 585193323Sed // Finally, if the node is now dead, remove it from the graph. The node 586193323Sed // may not be dead if the replacement process recursively simplified to 587193323Sed // something else needing this node. 588193323Sed if (TLO.Old.getNode()->use_empty()) { 589193323Sed removeFromWorkList(TLO.Old.getNode()); 590193323Sed 591193323Sed // If the operands of this node are only used by the node, they will now 592193323Sed // be dead. Make sure to visit them first to delete dead nodes early. 593193323Sed for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 594193323Sed if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 595193323Sed AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 596193323Sed 597193323Sed DAG.DeleteNode(TLO.Old.getNode()); 598193323Sed } 599193323Sed} 600193323Sed 601193323Sed/// SimplifyDemandedBits - Check the specified integer node value to see if 602193323Sed/// it can be simplified or if things it uses can be simplified by bit 603193323Sed/// propagation. If so, return true. 604193323Sedbool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 605193323Sed TargetLowering::TargetLoweringOpt TLO(DAG); 606193323Sed APInt KnownZero, KnownOne; 607193323Sed if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 608193323Sed return false; 609193323Sed 610193323Sed // Revisit the node. 611193323Sed AddToWorkList(Op.getNode()); 612193323Sed 613193323Sed // Replace the old value with the new one. 614193323Sed ++NodesCombined; 615193323Sed DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 616193323Sed DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 617193323Sed DOUT << '\n'; 618193323Sed 619193323Sed CommitTargetLoweringOpt(TLO); 620193323Sed return true; 621193323Sed} 622193323Sed 623193323Sed//===----------------------------------------------------------------------===// 624193323Sed// Main DAG Combiner implementation 625193323Sed//===----------------------------------------------------------------------===// 626193323Sed 627193323Sedvoid DAGCombiner::Run(CombineLevel AtLevel) { 628193323Sed // set the instance variables, so that the various visit routines may use it. 629193323Sed Level = AtLevel; 630193323Sed LegalOperations = Level >= NoIllegalOperations; 631193323Sed LegalTypes = Level >= NoIllegalTypes; 632193323Sed 633193323Sed // Add all the dag nodes to the worklist. 634193323Sed WorkList.reserve(DAG.allnodes_size()); 635193323Sed for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 636193323Sed E = DAG.allnodes_end(); I != E; ++I) 637193323Sed WorkList.push_back(I); 638193323Sed 639193323Sed // Create a dummy node (which is not added to allnodes), that adds a reference 640193323Sed // to the root node, preventing it from being deleted, and tracking any 641193323Sed // changes of the root. 642193323Sed HandleSDNode Dummy(DAG.getRoot()); 643193323Sed 644193323Sed // The root of the dag may dangle to deleted nodes until the dag combiner is 645193323Sed // done. Set it to null to avoid confusion. 646193323Sed DAG.setRoot(SDValue()); 647193323Sed 648193323Sed // while the worklist isn't empty, inspect the node on the end of it and 649193323Sed // try and combine it. 650193323Sed while (!WorkList.empty()) { 651193323Sed SDNode *N = WorkList.back(); 652193323Sed WorkList.pop_back(); 653193323Sed 654193323Sed // If N has no uses, it is dead. Make sure to revisit all N's operands once 655193323Sed // N is deleted from the DAG, since they too may now be dead or may have a 656193323Sed // reduced number of uses, allowing other xforms. 657193323Sed if (N->use_empty() && N != &Dummy) { 658193323Sed for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 659193323Sed AddToWorkList(N->getOperand(i).getNode()); 660193323Sed 661193323Sed DAG.DeleteNode(N); 662193323Sed continue; 663193323Sed } 664193323Sed 665193323Sed SDValue RV = combine(N); 666193323Sed 667193323Sed if (RV.getNode() == 0) 668193323Sed continue; 669193323Sed 670193323Sed ++NodesCombined; 671193323Sed 672193323Sed // If we get back the same node we passed in, rather than a new node or 673193323Sed // zero, we know that the node must have defined multiple values and 674193323Sed // CombineTo was used. Since CombineTo takes care of the worklist 675193323Sed // mechanics for us, we have no work to do in this case. 676193323Sed if (RV.getNode() == N) 677193323Sed continue; 678193323Sed 679193323Sed assert(N->getOpcode() != ISD::DELETED_NODE && 680193323Sed RV.getNode()->getOpcode() != ISD::DELETED_NODE && 681193323Sed "Node was deleted but visit returned new node!"); 682193323Sed 683193323Sed DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 684193323Sed DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 685193323Sed DOUT << '\n'; 686193323Sed WorkListRemover DeadNodes(*this); 687193323Sed if (N->getNumValues() == RV.getNode()->getNumValues()) 688193323Sed DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 689193323Sed else { 690193323Sed assert(N->getValueType(0) == RV.getValueType() && 691193323Sed N->getNumValues() == 1 && "Type mismatch"); 692193323Sed SDValue OpV = RV; 693193323Sed DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 694193323Sed } 695193323Sed 696193323Sed // Push the new node and any users onto the worklist 697193323Sed AddToWorkList(RV.getNode()); 698193323Sed AddUsersToWorkList(RV.getNode()); 699193323Sed 700193323Sed // Add any uses of the old node to the worklist in case this node is the 701193323Sed // last one that uses them. They may become dead after this node is 702193323Sed // deleted. 703193323Sed for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 704193323Sed AddToWorkList(N->getOperand(i).getNode()); 705193323Sed 706193323Sed // Finally, if the node is now dead, remove it from the graph. The node 707193323Sed // may not be dead if the replacement process recursively simplified to 708193323Sed // something else needing this node. 709193323Sed if (N->use_empty()) { 710193323Sed // Nodes can be reintroduced into the worklist. Make sure we do not 711193323Sed // process a node that has been replaced. 712193323Sed removeFromWorkList(N); 713193323Sed 714193323Sed // Finally, since the node is now dead, remove it from the graph. 715193323Sed DAG.DeleteNode(N); 716193323Sed } 717193323Sed } 718193323Sed 719193323Sed // If the root changed (e.g. it was a dead load, update the root). 720193323Sed DAG.setRoot(Dummy.getValue()); 721193323Sed} 722193323Sed 723193323SedSDValue DAGCombiner::visit(SDNode *N) { 724193323Sed switch(N->getOpcode()) { 725193323Sed default: break; 726193323Sed case ISD::TokenFactor: return visitTokenFactor(N); 727193323Sed case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 728193323Sed case ISD::ADD: return visitADD(N); 729193323Sed case ISD::SUB: return visitSUB(N); 730193323Sed case ISD::ADDC: return visitADDC(N); 731193323Sed case ISD::ADDE: return visitADDE(N); 732193323Sed case ISD::MUL: return visitMUL(N); 733193323Sed case ISD::SDIV: return visitSDIV(N); 734193323Sed case ISD::UDIV: return visitUDIV(N); 735193323Sed case ISD::SREM: return visitSREM(N); 736193323Sed case ISD::UREM: return visitUREM(N); 737193323Sed case ISD::MULHU: return visitMULHU(N); 738193323Sed case ISD::MULHS: return visitMULHS(N); 739193323Sed case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 740193323Sed case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 741193323Sed case ISD::SDIVREM: return visitSDIVREM(N); 742193323Sed case ISD::UDIVREM: return visitUDIVREM(N); 743193323Sed case ISD::AND: return visitAND(N); 744193323Sed case ISD::OR: return visitOR(N); 745193323Sed case ISD::XOR: return visitXOR(N); 746193323Sed case ISD::SHL: return visitSHL(N); 747193323Sed case ISD::SRA: return visitSRA(N); 748193323Sed case ISD::SRL: return visitSRL(N); 749193323Sed case ISD::CTLZ: return visitCTLZ(N); 750193323Sed case ISD::CTTZ: return visitCTTZ(N); 751193323Sed case ISD::CTPOP: return visitCTPOP(N); 752193323Sed case ISD::SELECT: return visitSELECT(N); 753193323Sed case ISD::SELECT_CC: return visitSELECT_CC(N); 754193323Sed case ISD::SETCC: return visitSETCC(N); 755193323Sed case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 756193323Sed case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 757193323Sed case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 758193323Sed case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 759193323Sed case ISD::TRUNCATE: return visitTRUNCATE(N); 760193323Sed case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 761193323Sed case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 762193323Sed case ISD::FADD: return visitFADD(N); 763193323Sed case ISD::FSUB: return visitFSUB(N); 764193323Sed case ISD::FMUL: return visitFMUL(N); 765193323Sed case ISD::FDIV: return visitFDIV(N); 766193323Sed case ISD::FREM: return visitFREM(N); 767193323Sed case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 768193323Sed case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 769193323Sed case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 770193323Sed case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 771193323Sed case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 772193323Sed case ISD::FP_ROUND: return visitFP_ROUND(N); 773193323Sed case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 774193323Sed case ISD::FP_EXTEND: return visitFP_EXTEND(N); 775193323Sed case ISD::FNEG: return visitFNEG(N); 776193323Sed case ISD::FABS: return visitFABS(N); 777193323Sed case ISD::BRCOND: return visitBRCOND(N); 778193323Sed case ISD::BR_CC: return visitBR_CC(N); 779193323Sed case ISD::LOAD: return visitLOAD(N); 780193323Sed case ISD::STORE: return visitSTORE(N); 781193323Sed case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 782193323Sed case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 783193323Sed case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 784193323Sed case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 785193323Sed case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 786193323Sed } 787193323Sed return SDValue(); 788193323Sed} 789193323Sed 790193323SedSDValue DAGCombiner::combine(SDNode *N) { 791193323Sed SDValue RV = visit(N); 792193323Sed 793193323Sed // If nothing happened, try a target-specific DAG combine. 794193323Sed if (RV.getNode() == 0) { 795193323Sed assert(N->getOpcode() != ISD::DELETED_NODE && 796193323Sed "Node was deleted but visit returned NULL!"); 797193323Sed 798193323Sed if (N->getOpcode() >= ISD::BUILTIN_OP_END || 799193323Sed TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 800193323Sed 801193323Sed // Expose the DAG combiner to the target combiner impls. 802193323Sed TargetLowering::DAGCombinerInfo 803193323Sed DagCombineInfo(DAG, Level == Unrestricted, false, this); 804193323Sed 805193323Sed RV = TLI.PerformDAGCombine(N, DagCombineInfo); 806193323Sed } 807193323Sed } 808193323Sed 809193323Sed // If N is a commutative binary node, try commuting it to enable more 810193323Sed // sdisel CSE. 811193323Sed if (RV.getNode() == 0 && 812193323Sed SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 813193323Sed N->getNumValues() == 1) { 814193323Sed SDValue N0 = N->getOperand(0); 815193323Sed SDValue N1 = N->getOperand(1); 816193323Sed 817193323Sed // Constant operands are canonicalized to RHS. 818193323Sed if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 819193323Sed SDValue Ops[] = { N1, N0 }; 820193323Sed SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 821193323Sed Ops, 2); 822193323Sed if (CSENode) 823193323Sed return SDValue(CSENode, 0); 824193323Sed } 825193323Sed } 826193323Sed 827193323Sed return RV; 828193323Sed} 829193323Sed 830193323Sed/// getInputChainForNode - Given a node, return its input chain if it has one, 831193323Sed/// otherwise return a null sd operand. 832193323Sedstatic SDValue getInputChainForNode(SDNode *N) { 833193323Sed if (unsigned NumOps = N->getNumOperands()) { 834193323Sed if (N->getOperand(0).getValueType() == MVT::Other) 835193323Sed return N->getOperand(0); 836193323Sed else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 837193323Sed return N->getOperand(NumOps-1); 838193323Sed for (unsigned i = 1; i < NumOps-1; ++i) 839193323Sed if (N->getOperand(i).getValueType() == MVT::Other) 840193323Sed return N->getOperand(i); 841193323Sed } 842193323Sed return SDValue(); 843193323Sed} 844193323Sed 845193323SedSDValue DAGCombiner::visitTokenFactor(SDNode *N) { 846193323Sed // If N has two operands, where one has an input chain equal to the other, 847193323Sed // the 'other' chain is redundant. 848193323Sed if (N->getNumOperands() == 2) { 849193323Sed if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 850193323Sed return N->getOperand(0); 851193323Sed if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 852193323Sed return N->getOperand(1); 853193323Sed } 854193323Sed 855193323Sed SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 856193323Sed SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 857193323Sed SmallPtrSet<SDNode*, 16> SeenOps; 858193323Sed bool Changed = false; // If we should replace this token factor. 859193323Sed 860193323Sed // Start out with this token factor. 861193323Sed TFs.push_back(N); 862193323Sed 863193323Sed // Iterate through token factors. The TFs grows when new token factors are 864193323Sed // encountered. 865193323Sed for (unsigned i = 0; i < TFs.size(); ++i) { 866193323Sed SDNode *TF = TFs[i]; 867193323Sed 868193323Sed // Check each of the operands. 869193323Sed for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 870193323Sed SDValue Op = TF->getOperand(i); 871193323Sed 872193323Sed switch (Op.getOpcode()) { 873193323Sed case ISD::EntryToken: 874193323Sed // Entry tokens don't need to be added to the list. They are 875193323Sed // rededundant. 876193323Sed Changed = true; 877193323Sed break; 878193323Sed 879193323Sed case ISD::TokenFactor: 880193323Sed if ((CombinerAA || Op.hasOneUse()) && 881193323Sed std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 882193323Sed // Queue up for processing. 883193323Sed TFs.push_back(Op.getNode()); 884193323Sed // Clean up in case the token factor is removed. 885193323Sed AddToWorkList(Op.getNode()); 886193323Sed Changed = true; 887193323Sed break; 888193323Sed } 889193323Sed // Fall thru 890193323Sed 891193323Sed default: 892193323Sed // Only add if it isn't already in the list. 893193323Sed if (SeenOps.insert(Op.getNode())) 894193323Sed Ops.push_back(Op); 895193323Sed else 896193323Sed Changed = true; 897193323Sed break; 898193323Sed } 899193323Sed } 900193323Sed } 901193323Sed 902193323Sed SDValue Result; 903193323Sed 904193323Sed // If we've change things around then replace token factor. 905193323Sed if (Changed) { 906193323Sed if (Ops.empty()) { 907193323Sed // The entry token is the only possible outcome. 908193323Sed Result = DAG.getEntryNode(); 909193323Sed } else { 910193323Sed // New and improved token factor. 911193323Sed Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 912193323Sed MVT::Other, &Ops[0], Ops.size()); 913193323Sed } 914193323Sed 915193323Sed // Don't add users to work list. 916193323Sed return CombineTo(N, Result, false); 917193323Sed } 918193323Sed 919193323Sed return Result; 920193323Sed} 921193323Sed 922193323Sed/// MERGE_VALUES can always be eliminated. 923193323SedSDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 924193323Sed WorkListRemover DeadNodes(*this); 925193323Sed for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 926193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 927193323Sed &DeadNodes); 928193323Sed removeFromWorkList(N); 929193323Sed DAG.DeleteNode(N); 930193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 931193323Sed} 932193323Sed 933193323Sedstatic 934193323SedSDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 935193323Sed SelectionDAG &DAG) { 936193323Sed MVT VT = N0.getValueType(); 937193323Sed SDValue N00 = N0.getOperand(0); 938193323Sed SDValue N01 = N0.getOperand(1); 939193323Sed ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 940193323Sed 941193323Sed if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 942193323Sed isa<ConstantSDNode>(N00.getOperand(1))) { 943193323Sed // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 944193323Sed N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 945193323Sed DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 946193323Sed N00.getOperand(0), N01), 947193323Sed DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 948193323Sed N00.getOperand(1), N01)); 949193323Sed return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 950193323Sed } 951193323Sed 952193323Sed return SDValue(); 953193323Sed} 954193323Sed 955193323SedSDValue DAGCombiner::visitADD(SDNode *N) { 956193323Sed SDValue N0 = N->getOperand(0); 957193323Sed SDValue N1 = N->getOperand(1); 958193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 959193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 960193323Sed MVT VT = N0.getValueType(); 961193323Sed 962193323Sed // fold vector ops 963193323Sed if (VT.isVector()) { 964193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 965193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 966193323Sed } 967193323Sed 968193323Sed // fold (add x, undef) -> undef 969193323Sed if (N0.getOpcode() == ISD::UNDEF) 970193323Sed return N0; 971193323Sed if (N1.getOpcode() == ISD::UNDEF) 972193323Sed return N1; 973193323Sed // fold (add c1, c2) -> c1+c2 974193323Sed if (N0C && N1C) 975193323Sed return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 976193323Sed // canonicalize constant to RHS 977193323Sed if (N0C && !N1C) 978193323Sed return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 979193323Sed // fold (add x, 0) -> x 980193323Sed if (N1C && N1C->isNullValue()) 981193323Sed return N0; 982193323Sed // fold (add Sym, c) -> Sym+c 983193323Sed if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 984193323Sed if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 985193323Sed GA->getOpcode() == ISD::GlobalAddress) 986193323Sed return DAG.getGlobalAddress(GA->getGlobal(), VT, 987193323Sed GA->getOffset() + 988193323Sed (uint64_t)N1C->getSExtValue()); 989193323Sed // fold ((c1-A)+c2) -> (c1+c2)-A 990193323Sed if (N1C && N0.getOpcode() == ISD::SUB) 991193323Sed if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 992193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 993193323Sed DAG.getConstant(N1C->getAPIntValue()+ 994193323Sed N0C->getAPIntValue(), VT), 995193323Sed N0.getOperand(1)); 996193323Sed // reassociate add 997193323Sed SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 998193323Sed if (RADD.getNode() != 0) 999193323Sed return RADD; 1000193323Sed // fold ((0-A) + B) -> B-A 1001193323Sed if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1002193323Sed cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1003193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1004193323Sed // fold (A + (0-B)) -> A-B 1005193323Sed if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1006193323Sed cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1007193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1008193323Sed // fold (A+(B-A)) -> B 1009193323Sed if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1010193323Sed return N1.getOperand(0); 1011193323Sed // fold ((B-A)+A) -> B 1012193323Sed if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1013193323Sed return N0.getOperand(0); 1014193323Sed // fold (A+(B-(A+C))) to (B-C) 1015193323Sed if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1016193323Sed N0 == N1.getOperand(1).getOperand(0)) 1017193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1018193323Sed N1.getOperand(1).getOperand(1)); 1019193323Sed // fold (A+(B-(C+A))) to (B-C) 1020193323Sed if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1021193323Sed N0 == N1.getOperand(1).getOperand(1)) 1022193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1023193323Sed N1.getOperand(1).getOperand(0)); 1024193323Sed // fold (A+((B-A)+or-C)) to (B+or-C) 1025193323Sed if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1026193323Sed N1.getOperand(0).getOpcode() == ISD::SUB && 1027193323Sed N0 == N1.getOperand(0).getOperand(1)) 1028193323Sed return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1029193323Sed N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1030193323Sed 1031193323Sed // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1032193323Sed if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1033193323Sed SDValue N00 = N0.getOperand(0); 1034193323Sed SDValue N01 = N0.getOperand(1); 1035193323Sed SDValue N10 = N1.getOperand(0); 1036193323Sed SDValue N11 = N1.getOperand(1); 1037193323Sed 1038193323Sed if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1039193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1040193323Sed DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1041193323Sed DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1042193323Sed } 1043193323Sed 1044193323Sed if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1045193323Sed return SDValue(N, 0); 1046193323Sed 1047193323Sed // fold (a+b) -> (a|b) iff a and b share no bits. 1048193323Sed if (VT.isInteger() && !VT.isVector()) { 1049193323Sed APInt LHSZero, LHSOne; 1050193323Sed APInt RHSZero, RHSOne; 1051193323Sed APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1052193323Sed DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1053193323Sed 1054193323Sed if (LHSZero.getBoolValue()) { 1055193323Sed DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1056193323Sed 1057193323Sed // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1058193323Sed // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1059193323Sed if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1060193323Sed (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1061193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1062193323Sed } 1063193323Sed } 1064193323Sed 1065193323Sed // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1066193323Sed if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1067193323Sed SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1068193323Sed if (Result.getNode()) return Result; 1069193323Sed } 1070193323Sed if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1071193323Sed SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1072193323Sed if (Result.getNode()) return Result; 1073193323Sed } 1074193323Sed 1075193323Sed return SDValue(); 1076193323Sed} 1077193323Sed 1078193323SedSDValue DAGCombiner::visitADDC(SDNode *N) { 1079193323Sed SDValue N0 = N->getOperand(0); 1080193323Sed SDValue N1 = N->getOperand(1); 1081193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1082193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1083193323Sed MVT VT = N0.getValueType(); 1084193323Sed 1085193323Sed // If the flag result is dead, turn this into an ADD. 1086193323Sed if (N->hasNUsesOfValue(0, 1)) 1087193323Sed return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1088193323Sed DAG.getNode(ISD::CARRY_FALSE, 1089193323Sed N->getDebugLoc(), MVT::Flag)); 1090193323Sed 1091193323Sed // canonicalize constant to RHS. 1092193323Sed if (N0C && !N1C) 1093193323Sed return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1094193323Sed 1095193323Sed // fold (addc x, 0) -> x + no carry out 1096193323Sed if (N1C && N1C->isNullValue()) 1097193323Sed return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1098193323Sed N->getDebugLoc(), MVT::Flag)); 1099193323Sed 1100193323Sed // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1101193323Sed APInt LHSZero, LHSOne; 1102193323Sed APInt RHSZero, RHSOne; 1103193323Sed APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1104193323Sed DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1105193323Sed 1106193323Sed if (LHSZero.getBoolValue()) { 1107193323Sed DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1108193323Sed 1109193323Sed // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1110193323Sed // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1111193323Sed if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1112193323Sed (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1113193323Sed return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1114193323Sed DAG.getNode(ISD::CARRY_FALSE, 1115193323Sed N->getDebugLoc(), MVT::Flag)); 1116193323Sed } 1117193323Sed 1118193323Sed return SDValue(); 1119193323Sed} 1120193323Sed 1121193323SedSDValue DAGCombiner::visitADDE(SDNode *N) { 1122193323Sed SDValue N0 = N->getOperand(0); 1123193323Sed SDValue N1 = N->getOperand(1); 1124193323Sed SDValue CarryIn = N->getOperand(2); 1125193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1126193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1127193323Sed 1128193323Sed // canonicalize constant to RHS 1129193323Sed if (N0C && !N1C) 1130193323Sed return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1131193323Sed N1, N0, CarryIn); 1132193323Sed 1133193323Sed // fold (adde x, y, false) -> (addc x, y) 1134193323Sed if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1135193323Sed return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1136193323Sed 1137193323Sed return SDValue(); 1138193323Sed} 1139193323Sed 1140193323SedSDValue DAGCombiner::visitSUB(SDNode *N) { 1141193323Sed SDValue N0 = N->getOperand(0); 1142193323Sed SDValue N1 = N->getOperand(1); 1143193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1144193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1145193323Sed MVT VT = N0.getValueType(); 1146193323Sed 1147193323Sed // fold vector ops 1148193323Sed if (VT.isVector()) { 1149193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1150193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1151193323Sed } 1152193323Sed 1153193323Sed // fold (sub x, x) -> 0 1154193323Sed if (N0 == N1) 1155193323Sed return DAG.getConstant(0, N->getValueType(0)); 1156193323Sed // fold (sub c1, c2) -> c1-c2 1157193323Sed if (N0C && N1C) 1158193323Sed return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1159193323Sed // fold (sub x, c) -> (add x, -c) 1160193323Sed if (N1C) 1161193323Sed return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1162193323Sed DAG.getConstant(-N1C->getAPIntValue(), VT)); 1163193323Sed // fold (A+B)-A -> B 1164193323Sed if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1165193323Sed return N0.getOperand(1); 1166193323Sed // fold (A+B)-B -> A 1167193323Sed if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1168193323Sed return N0.getOperand(0); 1169193323Sed // fold ((A+(B+or-C))-B) -> A+or-C 1170193323Sed if (N0.getOpcode() == ISD::ADD && 1171193323Sed (N0.getOperand(1).getOpcode() == ISD::SUB || 1172193323Sed N0.getOperand(1).getOpcode() == ISD::ADD) && 1173193323Sed N0.getOperand(1).getOperand(0) == N1) 1174193323Sed return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1175193323Sed N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1176193323Sed // fold ((A+(C+B))-B) -> A+C 1177193323Sed if (N0.getOpcode() == ISD::ADD && 1178193323Sed N0.getOperand(1).getOpcode() == ISD::ADD && 1179193323Sed N0.getOperand(1).getOperand(1) == N1) 1180193323Sed return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1181193323Sed N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1182193323Sed // fold ((A-(B-C))-C) -> A-B 1183193323Sed if (N0.getOpcode() == ISD::SUB && 1184193323Sed N0.getOperand(1).getOpcode() == ISD::SUB && 1185193323Sed N0.getOperand(1).getOperand(1) == N1) 1186193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1187193323Sed N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1188193323Sed 1189193323Sed // If either operand of a sub is undef, the result is undef 1190193323Sed if (N0.getOpcode() == ISD::UNDEF) 1191193323Sed return N0; 1192193323Sed if (N1.getOpcode() == ISD::UNDEF) 1193193323Sed return N1; 1194193323Sed 1195193323Sed // If the relocation model supports it, consider symbol offsets. 1196193323Sed if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1197193323Sed if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1198193323Sed // fold (sub Sym, c) -> Sym-c 1199193323Sed if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1200193323Sed return DAG.getGlobalAddress(GA->getGlobal(), VT, 1201193323Sed GA->getOffset() - 1202193323Sed (uint64_t)N1C->getSExtValue()); 1203193323Sed // fold (sub Sym+c1, Sym+c2) -> c1-c2 1204193323Sed if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1205193323Sed if (GA->getGlobal() == GB->getGlobal()) 1206193323Sed return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1207193323Sed VT); 1208193323Sed } 1209193323Sed 1210193323Sed return SDValue(); 1211193323Sed} 1212193323Sed 1213193323SedSDValue DAGCombiner::visitMUL(SDNode *N) { 1214193323Sed SDValue N0 = N->getOperand(0); 1215193323Sed SDValue N1 = N->getOperand(1); 1216193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1217193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1218193323Sed MVT VT = N0.getValueType(); 1219193323Sed 1220193323Sed // fold vector ops 1221193323Sed if (VT.isVector()) { 1222193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1223193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1224193323Sed } 1225193323Sed 1226193323Sed // fold (mul x, undef) -> 0 1227193323Sed if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1228193323Sed return DAG.getConstant(0, VT); 1229193323Sed // fold (mul c1, c2) -> c1*c2 1230193323Sed if (N0C && N1C) 1231193323Sed return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1232193323Sed // canonicalize constant to RHS 1233193323Sed if (N0C && !N1C) 1234193323Sed return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1235193323Sed // fold (mul x, 0) -> 0 1236193323Sed if (N1C && N1C->isNullValue()) 1237193323Sed return N1; 1238193323Sed // fold (mul x, -1) -> 0-x 1239193323Sed if (N1C && N1C->isAllOnesValue()) 1240193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1241193323Sed DAG.getConstant(0, VT), N0); 1242193323Sed // fold (mul x, (1 << c)) -> x << c 1243193323Sed if (N1C && N1C->getAPIntValue().isPowerOf2()) 1244193323Sed return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1245193323Sed DAG.getConstant(N1C->getAPIntValue().logBase2(), 1246193323Sed getShiftAmountTy())); 1247193323Sed // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1248193323Sed if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1249193323Sed unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1250193323Sed // FIXME: If the input is something that is easily negated (e.g. a 1251193323Sed // single-use add), we should put the negate there. 1252193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1253193323Sed DAG.getConstant(0, VT), 1254193323Sed DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1255193323Sed DAG.getConstant(Log2Val, getShiftAmountTy()))); 1256193323Sed } 1257193323Sed // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1258193323Sed if (N1C && N0.getOpcode() == ISD::SHL && 1259193323Sed isa<ConstantSDNode>(N0.getOperand(1))) { 1260193323Sed SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1261193323Sed N1, N0.getOperand(1)); 1262193323Sed AddToWorkList(C3.getNode()); 1263193323Sed return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1264193323Sed N0.getOperand(0), C3); 1265193323Sed } 1266193323Sed 1267193323Sed // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1268193323Sed // use. 1269193323Sed { 1270193323Sed SDValue Sh(0,0), Y(0,0); 1271193323Sed // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1272193323Sed if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1273193323Sed N0.getNode()->hasOneUse()) { 1274193323Sed Sh = N0; Y = N1; 1275193323Sed } else if (N1.getOpcode() == ISD::SHL && 1276193323Sed isa<ConstantSDNode>(N1.getOperand(1)) && 1277193323Sed N1.getNode()->hasOneUse()) { 1278193323Sed Sh = N1; Y = N0; 1279193323Sed } 1280193323Sed 1281193323Sed if (Sh.getNode()) { 1282193323Sed SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1283193323Sed Sh.getOperand(0), Y); 1284193323Sed return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1285193323Sed Mul, Sh.getOperand(1)); 1286193323Sed } 1287193323Sed } 1288193323Sed 1289193323Sed // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1290193323Sed if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1291193323Sed isa<ConstantSDNode>(N0.getOperand(1))) 1292193323Sed return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1293193323Sed DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1294193323Sed N0.getOperand(0), N1), 1295193323Sed DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1296193323Sed N0.getOperand(1), N1)); 1297193323Sed 1298193323Sed // reassociate mul 1299193323Sed SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1300193323Sed if (RMUL.getNode() != 0) 1301193323Sed return RMUL; 1302193323Sed 1303193323Sed return SDValue(); 1304193323Sed} 1305193323Sed 1306193323SedSDValue DAGCombiner::visitSDIV(SDNode *N) { 1307193323Sed SDValue N0 = N->getOperand(0); 1308193323Sed SDValue N1 = N->getOperand(1); 1309193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1310193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1311193323Sed MVT VT = N->getValueType(0); 1312193323Sed 1313193323Sed // fold vector ops 1314193323Sed if (VT.isVector()) { 1315193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1316193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1317193323Sed } 1318193323Sed 1319193323Sed // fold (sdiv c1, c2) -> c1/c2 1320193323Sed if (N0C && N1C && !N1C->isNullValue()) 1321193323Sed return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1322193323Sed // fold (sdiv X, 1) -> X 1323193323Sed if (N1C && N1C->getSExtValue() == 1LL) 1324193323Sed return N0; 1325193323Sed // fold (sdiv X, -1) -> 0-X 1326193323Sed if (N1C && N1C->isAllOnesValue()) 1327193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1328193323Sed DAG.getConstant(0, VT), N0); 1329193323Sed // If we know the sign bits of both operands are zero, strength reduce to a 1330193323Sed // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1331193323Sed if (!VT.isVector()) { 1332193323Sed if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1333193323Sed return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1334193323Sed N0, N1); 1335193323Sed } 1336193323Sed // fold (sdiv X, pow2) -> simple ops after legalize 1337193323Sed if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1338193323Sed (isPowerOf2_64(N1C->getSExtValue()) || 1339193323Sed isPowerOf2_64(-N1C->getSExtValue()))) { 1340193323Sed // If dividing by powers of two is cheap, then don't perform the following 1341193323Sed // fold. 1342193323Sed if (TLI.isPow2DivCheap()) 1343193323Sed return SDValue(); 1344193323Sed 1345193323Sed int64_t pow2 = N1C->getSExtValue(); 1346193323Sed int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1347193323Sed unsigned lg2 = Log2_64(abs2); 1348193323Sed 1349193323Sed // Splat the sign bit into the register 1350193323Sed SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1351193323Sed DAG.getConstant(VT.getSizeInBits()-1, 1352193323Sed getShiftAmountTy())); 1353193323Sed AddToWorkList(SGN.getNode()); 1354193323Sed 1355193323Sed // Add (N0 < 0) ? abs2 - 1 : 0; 1356193323Sed SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1357193323Sed DAG.getConstant(VT.getSizeInBits() - lg2, 1358193323Sed getShiftAmountTy())); 1359193323Sed SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1360193323Sed AddToWorkList(SRL.getNode()); 1361193323Sed AddToWorkList(ADD.getNode()); // Divide by pow2 1362193323Sed SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1363193323Sed DAG.getConstant(lg2, getShiftAmountTy())); 1364193323Sed 1365193323Sed // If we're dividing by a positive value, we're done. Otherwise, we must 1366193323Sed // negate the result. 1367193323Sed if (pow2 > 0) 1368193323Sed return SRA; 1369193323Sed 1370193323Sed AddToWorkList(SRA.getNode()); 1371193323Sed return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1372193323Sed DAG.getConstant(0, VT), SRA); 1373193323Sed } 1374193323Sed 1375193323Sed // if integer divide is expensive and we satisfy the requirements, emit an 1376193323Sed // alternate sequence. 1377193323Sed if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1378193323Sed !TLI.isIntDivCheap()) { 1379193323Sed SDValue Op = BuildSDIV(N); 1380193323Sed if (Op.getNode()) return Op; 1381193323Sed } 1382193323Sed 1383193323Sed // undef / X -> 0 1384193323Sed if (N0.getOpcode() == ISD::UNDEF) 1385193323Sed return DAG.getConstant(0, VT); 1386193323Sed // X / undef -> undef 1387193323Sed if (N1.getOpcode() == ISD::UNDEF) 1388193323Sed return N1; 1389193323Sed 1390193323Sed return SDValue(); 1391193323Sed} 1392193323Sed 1393193323SedSDValue DAGCombiner::visitUDIV(SDNode *N) { 1394193323Sed SDValue N0 = N->getOperand(0); 1395193323Sed SDValue N1 = N->getOperand(1); 1396193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1397193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1398193323Sed MVT VT = N->getValueType(0); 1399193323Sed 1400193323Sed // fold vector ops 1401193323Sed if (VT.isVector()) { 1402193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1403193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1404193323Sed } 1405193323Sed 1406193323Sed // fold (udiv c1, c2) -> c1/c2 1407193323Sed if (N0C && N1C && !N1C->isNullValue()) 1408193323Sed return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1409193323Sed // fold (udiv x, (1 << c)) -> x >>u c 1410193323Sed if (N1C && N1C->getAPIntValue().isPowerOf2()) 1411193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1412193323Sed DAG.getConstant(N1C->getAPIntValue().logBase2(), 1413193323Sed getShiftAmountTy())); 1414193323Sed // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1415193323Sed if (N1.getOpcode() == ISD::SHL) { 1416193323Sed if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1417193323Sed if (SHC->getAPIntValue().isPowerOf2()) { 1418193323Sed MVT ADDVT = N1.getOperand(1).getValueType(); 1419193323Sed SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1420193323Sed N1.getOperand(1), 1421193323Sed DAG.getConstant(SHC->getAPIntValue() 1422193323Sed .logBase2(), 1423193323Sed ADDVT)); 1424193323Sed AddToWorkList(Add.getNode()); 1425193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1426193323Sed } 1427193323Sed } 1428193323Sed } 1429193323Sed // fold (udiv x, c) -> alternate 1430193323Sed if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1431193323Sed SDValue Op = BuildUDIV(N); 1432193323Sed if (Op.getNode()) return Op; 1433193323Sed } 1434193323Sed 1435193323Sed // undef / X -> 0 1436193323Sed if (N0.getOpcode() == ISD::UNDEF) 1437193323Sed return DAG.getConstant(0, VT); 1438193323Sed // X / undef -> undef 1439193323Sed if (N1.getOpcode() == ISD::UNDEF) 1440193323Sed return N1; 1441193323Sed 1442193323Sed return SDValue(); 1443193323Sed} 1444193323Sed 1445193323SedSDValue DAGCombiner::visitSREM(SDNode *N) { 1446193323Sed SDValue N0 = N->getOperand(0); 1447193323Sed SDValue N1 = N->getOperand(1); 1448193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1449193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1450193323Sed MVT VT = N->getValueType(0); 1451193323Sed 1452193323Sed // fold (srem c1, c2) -> c1%c2 1453193323Sed if (N0C && N1C && !N1C->isNullValue()) 1454193323Sed return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1455193323Sed // If we know the sign bits of both operands are zero, strength reduce to a 1456193323Sed // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1457193323Sed if (!VT.isVector()) { 1458193323Sed if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1459193323Sed return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1460193323Sed } 1461193323Sed 1462193323Sed // If X/C can be simplified by the division-by-constant logic, lower 1463193323Sed // X%C to the equivalent of X-X/C*C. 1464193323Sed if (N1C && !N1C->isNullValue()) { 1465193323Sed SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1466193323Sed AddToWorkList(Div.getNode()); 1467193323Sed SDValue OptimizedDiv = combine(Div.getNode()); 1468193323Sed if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1469193323Sed SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1470193323Sed OptimizedDiv, N1); 1471193323Sed SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1472193323Sed AddToWorkList(Mul.getNode()); 1473193323Sed return Sub; 1474193323Sed } 1475193323Sed } 1476193323Sed 1477193323Sed // undef % X -> 0 1478193323Sed if (N0.getOpcode() == ISD::UNDEF) 1479193323Sed return DAG.getConstant(0, VT); 1480193323Sed // X % undef -> undef 1481193323Sed if (N1.getOpcode() == ISD::UNDEF) 1482193323Sed return N1; 1483193323Sed 1484193323Sed return SDValue(); 1485193323Sed} 1486193323Sed 1487193323SedSDValue DAGCombiner::visitUREM(SDNode *N) { 1488193323Sed SDValue N0 = N->getOperand(0); 1489193323Sed SDValue N1 = N->getOperand(1); 1490193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1491193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1492193323Sed MVT VT = N->getValueType(0); 1493193323Sed 1494193323Sed // fold (urem c1, c2) -> c1%c2 1495193323Sed if (N0C && N1C && !N1C->isNullValue()) 1496193323Sed return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1497193323Sed // fold (urem x, pow2) -> (and x, pow2-1) 1498193323Sed if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1499193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1500193323Sed DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1501193323Sed // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1502193323Sed if (N1.getOpcode() == ISD::SHL) { 1503193323Sed if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1504193323Sed if (SHC->getAPIntValue().isPowerOf2()) { 1505193323Sed SDValue Add = 1506193323Sed DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1507193323Sed DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1508193323Sed VT)); 1509193323Sed AddToWorkList(Add.getNode()); 1510193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1511193323Sed } 1512193323Sed } 1513193323Sed } 1514193323Sed 1515193323Sed // If X/C can be simplified by the division-by-constant logic, lower 1516193323Sed // X%C to the equivalent of X-X/C*C. 1517193323Sed if (N1C && !N1C->isNullValue()) { 1518193323Sed SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1519193323Sed AddToWorkList(Div.getNode()); 1520193323Sed SDValue OptimizedDiv = combine(Div.getNode()); 1521193323Sed if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1522193323Sed SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1523193323Sed OptimizedDiv, N1); 1524193323Sed SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1525193323Sed AddToWorkList(Mul.getNode()); 1526193323Sed return Sub; 1527193323Sed } 1528193323Sed } 1529193323Sed 1530193323Sed // undef % X -> 0 1531193323Sed if (N0.getOpcode() == ISD::UNDEF) 1532193323Sed return DAG.getConstant(0, VT); 1533193323Sed // X % undef -> undef 1534193323Sed if (N1.getOpcode() == ISD::UNDEF) 1535193323Sed return N1; 1536193323Sed 1537193323Sed return SDValue(); 1538193323Sed} 1539193323Sed 1540193323SedSDValue DAGCombiner::visitMULHS(SDNode *N) { 1541193323Sed SDValue N0 = N->getOperand(0); 1542193323Sed SDValue N1 = N->getOperand(1); 1543193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1544193323Sed MVT VT = N->getValueType(0); 1545193323Sed 1546193323Sed // fold (mulhs x, 0) -> 0 1547193323Sed if (N1C && N1C->isNullValue()) 1548193323Sed return N1; 1549193323Sed // fold (mulhs x, 1) -> (sra x, size(x)-1) 1550193323Sed if (N1C && N1C->getAPIntValue() == 1) 1551193323Sed return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1552193323Sed DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1553193323Sed getShiftAmountTy())); 1554193323Sed // fold (mulhs x, undef) -> 0 1555193323Sed if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1556193323Sed return DAG.getConstant(0, VT); 1557193323Sed 1558193323Sed return SDValue(); 1559193323Sed} 1560193323Sed 1561193323SedSDValue DAGCombiner::visitMULHU(SDNode *N) { 1562193323Sed SDValue N0 = N->getOperand(0); 1563193323Sed SDValue N1 = N->getOperand(1); 1564193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1565193323Sed MVT VT = N->getValueType(0); 1566193323Sed 1567193323Sed // fold (mulhu x, 0) -> 0 1568193323Sed if (N1C && N1C->isNullValue()) 1569193323Sed return N1; 1570193323Sed // fold (mulhu x, 1) -> 0 1571193323Sed if (N1C && N1C->getAPIntValue() == 1) 1572193323Sed return DAG.getConstant(0, N0.getValueType()); 1573193323Sed // fold (mulhu x, undef) -> 0 1574193323Sed if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1575193323Sed return DAG.getConstant(0, VT); 1576193323Sed 1577193323Sed return SDValue(); 1578193323Sed} 1579193323Sed 1580193323Sed/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1581193323Sed/// compute two values. LoOp and HiOp give the opcodes for the two computations 1582193323Sed/// that are being performed. Return true if a simplification was made. 1583193323Sed/// 1584193323SedSDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1585193323Sed unsigned HiOp) { 1586193323Sed // If the high half is not needed, just compute the low half. 1587193323Sed bool HiExists = N->hasAnyUseOfValue(1); 1588193323Sed if (!HiExists && 1589193323Sed (!LegalOperations || 1590193323Sed TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1591193323Sed SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1592193323Sed N->op_begin(), N->getNumOperands()); 1593193323Sed return CombineTo(N, Res, Res); 1594193323Sed } 1595193323Sed 1596193323Sed // If the low half is not needed, just compute the high half. 1597193323Sed bool LoExists = N->hasAnyUseOfValue(0); 1598193323Sed if (!LoExists && 1599193323Sed (!LegalOperations || 1600193323Sed TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1601193323Sed SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1602193323Sed N->op_begin(), N->getNumOperands()); 1603193323Sed return CombineTo(N, Res, Res); 1604193323Sed } 1605193323Sed 1606193323Sed // If both halves are used, return as it is. 1607193323Sed if (LoExists && HiExists) 1608193323Sed return SDValue(); 1609193323Sed 1610193323Sed // If the two computed results can be simplified separately, separate them. 1611193323Sed if (LoExists) { 1612193323Sed SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1613193323Sed N->op_begin(), N->getNumOperands()); 1614193323Sed AddToWorkList(Lo.getNode()); 1615193323Sed SDValue LoOpt = combine(Lo.getNode()); 1616193323Sed if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1617193323Sed (!LegalOperations || 1618193323Sed TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1619193323Sed return CombineTo(N, LoOpt, LoOpt); 1620193323Sed } 1621193323Sed 1622193323Sed if (HiExists) { 1623193323Sed SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1624193323Sed N->op_begin(), N->getNumOperands()); 1625193323Sed AddToWorkList(Hi.getNode()); 1626193323Sed SDValue HiOpt = combine(Hi.getNode()); 1627193323Sed if (HiOpt.getNode() && HiOpt != Hi && 1628193323Sed (!LegalOperations || 1629193323Sed TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1630193323Sed return CombineTo(N, HiOpt, HiOpt); 1631193323Sed } 1632193323Sed 1633193323Sed return SDValue(); 1634193323Sed} 1635193323Sed 1636193323SedSDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1637193323Sed SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1638193323Sed if (Res.getNode()) return Res; 1639193323Sed 1640193323Sed return SDValue(); 1641193323Sed} 1642193323Sed 1643193323SedSDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1644193323Sed SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1645193323Sed if (Res.getNode()) return Res; 1646193323Sed 1647193323Sed return SDValue(); 1648193323Sed} 1649193323Sed 1650193323SedSDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1651193323Sed SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1652193323Sed if (Res.getNode()) return Res; 1653193323Sed 1654193323Sed return SDValue(); 1655193323Sed} 1656193323Sed 1657193323SedSDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1658193323Sed SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1659193323Sed if (Res.getNode()) return Res; 1660193323Sed 1661193323Sed return SDValue(); 1662193323Sed} 1663193323Sed 1664193323Sed/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1665193323Sed/// two operands of the same opcode, try to simplify it. 1666193323SedSDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1667193323Sed SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1668193323Sed MVT VT = N0.getValueType(); 1669193323Sed assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1670193323Sed 1671193323Sed // For each of OP in AND/OR/XOR: 1672193323Sed // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1673193323Sed // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1674193323Sed // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1675193323Sed // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1676193323Sed if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1677193323Sed N0.getOpcode() == ISD::SIGN_EXTEND || 1678193323Sed (N0.getOpcode() == ISD::TRUNCATE && 1679193323Sed !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1680193323Sed N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1681193323Sed SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1682193323Sed N0.getOperand(0).getValueType(), 1683193323Sed N0.getOperand(0), N1.getOperand(0)); 1684193323Sed AddToWorkList(ORNode.getNode()); 1685193323Sed return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1686193323Sed } 1687193323Sed 1688193323Sed // For each of OP in SHL/SRL/SRA/AND... 1689193323Sed // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1690193323Sed // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1691193323Sed // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1692193323Sed if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1693193323Sed N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1694193323Sed N0.getOperand(1) == N1.getOperand(1)) { 1695193323Sed SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1696193323Sed N0.getOperand(0).getValueType(), 1697193323Sed N0.getOperand(0), N1.getOperand(0)); 1698193323Sed AddToWorkList(ORNode.getNode()); 1699193323Sed return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1700193323Sed ORNode, N0.getOperand(1)); 1701193323Sed } 1702193323Sed 1703193323Sed return SDValue(); 1704193323Sed} 1705193323Sed 1706193323SedSDValue DAGCombiner::visitAND(SDNode *N) { 1707193323Sed SDValue N0 = N->getOperand(0); 1708193323Sed SDValue N1 = N->getOperand(1); 1709193323Sed SDValue LL, LR, RL, RR, CC0, CC1; 1710193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1711193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1712193323Sed MVT VT = N1.getValueType(); 1713193323Sed unsigned BitWidth = VT.getSizeInBits(); 1714193323Sed 1715193323Sed // fold vector ops 1716193323Sed if (VT.isVector()) { 1717193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1718193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1719193323Sed } 1720193323Sed 1721193323Sed // fold (and x, undef) -> 0 1722193323Sed if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1723193323Sed return DAG.getConstant(0, VT); 1724193323Sed // fold (and c1, c2) -> c1&c2 1725193323Sed if (N0C && N1C) 1726193323Sed return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1727193323Sed // canonicalize constant to RHS 1728193323Sed if (N0C && !N1C) 1729193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1730193323Sed // fold (and x, -1) -> x 1731193323Sed if (N1C && N1C->isAllOnesValue()) 1732193323Sed return N0; 1733193323Sed // if (and x, c) is known to be zero, return 0 1734193323Sed if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1735193323Sed APInt::getAllOnesValue(BitWidth))) 1736193323Sed return DAG.getConstant(0, VT); 1737193323Sed // reassociate and 1738193323Sed SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1739193323Sed if (RAND.getNode() != 0) 1740193323Sed return RAND; 1741193323Sed // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1742193323Sed if (N1C && N0.getOpcode() == ISD::OR) 1743193323Sed if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1744193323Sed if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1745193323Sed return N1; 1746193323Sed // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1747193323Sed if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1748193323Sed SDValue N0Op0 = N0.getOperand(0); 1749193323Sed APInt Mask = ~N1C->getAPIntValue(); 1750193323Sed Mask.trunc(N0Op0.getValueSizeInBits()); 1751193323Sed if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1752193323Sed SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1753193323Sed N0.getValueType(), N0Op0); 1754193323Sed 1755193323Sed // Replace uses of the AND with uses of the Zero extend node. 1756193323Sed CombineTo(N, Zext); 1757193323Sed 1758193323Sed // We actually want to replace all uses of the any_extend with the 1759193323Sed // zero_extend, to avoid duplicating things. This will later cause this 1760193323Sed // AND to be folded. 1761193323Sed CombineTo(N0.getNode(), Zext); 1762193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 1763193323Sed } 1764193323Sed } 1765193323Sed // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1766193323Sed if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1767193323Sed ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1768193323Sed ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1769193323Sed 1770193323Sed if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1771193323Sed LL.getValueType().isInteger()) { 1772193323Sed // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1773193323Sed if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1774193323Sed SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1775193323Sed LR.getValueType(), LL, RL); 1776193323Sed AddToWorkList(ORNode.getNode()); 1777193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1778193323Sed } 1779193323Sed // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1780193323Sed if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1781193323Sed SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1782193323Sed LR.getValueType(), LL, RL); 1783193323Sed AddToWorkList(ANDNode.getNode()); 1784193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1785193323Sed } 1786193323Sed // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1787193323Sed if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1788193323Sed SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1789193323Sed LR.getValueType(), LL, RL); 1790193323Sed AddToWorkList(ORNode.getNode()); 1791193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1792193323Sed } 1793193323Sed } 1794193323Sed // canonicalize equivalent to ll == rl 1795193323Sed if (LL == RR && LR == RL) { 1796193323Sed Op1 = ISD::getSetCCSwappedOperands(Op1); 1797193323Sed std::swap(RL, RR); 1798193323Sed } 1799193323Sed if (LL == RL && LR == RR) { 1800193323Sed bool isInteger = LL.getValueType().isInteger(); 1801193323Sed ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1802193323Sed if (Result != ISD::SETCC_INVALID && 1803193323Sed (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1804193323Sed return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1805193323Sed LL, LR, Result); 1806193323Sed } 1807193323Sed } 1808193323Sed 1809193323Sed // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1810193323Sed if (N0.getOpcode() == N1.getOpcode()) { 1811193323Sed SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1812193323Sed if (Tmp.getNode()) return Tmp; 1813193323Sed } 1814193323Sed 1815193323Sed // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1816193323Sed // fold (and (sra)) -> (and (srl)) when possible. 1817193323Sed if (!VT.isVector() && 1818193323Sed SimplifyDemandedBits(SDValue(N, 0))) 1819193323Sed return SDValue(N, 0); 1820193323Sed // fold (zext_inreg (extload x)) -> (zextload x) 1821193323Sed if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1822193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1823193323Sed MVT EVT = LN0->getMemoryVT(); 1824193323Sed // If we zero all the possible extended bits, then we can turn this into 1825193323Sed // a zextload if we are running before legalize or the operation is legal. 1826193323Sed unsigned BitWidth = N1.getValueSizeInBits(); 1827193323Sed if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1828193323Sed BitWidth - EVT.getSizeInBits())) && 1829193323Sed ((!LegalOperations && !LN0->isVolatile()) || 1830193323Sed TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1831193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1832193323Sed LN0->getChain(), LN0->getBasePtr(), 1833193323Sed LN0->getSrcValue(), 1834193323Sed LN0->getSrcValueOffset(), EVT, 1835193323Sed LN0->isVolatile(), LN0->getAlignment()); 1836193323Sed AddToWorkList(N); 1837193323Sed CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1838193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 1839193323Sed } 1840193323Sed } 1841193323Sed // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1842193323Sed if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1843193323Sed N0.hasOneUse()) { 1844193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1845193323Sed MVT EVT = LN0->getMemoryVT(); 1846193323Sed // If we zero all the possible extended bits, then we can turn this into 1847193323Sed // a zextload if we are running before legalize or the operation is legal. 1848193323Sed unsigned BitWidth = N1.getValueSizeInBits(); 1849193323Sed if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1850193323Sed BitWidth - EVT.getSizeInBits())) && 1851193323Sed ((!LegalOperations && !LN0->isVolatile()) || 1852193323Sed TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1853193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1854193323Sed LN0->getChain(), 1855193323Sed LN0->getBasePtr(), LN0->getSrcValue(), 1856193323Sed LN0->getSrcValueOffset(), EVT, 1857193323Sed LN0->isVolatile(), LN0->getAlignment()); 1858193323Sed AddToWorkList(N); 1859193323Sed CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1860193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 1861193323Sed } 1862193323Sed } 1863193323Sed 1864193323Sed // fold (and (load x), 255) -> (zextload x, i8) 1865193323Sed // fold (and (extload x, i16), 255) -> (zextload x, i8) 1866193323Sed if (N1C && N0.getOpcode() == ISD::LOAD) { 1867193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1868193323Sed if (LN0->getExtensionType() != ISD::SEXTLOAD && 1869193323Sed LN0->isUnindexed() && N0.hasOneUse() && 1870193323Sed // Do not change the width of a volatile load. 1871193323Sed !LN0->isVolatile()) { 1872193323Sed MVT EVT = MVT::Other; 1873193323Sed uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1874193323Sed if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1875193323Sed EVT = MVT::getIntegerVT(ActiveBits); 1876193323Sed 1877193323Sed MVT LoadedVT = LN0->getMemoryVT(); 1878193323Sed 1879193323Sed // Do not generate loads of non-round integer types since these can 1880193323Sed // be expensive (and would be wrong if the type is not byte sized). 1881193323Sed if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1882193323Sed (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1883193323Sed MVT PtrType = N0.getOperand(1).getValueType(); 1884193323Sed 1885193323Sed // For big endian targets, we need to add an offset to the pointer to 1886193323Sed // load the correct bytes. For little endian systems, we merely need to 1887193323Sed // read fewer bytes from the same pointer. 1888193323Sed unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1889193323Sed unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1890193323Sed unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1891193323Sed unsigned Alignment = LN0->getAlignment(); 1892193323Sed SDValue NewPtr = LN0->getBasePtr(); 1893193323Sed 1894193323Sed if (TLI.isBigEndian()) { 1895193323Sed NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1896193323Sed NewPtr, DAG.getConstant(PtrOff, PtrType)); 1897193323Sed Alignment = MinAlign(Alignment, PtrOff); 1898193323Sed } 1899193323Sed 1900193323Sed AddToWorkList(NewPtr.getNode()); 1901193323Sed SDValue Load = 1902193323Sed DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1903193323Sed NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1904193323Sed EVT, LN0->isVolatile(), Alignment); 1905193323Sed AddToWorkList(N); 1906193323Sed CombineTo(N0.getNode(), Load, Load.getValue(1)); 1907193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 1908193323Sed } 1909193323Sed } 1910193323Sed } 1911193323Sed 1912193323Sed return SDValue(); 1913193323Sed} 1914193323Sed 1915193323SedSDValue DAGCombiner::visitOR(SDNode *N) { 1916193323Sed SDValue N0 = N->getOperand(0); 1917193323Sed SDValue N1 = N->getOperand(1); 1918193323Sed SDValue LL, LR, RL, RR, CC0, CC1; 1919193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1920193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1921193323Sed MVT VT = N1.getValueType(); 1922193323Sed 1923193323Sed // fold vector ops 1924193323Sed if (VT.isVector()) { 1925193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 1926193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 1927193323Sed } 1928193323Sed 1929193323Sed // fold (or x, undef) -> -1 1930193323Sed if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1931193323Sed return DAG.getConstant(~0ULL, VT); 1932193323Sed // fold (or c1, c2) -> c1|c2 1933193323Sed if (N0C && N1C) 1934193323Sed return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1935193323Sed // canonicalize constant to RHS 1936193323Sed if (N0C && !N1C) 1937193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1938193323Sed // fold (or x, 0) -> x 1939193323Sed if (N1C && N1C->isNullValue()) 1940193323Sed return N0; 1941193323Sed // fold (or x, -1) -> -1 1942193323Sed if (N1C && N1C->isAllOnesValue()) 1943193323Sed return N1; 1944193323Sed // fold (or x, c) -> c iff (x & ~c) == 0 1945193323Sed if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1946193323Sed return N1; 1947193323Sed // reassociate or 1948193323Sed SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1949193323Sed if (ROR.getNode() != 0) 1950193323Sed return ROR; 1951193323Sed // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1952193323Sed if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1953193323Sed isa<ConstantSDNode>(N0.getOperand(1))) { 1954193323Sed ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1955193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1956193323Sed DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1957193323Sed N0.getOperand(0), N1), 1958193323Sed DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1959193323Sed } 1960193323Sed // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1961193323Sed if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1962193323Sed ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1963193323Sed ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1964193323Sed 1965193323Sed if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1966193323Sed LL.getValueType().isInteger()) { 1967193323Sed // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1968193323Sed // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1969193323Sed if (cast<ConstantSDNode>(LR)->isNullValue() && 1970193323Sed (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1971193323Sed SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1972193323Sed LR.getValueType(), LL, RL); 1973193323Sed AddToWorkList(ORNode.getNode()); 1974193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1975193323Sed } 1976193323Sed // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1977193323Sed // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1978193323Sed if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1979193323Sed (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1980193323Sed SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1981193323Sed LR.getValueType(), LL, RL); 1982193323Sed AddToWorkList(ANDNode.getNode()); 1983193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1984193323Sed } 1985193323Sed } 1986193323Sed // canonicalize equivalent to ll == rl 1987193323Sed if (LL == RR && LR == RL) { 1988193323Sed Op1 = ISD::getSetCCSwappedOperands(Op1); 1989193323Sed std::swap(RL, RR); 1990193323Sed } 1991193323Sed if (LL == RL && LR == RR) { 1992193323Sed bool isInteger = LL.getValueType().isInteger(); 1993193323Sed ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1994193323Sed if (Result != ISD::SETCC_INVALID && 1995193323Sed (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1996193323Sed return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1997193323Sed LL, LR, Result); 1998193323Sed } 1999193323Sed } 2000193323Sed 2001193323Sed // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2002193323Sed if (N0.getOpcode() == N1.getOpcode()) { 2003193323Sed SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2004193323Sed if (Tmp.getNode()) return Tmp; 2005193323Sed } 2006193323Sed 2007193323Sed // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2008193323Sed if (N0.getOpcode() == ISD::AND && 2009193323Sed N1.getOpcode() == ISD::AND && 2010193323Sed N0.getOperand(1).getOpcode() == ISD::Constant && 2011193323Sed N1.getOperand(1).getOpcode() == ISD::Constant && 2012193323Sed // Don't increase # computations. 2013193323Sed (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2014193323Sed // We can only do this xform if we know that bits from X that are set in C2 2015193323Sed // but not in C1 are already zero. Likewise for Y. 2016193323Sed const APInt &LHSMask = 2017193323Sed cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2018193323Sed const APInt &RHSMask = 2019193323Sed cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2020193323Sed 2021193323Sed if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2022193323Sed DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2023193323Sed SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2024193323Sed N0.getOperand(0), N1.getOperand(0)); 2025193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2026193323Sed DAG.getConstant(LHSMask | RHSMask, VT)); 2027193323Sed } 2028193323Sed } 2029193323Sed 2030193323Sed // See if this is some rotate idiom. 2031193323Sed if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2032193323Sed return SDValue(Rot, 0); 2033193323Sed 2034193323Sed return SDValue(); 2035193323Sed} 2036193323Sed 2037193323Sed/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2038193323Sedstatic bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2039193323Sed if (Op.getOpcode() == ISD::AND) { 2040193323Sed if (isa<ConstantSDNode>(Op.getOperand(1))) { 2041193323Sed Mask = Op.getOperand(1); 2042193323Sed Op = Op.getOperand(0); 2043193323Sed } else { 2044193323Sed return false; 2045193323Sed } 2046193323Sed } 2047193323Sed 2048193323Sed if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2049193323Sed Shift = Op; 2050193323Sed return true; 2051193323Sed } 2052193323Sed 2053193323Sed return false; 2054193323Sed} 2055193323Sed 2056193323Sed// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2057193323Sed// idioms for rotate, and if the target supports rotation instructions, generate 2058193323Sed// a rot[lr]. 2059193323SedSDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2060193323Sed // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2061193323Sed MVT VT = LHS.getValueType(); 2062193323Sed if (!TLI.isTypeLegal(VT)) return 0; 2063193323Sed 2064193323Sed // The target must have at least one rotate flavor. 2065193323Sed bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2066193323Sed bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2067193323Sed if (!HasROTL && !HasROTR) return 0; 2068193323Sed 2069193323Sed // Match "(X shl/srl V1) & V2" where V2 may not be present. 2070193323Sed SDValue LHSShift; // The shift. 2071193323Sed SDValue LHSMask; // AND value if any. 2072193323Sed if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2073193323Sed return 0; // Not part of a rotate. 2074193323Sed 2075193323Sed SDValue RHSShift; // The shift. 2076193323Sed SDValue RHSMask; // AND value if any. 2077193323Sed if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2078193323Sed return 0; // Not part of a rotate. 2079193323Sed 2080193323Sed if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2081193323Sed return 0; // Not shifting the same value. 2082193323Sed 2083193323Sed if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2084193323Sed return 0; // Shifts must disagree. 2085193323Sed 2086193323Sed // Canonicalize shl to left side in a shl/srl pair. 2087193323Sed if (RHSShift.getOpcode() == ISD::SHL) { 2088193323Sed std::swap(LHS, RHS); 2089193323Sed std::swap(LHSShift, RHSShift); 2090193323Sed std::swap(LHSMask , RHSMask ); 2091193323Sed } 2092193323Sed 2093193323Sed unsigned OpSizeInBits = VT.getSizeInBits(); 2094193323Sed SDValue LHSShiftArg = LHSShift.getOperand(0); 2095193323Sed SDValue LHSShiftAmt = LHSShift.getOperand(1); 2096193323Sed SDValue RHSShiftAmt = RHSShift.getOperand(1); 2097193323Sed 2098193323Sed // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2099193323Sed // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2100193323Sed if (LHSShiftAmt.getOpcode() == ISD::Constant && 2101193323Sed RHSShiftAmt.getOpcode() == ISD::Constant) { 2102193323Sed uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2103193323Sed uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2104193323Sed if ((LShVal + RShVal) != OpSizeInBits) 2105193323Sed return 0; 2106193323Sed 2107193323Sed SDValue Rot; 2108193323Sed if (HasROTL) 2109193323Sed Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2110193323Sed else 2111193323Sed Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2112193323Sed 2113193323Sed // If there is an AND of either shifted operand, apply it to the result. 2114193323Sed if (LHSMask.getNode() || RHSMask.getNode()) { 2115193323Sed APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2116193323Sed 2117193323Sed if (LHSMask.getNode()) { 2118193323Sed APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2119193323Sed Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2120193323Sed } 2121193323Sed if (RHSMask.getNode()) { 2122193323Sed APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2123193323Sed Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2124193323Sed } 2125193323Sed 2126193323Sed Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2127193323Sed } 2128193323Sed 2129193323Sed return Rot.getNode(); 2130193323Sed } 2131193323Sed 2132193323Sed // If there is a mask here, and we have a variable shift, we can't be sure 2133193323Sed // that we're masking out the right stuff. 2134193323Sed if (LHSMask.getNode() || RHSMask.getNode()) 2135193323Sed return 0; 2136193323Sed 2137193323Sed // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2138193323Sed // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2139193323Sed if (RHSShiftAmt.getOpcode() == ISD::SUB && 2140193323Sed LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2141193323Sed if (ConstantSDNode *SUBC = 2142193323Sed dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2143193323Sed if (SUBC->getAPIntValue() == OpSizeInBits) { 2144193323Sed if (HasROTL) 2145193323Sed return DAG.getNode(ISD::ROTL, DL, VT, 2146193323Sed LHSShiftArg, LHSShiftAmt).getNode(); 2147193323Sed else 2148193323Sed return DAG.getNode(ISD::ROTR, DL, VT, 2149193323Sed LHSShiftArg, RHSShiftAmt).getNode(); 2150193323Sed } 2151193323Sed } 2152193323Sed } 2153193323Sed 2154193323Sed // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2155193323Sed // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2156193323Sed if (LHSShiftAmt.getOpcode() == ISD::SUB && 2157193323Sed RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2158193323Sed if (ConstantSDNode *SUBC = 2159193323Sed dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2160193323Sed if (SUBC->getAPIntValue() == OpSizeInBits) { 2161193323Sed if (HasROTR) 2162193323Sed return DAG.getNode(ISD::ROTR, DL, VT, 2163193323Sed LHSShiftArg, RHSShiftAmt).getNode(); 2164193323Sed else 2165193323Sed return DAG.getNode(ISD::ROTL, DL, VT, 2166193323Sed LHSShiftArg, LHSShiftAmt).getNode(); 2167193323Sed } 2168193323Sed } 2169193323Sed } 2170193323Sed 2171193323Sed // Look for sign/zext/any-extended or truncate cases: 2172193323Sed if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2173193323Sed || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2174193323Sed || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2175193323Sed || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2176193323Sed (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2177193323Sed || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2178193323Sed || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2179193323Sed || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2180193323Sed SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2181193323Sed SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2182193323Sed if (RExtOp0.getOpcode() == ISD::SUB && 2183193323Sed RExtOp0.getOperand(1) == LExtOp0) { 2184193323Sed // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2185193323Sed // (rotl x, y) 2186193323Sed // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2187193323Sed // (rotr x, (sub 32, y)) 2188193323Sed if (ConstantSDNode *SUBC = 2189193323Sed dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2190193323Sed if (SUBC->getAPIntValue() == OpSizeInBits) { 2191193323Sed return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2192193323Sed LHSShiftArg, 2193193323Sed HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2194193323Sed } 2195193323Sed } 2196193323Sed } else if (LExtOp0.getOpcode() == ISD::SUB && 2197193323Sed RExtOp0 == LExtOp0.getOperand(1)) { 2198193323Sed // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2199193323Sed // (rotr x, y) 2200193323Sed // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2201193323Sed // (rotl x, (sub 32, y)) 2202193323Sed if (ConstantSDNode *SUBC = 2203193323Sed dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2204193323Sed if (SUBC->getAPIntValue() == OpSizeInBits) { 2205193323Sed return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2206193323Sed LHSShiftArg, 2207193323Sed HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2208193323Sed } 2209193323Sed } 2210193323Sed } 2211193323Sed } 2212193323Sed 2213193323Sed return 0; 2214193323Sed} 2215193323Sed 2216193323SedSDValue DAGCombiner::visitXOR(SDNode *N) { 2217193323Sed SDValue N0 = N->getOperand(0); 2218193323Sed SDValue N1 = N->getOperand(1); 2219193323Sed SDValue LHS, RHS, CC; 2220193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2221193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2222193323Sed MVT VT = N0.getValueType(); 2223193323Sed 2224193323Sed // fold vector ops 2225193323Sed if (VT.isVector()) { 2226193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 2227193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 2228193323Sed } 2229193323Sed 2230193323Sed // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2231193323Sed if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2232193323Sed return DAG.getConstant(0, VT); 2233193323Sed // fold (xor x, undef) -> undef 2234193323Sed if (N0.getOpcode() == ISD::UNDEF) 2235193323Sed return N0; 2236193323Sed if (N1.getOpcode() == ISD::UNDEF) 2237193323Sed return N1; 2238193323Sed // fold (xor c1, c2) -> c1^c2 2239193323Sed if (N0C && N1C) 2240193323Sed return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2241193323Sed // canonicalize constant to RHS 2242193323Sed if (N0C && !N1C) 2243193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2244193323Sed // fold (xor x, 0) -> x 2245193323Sed if (N1C && N1C->isNullValue()) 2246193323Sed return N0; 2247193323Sed // reassociate xor 2248193323Sed SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2249193323Sed if (RXOR.getNode() != 0) 2250193323Sed return RXOR; 2251193323Sed 2252193323Sed // fold !(x cc y) -> (x !cc y) 2253193323Sed if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2254193323Sed bool isInt = LHS.getValueType().isInteger(); 2255193323Sed ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2256193323Sed isInt); 2257193323Sed 2258193323Sed if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2259193323Sed switch (N0.getOpcode()) { 2260193323Sed default: 2261193323Sed assert(0 && "Unhandled SetCC Equivalent!"); 2262193323Sed abort(); 2263193323Sed case ISD::SETCC: 2264193323Sed return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2265193323Sed case ISD::SELECT_CC: 2266193323Sed return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2267193323Sed N0.getOperand(3), NotCC); 2268193323Sed } 2269193323Sed } 2270193323Sed } 2271193323Sed 2272193323Sed // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2273193323Sed if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2274193323Sed N0.getNode()->hasOneUse() && 2275193323Sed isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2276193323Sed SDValue V = N0.getOperand(0); 2277193323Sed V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2278193323Sed DAG.getConstant(1, V.getValueType())); 2279193323Sed AddToWorkList(V.getNode()); 2280193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2281193323Sed } 2282193323Sed 2283193323Sed // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2284193323Sed if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2285193323Sed (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2286193323Sed SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2287193323Sed if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2288193323Sed unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2289193323Sed LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2290193323Sed RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2291193323Sed AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2292193323Sed return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2293193323Sed } 2294193323Sed } 2295193323Sed // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2296193323Sed if (N1C && N1C->isAllOnesValue() && 2297193323Sed (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2298193323Sed SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2299193323Sed if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2300193323Sed unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2301193323Sed LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2302193323Sed RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2303193323Sed AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2304193323Sed return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2305193323Sed } 2306193323Sed } 2307193323Sed // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2308193323Sed if (N1C && N0.getOpcode() == ISD::XOR) { 2309193323Sed ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2310193323Sed ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2311193323Sed if (N00C) 2312193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2313193323Sed DAG.getConstant(N1C->getAPIntValue() ^ 2314193323Sed N00C->getAPIntValue(), VT)); 2315193323Sed if (N01C) 2316193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2317193323Sed DAG.getConstant(N1C->getAPIntValue() ^ 2318193323Sed N01C->getAPIntValue(), VT)); 2319193323Sed } 2320193323Sed // fold (xor x, x) -> 0 2321193323Sed if (N0 == N1) { 2322193323Sed if (!VT.isVector()) { 2323193323Sed return DAG.getConstant(0, VT); 2324193323Sed } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2325193323Sed // Produce a vector of zeros. 2326193323Sed SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2327193323Sed std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2328193323Sed return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2329193323Sed &Ops[0], Ops.size()); 2330193323Sed } 2331193323Sed } 2332193323Sed 2333193323Sed // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2334193323Sed if (N0.getOpcode() == N1.getOpcode()) { 2335193323Sed SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2336193323Sed if (Tmp.getNode()) return Tmp; 2337193323Sed } 2338193323Sed 2339193323Sed // Simplify the expression using non-local knowledge. 2340193323Sed if (!VT.isVector() && 2341193323Sed SimplifyDemandedBits(SDValue(N, 0))) 2342193323Sed return SDValue(N, 0); 2343193323Sed 2344193323Sed return SDValue(); 2345193323Sed} 2346193323Sed 2347193323Sed/// visitShiftByConstant - Handle transforms common to the three shifts, when 2348193323Sed/// the shift amount is a constant. 2349193323SedSDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2350193323Sed SDNode *LHS = N->getOperand(0).getNode(); 2351193323Sed if (!LHS->hasOneUse()) return SDValue(); 2352193323Sed 2353193323Sed // We want to pull some binops through shifts, so that we have (and (shift)) 2354193323Sed // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2355193323Sed // thing happens with address calculations, so it's important to canonicalize 2356193323Sed // it. 2357193323Sed bool HighBitSet = false; // Can we transform this if the high bit is set? 2358193323Sed 2359193323Sed switch (LHS->getOpcode()) { 2360193323Sed default: return SDValue(); 2361193323Sed case ISD::OR: 2362193323Sed case ISD::XOR: 2363193323Sed HighBitSet = false; // We can only transform sra if the high bit is clear. 2364193323Sed break; 2365193323Sed case ISD::AND: 2366193323Sed HighBitSet = true; // We can only transform sra if the high bit is set. 2367193323Sed break; 2368193323Sed case ISD::ADD: 2369193323Sed if (N->getOpcode() != ISD::SHL) 2370193323Sed return SDValue(); // only shl(add) not sr[al](add). 2371193323Sed HighBitSet = false; // We can only transform sra if the high bit is clear. 2372193323Sed break; 2373193323Sed } 2374193323Sed 2375193323Sed // We require the RHS of the binop to be a constant as well. 2376193323Sed ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2377193323Sed if (!BinOpCst) return SDValue(); 2378193323Sed 2379193323Sed // FIXME: disable this unless the input to the binop is a shift by a constant. 2380193323Sed // If it is not a shift, it pessimizes some common cases like: 2381193323Sed // 2382193323Sed // void foo(int *X, int i) { X[i & 1235] = 1; } 2383193323Sed // int bar(int *X, int i) { return X[i & 255]; } 2384193323Sed SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2385193323Sed if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2386193323Sed BinOpLHSVal->getOpcode() != ISD::SRA && 2387193323Sed BinOpLHSVal->getOpcode() != ISD::SRL) || 2388193323Sed !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2389193323Sed return SDValue(); 2390193323Sed 2391193323Sed MVT VT = N->getValueType(0); 2392193323Sed 2393193323Sed // If this is a signed shift right, and the high bit is modified by the 2394193323Sed // logical operation, do not perform the transformation. The highBitSet 2395193323Sed // boolean indicates the value of the high bit of the constant which would 2396193323Sed // cause it to be modified for this operation. 2397193323Sed if (N->getOpcode() == ISD::SRA) { 2398193323Sed bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2399193323Sed if (BinOpRHSSignSet != HighBitSet) 2400193323Sed return SDValue(); 2401193323Sed } 2402193323Sed 2403193323Sed // Fold the constants, shifting the binop RHS by the shift amount. 2404193323Sed SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2405193323Sed N->getValueType(0), 2406193323Sed LHS->getOperand(1), N->getOperand(1)); 2407193323Sed 2408193323Sed // Create the new shift. 2409193323Sed SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2410193323Sed VT, LHS->getOperand(0), N->getOperand(1)); 2411193323Sed 2412193323Sed // Create the new binop. 2413193323Sed return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2414193323Sed} 2415193323Sed 2416193323SedSDValue DAGCombiner::visitSHL(SDNode *N) { 2417193323Sed SDValue N0 = N->getOperand(0); 2418193323Sed SDValue N1 = N->getOperand(1); 2419193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2420193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2421193323Sed MVT VT = N0.getValueType(); 2422193323Sed unsigned OpSizeInBits = VT.getSizeInBits(); 2423193323Sed 2424193323Sed // fold (shl c1, c2) -> c1<<c2 2425193323Sed if (N0C && N1C) 2426193323Sed return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2427193323Sed // fold (shl 0, x) -> 0 2428193323Sed if (N0C && N0C->isNullValue()) 2429193323Sed return N0; 2430193323Sed // fold (shl x, c >= size(x)) -> undef 2431193323Sed if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2432193323Sed return DAG.getUNDEF(VT); 2433193323Sed // fold (shl x, 0) -> x 2434193323Sed if (N1C && N1C->isNullValue()) 2435193323Sed return N0; 2436193323Sed // if (shl x, c) is known to be zero, return 0 2437193323Sed if (DAG.MaskedValueIsZero(SDValue(N, 0), 2438193323Sed APInt::getAllOnesValue(VT.getSizeInBits()))) 2439193323Sed return DAG.getConstant(0, VT); 2440193323Sed // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2441193323Sed if (N1.getOpcode() == ISD::TRUNCATE && 2442193323Sed N1.getOperand(0).getOpcode() == ISD::AND && 2443193323Sed N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2444193323Sed SDValue N101 = N1.getOperand(0).getOperand(1); 2445193323Sed if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2446193323Sed MVT TruncVT = N1.getValueType(); 2447193323Sed SDValue N100 = N1.getOperand(0).getOperand(0); 2448193323Sed APInt TruncC = N101C->getAPIntValue(); 2449193323Sed TruncC.trunc(TruncVT.getSizeInBits()); 2450193323Sed return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2451193323Sed DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2452193323Sed DAG.getNode(ISD::TRUNCATE, 2453193323Sed N->getDebugLoc(), 2454193323Sed TruncVT, N100), 2455193323Sed DAG.getConstant(TruncC, TruncVT))); 2456193323Sed } 2457193323Sed } 2458193323Sed 2459193323Sed if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2460193323Sed return SDValue(N, 0); 2461193323Sed 2462193323Sed // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2463193323Sed if (N1C && N0.getOpcode() == ISD::SHL && 2464193323Sed N0.getOperand(1).getOpcode() == ISD::Constant) { 2465193323Sed uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2466193323Sed uint64_t c2 = N1C->getZExtValue(); 2467193323Sed if (c1 + c2 > OpSizeInBits) 2468193323Sed return DAG.getConstant(0, VT); 2469193323Sed return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2470193323Sed DAG.getConstant(c1 + c2, N1.getValueType())); 2471193323Sed } 2472193323Sed // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2473193323Sed // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2474193323Sed if (N1C && N0.getOpcode() == ISD::SRL && 2475193323Sed N0.getOperand(1).getOpcode() == ISD::Constant) { 2476193323Sed uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2477193323Sed uint64_t c2 = N1C->getZExtValue(); 2478193323Sed SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0), 2479193323Sed DAG.getConstant(~0ULL << c1, VT)); 2480193323Sed if (c2 > c1) 2481193323Sed return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2482193323Sed DAG.getConstant(c2-c1, N1.getValueType())); 2483193323Sed else 2484193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2485193323Sed DAG.getConstant(c1-c2, N1.getValueType())); 2486193323Sed } 2487193323Sed // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2488193323Sed if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2489193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2490193323Sed DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2491193323Sed 2492193323Sed return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2493193323Sed} 2494193323Sed 2495193323SedSDValue DAGCombiner::visitSRA(SDNode *N) { 2496193323Sed SDValue N0 = N->getOperand(0); 2497193323Sed SDValue N1 = N->getOperand(1); 2498193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2499193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2500193323Sed MVT VT = N0.getValueType(); 2501193323Sed 2502193323Sed // fold (sra c1, c2) -> (sra c1, c2) 2503193323Sed if (N0C && N1C) 2504193323Sed return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2505193323Sed // fold (sra 0, x) -> 0 2506193323Sed if (N0C && N0C->isNullValue()) 2507193323Sed return N0; 2508193323Sed // fold (sra -1, x) -> -1 2509193323Sed if (N0C && N0C->isAllOnesValue()) 2510193323Sed return N0; 2511193323Sed // fold (sra x, (setge c, size(x))) -> undef 2512193323Sed if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2513193323Sed return DAG.getUNDEF(VT); 2514193323Sed // fold (sra x, 0) -> x 2515193323Sed if (N1C && N1C->isNullValue()) 2516193323Sed return N0; 2517193323Sed // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2518193323Sed // sext_inreg. 2519193323Sed if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2520193323Sed unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2521193323Sed MVT EVT = MVT::getIntegerVT(LowBits); 2522193323Sed if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2523193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2524193323Sed N0.getOperand(0), DAG.getValueType(EVT)); 2525193323Sed } 2526193323Sed 2527193323Sed // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2528193323Sed if (N1C && N0.getOpcode() == ISD::SRA) { 2529193323Sed if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2530193323Sed unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2531193323Sed if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2532193323Sed return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2533193323Sed DAG.getConstant(Sum, N1C->getValueType(0))); 2534193323Sed } 2535193323Sed } 2536193323Sed 2537193323Sed // fold (sra (shl X, m), (sub result_size, n)) 2538193323Sed // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2539193323Sed // result_size - n != m. 2540193323Sed // If truncate is free for the target sext(shl) is likely to result in better 2541193323Sed // code. 2542193323Sed if (N0.getOpcode() == ISD::SHL) { 2543193323Sed // Get the two constanst of the shifts, CN0 = m, CN = n. 2544193323Sed const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2545193323Sed if (N01C && N1C) { 2546193323Sed // Determine what the truncate's result bitsize and type would be. 2547193323Sed unsigned VTValSize = VT.getSizeInBits(); 2548193323Sed MVT TruncVT = 2549193323Sed MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2550193323Sed // Determine the residual right-shift amount. 2551193323Sed signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2552193323Sed 2553193323Sed // If the shift is not a no-op (in which case this should be just a sign 2554193323Sed // extend already), the truncated to type is legal, sign_extend is legal 2555193323Sed // on that type, and the the truncate to that type is both legal and free, 2556193323Sed // perform the transform. 2557193323Sed if ((ShiftAmt > 0) && 2558193323Sed TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2559193323Sed TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2560193323Sed TLI.isTruncateFree(VT, TruncVT)) { 2561193323Sed 2562193323Sed SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2563193323Sed SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2564193323Sed N0.getOperand(0), Amt); 2565193323Sed SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2566193323Sed Shift); 2567193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2568193323Sed N->getValueType(0), Trunc); 2569193323Sed } 2570193323Sed } 2571193323Sed } 2572193323Sed 2573193323Sed // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2574193323Sed if (N1.getOpcode() == ISD::TRUNCATE && 2575193323Sed N1.getOperand(0).getOpcode() == ISD::AND && 2576193323Sed N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2577193323Sed SDValue N101 = N1.getOperand(0).getOperand(1); 2578193323Sed if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2579193323Sed MVT TruncVT = N1.getValueType(); 2580193323Sed SDValue N100 = N1.getOperand(0).getOperand(0); 2581193323Sed APInt TruncC = N101C->getAPIntValue(); 2582193323Sed TruncC.trunc(TruncVT.getSizeInBits()); 2583193323Sed return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2584193323Sed DAG.getNode(ISD::AND, N->getDebugLoc(), 2585193323Sed TruncVT, 2586193323Sed DAG.getNode(ISD::TRUNCATE, 2587193323Sed N->getDebugLoc(), 2588193323Sed TruncVT, N100), 2589193323Sed DAG.getConstant(TruncC, TruncVT))); 2590193323Sed } 2591193323Sed } 2592193323Sed 2593193323Sed // Simplify, based on bits shifted out of the LHS. 2594193323Sed if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2595193323Sed return SDValue(N, 0); 2596193323Sed 2597193323Sed 2598193323Sed // If the sign bit is known to be zero, switch this to a SRL. 2599193323Sed if (DAG.SignBitIsZero(N0)) 2600193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2601193323Sed 2602193323Sed return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2603193323Sed} 2604193323Sed 2605193323SedSDValue DAGCombiner::visitSRL(SDNode *N) { 2606193323Sed SDValue N0 = N->getOperand(0); 2607193323Sed SDValue N1 = N->getOperand(1); 2608193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2609193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2610193323Sed MVT VT = N0.getValueType(); 2611193323Sed unsigned OpSizeInBits = VT.getSizeInBits(); 2612193323Sed 2613193323Sed // fold (srl c1, c2) -> c1 >>u c2 2614193323Sed if (N0C && N1C) 2615193323Sed return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2616193323Sed // fold (srl 0, x) -> 0 2617193323Sed if (N0C && N0C->isNullValue()) 2618193323Sed return N0; 2619193323Sed // fold (srl x, c >= size(x)) -> undef 2620193323Sed if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2621193323Sed return DAG.getUNDEF(VT); 2622193323Sed // fold (srl x, 0) -> x 2623193323Sed if (N1C && N1C->isNullValue()) 2624193323Sed return N0; 2625193323Sed // if (srl x, c) is known to be zero, return 0 2626193323Sed if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2627193323Sed APInt::getAllOnesValue(OpSizeInBits))) 2628193323Sed return DAG.getConstant(0, VT); 2629193323Sed 2630193323Sed // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2631193323Sed if (N1C && N0.getOpcode() == ISD::SRL && 2632193323Sed N0.getOperand(1).getOpcode() == ISD::Constant) { 2633193323Sed uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2634193323Sed uint64_t c2 = N1C->getZExtValue(); 2635193323Sed if (c1 + c2 > OpSizeInBits) 2636193323Sed return DAG.getConstant(0, VT); 2637193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2638193323Sed DAG.getConstant(c1 + c2, N1.getValueType())); 2639193323Sed } 2640193323Sed 2641193323Sed // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2642193323Sed if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2643193323Sed // Shifting in all undef bits? 2644193323Sed MVT SmallVT = N0.getOperand(0).getValueType(); 2645193323Sed if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2646193323Sed return DAG.getUNDEF(VT); 2647193323Sed 2648193323Sed SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2649193323Sed N0.getOperand(0), N1); 2650193323Sed AddToWorkList(SmallShift.getNode()); 2651193323Sed return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2652193323Sed } 2653193323Sed 2654193323Sed // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2655193323Sed // bit, which is unmodified by sra. 2656193323Sed if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2657193323Sed if (N0.getOpcode() == ISD::SRA) 2658193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2659193323Sed } 2660193323Sed 2661193323Sed // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2662193323Sed if (N1C && N0.getOpcode() == ISD::CTLZ && 2663193323Sed N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2664193323Sed APInt KnownZero, KnownOne; 2665193323Sed APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2666193323Sed DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2667193323Sed 2668193323Sed // If any of the input bits are KnownOne, then the input couldn't be all 2669193323Sed // zeros, thus the result of the srl will always be zero. 2670193323Sed if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2671193323Sed 2672193323Sed // If all of the bits input the to ctlz node are known to be zero, then 2673193323Sed // the result of the ctlz is "32" and the result of the shift is one. 2674193323Sed APInt UnknownBits = ~KnownZero & Mask; 2675193323Sed if (UnknownBits == 0) return DAG.getConstant(1, VT); 2676193323Sed 2677193323Sed // Otherwise, check to see if there is exactly one bit input to the ctlz. 2678193323Sed if ((UnknownBits & (UnknownBits - 1)) == 0) { 2679193323Sed // Okay, we know that only that the single bit specified by UnknownBits 2680193323Sed // could be set on input to the CTLZ node. If this bit is set, the SRL 2681193323Sed // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2682193323Sed // to an SRL/XOR pair, which is likely to simplify more. 2683193323Sed unsigned ShAmt = UnknownBits.countTrailingZeros(); 2684193323Sed SDValue Op = N0.getOperand(0); 2685193323Sed 2686193323Sed if (ShAmt) { 2687193323Sed Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2688193323Sed DAG.getConstant(ShAmt, getShiftAmountTy())); 2689193323Sed AddToWorkList(Op.getNode()); 2690193323Sed } 2691193323Sed 2692193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2693193323Sed Op, DAG.getConstant(1, VT)); 2694193323Sed } 2695193323Sed } 2696193323Sed 2697193323Sed // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2698193323Sed if (N1.getOpcode() == ISD::TRUNCATE && 2699193323Sed N1.getOperand(0).getOpcode() == ISD::AND && 2700193323Sed N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2701193323Sed SDValue N101 = N1.getOperand(0).getOperand(1); 2702193323Sed if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2703193323Sed MVT TruncVT = N1.getValueType(); 2704193323Sed SDValue N100 = N1.getOperand(0).getOperand(0); 2705193323Sed APInt TruncC = N101C->getAPIntValue(); 2706193323Sed TruncC.trunc(TruncVT.getSizeInBits()); 2707193323Sed return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2708193323Sed DAG.getNode(ISD::AND, N->getDebugLoc(), 2709193323Sed TruncVT, 2710193323Sed DAG.getNode(ISD::TRUNCATE, 2711193323Sed N->getDebugLoc(), 2712193323Sed TruncVT, N100), 2713193323Sed DAG.getConstant(TruncC, TruncVT))); 2714193323Sed } 2715193323Sed } 2716193323Sed 2717193323Sed // fold operands of srl based on knowledge that the low bits are not 2718193323Sed // demanded. 2719193323Sed if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2720193323Sed return SDValue(N, 0); 2721193323Sed 2722193323Sed return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2723193323Sed} 2724193323Sed 2725193323SedSDValue DAGCombiner::visitCTLZ(SDNode *N) { 2726193323Sed SDValue N0 = N->getOperand(0); 2727193323Sed MVT VT = N->getValueType(0); 2728193323Sed 2729193323Sed // fold (ctlz c1) -> c2 2730193323Sed if (isa<ConstantSDNode>(N0)) 2731193323Sed return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2732193323Sed return SDValue(); 2733193323Sed} 2734193323Sed 2735193323SedSDValue DAGCombiner::visitCTTZ(SDNode *N) { 2736193323Sed SDValue N0 = N->getOperand(0); 2737193323Sed MVT VT = N->getValueType(0); 2738193323Sed 2739193323Sed // fold (cttz c1) -> c2 2740193323Sed if (isa<ConstantSDNode>(N0)) 2741193323Sed return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2742193323Sed return SDValue(); 2743193323Sed} 2744193323Sed 2745193323SedSDValue DAGCombiner::visitCTPOP(SDNode *N) { 2746193323Sed SDValue N0 = N->getOperand(0); 2747193323Sed MVT VT = N->getValueType(0); 2748193323Sed 2749193323Sed // fold (ctpop c1) -> c2 2750193323Sed if (isa<ConstantSDNode>(N0)) 2751193323Sed return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2752193323Sed return SDValue(); 2753193323Sed} 2754193323Sed 2755193323SedSDValue DAGCombiner::visitSELECT(SDNode *N) { 2756193323Sed SDValue N0 = N->getOperand(0); 2757193323Sed SDValue N1 = N->getOperand(1); 2758193323Sed SDValue N2 = N->getOperand(2); 2759193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2760193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2761193323Sed ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2762193323Sed MVT VT = N->getValueType(0); 2763193323Sed MVT VT0 = N0.getValueType(); 2764193323Sed 2765193323Sed // fold (select C, X, X) -> X 2766193323Sed if (N1 == N2) 2767193323Sed return N1; 2768193323Sed // fold (select true, X, Y) -> X 2769193323Sed if (N0C && !N0C->isNullValue()) 2770193323Sed return N1; 2771193323Sed // fold (select false, X, Y) -> Y 2772193323Sed if (N0C && N0C->isNullValue()) 2773193323Sed return N2; 2774193323Sed // fold (select C, 1, X) -> (or C, X) 2775193323Sed if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2776193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2777193323Sed // fold (select C, 0, 1) -> (xor C, 1) 2778193323Sed if (VT.isInteger() && 2779193323Sed (VT0 == MVT::i1 || 2780193323Sed (VT0.isInteger() && 2781193323Sed TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2782193323Sed N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2783193323Sed SDValue XORNode; 2784193323Sed if (VT == VT0) 2785193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2786193323Sed N0, DAG.getConstant(1, VT0)); 2787193323Sed XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2788193323Sed N0, DAG.getConstant(1, VT0)); 2789193323Sed AddToWorkList(XORNode.getNode()); 2790193323Sed if (VT.bitsGT(VT0)) 2791193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2792193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2793193323Sed } 2794193323Sed // fold (select C, 0, X) -> (and (not C), X) 2795193323Sed if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2796193323Sed SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2797193323Sed AddToWorkList(NOTNode.getNode()); 2798193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2799193323Sed } 2800193323Sed // fold (select C, X, 1) -> (or (not C), X) 2801193323Sed if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2802193323Sed SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2803193323Sed AddToWorkList(NOTNode.getNode()); 2804193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2805193323Sed } 2806193323Sed // fold (select C, X, 0) -> (and C, X) 2807193323Sed if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2808193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2809193323Sed // fold (select X, X, Y) -> (or X, Y) 2810193323Sed // fold (select X, 1, Y) -> (or X, Y) 2811193323Sed if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2812193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2813193323Sed // fold (select X, Y, X) -> (and X, Y) 2814193323Sed // fold (select X, Y, 0) -> (and X, Y) 2815193323Sed if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2816193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2817193323Sed 2818193323Sed // If we can fold this based on the true/false value, do so. 2819193323Sed if (SimplifySelectOps(N, N1, N2)) 2820193323Sed return SDValue(N, 0); // Don't revisit N. 2821193323Sed 2822193323Sed // fold selects based on a setcc into other things, such as min/max/abs 2823193323Sed if (N0.getOpcode() == ISD::SETCC) { 2824193323Sed // FIXME: 2825193323Sed // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2826193323Sed // having to say they don't support SELECT_CC on every type the DAG knows 2827193323Sed // about, since there is no way to mark an opcode illegal at all value types 2828193323Sed if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2829193323Sed return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2830193323Sed N0.getOperand(0), N0.getOperand(1), 2831193323Sed N1, N2, N0.getOperand(2)); 2832193323Sed return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2833193323Sed } 2834193323Sed 2835193323Sed return SDValue(); 2836193323Sed} 2837193323Sed 2838193323SedSDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2839193323Sed SDValue N0 = N->getOperand(0); 2840193323Sed SDValue N1 = N->getOperand(1); 2841193323Sed SDValue N2 = N->getOperand(2); 2842193323Sed SDValue N3 = N->getOperand(3); 2843193323Sed SDValue N4 = N->getOperand(4); 2844193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2845193323Sed 2846193323Sed // fold select_cc lhs, rhs, x, x, cc -> x 2847193323Sed if (N2 == N3) 2848193323Sed return N2; 2849193323Sed 2850193323Sed // Determine if the condition we're dealing with is constant 2851193323Sed SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2852193323Sed N0, N1, CC, N->getDebugLoc(), false); 2853193323Sed if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2854193323Sed 2855193323Sed if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2856193323Sed if (!SCCC->isNullValue()) 2857193323Sed return N2; // cond always true -> true val 2858193323Sed else 2859193323Sed return N3; // cond always false -> false val 2860193323Sed } 2861193323Sed 2862193323Sed // Fold to a simpler select_cc 2863193323Sed if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2864193323Sed return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2865193323Sed SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2866193323Sed SCC.getOperand(2)); 2867193323Sed 2868193323Sed // If we can fold this based on the true/false value, do so. 2869193323Sed if (SimplifySelectOps(N, N2, N3)) 2870193323Sed return SDValue(N, 0); // Don't revisit N. 2871193323Sed 2872193323Sed // fold select_cc into other things, such as min/max/abs 2873193323Sed return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2874193323Sed} 2875193323Sed 2876193323SedSDValue DAGCombiner::visitSETCC(SDNode *N) { 2877193323Sed return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2878193323Sed cast<CondCodeSDNode>(N->getOperand(2))->get(), 2879193323Sed N->getDebugLoc()); 2880193323Sed} 2881193323Sed 2882193323Sed// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2883193323Sed// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2884193323Sed// transformation. Returns true if extension are possible and the above 2885193323Sed// mentioned transformation is profitable. 2886193323Sedstatic bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2887193323Sed unsigned ExtOpc, 2888193323Sed SmallVector<SDNode*, 4> &ExtendNodes, 2889193323Sed const TargetLowering &TLI) { 2890193323Sed bool HasCopyToRegUses = false; 2891193323Sed bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2892193323Sed for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2893193323Sed UE = N0.getNode()->use_end(); 2894193323Sed UI != UE; ++UI) { 2895193323Sed SDNode *User = *UI; 2896193323Sed if (User == N) 2897193323Sed continue; 2898193323Sed if (UI.getUse().getResNo() != N0.getResNo()) 2899193323Sed continue; 2900193323Sed // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2901193323Sed if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2902193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2903193323Sed if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2904193323Sed // Sign bits will be lost after a zext. 2905193323Sed return false; 2906193323Sed bool Add = false; 2907193323Sed for (unsigned i = 0; i != 2; ++i) { 2908193323Sed SDValue UseOp = User->getOperand(i); 2909193323Sed if (UseOp == N0) 2910193323Sed continue; 2911193323Sed if (!isa<ConstantSDNode>(UseOp)) 2912193323Sed return false; 2913193323Sed Add = true; 2914193323Sed } 2915193323Sed if (Add) 2916193323Sed ExtendNodes.push_back(User); 2917193323Sed continue; 2918193323Sed } 2919193323Sed // If truncates aren't free and there are users we can't 2920193323Sed // extend, it isn't worthwhile. 2921193323Sed if (!isTruncFree) 2922193323Sed return false; 2923193323Sed // Remember if this value is live-out. 2924193323Sed if (User->getOpcode() == ISD::CopyToReg) 2925193323Sed HasCopyToRegUses = true; 2926193323Sed } 2927193323Sed 2928193323Sed if (HasCopyToRegUses) { 2929193323Sed bool BothLiveOut = false; 2930193323Sed for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2931193323Sed UI != UE; ++UI) { 2932193323Sed SDUse &Use = UI.getUse(); 2933193323Sed if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2934193323Sed BothLiveOut = true; 2935193323Sed break; 2936193323Sed } 2937193323Sed } 2938193323Sed if (BothLiveOut) 2939193323Sed // Both unextended and extended values are live out. There had better be 2940193323Sed // good a reason for the transformation. 2941193323Sed return ExtendNodes.size(); 2942193323Sed } 2943193323Sed return true; 2944193323Sed} 2945193323Sed 2946193323SedSDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2947193323Sed SDValue N0 = N->getOperand(0); 2948193323Sed MVT VT = N->getValueType(0); 2949193323Sed 2950193323Sed // fold (sext c1) -> c1 2951193323Sed if (isa<ConstantSDNode>(N0)) 2952193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2953193323Sed 2954193323Sed // fold (sext (sext x)) -> (sext x) 2955193323Sed // fold (sext (aext x)) -> (sext x) 2956193323Sed if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2957193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2958193323Sed N0.getOperand(0)); 2959193323Sed 2960193323Sed if (N0.getOpcode() == ISD::TRUNCATE) { 2961193323Sed // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2962193323Sed // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2963193323Sed SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2964193323Sed if (NarrowLoad.getNode()) { 2965193323Sed if (NarrowLoad.getNode() != N0.getNode()) 2966193323Sed CombineTo(N0.getNode(), NarrowLoad); 2967193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 2968193323Sed } 2969193323Sed 2970193323Sed // See if the value being truncated is already sign extended. If so, just 2971193323Sed // eliminate the trunc/sext pair. 2972193323Sed SDValue Op = N0.getOperand(0); 2973193323Sed unsigned OpBits = Op.getValueType().getSizeInBits(); 2974193323Sed unsigned MidBits = N0.getValueType().getSizeInBits(); 2975193323Sed unsigned DestBits = VT.getSizeInBits(); 2976193323Sed unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2977193323Sed 2978193323Sed if (OpBits == DestBits) { 2979193323Sed // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2980193323Sed // bits, it is already ready. 2981193323Sed if (NumSignBits > DestBits-MidBits) 2982193323Sed return Op; 2983193323Sed } else if (OpBits < DestBits) { 2984193323Sed // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2985193323Sed // bits, just sext from i32. 2986193323Sed if (NumSignBits > OpBits-MidBits) 2987193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 2988193323Sed } else { 2989193323Sed // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2990193323Sed // bits, just truncate to i32. 2991193323Sed if (NumSignBits > OpBits-MidBits) 2992193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 2993193323Sed } 2994193323Sed 2995193323Sed // fold (sext (truncate x)) -> (sextinreg x). 2996193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2997193323Sed N0.getValueType())) { 2998193323Sed if (Op.getValueType().bitsLT(VT)) 2999193323Sed Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3000193323Sed else if (Op.getValueType().bitsGT(VT)) 3001193323Sed Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3002193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3003193323Sed DAG.getValueType(N0.getValueType())); 3004193323Sed } 3005193323Sed } 3006193323Sed 3007193323Sed // fold (sext (load x)) -> (sext (truncate (sextload x))) 3008193323Sed if (ISD::isNON_EXTLoad(N0.getNode()) && 3009193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3010193323Sed TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3011193323Sed bool DoXform = true; 3012193323Sed SmallVector<SDNode*, 4> SetCCs; 3013193323Sed if (!N0.hasOneUse()) 3014193323Sed DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3015193323Sed if (DoXform) { 3016193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3017193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3018193323Sed LN0->getChain(), 3019193323Sed LN0->getBasePtr(), LN0->getSrcValue(), 3020193323Sed LN0->getSrcValueOffset(), 3021193323Sed N0.getValueType(), 3022193323Sed LN0->isVolatile(), LN0->getAlignment()); 3023193323Sed CombineTo(N, ExtLoad); 3024193323Sed SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3025193323Sed N0.getValueType(), ExtLoad); 3026193323Sed CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3027193323Sed 3028193323Sed // Extend SetCC uses if necessary. 3029193323Sed for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3030193323Sed SDNode *SetCC = SetCCs[i]; 3031193323Sed SmallVector<SDValue, 4> Ops; 3032193323Sed 3033193323Sed for (unsigned j = 0; j != 2; ++j) { 3034193323Sed SDValue SOp = SetCC->getOperand(j); 3035193323Sed if (SOp == Trunc) 3036193323Sed Ops.push_back(ExtLoad); 3037193323Sed else 3038193323Sed Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3039193323Sed N->getDebugLoc(), VT, SOp)); 3040193323Sed } 3041193323Sed 3042193323Sed Ops.push_back(SetCC->getOperand(2)); 3043193323Sed CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3044193323Sed SetCC->getValueType(0), 3045193323Sed &Ops[0], Ops.size())); 3046193323Sed } 3047193323Sed 3048193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3049193323Sed } 3050193323Sed } 3051193323Sed 3052193323Sed // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3053193323Sed // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3054193323Sed if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3055193323Sed ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3056193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3057193323Sed MVT EVT = LN0->getMemoryVT(); 3058193323Sed if ((!LegalOperations && !LN0->isVolatile()) || 3059193323Sed TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3060193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3061193323Sed LN0->getChain(), 3062193323Sed LN0->getBasePtr(), LN0->getSrcValue(), 3063193323Sed LN0->getSrcValueOffset(), EVT, 3064193323Sed LN0->isVolatile(), LN0->getAlignment()); 3065193323Sed CombineTo(N, ExtLoad); 3066193323Sed CombineTo(N0.getNode(), 3067193323Sed DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3068193323Sed N0.getValueType(), ExtLoad), 3069193323Sed ExtLoad.getValue(1)); 3070193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3071193323Sed } 3072193323Sed } 3073193323Sed 3074193323Sed // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3075193323Sed if (N0.getOpcode() == ISD::SETCC) { 3076193323Sed SDValue SCC = 3077193323Sed SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3078193323Sed DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3079193323Sed cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3080193323Sed if (SCC.getNode()) return SCC; 3081193323Sed } 3082193323Sed 3083193323Sed // fold (sext x) -> (zext x) if the sign bit is known zero. 3084193323Sed if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3085193323Sed DAG.SignBitIsZero(N0)) 3086193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3087193323Sed 3088193323Sed return SDValue(); 3089193323Sed} 3090193323Sed 3091193323SedSDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3092193323Sed SDValue N0 = N->getOperand(0); 3093193323Sed MVT VT = N->getValueType(0); 3094193323Sed 3095193323Sed // fold (zext c1) -> c1 3096193323Sed if (isa<ConstantSDNode>(N0)) 3097193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3098193323Sed // fold (zext (zext x)) -> (zext x) 3099193323Sed // fold (zext (aext x)) -> (zext x) 3100193323Sed if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3101193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3102193323Sed N0.getOperand(0)); 3103193323Sed 3104193323Sed // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3105193323Sed // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3106193323Sed if (N0.getOpcode() == ISD::TRUNCATE) { 3107193323Sed SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3108193323Sed if (NarrowLoad.getNode()) { 3109193323Sed if (NarrowLoad.getNode() != N0.getNode()) 3110193323Sed CombineTo(N0.getNode(), NarrowLoad); 3111193323Sed return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3112193323Sed } 3113193323Sed } 3114193323Sed 3115193323Sed // fold (zext (truncate x)) -> (and x, mask) 3116193323Sed if (N0.getOpcode() == ISD::TRUNCATE && 3117193323Sed (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3118193323Sed SDValue Op = N0.getOperand(0); 3119193323Sed if (Op.getValueType().bitsLT(VT)) { 3120193323Sed Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3121193323Sed } else if (Op.getValueType().bitsGT(VT)) { 3122193323Sed Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3123193323Sed } 3124193323Sed return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3125193323Sed } 3126193323Sed 3127193323Sed // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3128193323Sed // if either of the casts is not free. 3129193323Sed if (N0.getOpcode() == ISD::AND && 3130193323Sed N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3131193323Sed N0.getOperand(1).getOpcode() == ISD::Constant && 3132193323Sed (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3133193323Sed N0.getValueType()) || 3134193323Sed !TLI.isZExtFree(N0.getValueType(), VT))) { 3135193323Sed SDValue X = N0.getOperand(0).getOperand(0); 3136193323Sed if (X.getValueType().bitsLT(VT)) { 3137193323Sed X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3138193323Sed } else if (X.getValueType().bitsGT(VT)) { 3139193323Sed X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3140193323Sed } 3141193323Sed APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3142193323Sed Mask.zext(VT.getSizeInBits()); 3143193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3144193323Sed X, DAG.getConstant(Mask, VT)); 3145193323Sed } 3146193323Sed 3147193323Sed // fold (zext (load x)) -> (zext (truncate (zextload x))) 3148193323Sed if (ISD::isNON_EXTLoad(N0.getNode()) && 3149193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3150193323Sed TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3151193323Sed bool DoXform = true; 3152193323Sed SmallVector<SDNode*, 4> SetCCs; 3153193323Sed if (!N0.hasOneUse()) 3154193323Sed DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3155193323Sed if (DoXform) { 3156193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3157193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3158193323Sed LN0->getChain(), 3159193323Sed LN0->getBasePtr(), LN0->getSrcValue(), 3160193323Sed LN0->getSrcValueOffset(), 3161193323Sed N0.getValueType(), 3162193323Sed LN0->isVolatile(), LN0->getAlignment()); 3163193323Sed CombineTo(N, ExtLoad); 3164193323Sed SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3165193323Sed N0.getValueType(), ExtLoad); 3166193323Sed CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3167193323Sed 3168193323Sed // Extend SetCC uses if necessary. 3169193323Sed for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3170193323Sed SDNode *SetCC = SetCCs[i]; 3171193323Sed SmallVector<SDValue, 4> Ops; 3172193323Sed 3173193323Sed for (unsigned j = 0; j != 2; ++j) { 3174193323Sed SDValue SOp = SetCC->getOperand(j); 3175193323Sed if (SOp == Trunc) 3176193323Sed Ops.push_back(ExtLoad); 3177193323Sed else 3178193323Sed Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3179193323Sed N->getDebugLoc(), VT, SOp)); 3180193323Sed } 3181193323Sed 3182193323Sed Ops.push_back(SetCC->getOperand(2)); 3183193323Sed CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3184193323Sed SetCC->getValueType(0), 3185193323Sed &Ops[0], Ops.size())); 3186193323Sed } 3187193323Sed 3188193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3189193323Sed } 3190193323Sed } 3191193323Sed 3192193323Sed // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3193193323Sed // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3194193323Sed if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3195193323Sed ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3196193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3197193323Sed MVT EVT = LN0->getMemoryVT(); 3198193323Sed if ((!LegalOperations && !LN0->isVolatile()) || 3199193323Sed TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3200193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3201193323Sed LN0->getChain(), 3202193323Sed LN0->getBasePtr(), LN0->getSrcValue(), 3203193323Sed LN0->getSrcValueOffset(), EVT, 3204193323Sed LN0->isVolatile(), LN0->getAlignment()); 3205193323Sed CombineTo(N, ExtLoad); 3206193323Sed CombineTo(N0.getNode(), 3207193323Sed DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3208193323Sed ExtLoad), 3209193323Sed ExtLoad.getValue(1)); 3210193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3211193323Sed } 3212193323Sed } 3213193323Sed 3214193323Sed // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3215193323Sed if (N0.getOpcode() == ISD::SETCC) { 3216193323Sed SDValue SCC = 3217193323Sed SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3218193323Sed DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3219193323Sed cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3220193323Sed if (SCC.getNode()) return SCC; 3221193323Sed } 3222193323Sed 3223193323Sed return SDValue(); 3224193323Sed} 3225193323Sed 3226193323SedSDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3227193323Sed SDValue N0 = N->getOperand(0); 3228193323Sed MVT VT = N->getValueType(0); 3229193323Sed 3230193323Sed // fold (aext c1) -> c1 3231193323Sed if (isa<ConstantSDNode>(N0)) 3232193323Sed return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3233193323Sed // fold (aext (aext x)) -> (aext x) 3234193323Sed // fold (aext (zext x)) -> (zext x) 3235193323Sed // fold (aext (sext x)) -> (sext x) 3236193323Sed if (N0.getOpcode() == ISD::ANY_EXTEND || 3237193323Sed N0.getOpcode() == ISD::ZERO_EXTEND || 3238193323Sed N0.getOpcode() == ISD::SIGN_EXTEND) 3239193323Sed return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3240193323Sed 3241193323Sed // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3242193323Sed // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3243193323Sed if (N0.getOpcode() == ISD::TRUNCATE) { 3244193323Sed SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3245193323Sed if (NarrowLoad.getNode()) { 3246193323Sed if (NarrowLoad.getNode() != N0.getNode()) 3247193323Sed CombineTo(N0.getNode(), NarrowLoad); 3248193323Sed return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3249193323Sed } 3250193323Sed } 3251193323Sed 3252193323Sed // fold (aext (truncate x)) 3253193323Sed if (N0.getOpcode() == ISD::TRUNCATE) { 3254193323Sed SDValue TruncOp = N0.getOperand(0); 3255193323Sed if (TruncOp.getValueType() == VT) 3256193323Sed return TruncOp; // x iff x size == zext size. 3257193323Sed if (TruncOp.getValueType().bitsGT(VT)) 3258193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3259193323Sed return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3260193323Sed } 3261193323Sed 3262193323Sed // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3263193323Sed // if the trunc is not free. 3264193323Sed if (N0.getOpcode() == ISD::AND && 3265193323Sed N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3266193323Sed N0.getOperand(1).getOpcode() == ISD::Constant && 3267193323Sed !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3268193323Sed N0.getValueType())) { 3269193323Sed SDValue X = N0.getOperand(0).getOperand(0); 3270193323Sed if (X.getValueType().bitsLT(VT)) { 3271193323Sed X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3272193323Sed } else if (X.getValueType().bitsGT(VT)) { 3273193323Sed X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3274193323Sed } 3275193323Sed APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3276193323Sed Mask.zext(VT.getSizeInBits()); 3277193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3278193323Sed X, DAG.getConstant(Mask, VT)); 3279193323Sed } 3280193323Sed 3281193323Sed // fold (aext (load x)) -> (aext (truncate (extload x))) 3282193323Sed if (ISD::isNON_EXTLoad(N0.getNode()) && 3283193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3284193323Sed TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3285193323Sed bool DoXform = true; 3286193323Sed SmallVector<SDNode*, 4> SetCCs; 3287193323Sed if (!N0.hasOneUse()) 3288193323Sed DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3289193323Sed if (DoXform) { 3290193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3291193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3292193323Sed LN0->getChain(), 3293193323Sed LN0->getBasePtr(), LN0->getSrcValue(), 3294193323Sed LN0->getSrcValueOffset(), 3295193323Sed N0.getValueType(), 3296193323Sed LN0->isVolatile(), LN0->getAlignment()); 3297193323Sed CombineTo(N, ExtLoad); 3298193323Sed SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3299193323Sed N0.getValueType(), ExtLoad); 3300193323Sed CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3301193323Sed 3302193323Sed // Extend SetCC uses if necessary. 3303193323Sed for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3304193323Sed SDNode *SetCC = SetCCs[i]; 3305193323Sed SmallVector<SDValue, 4> Ops; 3306193323Sed 3307193323Sed for (unsigned j = 0; j != 2; ++j) { 3308193323Sed SDValue SOp = SetCC->getOperand(j); 3309193323Sed if (SOp == Trunc) 3310193323Sed Ops.push_back(ExtLoad); 3311193323Sed else 3312193323Sed Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3313193323Sed N->getDebugLoc(), VT, SOp)); 3314193323Sed } 3315193323Sed 3316193323Sed Ops.push_back(SetCC->getOperand(2)); 3317193323Sed CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3318193323Sed SetCC->getValueType(0), 3319193323Sed &Ops[0], Ops.size())); 3320193323Sed } 3321193323Sed 3322193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3323193323Sed } 3324193323Sed } 3325193323Sed 3326193323Sed // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3327193323Sed // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3328193323Sed // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3329193323Sed if (N0.getOpcode() == ISD::LOAD && 3330193323Sed !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3331193323Sed N0.hasOneUse()) { 3332193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3333193323Sed MVT EVT = LN0->getMemoryVT(); 3334193323Sed SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3335193323Sed VT, LN0->getChain(), LN0->getBasePtr(), 3336193323Sed LN0->getSrcValue(), 3337193323Sed LN0->getSrcValueOffset(), EVT, 3338193323Sed LN0->isVolatile(), LN0->getAlignment()); 3339193323Sed CombineTo(N, ExtLoad); 3340193323Sed CombineTo(N0.getNode(), 3341193323Sed DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3342193323Sed N0.getValueType(), ExtLoad), 3343193323Sed ExtLoad.getValue(1)); 3344193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3345193323Sed } 3346193323Sed 3347193323Sed // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3348193323Sed if (N0.getOpcode() == ISD::SETCC) { 3349193323Sed SDValue SCC = 3350193323Sed SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3351193323Sed DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3352193323Sed cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3353193323Sed if (SCC.getNode()) 3354193323Sed return SCC; 3355193323Sed } 3356193323Sed 3357193323Sed return SDValue(); 3358193323Sed} 3359193323Sed 3360193323Sed/// GetDemandedBits - See if the specified operand can be simplified with the 3361193323Sed/// knowledge that only the bits specified by Mask are used. If so, return the 3362193323Sed/// simpler operand, otherwise return a null SDValue. 3363193323SedSDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3364193323Sed switch (V.getOpcode()) { 3365193323Sed default: break; 3366193323Sed case ISD::OR: 3367193323Sed case ISD::XOR: 3368193323Sed // If the LHS or RHS don't contribute bits to the or, drop them. 3369193323Sed if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3370193323Sed return V.getOperand(1); 3371193323Sed if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3372193323Sed return V.getOperand(0); 3373193323Sed break; 3374193323Sed case ISD::SRL: 3375193323Sed // Only look at single-use SRLs. 3376193323Sed if (!V.getNode()->hasOneUse()) 3377193323Sed break; 3378193323Sed if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3379193323Sed // See if we can recursively simplify the LHS. 3380193323Sed unsigned Amt = RHSC->getZExtValue(); 3381193323Sed 3382193323Sed // Watch out for shift count overflow though. 3383193323Sed if (Amt >= Mask.getBitWidth()) break; 3384193323Sed APInt NewMask = Mask << Amt; 3385193323Sed SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3386193323Sed if (SimplifyLHS.getNode()) 3387193323Sed return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3388193323Sed SimplifyLHS, V.getOperand(1)); 3389193323Sed } 3390193323Sed } 3391193323Sed return SDValue(); 3392193323Sed} 3393193323Sed 3394193323Sed/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3395193323Sed/// bits and then truncated to a narrower type and where N is a multiple 3396193323Sed/// of number of bits of the narrower type, transform it to a narrower load 3397193323Sed/// from address + N / num of bits of new type. If the result is to be 3398193323Sed/// extended, also fold the extension to form a extending load. 3399193323SedSDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3400193323Sed unsigned Opc = N->getOpcode(); 3401193323Sed ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3402193323Sed SDValue N0 = N->getOperand(0); 3403193323Sed MVT VT = N->getValueType(0); 3404193323Sed MVT EVT = VT; 3405193323Sed 3406193323Sed // This transformation isn't valid for vector loads. 3407193323Sed if (VT.isVector()) 3408193323Sed return SDValue(); 3409193323Sed 3410193323Sed // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3411193323Sed // extended to VT. 3412193323Sed if (Opc == ISD::SIGN_EXTEND_INREG) { 3413193323Sed ExtType = ISD::SEXTLOAD; 3414193323Sed EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3415193323Sed if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3416193323Sed return SDValue(); 3417193323Sed } 3418193323Sed 3419193323Sed unsigned EVTBits = EVT.getSizeInBits(); 3420193323Sed unsigned ShAmt = 0; 3421193323Sed if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3422193323Sed if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3423193323Sed ShAmt = N01->getZExtValue(); 3424193323Sed // Is the shift amount a multiple of size of VT? 3425193323Sed if ((ShAmt & (EVTBits-1)) == 0) { 3426193323Sed N0 = N0.getOperand(0); 3427193323Sed if (N0.getValueType().getSizeInBits() <= EVTBits) 3428193323Sed return SDValue(); 3429193323Sed } 3430193323Sed } 3431193323Sed } 3432193323Sed 3433193323Sed // Do not generate loads of non-round integer types since these can 3434193323Sed // be expensive (and would be wrong if the type is not byte sized). 3435193323Sed if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3436193323Sed cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3437193323Sed // Do not change the width of a volatile load. 3438193323Sed !cast<LoadSDNode>(N0)->isVolatile()) { 3439193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3440193323Sed MVT PtrType = N0.getOperand(1).getValueType(); 3441193323Sed 3442193323Sed // For big endian targets, we need to adjust the offset to the pointer to 3443193323Sed // load the correct bytes. 3444193323Sed if (TLI.isBigEndian()) { 3445193323Sed unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3446193323Sed unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3447193323Sed ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3448193323Sed } 3449193323Sed 3450193323Sed uint64_t PtrOff = ShAmt / 8; 3451193323Sed unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3452193323Sed SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3453193323Sed PtrType, LN0->getBasePtr(), 3454193323Sed DAG.getConstant(PtrOff, PtrType)); 3455193323Sed AddToWorkList(NewPtr.getNode()); 3456193323Sed 3457193323Sed SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3458193323Sed ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3459193323Sed LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3460193323Sed LN0->isVolatile(), NewAlign) 3461193323Sed : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3462193323Sed LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3463193323Sed EVT, LN0->isVolatile(), NewAlign); 3464193323Sed 3465193323Sed // Replace the old load's chain with the new load's chain. 3466193323Sed WorkListRemover DeadNodes(*this); 3467193323Sed DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3468193323Sed &DeadNodes); 3469193323Sed 3470193323Sed // Return the new loaded value. 3471193323Sed return Load; 3472193323Sed } 3473193323Sed 3474193323Sed return SDValue(); 3475193323Sed} 3476193323Sed 3477193323SedSDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3478193323Sed SDValue N0 = N->getOperand(0); 3479193323Sed SDValue N1 = N->getOperand(1); 3480193323Sed MVT VT = N->getValueType(0); 3481193323Sed MVT EVT = cast<VTSDNode>(N1)->getVT(); 3482193323Sed unsigned VTBits = VT.getSizeInBits(); 3483193323Sed unsigned EVTBits = EVT.getSizeInBits(); 3484193323Sed 3485193323Sed // fold (sext_in_reg c1) -> c1 3486193323Sed if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3487193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3488193323Sed 3489193323Sed // If the input is already sign extended, just drop the extension. 3490193323Sed if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3491193323Sed return N0; 3492193323Sed 3493193323Sed // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3494193323Sed if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3495193323Sed EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3496193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3497193323Sed N0.getOperand(0), N1); 3498193323Sed } 3499193323Sed 3500193323Sed // fold (sext_in_reg (sext x)) -> (sext x) 3501193323Sed // fold (sext_in_reg (aext x)) -> (sext x) 3502193323Sed // if x is small enough. 3503193323Sed if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3504193323Sed SDValue N00 = N0.getOperand(0); 3505193323Sed if (N00.getValueType().getSizeInBits() < EVTBits) 3506193323Sed return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3507193323Sed } 3508193323Sed 3509193323Sed // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3510193323Sed if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3511193323Sed return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3512193323Sed 3513193323Sed // fold operands of sext_in_reg based on knowledge that the top bits are not 3514193323Sed // demanded. 3515193323Sed if (SimplifyDemandedBits(SDValue(N, 0))) 3516193323Sed return SDValue(N, 0); 3517193323Sed 3518193323Sed // fold (sext_in_reg (load x)) -> (smaller sextload x) 3519193323Sed // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3520193323Sed SDValue NarrowLoad = ReduceLoadWidth(N); 3521193323Sed if (NarrowLoad.getNode()) 3522193323Sed return NarrowLoad; 3523193323Sed 3524193323Sed // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3525193323Sed // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3526193323Sed // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3527193323Sed if (N0.getOpcode() == ISD::SRL) { 3528193323Sed if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3529193323Sed if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3530193323Sed // We can turn this into an SRA iff the input to the SRL is already sign 3531193323Sed // extended enough. 3532193323Sed unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3533193323Sed if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3534193323Sed return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3535193323Sed N0.getOperand(0), N0.getOperand(1)); 3536193323Sed } 3537193323Sed } 3538193323Sed 3539193323Sed // fold (sext_inreg (extload x)) -> (sextload x) 3540193323Sed if (ISD::isEXTLoad(N0.getNode()) && 3541193323Sed ISD::isUNINDEXEDLoad(N0.getNode()) && 3542193323Sed EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3543193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3544193323Sed TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3545193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3546193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3547193323Sed LN0->getChain(), 3548193323Sed LN0->getBasePtr(), LN0->getSrcValue(), 3549193323Sed LN0->getSrcValueOffset(), EVT, 3550193323Sed LN0->isVolatile(), LN0->getAlignment()); 3551193323Sed CombineTo(N, ExtLoad); 3552193323Sed CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3553193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3554193323Sed } 3555193323Sed // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3556193323Sed if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3557193323Sed N0.hasOneUse() && 3558193323Sed EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3559193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3560193323Sed TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3561193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3562193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3563193323Sed LN0->getChain(), 3564193323Sed LN0->getBasePtr(), LN0->getSrcValue(), 3565193323Sed LN0->getSrcValueOffset(), EVT, 3566193323Sed LN0->isVolatile(), LN0->getAlignment()); 3567193323Sed CombineTo(N, ExtLoad); 3568193323Sed CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3569193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 3570193323Sed } 3571193323Sed return SDValue(); 3572193323Sed} 3573193323Sed 3574193323SedSDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3575193323Sed SDValue N0 = N->getOperand(0); 3576193323Sed MVT VT = N->getValueType(0); 3577193323Sed 3578193323Sed // noop truncate 3579193323Sed if (N0.getValueType() == N->getValueType(0)) 3580193323Sed return N0; 3581193323Sed // fold (truncate c1) -> c1 3582193323Sed if (isa<ConstantSDNode>(N0)) 3583193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3584193323Sed // fold (truncate (truncate x)) -> (truncate x) 3585193323Sed if (N0.getOpcode() == ISD::TRUNCATE) 3586193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3587193323Sed // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3588193323Sed if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3589193323Sed N0.getOpcode() == ISD::ANY_EXTEND) { 3590193323Sed if (N0.getOperand(0).getValueType().bitsLT(VT)) 3591193323Sed // if the source is smaller than the dest, we still need an extend 3592193323Sed return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3593193323Sed N0.getOperand(0)); 3594193323Sed else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3595193323Sed // if the source is larger than the dest, than we just need the truncate 3596193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3597193323Sed else 3598193323Sed // if the source and dest are the same type, we can drop both the extend 3599193323Sed // and the truncate 3600193323Sed return N0.getOperand(0); 3601193323Sed } 3602193323Sed 3603193323Sed // See if we can simplify the input to this truncate through knowledge that 3604193323Sed // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3605193323Sed // -> trunc y 3606193323Sed SDValue Shorter = 3607193323Sed GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3608193323Sed VT.getSizeInBits())); 3609193323Sed if (Shorter.getNode()) 3610193323Sed return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3611193323Sed 3612193323Sed // fold (truncate (load x)) -> (smaller load x) 3613193323Sed // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3614193323Sed return ReduceLoadWidth(N); 3615193323Sed} 3616193323Sed 3617193323Sedstatic SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3618193323Sed SDValue Elt = N->getOperand(i); 3619193323Sed if (Elt.getOpcode() != ISD::MERGE_VALUES) 3620193323Sed return Elt.getNode(); 3621193323Sed return Elt.getOperand(Elt.getResNo()).getNode(); 3622193323Sed} 3623193323Sed 3624193323Sed/// CombineConsecutiveLoads - build_pair (load, load) -> load 3625193323Sed/// if load locations are consecutive. 3626193323SedSDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3627193323Sed assert(N->getOpcode() == ISD::BUILD_PAIR); 3628193323Sed 3629193323Sed SDNode *LD1 = getBuildPairElt(N, 0); 3630193323Sed if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3631193323Sed return SDValue(); 3632193323Sed MVT LD1VT = LD1->getValueType(0); 3633193323Sed SDNode *LD2 = getBuildPairElt(N, 1); 3634193323Sed const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3635193323Sed 3636193323Sed if (ISD::isNON_EXTLoad(LD2) && 3637193323Sed LD2->hasOneUse() && 3638193323Sed // If both are volatile this would reduce the number of volatile loads. 3639193323Sed // If one is volatile it might be ok, but play conservative and bail out. 3640193323Sed !cast<LoadSDNode>(LD1)->isVolatile() && 3641193323Sed !cast<LoadSDNode>(LD2)->isVolatile() && 3642193323Sed TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3643193323Sed LoadSDNode *LD = cast<LoadSDNode>(LD1); 3644193323Sed unsigned Align = LD->getAlignment(); 3645193323Sed unsigned NewAlign = TLI.getTargetData()-> 3646193323Sed getABITypeAlignment(VT.getTypeForMVT()); 3647193323Sed 3648193323Sed if (NewAlign <= Align && 3649193323Sed (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3650193323Sed return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(), 3651193323Sed LD->getSrcValue(), LD->getSrcValueOffset(), 3652193323Sed false, Align); 3653193323Sed } 3654193323Sed 3655193323Sed return SDValue(); 3656193323Sed} 3657193323Sed 3658193323SedSDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3659193323Sed SDValue N0 = N->getOperand(0); 3660193323Sed MVT VT = N->getValueType(0); 3661193323Sed 3662193323Sed // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3663193323Sed // Only do this before legalize, since afterward the target may be depending 3664193323Sed // on the bitconvert. 3665193323Sed // First check to see if this is all constant. 3666193323Sed if (!LegalTypes && 3667193323Sed N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3668193323Sed VT.isVector()) { 3669193323Sed bool isSimple = true; 3670193323Sed for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3671193323Sed if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3672193323Sed N0.getOperand(i).getOpcode() != ISD::Constant && 3673193323Sed N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3674193323Sed isSimple = false; 3675193323Sed break; 3676193323Sed } 3677193323Sed 3678193323Sed MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3679193323Sed assert(!DestEltVT.isVector() && 3680193323Sed "Element type of vector ValueType must not be vector!"); 3681193323Sed if (isSimple) 3682193323Sed return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3683193323Sed } 3684193323Sed 3685193323Sed // If the input is a constant, let getNode fold it. 3686193323Sed if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3687193323Sed SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3688193323Sed if (Res.getNode() != N) return Res; 3689193323Sed } 3690193323Sed 3691193323Sed // (conv (conv x, t1), t2) -> (conv x, t2) 3692193323Sed if (N0.getOpcode() == ISD::BIT_CONVERT) 3693193323Sed return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3694193323Sed N0.getOperand(0)); 3695193323Sed 3696193323Sed // fold (conv (load x)) -> (load (conv*)x) 3697193323Sed // If the resultant load doesn't need a higher alignment than the original! 3698193323Sed if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3699193323Sed // Do not change the width of a volatile load. 3700193323Sed !cast<LoadSDNode>(N0)->isVolatile() && 3701193323Sed (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3702193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3703193323Sed unsigned Align = TLI.getTargetData()-> 3704193323Sed getABITypeAlignment(VT.getTypeForMVT()); 3705193323Sed unsigned OrigAlign = LN0->getAlignment(); 3706193323Sed 3707193323Sed if (Align <= OrigAlign) { 3708193323Sed SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3709193323Sed LN0->getBasePtr(), 3710193323Sed LN0->getSrcValue(), LN0->getSrcValueOffset(), 3711193323Sed LN0->isVolatile(), OrigAlign); 3712193323Sed AddToWorkList(N); 3713193323Sed CombineTo(N0.getNode(), 3714193323Sed DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3715193323Sed N0.getValueType(), Load), 3716193323Sed Load.getValue(1)); 3717193323Sed return Load; 3718193323Sed } 3719193323Sed } 3720193323Sed 3721193323Sed // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3722193323Sed // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3723193323Sed // This often reduces constant pool loads. 3724193323Sed if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3725193323Sed N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3726193323Sed SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3727193323Sed N0.getOperand(0)); 3728193323Sed AddToWorkList(NewConv.getNode()); 3729193323Sed 3730193323Sed APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3731193323Sed if (N0.getOpcode() == ISD::FNEG) 3732193323Sed return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3733193323Sed NewConv, DAG.getConstant(SignBit, VT)); 3734193323Sed assert(N0.getOpcode() == ISD::FABS); 3735193323Sed return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3736193323Sed NewConv, DAG.getConstant(~SignBit, VT)); 3737193323Sed } 3738193323Sed 3739193323Sed // fold (bitconvert (fcopysign cst, x)) -> 3740193323Sed // (or (and (bitconvert x), sign), (and cst, (not sign))) 3741193323Sed // Note that we don't handle (copysign x, cst) because this can always be 3742193323Sed // folded to an fneg or fabs. 3743193323Sed if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3744193323Sed isa<ConstantFPSDNode>(N0.getOperand(0)) && 3745193323Sed VT.isInteger() && !VT.isVector()) { 3746193323Sed unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3747193323Sed MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3748193323Sed if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3749193323Sed SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3750193323Sed IntXVT, N0.getOperand(1)); 3751193323Sed AddToWorkList(X.getNode()); 3752193323Sed 3753193323Sed // If X has a different width than the result/lhs, sext it or truncate it. 3754193323Sed unsigned VTWidth = VT.getSizeInBits(); 3755193323Sed if (OrigXWidth < VTWidth) { 3756193323Sed X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3757193323Sed AddToWorkList(X.getNode()); 3758193323Sed } else if (OrigXWidth > VTWidth) { 3759193323Sed // To get the sign bit in the right place, we have to shift it right 3760193323Sed // before truncating. 3761193323Sed X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3762193323Sed X.getValueType(), X, 3763193323Sed DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3764193323Sed AddToWorkList(X.getNode()); 3765193323Sed X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3766193323Sed AddToWorkList(X.getNode()); 3767193323Sed } 3768193323Sed 3769193323Sed APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3770193323Sed X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3771193323Sed X, DAG.getConstant(SignBit, VT)); 3772193323Sed AddToWorkList(X.getNode()); 3773193323Sed 3774193323Sed SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3775193323Sed VT, N0.getOperand(0)); 3776193323Sed Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3777193323Sed Cst, DAG.getConstant(~SignBit, VT)); 3778193323Sed AddToWorkList(Cst.getNode()); 3779193323Sed 3780193323Sed return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3781193323Sed } 3782193323Sed } 3783193323Sed 3784193323Sed // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3785193323Sed if (N0.getOpcode() == ISD::BUILD_PAIR) { 3786193323Sed SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3787193323Sed if (CombineLD.getNode()) 3788193323Sed return CombineLD; 3789193323Sed } 3790193323Sed 3791193323Sed return SDValue(); 3792193323Sed} 3793193323Sed 3794193323SedSDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3795193323Sed MVT VT = N->getValueType(0); 3796193323Sed return CombineConsecutiveLoads(N, VT); 3797193323Sed} 3798193323Sed 3799193323Sed/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3800193323Sed/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3801193323Sed/// destination element value type. 3802193323SedSDValue DAGCombiner:: 3803193323SedConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3804193323Sed MVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3805193323Sed 3806193323Sed // If this is already the right type, we're done. 3807193323Sed if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3808193323Sed 3809193323Sed unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3810193323Sed unsigned DstBitSize = DstEltVT.getSizeInBits(); 3811193323Sed 3812193323Sed // If this is a conversion of N elements of one type to N elements of another 3813193323Sed // type, convert each element. This handles FP<->INT cases. 3814193323Sed if (SrcBitSize == DstBitSize) { 3815193323Sed SmallVector<SDValue, 8> Ops; 3816193323Sed for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3817193323Sed SDValue Op = BV->getOperand(i); 3818193323Sed // If the vector element type is not legal, the BUILD_VECTOR operands 3819193323Sed // are promoted and implicitly truncated. Make that explicit here. 3820193323Sed if (Op.getValueType() != SrcEltVT) 3821193323Sed Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3822193323Sed Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3823193323Sed DstEltVT, Op)); 3824193323Sed AddToWorkList(Ops.back().getNode()); 3825193323Sed } 3826193323Sed MVT VT = MVT::getVectorVT(DstEltVT, 3827193323Sed BV->getValueType(0).getVectorNumElements()); 3828193323Sed return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3829193323Sed &Ops[0], Ops.size()); 3830193323Sed } 3831193323Sed 3832193323Sed // Otherwise, we're growing or shrinking the elements. To avoid having to 3833193323Sed // handle annoying details of growing/shrinking FP values, we convert them to 3834193323Sed // int first. 3835193323Sed if (SrcEltVT.isFloatingPoint()) { 3836193323Sed // Convert the input float vector to a int vector where the elements are the 3837193323Sed // same sizes. 3838193323Sed assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3839193323Sed MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3840193323Sed BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3841193323Sed SrcEltVT = IntVT; 3842193323Sed } 3843193323Sed 3844193323Sed // Now we know the input is an integer vector. If the output is a FP type, 3845193323Sed // convert to integer first, then to FP of the right size. 3846193323Sed if (DstEltVT.isFloatingPoint()) { 3847193323Sed assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3848193323Sed MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3849193323Sed SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3850193323Sed 3851193323Sed // Next, convert to FP elements of the same size. 3852193323Sed return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3853193323Sed } 3854193323Sed 3855193323Sed // Okay, we know the src/dst types are both integers of differing types. 3856193323Sed // Handling growing first. 3857193323Sed assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3858193323Sed if (SrcBitSize < DstBitSize) { 3859193323Sed unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3860193323Sed 3861193323Sed SmallVector<SDValue, 8> Ops; 3862193323Sed for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3863193323Sed i += NumInputsPerOutput) { 3864193323Sed bool isLE = TLI.isLittleEndian(); 3865193323Sed APInt NewBits = APInt(DstBitSize, 0); 3866193323Sed bool EltIsUndef = true; 3867193323Sed for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3868193323Sed // Shift the previously computed bits over. 3869193323Sed NewBits <<= SrcBitSize; 3870193323Sed SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3871193323Sed if (Op.getOpcode() == ISD::UNDEF) continue; 3872193323Sed EltIsUndef = false; 3873193323Sed 3874193323Sed NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3875193323Sed zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3876193323Sed } 3877193323Sed 3878193323Sed if (EltIsUndef) 3879193323Sed Ops.push_back(DAG.getUNDEF(DstEltVT)); 3880193323Sed else 3881193323Sed Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3882193323Sed } 3883193323Sed 3884193323Sed MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3885193323Sed return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3886193323Sed &Ops[0], Ops.size()); 3887193323Sed } 3888193323Sed 3889193323Sed // Finally, this must be the case where we are shrinking elements: each input 3890193323Sed // turns into multiple outputs. 3891193323Sed bool isS2V = ISD::isScalarToVector(BV); 3892193323Sed unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3893193323Sed MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3894193323Sed SmallVector<SDValue, 8> Ops; 3895193323Sed 3896193323Sed for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3897193323Sed if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3898193323Sed for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3899193323Sed Ops.push_back(DAG.getUNDEF(DstEltVT)); 3900193323Sed continue; 3901193323Sed } 3902193323Sed 3903193323Sed APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 3904193323Sed getAPIntValue()).zextOrTrunc(SrcBitSize); 3905193323Sed 3906193323Sed for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3907193323Sed APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3908193323Sed Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3909193323Sed if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3910193323Sed // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3911193323Sed return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3912193323Sed Ops[0]); 3913193323Sed OpVal = OpVal.lshr(DstBitSize); 3914193323Sed } 3915193323Sed 3916193323Sed // For big endian targets, swap the order of the pieces of each element. 3917193323Sed if (TLI.isBigEndian()) 3918193323Sed std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3919193323Sed } 3920193323Sed 3921193323Sed return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3922193323Sed &Ops[0], Ops.size()); 3923193323Sed} 3924193323Sed 3925193323SedSDValue DAGCombiner::visitFADD(SDNode *N) { 3926193323Sed SDValue N0 = N->getOperand(0); 3927193323Sed SDValue N1 = N->getOperand(1); 3928193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3929193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3930193323Sed MVT VT = N->getValueType(0); 3931193323Sed 3932193323Sed // fold vector ops 3933193323Sed if (VT.isVector()) { 3934193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 3935193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 3936193323Sed } 3937193323Sed 3938193323Sed // fold (fadd c1, c2) -> (fadd c1, c2) 3939193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 3940193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3941193323Sed // canonicalize constant to RHS 3942193323Sed if (N0CFP && !N1CFP) 3943193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3944193323Sed // fold (fadd A, 0) -> A 3945193323Sed if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3946193323Sed return N0; 3947193323Sed // fold (fadd A, (fneg B)) -> (fsub A, B) 3948193323Sed if (isNegatibleForFree(N1, LegalOperations) == 2) 3949193323Sed return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3950193323Sed GetNegatedExpression(N1, DAG, LegalOperations)); 3951193323Sed // fold (fadd (fneg A), B) -> (fsub B, A) 3952193323Sed if (isNegatibleForFree(N0, LegalOperations) == 2) 3953193323Sed return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3954193323Sed GetNegatedExpression(N0, DAG, LegalOperations)); 3955193323Sed 3956193323Sed // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3957193323Sed if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3958193323Sed N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3959193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3960193323Sed DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3961193323Sed N0.getOperand(1), N1)); 3962193323Sed 3963193323Sed return SDValue(); 3964193323Sed} 3965193323Sed 3966193323SedSDValue DAGCombiner::visitFSUB(SDNode *N) { 3967193323Sed SDValue N0 = N->getOperand(0); 3968193323Sed SDValue N1 = N->getOperand(1); 3969193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3970193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3971193323Sed MVT VT = N->getValueType(0); 3972193323Sed 3973193323Sed // fold vector ops 3974193323Sed if (VT.isVector()) { 3975193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 3976193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 3977193323Sed } 3978193323Sed 3979193323Sed // fold (fsub c1, c2) -> c1-c2 3980193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 3981193323Sed return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 3982193323Sed // fold (fsub A, 0) -> A 3983193323Sed if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3984193323Sed return N0; 3985193323Sed // fold (fsub 0, B) -> -B 3986193323Sed if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3987193323Sed if (isNegatibleForFree(N1, LegalOperations)) 3988193323Sed return GetNegatedExpression(N1, DAG, LegalOperations); 3989193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 3990193323Sed return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 3991193323Sed } 3992193323Sed // fold (fsub A, (fneg B)) -> (fadd A, B) 3993193323Sed if (isNegatibleForFree(N1, LegalOperations)) 3994193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 3995193323Sed GetNegatedExpression(N1, DAG, LegalOperations)); 3996193323Sed 3997193323Sed return SDValue(); 3998193323Sed} 3999193323Sed 4000193323SedSDValue DAGCombiner::visitFMUL(SDNode *N) { 4001193323Sed SDValue N0 = N->getOperand(0); 4002193323Sed SDValue N1 = N->getOperand(1); 4003193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4004193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4005193323Sed MVT VT = N->getValueType(0); 4006193323Sed 4007193323Sed // fold vector ops 4008193323Sed if (VT.isVector()) { 4009193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 4010193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 4011193323Sed } 4012193323Sed 4013193323Sed // fold (fmul c1, c2) -> c1*c2 4014193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 4015193323Sed return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4016193323Sed // canonicalize constant to RHS 4017193323Sed if (N0CFP && !N1CFP) 4018193323Sed return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4019193323Sed // fold (fmul A, 0) -> 0 4020193323Sed if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4021193323Sed return N1; 4022193323Sed // fold (fmul X, 2.0) -> (fadd X, X) 4023193323Sed if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4024193323Sed return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4025193323Sed // fold (fmul X, (fneg 1.0)) -> (fneg X) 4026193323Sed if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4027193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4028193323Sed return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4029193323Sed 4030193323Sed // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4031193323Sed if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4032193323Sed if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4033193323Sed // Both can be negated for free, check to see if at least one is cheaper 4034193323Sed // negated. 4035193323Sed if (LHSNeg == 2 || RHSNeg == 2) 4036193323Sed return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4037193323Sed GetNegatedExpression(N0, DAG, LegalOperations), 4038193323Sed GetNegatedExpression(N1, DAG, LegalOperations)); 4039193323Sed } 4040193323Sed } 4041193323Sed 4042193323Sed // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4043193323Sed if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4044193323Sed N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4045193323Sed return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4046193323Sed DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4047193323Sed N0.getOperand(1), N1)); 4048193323Sed 4049193323Sed return SDValue(); 4050193323Sed} 4051193323Sed 4052193323SedSDValue DAGCombiner::visitFDIV(SDNode *N) { 4053193323Sed SDValue N0 = N->getOperand(0); 4054193323Sed SDValue N1 = N->getOperand(1); 4055193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4056193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4057193323Sed MVT VT = N->getValueType(0); 4058193323Sed 4059193323Sed // fold vector ops 4060193323Sed if (VT.isVector()) { 4061193323Sed SDValue FoldedVOp = SimplifyVBinOp(N); 4062193323Sed if (FoldedVOp.getNode()) return FoldedVOp; 4063193323Sed } 4064193323Sed 4065193323Sed // fold (fdiv c1, c2) -> c1/c2 4066193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 4067193323Sed return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4068193323Sed 4069193323Sed 4070193323Sed // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4071193323Sed if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4072193323Sed if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4073193323Sed // Both can be negated for free, check to see if at least one is cheaper 4074193323Sed // negated. 4075193323Sed if (LHSNeg == 2 || RHSNeg == 2) 4076193323Sed return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4077193323Sed GetNegatedExpression(N0, DAG, LegalOperations), 4078193323Sed GetNegatedExpression(N1, DAG, LegalOperations)); 4079193323Sed } 4080193323Sed } 4081193323Sed 4082193323Sed return SDValue(); 4083193323Sed} 4084193323Sed 4085193323SedSDValue DAGCombiner::visitFREM(SDNode *N) { 4086193323Sed SDValue N0 = N->getOperand(0); 4087193323Sed SDValue N1 = N->getOperand(1); 4088193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4089193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4090193323Sed MVT VT = N->getValueType(0); 4091193323Sed 4092193323Sed // fold (frem c1, c2) -> fmod(c1,c2) 4093193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) 4094193323Sed return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4095193323Sed 4096193323Sed return SDValue(); 4097193323Sed} 4098193323Sed 4099193323SedSDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4100193323Sed SDValue N0 = N->getOperand(0); 4101193323Sed SDValue N1 = N->getOperand(1); 4102193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4103193323Sed ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4104193323Sed MVT VT = N->getValueType(0); 4105193323Sed 4106193323Sed if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4107193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4108193323Sed 4109193323Sed if (N1CFP) { 4110193323Sed const APFloat& V = N1CFP->getValueAPF(); 4111193323Sed // copysign(x, c1) -> fabs(x) iff ispos(c1) 4112193323Sed // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4113193323Sed if (!V.isNegative()) { 4114193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4115193323Sed return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4116193323Sed } else { 4117193323Sed if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4118193323Sed return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4119193323Sed DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4120193323Sed } 4121193323Sed } 4122193323Sed 4123193323Sed // copysign(fabs(x), y) -> copysign(x, y) 4124193323Sed // copysign(fneg(x), y) -> copysign(x, y) 4125193323Sed // copysign(copysign(x,z), y) -> copysign(x, y) 4126193323Sed if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4127193323Sed N0.getOpcode() == ISD::FCOPYSIGN) 4128193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4129193323Sed N0.getOperand(0), N1); 4130193323Sed 4131193323Sed // copysign(x, abs(y)) -> abs(x) 4132193323Sed if (N1.getOpcode() == ISD::FABS) 4133193323Sed return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4134193323Sed 4135193323Sed // copysign(x, copysign(y,z)) -> copysign(x, z) 4136193323Sed if (N1.getOpcode() == ISD::FCOPYSIGN) 4137193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4138193323Sed N0, N1.getOperand(1)); 4139193323Sed 4140193323Sed // copysign(x, fp_extend(y)) -> copysign(x, y) 4141193323Sed // copysign(x, fp_round(y)) -> copysign(x, y) 4142193323Sed if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4143193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4144193323Sed N0, N1.getOperand(0)); 4145193323Sed 4146193323Sed return SDValue(); 4147193323Sed} 4148193323Sed 4149193323SedSDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4150193323Sed SDValue N0 = N->getOperand(0); 4151193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4152193323Sed MVT VT = N->getValueType(0); 4153193323Sed MVT OpVT = N0.getValueType(); 4154193323Sed 4155193323Sed // fold (sint_to_fp c1) -> c1fp 4156193323Sed if (N0C && OpVT != MVT::ppcf128) 4157193323Sed return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4158193323Sed 4159193323Sed // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4160193323Sed // but UINT_TO_FP is legal on this target, try to convert. 4161193323Sed if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4162193323Sed TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4163193323Sed // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4164193323Sed if (DAG.SignBitIsZero(N0)) 4165193323Sed return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4166193323Sed } 4167193323Sed 4168193323Sed return SDValue(); 4169193323Sed} 4170193323Sed 4171193323SedSDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4172193323Sed SDValue N0 = N->getOperand(0); 4173193323Sed ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4174193323Sed MVT VT = N->getValueType(0); 4175193323Sed MVT OpVT = N0.getValueType(); 4176193323Sed 4177193323Sed // fold (uint_to_fp c1) -> c1fp 4178193323Sed if (N0C && OpVT != MVT::ppcf128) 4179193323Sed return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4180193323Sed 4181193323Sed // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4182193323Sed // but SINT_TO_FP is legal on this target, try to convert. 4183193323Sed if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4184193323Sed TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4185193323Sed // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4186193323Sed if (DAG.SignBitIsZero(N0)) 4187193323Sed return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4188193323Sed } 4189193323Sed 4190193323Sed return SDValue(); 4191193323Sed} 4192193323Sed 4193193323SedSDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4194193323Sed SDValue N0 = N->getOperand(0); 4195193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4196193323Sed MVT VT = N->getValueType(0); 4197193323Sed 4198193323Sed // fold (fp_to_sint c1fp) -> c1 4199193323Sed if (N0CFP) 4200193323Sed return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4201193323Sed 4202193323Sed return SDValue(); 4203193323Sed} 4204193323Sed 4205193323SedSDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4206193323Sed SDValue N0 = N->getOperand(0); 4207193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4208193323Sed MVT VT = N->getValueType(0); 4209193323Sed 4210193323Sed // fold (fp_to_uint c1fp) -> c1 4211193323Sed if (N0CFP && VT != MVT::ppcf128) 4212193323Sed return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4213193323Sed 4214193323Sed return SDValue(); 4215193323Sed} 4216193323Sed 4217193323SedSDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4218193323Sed SDValue N0 = N->getOperand(0); 4219193323Sed SDValue N1 = N->getOperand(1); 4220193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4221193323Sed MVT VT = N->getValueType(0); 4222193323Sed 4223193323Sed // fold (fp_round c1fp) -> c1fp 4224193323Sed if (N0CFP && N0.getValueType() != MVT::ppcf128) 4225193323Sed return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4226193323Sed 4227193323Sed // fold (fp_round (fp_extend x)) -> x 4228193323Sed if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4229193323Sed return N0.getOperand(0); 4230193323Sed 4231193323Sed // fold (fp_round (fp_round x)) -> (fp_round x) 4232193323Sed if (N0.getOpcode() == ISD::FP_ROUND) { 4233193323Sed // This is a value preserving truncation if both round's are. 4234193323Sed bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4235193323Sed N0.getNode()->getConstantOperandVal(1) == 1; 4236193323Sed return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4237193323Sed DAG.getIntPtrConstant(IsTrunc)); 4238193323Sed } 4239193323Sed 4240193323Sed // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4241193323Sed if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4242193323Sed SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4243193323Sed N0.getOperand(0), N1); 4244193323Sed AddToWorkList(Tmp.getNode()); 4245193323Sed return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4246193323Sed Tmp, N0.getOperand(1)); 4247193323Sed } 4248193323Sed 4249193323Sed return SDValue(); 4250193323Sed} 4251193323Sed 4252193323SedSDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4253193323Sed SDValue N0 = N->getOperand(0); 4254193323Sed MVT VT = N->getValueType(0); 4255193323Sed MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4256193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4257193323Sed 4258193323Sed // fold (fp_round_inreg c1fp) -> c1fp 4259193323Sed if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4260193323Sed SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4261193323Sed return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4262193323Sed } 4263193323Sed 4264193323Sed return SDValue(); 4265193323Sed} 4266193323Sed 4267193323SedSDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4268193323Sed SDValue N0 = N->getOperand(0); 4269193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4270193323Sed MVT VT = N->getValueType(0); 4271193323Sed 4272193323Sed // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4273193323Sed if (N->hasOneUse() && 4274193323Sed N->use_begin()->getOpcode() == ISD::FP_ROUND) 4275193323Sed return SDValue(); 4276193323Sed 4277193323Sed // fold (fp_extend c1fp) -> c1fp 4278193323Sed if (N0CFP && VT != MVT::ppcf128) 4279193323Sed return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4280193323Sed 4281193323Sed // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4282193323Sed // value of X. 4283193323Sed if (N0.getOpcode() == ISD::FP_ROUND 4284193323Sed && N0.getNode()->getConstantOperandVal(1) == 1) { 4285193323Sed SDValue In = N0.getOperand(0); 4286193323Sed if (In.getValueType() == VT) return In; 4287193323Sed if (VT.bitsLT(In.getValueType())) 4288193323Sed return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4289193323Sed In, N0.getOperand(1)); 4290193323Sed return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4291193323Sed } 4292193323Sed 4293193323Sed // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4294193323Sed if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4295193323Sed ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4296193323Sed TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4297193323Sed LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4298193323Sed SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4299193323Sed LN0->getChain(), 4300193323Sed LN0->getBasePtr(), LN0->getSrcValue(), 4301193323Sed LN0->getSrcValueOffset(), 4302193323Sed N0.getValueType(), 4303193323Sed LN0->isVolatile(), LN0->getAlignment()); 4304193323Sed CombineTo(N, ExtLoad); 4305193323Sed CombineTo(N0.getNode(), 4306193323Sed DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4307193323Sed N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4308193323Sed ExtLoad.getValue(1)); 4309193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 4310193323Sed } 4311193323Sed 4312193323Sed return SDValue(); 4313193323Sed} 4314193323Sed 4315193323SedSDValue DAGCombiner::visitFNEG(SDNode *N) { 4316193323Sed SDValue N0 = N->getOperand(0); 4317193323Sed 4318193323Sed if (isNegatibleForFree(N0, LegalOperations)) 4319193323Sed return GetNegatedExpression(N0, DAG, LegalOperations); 4320193323Sed 4321193323Sed // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4322193323Sed // constant pool values. 4323193323Sed if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4324193323Sed N0.getOperand(0).getValueType().isInteger() && 4325193323Sed !N0.getOperand(0).getValueType().isVector()) { 4326193323Sed SDValue Int = N0.getOperand(0); 4327193323Sed MVT IntVT = Int.getValueType(); 4328193323Sed if (IntVT.isInteger() && !IntVT.isVector()) { 4329193323Sed Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4330193323Sed DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4331193323Sed AddToWorkList(Int.getNode()); 4332193323Sed return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4333193323Sed N->getValueType(0), Int); 4334193323Sed } 4335193323Sed } 4336193323Sed 4337193323Sed return SDValue(); 4338193323Sed} 4339193323Sed 4340193323SedSDValue DAGCombiner::visitFABS(SDNode *N) { 4341193323Sed SDValue N0 = N->getOperand(0); 4342193323Sed ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4343193323Sed MVT VT = N->getValueType(0); 4344193323Sed 4345193323Sed // fold (fabs c1) -> fabs(c1) 4346193323Sed if (N0CFP && VT != MVT::ppcf128) 4347193323Sed return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4348193323Sed // fold (fabs (fabs x)) -> (fabs x) 4349193323Sed if (N0.getOpcode() == ISD::FABS) 4350193323Sed return N->getOperand(0); 4351193323Sed // fold (fabs (fneg x)) -> (fabs x) 4352193323Sed // fold (fabs (fcopysign x, y)) -> (fabs x) 4353193323Sed if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4354193323Sed return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4355193323Sed 4356193323Sed // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4357193323Sed // constant pool values. 4358193323Sed if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4359193323Sed N0.getOperand(0).getValueType().isInteger() && 4360193323Sed !N0.getOperand(0).getValueType().isVector()) { 4361193323Sed SDValue Int = N0.getOperand(0); 4362193323Sed MVT IntVT = Int.getValueType(); 4363193323Sed if (IntVT.isInteger() && !IntVT.isVector()) { 4364193323Sed Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4365193323Sed DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4366193323Sed AddToWorkList(Int.getNode()); 4367193323Sed return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4368193323Sed N->getValueType(0), Int); 4369193323Sed } 4370193323Sed } 4371193323Sed 4372193323Sed return SDValue(); 4373193323Sed} 4374193323Sed 4375193323SedSDValue DAGCombiner::visitBRCOND(SDNode *N) { 4376193323Sed SDValue Chain = N->getOperand(0); 4377193323Sed SDValue N1 = N->getOperand(1); 4378193323Sed SDValue N2 = N->getOperand(2); 4379193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4380193323Sed 4381193323Sed // never taken branch, fold to chain 4382193323Sed if (N1C && N1C->isNullValue()) 4383193323Sed return Chain; 4384193323Sed // unconditional branch 4385193323Sed if (N1C && N1C->getAPIntValue() == 1) 4386193323Sed return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4387193323Sed // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4388193323Sed // on the target. 4389193323Sed if (N1.getOpcode() == ISD::SETCC && 4390193323Sed TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4391193323Sed return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4392193323Sed Chain, N1.getOperand(2), 4393193323Sed N1.getOperand(0), N1.getOperand(1), N2); 4394193323Sed } 4395193323Sed 4396193323Sed if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4397193323Sed // Match this pattern so that we can generate simpler code: 4398193323Sed // 4399193323Sed // %a = ... 4400193323Sed // %b = and i32 %a, 2 4401193323Sed // %c = srl i32 %b, 1 4402193323Sed // brcond i32 %c ... 4403193323Sed // 4404193323Sed // into 4405193323Sed // 4406193323Sed // %a = ... 4407193323Sed // %b = and %a, 2 4408193323Sed // %c = setcc eq %b, 0 4409193323Sed // brcond %c ... 4410193323Sed // 4411193323Sed // This applies only when the AND constant value has one bit set and the 4412193323Sed // SRL constant is equal to the log2 of the AND constant. The back-end is 4413193323Sed // smart enough to convert the result into a TEST/JMP sequence. 4414193323Sed SDValue Op0 = N1.getOperand(0); 4415193323Sed SDValue Op1 = N1.getOperand(1); 4416193323Sed 4417193323Sed if (Op0.getOpcode() == ISD::AND && 4418193323Sed Op0.hasOneUse() && 4419193323Sed Op1.getOpcode() == ISD::Constant) { 4420193323Sed SDValue AndOp0 = Op0.getOperand(0); 4421193323Sed SDValue AndOp1 = Op0.getOperand(1); 4422193323Sed 4423193323Sed if (AndOp1.getOpcode() == ISD::Constant) { 4424193323Sed const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4425193323Sed 4426193323Sed if (AndConst.isPowerOf2() && 4427193323Sed cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4428193323Sed SDValue SetCC = 4429193323Sed DAG.getSetCC(N->getDebugLoc(), 4430193323Sed TLI.getSetCCResultType(Op0.getValueType()), 4431193323Sed Op0, DAG.getConstant(0, Op0.getValueType()), 4432193323Sed ISD::SETNE); 4433193323Sed 4434193323Sed // Replace the uses of SRL with SETCC 4435193323Sed DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4436193323Sed removeFromWorkList(N1.getNode()); 4437193323Sed DAG.DeleteNode(N1.getNode()); 4438193323Sed return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4439193323Sed MVT::Other, Chain, SetCC, N2); 4440193323Sed } 4441193323Sed } 4442193323Sed } 4443193323Sed } 4444193323Sed 4445193323Sed return SDValue(); 4446193323Sed} 4447193323Sed 4448193323Sed// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4449193323Sed// 4450193323SedSDValue DAGCombiner::visitBR_CC(SDNode *N) { 4451193323Sed CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4452193323Sed SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4453193323Sed 4454193323Sed // Use SimplifySetCC to simplify SETCC's. 4455193323Sed SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4456193323Sed CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4457193323Sed false); 4458193323Sed if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4459193323Sed 4460193323Sed ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4461193323Sed 4462193323Sed // fold br_cc true, dest -> br dest (unconditional branch) 4463193323Sed if (SCCC && !SCCC->isNullValue()) 4464193323Sed return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4465193323Sed N->getOperand(0), N->getOperand(4)); 4466193323Sed // fold br_cc false, dest -> unconditional fall through 4467193323Sed if (SCCC && SCCC->isNullValue()) 4468193323Sed return N->getOperand(0); 4469193323Sed 4470193323Sed // fold to a simpler setcc 4471193323Sed if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4472193323Sed return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4473193323Sed N->getOperand(0), Simp.getOperand(2), 4474193323Sed Simp.getOperand(0), Simp.getOperand(1), 4475193323Sed N->getOperand(4)); 4476193323Sed 4477193323Sed return SDValue(); 4478193323Sed} 4479193323Sed 4480193323Sed/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4481193323Sed/// pre-indexed load / store when the base pointer is an add or subtract 4482193323Sed/// and it has other uses besides the load / store. After the 4483193323Sed/// transformation, the new indexed load / store has effectively folded 4484193323Sed/// the add / subtract in and all of its other uses are redirected to the 4485193323Sed/// new load / store. 4486193323Sedbool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4487193323Sed if (!LegalOperations) 4488193323Sed return false; 4489193323Sed 4490193323Sed bool isLoad = true; 4491193323Sed SDValue Ptr; 4492193323Sed MVT VT; 4493193323Sed if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4494193323Sed if (LD->isIndexed()) 4495193323Sed return false; 4496193323Sed VT = LD->getMemoryVT(); 4497193323Sed if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4498193323Sed !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4499193323Sed return false; 4500193323Sed Ptr = LD->getBasePtr(); 4501193323Sed } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4502193323Sed if (ST->isIndexed()) 4503193323Sed return false; 4504193323Sed VT = ST->getMemoryVT(); 4505193323Sed if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4506193323Sed !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4507193323Sed return false; 4508193323Sed Ptr = ST->getBasePtr(); 4509193323Sed isLoad = false; 4510193323Sed } else { 4511193323Sed return false; 4512193323Sed } 4513193323Sed 4514193323Sed // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4515193323Sed // out. There is no reason to make this a preinc/predec. 4516193323Sed if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4517193323Sed Ptr.getNode()->hasOneUse()) 4518193323Sed return false; 4519193323Sed 4520193323Sed // Ask the target to do addressing mode selection. 4521193323Sed SDValue BasePtr; 4522193323Sed SDValue Offset; 4523193323Sed ISD::MemIndexedMode AM = ISD::UNINDEXED; 4524193323Sed if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4525193323Sed return false; 4526193323Sed // Don't create a indexed load / store with zero offset. 4527193323Sed if (isa<ConstantSDNode>(Offset) && 4528193323Sed cast<ConstantSDNode>(Offset)->isNullValue()) 4529193323Sed return false; 4530193323Sed 4531193323Sed // Try turning it into a pre-indexed load / store except when: 4532193323Sed // 1) The new base ptr is a frame index. 4533193323Sed // 2) If N is a store and the new base ptr is either the same as or is a 4534193323Sed // predecessor of the value being stored. 4535193323Sed // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4536193323Sed // that would create a cycle. 4537193323Sed // 4) All uses are load / store ops that use it as old base ptr. 4538193323Sed 4539193323Sed // Check #1. Preinc'ing a frame index would require copying the stack pointer 4540193323Sed // (plus the implicit offset) to a register to preinc anyway. 4541193323Sed if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4542193323Sed return false; 4543193323Sed 4544193323Sed // Check #2. 4545193323Sed if (!isLoad) { 4546193323Sed SDValue Val = cast<StoreSDNode>(N)->getValue(); 4547193323Sed if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4548193323Sed return false; 4549193323Sed } 4550193323Sed 4551193323Sed // Now check for #3 and #4. 4552193323Sed bool RealUse = false; 4553193323Sed for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4554193323Sed E = Ptr.getNode()->use_end(); I != E; ++I) { 4555193323Sed SDNode *Use = *I; 4556193323Sed if (Use == N) 4557193323Sed continue; 4558193323Sed if (Use->isPredecessorOf(N)) 4559193323Sed return false; 4560193323Sed 4561193323Sed if (!((Use->getOpcode() == ISD::LOAD && 4562193323Sed cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4563193323Sed (Use->getOpcode() == ISD::STORE && 4564193323Sed cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4565193323Sed RealUse = true; 4566193323Sed } 4567193323Sed 4568193323Sed if (!RealUse) 4569193323Sed return false; 4570193323Sed 4571193323Sed SDValue Result; 4572193323Sed if (isLoad) 4573193323Sed Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4574193323Sed BasePtr, Offset, AM); 4575193323Sed else 4576193323Sed Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4577193323Sed BasePtr, Offset, AM); 4578193323Sed ++PreIndexedNodes; 4579193323Sed ++NodesCombined; 4580193323Sed DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4581193323Sed DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4582193323Sed DOUT << '\n'; 4583193323Sed WorkListRemover DeadNodes(*this); 4584193323Sed if (isLoad) { 4585193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4586193323Sed &DeadNodes); 4587193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4588193323Sed &DeadNodes); 4589193323Sed } else { 4590193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4591193323Sed &DeadNodes); 4592193323Sed } 4593193323Sed 4594193323Sed // Finally, since the node is now dead, remove it from the graph. 4595193323Sed DAG.DeleteNode(N); 4596193323Sed 4597193323Sed // Replace the uses of Ptr with uses of the updated base value. 4598193323Sed DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4599193323Sed &DeadNodes); 4600193323Sed removeFromWorkList(Ptr.getNode()); 4601193323Sed DAG.DeleteNode(Ptr.getNode()); 4602193323Sed 4603193323Sed return true; 4604193323Sed} 4605193323Sed 4606193323Sed/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4607193323Sed/// add / sub of the base pointer node into a post-indexed load / store. 4608193323Sed/// The transformation folded the add / subtract into the new indexed 4609193323Sed/// load / store effectively and all of its uses are redirected to the 4610193323Sed/// new load / store. 4611193323Sedbool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4612193323Sed if (!LegalOperations) 4613193323Sed return false; 4614193323Sed 4615193323Sed bool isLoad = true; 4616193323Sed SDValue Ptr; 4617193323Sed MVT VT; 4618193323Sed if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4619193323Sed if (LD->isIndexed()) 4620193323Sed return false; 4621193323Sed VT = LD->getMemoryVT(); 4622193323Sed if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4623193323Sed !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4624193323Sed return false; 4625193323Sed Ptr = LD->getBasePtr(); 4626193323Sed } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4627193323Sed if (ST->isIndexed()) 4628193323Sed return false; 4629193323Sed VT = ST->getMemoryVT(); 4630193323Sed if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4631193323Sed !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4632193323Sed return false; 4633193323Sed Ptr = ST->getBasePtr(); 4634193323Sed isLoad = false; 4635193323Sed } else { 4636193323Sed return false; 4637193323Sed } 4638193323Sed 4639193323Sed if (Ptr.getNode()->hasOneUse()) 4640193323Sed return false; 4641193323Sed 4642193323Sed for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4643193323Sed E = Ptr.getNode()->use_end(); I != E; ++I) { 4644193323Sed SDNode *Op = *I; 4645193323Sed if (Op == N || 4646193323Sed (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4647193323Sed continue; 4648193323Sed 4649193323Sed SDValue BasePtr; 4650193323Sed SDValue Offset; 4651193323Sed ISD::MemIndexedMode AM = ISD::UNINDEXED; 4652193323Sed if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4653193323Sed if (Ptr == Offset) 4654193323Sed std::swap(BasePtr, Offset); 4655193323Sed if (Ptr != BasePtr) 4656193323Sed continue; 4657193323Sed // Don't create a indexed load / store with zero offset. 4658193323Sed if (isa<ConstantSDNode>(Offset) && 4659193323Sed cast<ConstantSDNode>(Offset)->isNullValue()) 4660193323Sed continue; 4661193323Sed 4662193323Sed // Try turning it into a post-indexed load / store except when 4663193323Sed // 1) All uses are load / store ops that use it as base ptr. 4664193323Sed // 2) Op must be independent of N, i.e. Op is neither a predecessor 4665193323Sed // nor a successor of N. Otherwise, if Op is folded that would 4666193323Sed // create a cycle. 4667193323Sed 4668193323Sed if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4669193323Sed continue; 4670193323Sed 4671193323Sed // Check for #1. 4672193323Sed bool TryNext = false; 4673193323Sed for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4674193323Sed EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4675193323Sed SDNode *Use = *II; 4676193323Sed if (Use == Ptr.getNode()) 4677193323Sed continue; 4678193323Sed 4679193323Sed // If all the uses are load / store addresses, then don't do the 4680193323Sed // transformation. 4681193323Sed if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4682193323Sed bool RealUse = false; 4683193323Sed for (SDNode::use_iterator III = Use->use_begin(), 4684193323Sed EEE = Use->use_end(); III != EEE; ++III) { 4685193323Sed SDNode *UseUse = *III; 4686193323Sed if (!((UseUse->getOpcode() == ISD::LOAD && 4687193323Sed cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4688193323Sed (UseUse->getOpcode() == ISD::STORE && 4689193323Sed cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4690193323Sed RealUse = true; 4691193323Sed } 4692193323Sed 4693193323Sed if (!RealUse) { 4694193323Sed TryNext = true; 4695193323Sed break; 4696193323Sed } 4697193323Sed } 4698193323Sed } 4699193323Sed 4700193323Sed if (TryNext) 4701193323Sed continue; 4702193323Sed 4703193323Sed // Check for #2 4704193323Sed if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4705193323Sed SDValue Result = isLoad 4706193323Sed ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4707193323Sed BasePtr, Offset, AM) 4708193323Sed : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4709193323Sed BasePtr, Offset, AM); 4710193323Sed ++PostIndexedNodes; 4711193323Sed ++NodesCombined; 4712193323Sed DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4713193323Sed DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4714193323Sed DOUT << '\n'; 4715193323Sed WorkListRemover DeadNodes(*this); 4716193323Sed if (isLoad) { 4717193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4718193323Sed &DeadNodes); 4719193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4720193323Sed &DeadNodes); 4721193323Sed } else { 4722193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4723193323Sed &DeadNodes); 4724193323Sed } 4725193323Sed 4726193323Sed // Finally, since the node is now dead, remove it from the graph. 4727193323Sed DAG.DeleteNode(N); 4728193323Sed 4729193323Sed // Replace the uses of Use with uses of the updated base value. 4730193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4731193323Sed Result.getValue(isLoad ? 1 : 0), 4732193323Sed &DeadNodes); 4733193323Sed removeFromWorkList(Op); 4734193323Sed DAG.DeleteNode(Op); 4735193323Sed return true; 4736193323Sed } 4737193323Sed } 4738193323Sed } 4739193323Sed 4740193323Sed return false; 4741193323Sed} 4742193323Sed 4743193323Sed/// InferAlignment - If we can infer some alignment information from this 4744193323Sed/// pointer, return it. 4745193323Sedstatic unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4746193323Sed // If this is a direct reference to a stack slot, use information about the 4747193323Sed // stack slot's alignment. 4748193323Sed int FrameIdx = 1 << 31; 4749193323Sed int64_t FrameOffset = 0; 4750193323Sed if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4751193323Sed FrameIdx = FI->getIndex(); 4752193323Sed } else if (Ptr.getOpcode() == ISD::ADD && 4753193323Sed isa<ConstantSDNode>(Ptr.getOperand(1)) && 4754193323Sed isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4755193323Sed FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4756193323Sed FrameOffset = Ptr.getConstantOperandVal(1); 4757193323Sed } 4758193323Sed 4759193323Sed if (FrameIdx != (1 << 31)) { 4760193323Sed // FIXME: Handle FI+CST. 4761193323Sed const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4762193323Sed if (MFI.isFixedObjectIndex(FrameIdx)) { 4763193323Sed int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4764193323Sed 4765193323Sed // The alignment of the frame index can be determined from its offset from 4766193323Sed // the incoming frame position. If the frame object is at offset 32 and 4767193323Sed // the stack is guaranteed to be 16-byte aligned, then we know that the 4768193323Sed // object is 16-byte aligned. 4769193323Sed unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4770193323Sed unsigned Align = MinAlign(ObjectOffset, StackAlign); 4771193323Sed 4772193323Sed // Finally, the frame object itself may have a known alignment. Factor 4773193323Sed // the alignment + offset into a new alignment. For example, if we know 4774193323Sed // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4775193323Sed // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4776193323Sed // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4777193323Sed unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4778193323Sed FrameOffset); 4779193323Sed return std::max(Align, FIInfoAlign); 4780193323Sed } 4781193323Sed } 4782193323Sed 4783193323Sed return 0; 4784193323Sed} 4785193323Sed 4786193323SedSDValue DAGCombiner::visitLOAD(SDNode *N) { 4787193323Sed LoadSDNode *LD = cast<LoadSDNode>(N); 4788193323Sed SDValue Chain = LD->getChain(); 4789193323Sed SDValue Ptr = LD->getBasePtr(); 4790193323Sed 4791193323Sed // Try to infer better alignment information than the load already has. 4792193323Sed if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4793193323Sed if (unsigned Align = InferAlignment(Ptr, DAG)) { 4794193323Sed if (Align > LD->getAlignment()) 4795193323Sed return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4796193323Sed LD->getValueType(0), 4797193323Sed Chain, Ptr, LD->getSrcValue(), 4798193323Sed LD->getSrcValueOffset(), LD->getMemoryVT(), 4799193323Sed LD->isVolatile(), Align); 4800193323Sed } 4801193323Sed } 4802193323Sed 4803193323Sed // If load is not volatile and there are no uses of the loaded value (and 4804193323Sed // the updated indexed value in case of indexed loads), change uses of the 4805193323Sed // chain value into uses of the chain input (i.e. delete the dead load). 4806193323Sed if (!LD->isVolatile()) { 4807193323Sed if (N->getValueType(1) == MVT::Other) { 4808193323Sed // Unindexed loads. 4809193323Sed if (N->hasNUsesOfValue(0, 0)) { 4810193323Sed // It's not safe to use the two value CombineTo variant here. e.g. 4811193323Sed // v1, chain2 = load chain1, loc 4812193323Sed // v2, chain3 = load chain2, loc 4813193323Sed // v3 = add v2, c 4814193323Sed // Now we replace use of chain2 with chain1. This makes the second load 4815193323Sed // isomorphic to the one we are deleting, and thus makes this load live. 4816193323Sed DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4817193323Sed DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4818193323Sed DOUT << "\n"; 4819193323Sed WorkListRemover DeadNodes(*this); 4820193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4821193323Sed 4822193323Sed if (N->use_empty()) { 4823193323Sed removeFromWorkList(N); 4824193323Sed DAG.DeleteNode(N); 4825193323Sed } 4826193323Sed 4827193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 4828193323Sed } 4829193323Sed } else { 4830193323Sed // Indexed loads. 4831193323Sed assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4832193323Sed if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4833193323Sed SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4834193323Sed DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4835193323Sed DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4836193323Sed DOUT << " and 2 other values\n"; 4837193323Sed WorkListRemover DeadNodes(*this); 4838193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4839193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4840193323Sed DAG.getUNDEF(N->getValueType(1)), 4841193323Sed &DeadNodes); 4842193323Sed DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4843193323Sed removeFromWorkList(N); 4844193323Sed DAG.DeleteNode(N); 4845193323Sed return SDValue(N, 0); // Return N so it doesn't get rechecked! 4846193323Sed } 4847193323Sed } 4848193323Sed } 4849193323Sed 4850193323Sed // If this load is directly stored, replace the load value with the stored 4851193323Sed // value. 4852193323Sed // TODO: Handle store large -> read small portion. 4853193323Sed // TODO: Handle TRUNCSTORE/LOADEXT 4854193323Sed if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4855193323Sed !LD->isVolatile()) { 4856193323Sed if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4857193323Sed StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4858193323Sed if (PrevST->getBasePtr() == Ptr && 4859193323Sed PrevST->getValue().getValueType() == N->getValueType(0)) 4860193323Sed return CombineTo(N, Chain.getOperand(1), Chain); 4861193323Sed } 4862193323Sed } 4863193323Sed 4864193323Sed if (CombinerAA) { 4865193323Sed // Walk up chain skipping non-aliasing memory nodes. 4866193323Sed SDValue BetterChain = FindBetterChain(N, Chain); 4867193323Sed 4868193323Sed // If there is a better chain. 4869193323Sed if (Chain != BetterChain) { 4870193323Sed SDValue ReplLoad; 4871193323Sed 4872193323Sed // Replace the chain to void dependency. 4873193323Sed if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4874193323Sed ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4875193323Sed BetterChain, Ptr, 4876193323Sed LD->getSrcValue(), LD->getSrcValueOffset(), 4877193323Sed LD->isVolatile(), LD->getAlignment()); 4878193323Sed } else { 4879193323Sed ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4880193323Sed LD->getValueType(0), 4881193323Sed BetterChain, Ptr, LD->getSrcValue(), 4882193323Sed LD->getSrcValueOffset(), 4883193323Sed LD->getMemoryVT(), 4884193323Sed LD->isVolatile(), 4885193323Sed LD->getAlignment()); 4886193323Sed } 4887193323Sed 4888193323Sed // Create token factor to keep old chain connected. 4889193323Sed SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4890193323Sed MVT::Other, Chain, ReplLoad.getValue(1)); 4891193323Sed 4892193323Sed // Replace uses with load result and token factor. Don't add users 4893193323Sed // to work list. 4894193323Sed return CombineTo(N, ReplLoad.getValue(0), Token, false); 4895193323Sed } 4896193323Sed } 4897193323Sed 4898193323Sed // Try transforming N to an indexed load. 4899193323Sed if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4900193323Sed return SDValue(N, 0); 4901193323Sed 4902193323Sed return SDValue(); 4903193323Sed} 4904193323Sed 4905193323Sed 4906193323Sed/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4907193323Sed/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4908193323Sed/// of the loaded bits, try narrowing the load and store if it would end up 4909193323Sed/// being a win for performance or code size. 4910193323SedSDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4911193323Sed StoreSDNode *ST = cast<StoreSDNode>(N); 4912193323Sed if (ST->isVolatile()) 4913193323Sed return SDValue(); 4914193323Sed 4915193323Sed SDValue Chain = ST->getChain(); 4916193323Sed SDValue Value = ST->getValue(); 4917193323Sed SDValue Ptr = ST->getBasePtr(); 4918193323Sed MVT VT = Value.getValueType(); 4919193323Sed 4920193323Sed if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 4921193323Sed return SDValue(); 4922193323Sed 4923193323Sed unsigned Opc = Value.getOpcode(); 4924193323Sed if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 4925193323Sed Value.getOperand(1).getOpcode() != ISD::Constant) 4926193323Sed return SDValue(); 4927193323Sed 4928193323Sed SDValue N0 = Value.getOperand(0); 4929193323Sed if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 4930193323Sed LoadSDNode *LD = cast<LoadSDNode>(N0); 4931193323Sed if (LD->getBasePtr() != Ptr) 4932193323Sed return SDValue(); 4933193323Sed 4934193323Sed // Find the type to narrow it the load / op / store to. 4935193323Sed SDValue N1 = Value.getOperand(1); 4936193323Sed unsigned BitWidth = N1.getValueSizeInBits(); 4937193323Sed APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 4938193323Sed if (Opc == ISD::AND) 4939193323Sed Imm ^= APInt::getAllOnesValue(BitWidth); 4940193323Sed if (Imm == 0 || Imm.isAllOnesValue()) 4941193323Sed return SDValue(); 4942193323Sed unsigned ShAmt = Imm.countTrailingZeros(); 4943193323Sed unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 4944193323Sed unsigned NewBW = NextPowerOf2(MSB - ShAmt); 4945193323Sed MVT NewVT = MVT::getIntegerVT(NewBW); 4946193323Sed while (NewBW < BitWidth && 4947193323Sed !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 4948193323Sed TLI.isNarrowingProfitable(VT, NewVT))) { 4949193323Sed NewBW = NextPowerOf2(NewBW); 4950193323Sed NewVT = MVT::getIntegerVT(NewBW); 4951193323Sed } 4952193323Sed if (NewBW >= BitWidth) 4953193323Sed return SDValue(); 4954193323Sed 4955193323Sed // If the lsb changed does not start at the type bitwidth boundary, 4956193323Sed // start at the previous one. 4957193323Sed if (ShAmt % NewBW) 4958193323Sed ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 4959193323Sed APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 4960193323Sed if ((Imm & Mask) == Imm) { 4961193323Sed APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 4962193323Sed if (Opc == ISD::AND) 4963193323Sed NewImm ^= APInt::getAllOnesValue(NewBW); 4964193323Sed uint64_t PtrOff = ShAmt / 8; 4965193323Sed // For big endian targets, we need to adjust the offset to the pointer to 4966193323Sed // load the correct bytes. 4967193323Sed if (TLI.isBigEndian()) 4968193323Sed PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 4969193323Sed 4970193323Sed unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 4971193323Sed if (NewAlign < 4972193323Sed TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT())) 4973193323Sed return SDValue(); 4974193323Sed 4975193323Sed SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 4976193323Sed Ptr.getValueType(), Ptr, 4977193323Sed DAG.getConstant(PtrOff, Ptr.getValueType())); 4978193323Sed SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 4979193323Sed LD->getChain(), NewPtr, 4980193323Sed LD->getSrcValue(), LD->getSrcValueOffset(), 4981193323Sed LD->isVolatile(), NewAlign); 4982193323Sed SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 4983193323Sed DAG.getConstant(NewImm, NewVT)); 4984193323Sed SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 4985193323Sed NewVal, NewPtr, 4986193323Sed ST->getSrcValue(), ST->getSrcValueOffset(), 4987193323Sed false, NewAlign); 4988193323Sed 4989193323Sed AddToWorkList(NewPtr.getNode()); 4990193323Sed AddToWorkList(NewLD.getNode()); 4991193323Sed AddToWorkList(NewVal.getNode()); 4992193323Sed WorkListRemover DeadNodes(*this); 4993193323Sed DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 4994193323Sed &DeadNodes); 4995193323Sed ++OpsNarrowed; 4996193323Sed return NewST; 4997193323Sed } 4998193323Sed } 4999193323Sed 5000193323Sed return SDValue(); 5001193323Sed} 5002193323Sed 5003193323SedSDValue DAGCombiner::visitSTORE(SDNode *N) { 5004193323Sed StoreSDNode *ST = cast<StoreSDNode>(N); 5005193323Sed SDValue Chain = ST->getChain(); 5006193323Sed SDValue Value = ST->getValue(); 5007193323Sed SDValue Ptr = ST->getBasePtr(); 5008193323Sed 5009193323Sed // Try to infer better alignment information than the store already has. 5010193323Sed if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5011193323Sed if (unsigned Align = InferAlignment(Ptr, DAG)) { 5012193323Sed if (Align > ST->getAlignment()) 5013193323Sed return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5014193323Sed Ptr, ST->getSrcValue(), 5015193323Sed ST->getSrcValueOffset(), ST->getMemoryVT(), 5016193323Sed ST->isVolatile(), Align); 5017193323Sed } 5018193323Sed } 5019193323Sed 5020193323Sed // If this is a store of a bit convert, store the input value if the 5021193323Sed // resultant store does not need a higher alignment than the original. 5022193323Sed if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5023193323Sed ST->isUnindexed()) { 5024193323Sed unsigned OrigAlign = ST->getAlignment(); 5025193323Sed MVT SVT = Value.getOperand(0).getValueType(); 5026193323Sed unsigned Align = TLI.getTargetData()-> 5027193323Sed getABITypeAlignment(SVT.getTypeForMVT()); 5028193323Sed if (Align <= OrigAlign && 5029193323Sed ((!LegalOperations && !ST->isVolatile()) || 5030193323Sed TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5031193323Sed return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5032193323Sed Ptr, ST->getSrcValue(), 5033193323Sed ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5034193323Sed } 5035193323Sed 5036193323Sed // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5037193323Sed if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5038193323Sed // NOTE: If the original store is volatile, this transform must not increase 5039193323Sed // the number of stores. For example, on x86-32 an f64 can be stored in one 5040193323Sed // processor operation but an i64 (which is not legal) requires two. So the 5041193323Sed // transform should not be done in this case. 5042193323Sed if (Value.getOpcode() != ISD::TargetConstantFP) { 5043193323Sed SDValue Tmp; 5044193323Sed switch (CFP->getValueType(0).getSimpleVT()) { 5045193323Sed default: assert(0 && "Unknown FP type"); 5046193323Sed case MVT::f80: // We don't do this for these yet. 5047193323Sed case MVT::f128: 5048193323Sed case MVT::ppcf128: 5049193323Sed break; 5050193323Sed case MVT::f32: 5051193323Sed if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5052193323Sed !ST->isVolatile()) || 5053193323Sed TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5054193323Sed Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5055193323Sed bitcastToAPInt().getZExtValue(), MVT::i32); 5056193323Sed return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5057193323Sed Ptr, ST->getSrcValue(), 5058193323Sed ST->getSrcValueOffset(), ST->isVolatile(), 5059193323Sed ST->getAlignment()); 5060193323Sed } 5061193323Sed break; 5062193323Sed case MVT::f64: 5063193323Sed if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5064193323Sed !ST->isVolatile()) || 5065193323Sed TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5066193323Sed Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5067193323Sed getZExtValue(), MVT::i64); 5068193323Sed return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5069193323Sed Ptr, ST->getSrcValue(), 5070193323Sed ST->getSrcValueOffset(), ST->isVolatile(), 5071193323Sed ST->getAlignment()); 5072193323Sed } else if (!ST->isVolatile() && 5073193323Sed TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5074193323Sed // Many FP stores are not made apparent until after legalize, e.g. for 5075193323Sed // argument passing. Since this is so common, custom legalize the 5076193323Sed // 64-bit integer store into two 32-bit stores. 5077193323Sed uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5078193323Sed SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5079193323Sed SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5080193323Sed if (TLI.isBigEndian()) std::swap(Lo, Hi); 5081193323Sed 5082193323Sed int SVOffset = ST->getSrcValueOffset(); 5083193323Sed unsigned Alignment = ST->getAlignment(); 5084193323Sed bool isVolatile = ST->isVolatile(); 5085193323Sed 5086193323Sed SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5087193323Sed Ptr, ST->getSrcValue(), 5088193323Sed ST->getSrcValueOffset(), 5089193323Sed isVolatile, ST->getAlignment()); 5090193323Sed Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5091193323Sed DAG.getConstant(4, Ptr.getValueType())); 5092193323Sed SVOffset += 4; 5093193323Sed Alignment = MinAlign(Alignment, 4U); 5094193323Sed SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5095193323Sed Ptr, ST->getSrcValue(), 5096193323Sed SVOffset, isVolatile, Alignment); 5097193323Sed return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5098193323Sed St0, St1); 5099193323Sed } 5100193323Sed 5101193323Sed break; 5102193323Sed } 5103193323Sed } 5104193323Sed } 5105193323Sed 5106193323Sed if (CombinerAA) { 5107193323Sed // Walk up chain skipping non-aliasing memory nodes. 5108193323Sed SDValue BetterChain = FindBetterChain(N, Chain); 5109193323Sed 5110193323Sed // If there is a better chain. 5111193323Sed if (Chain != BetterChain) { 5112193323Sed // Replace the chain to avoid dependency. 5113193323Sed SDValue ReplStore; 5114193323Sed if (ST->isTruncatingStore()) { 5115193323Sed ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5116193323Sed ST->getSrcValue(),ST->getSrcValueOffset(), 5117193323Sed ST->getMemoryVT(), 5118193323Sed ST->isVolatile(), ST->getAlignment()); 5119193323Sed } else { 5120193323Sed ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5121193323Sed ST->getSrcValue(), ST->getSrcValueOffset(), 5122193323Sed ST->isVolatile(), ST->getAlignment()); 5123193323Sed } 5124193323Sed 5125193323Sed // Create token to keep both nodes around. 5126193323Sed SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5127193323Sed MVT::Other, Chain, ReplStore); 5128193323Sed 5129193323Sed // Don't add users to work list. 5130193323Sed return CombineTo(N, Token, false); 5131193323Sed } 5132193323Sed } 5133193323Sed 5134193323Sed // Try transforming N to an indexed store. 5135193323Sed if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5136193323Sed return SDValue(N, 0); 5137193323Sed 5138193323Sed // FIXME: is there such a thing as a truncating indexed store? 5139193323Sed if (ST->isTruncatingStore() && ST->isUnindexed() && 5140193323Sed Value.getValueType().isInteger()) { 5141193323Sed // See if we can simplify the input to this truncstore with knowledge that 5142193323Sed // only the low bits are being used. For example: 5143193323Sed // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5144193323Sed SDValue Shorter = 5145193323Sed GetDemandedBits(Value, 5146193323Sed APInt::getLowBitsSet(Value.getValueSizeInBits(), 5147193323Sed ST->getMemoryVT().getSizeInBits())); 5148193323Sed AddToWorkList(Value.getNode()); 5149193323Sed if (Shorter.getNode()) 5150193323Sed return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5151193323Sed Ptr, ST->getSrcValue(), 5152193323Sed ST->getSrcValueOffset(), ST->getMemoryVT(), 5153193323Sed ST->isVolatile(), ST->getAlignment()); 5154193323Sed 5155193323Sed // Otherwise, see if we can simplify the operation with 5156193323Sed // SimplifyDemandedBits, which only works if the value has a single use. 5157193323Sed if (SimplifyDemandedBits(Value, 5158193323Sed APInt::getLowBitsSet( 5159193323Sed Value.getValueSizeInBits(), 5160193323Sed ST->getMemoryVT().getSizeInBits()))) 5161193323Sed return SDValue(N, 0); 5162193323Sed } 5163193323Sed 5164193323Sed // If this is a load followed by a store to the same location, then the store 5165193323Sed // is dead/noop. 5166193323Sed if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5167193323Sed if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5168193323Sed ST->isUnindexed() && !ST->isVolatile() && 5169193323Sed // There can't be any side effects between the load and store, such as 5170193323Sed // a call or store. 5171193323Sed Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5172193323Sed // The store is dead, remove it. 5173193323Sed return Chain; 5174193323Sed } 5175193323Sed } 5176193323Sed 5177193323Sed // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5178193323Sed // truncating store. We can do this even if this is already a truncstore. 5179193323Sed if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5180193323Sed && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5181193323Sed TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5182193323Sed ST->getMemoryVT())) { 5183193323Sed return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5184193323Sed Ptr, ST->getSrcValue(), 5185193323Sed ST->getSrcValueOffset(), ST->getMemoryVT(), 5186193323Sed ST->isVolatile(), ST->getAlignment()); 5187193323Sed } 5188193323Sed 5189193323Sed return ReduceLoadOpStoreWidth(N); 5190193323Sed} 5191193323Sed 5192193323SedSDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5193193323Sed SDValue InVec = N->getOperand(0); 5194193323Sed SDValue InVal = N->getOperand(1); 5195193323Sed SDValue EltNo = N->getOperand(2); 5196193323Sed 5197193323Sed // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5198193323Sed // vector with the inserted element. 5199193323Sed if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5200193323Sed unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5201193323Sed SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5202193323Sed InVec.getNode()->op_end()); 5203193323Sed if (Elt < Ops.size()) 5204193323Sed Ops[Elt] = InVal; 5205193323Sed return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5206193323Sed InVec.getValueType(), &Ops[0], Ops.size()); 5207193323Sed } 5208193323Sed // If the invec is an UNDEF and if EltNo is a constant, create a new 5209193323Sed // BUILD_VECTOR with undef elements and the inserted element. 5210193323Sed if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5211193323Sed isa<ConstantSDNode>(EltNo)) { 5212193323Sed MVT VT = InVec.getValueType(); 5213193323Sed MVT EVT = VT.getVectorElementType(); 5214193323Sed unsigned NElts = VT.getVectorNumElements(); 5215193323Sed SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT)); 5216193323Sed 5217193323Sed unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5218193323Sed if (Elt < Ops.size()) 5219193323Sed Ops[Elt] = InVal; 5220193323Sed return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5221193323Sed InVec.getValueType(), &Ops[0], Ops.size()); 5222193323Sed } 5223193323Sed return SDValue(); 5224193323Sed} 5225193323Sed 5226193323SedSDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5227193323Sed // (vextract (scalar_to_vector val, 0) -> val 5228193323Sed SDValue InVec = N->getOperand(0); 5229193323Sed 5230193323Sed if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5231193323Sed // If the operand is wider than the vector element type then it is implicitly 5232193323Sed // truncated. Make that explicit here. 5233193323Sed MVT EltVT = InVec.getValueType().getVectorElementType(); 5234193323Sed SDValue InOp = InVec.getOperand(0); 5235193323Sed if (InOp.getValueType() != EltVT) 5236193323Sed return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5237193323Sed return InOp; 5238193323Sed } 5239193323Sed 5240193323Sed // Perform only after legalization to ensure build_vector / vector_shuffle 5241193323Sed // optimizations have already been done. 5242193323Sed if (!LegalOperations) return SDValue(); 5243193323Sed 5244193323Sed // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5245193323Sed // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5246193323Sed // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5247193323Sed SDValue EltNo = N->getOperand(1); 5248193323Sed 5249193323Sed if (isa<ConstantSDNode>(EltNo)) { 5250193323Sed unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5251193323Sed bool NewLoad = false; 5252193323Sed bool BCNumEltsChanged = false; 5253193323Sed MVT VT = InVec.getValueType(); 5254193323Sed MVT EVT = VT.getVectorElementType(); 5255193323Sed MVT LVT = EVT; 5256193323Sed 5257193323Sed if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5258193323Sed MVT BCVT = InVec.getOperand(0).getValueType(); 5259193323Sed if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5260193323Sed return SDValue(); 5261193323Sed if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5262193323Sed BCNumEltsChanged = true; 5263193323Sed InVec = InVec.getOperand(0); 5264193323Sed EVT = BCVT.getVectorElementType(); 5265193323Sed NewLoad = true; 5266193323Sed } 5267193323Sed 5268193323Sed LoadSDNode *LN0 = NULL; 5269193323Sed const ShuffleVectorSDNode *SVN = NULL; 5270193323Sed if (ISD::isNormalLoad(InVec.getNode())) { 5271193323Sed LN0 = cast<LoadSDNode>(InVec); 5272193323Sed } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5273193323Sed InVec.getOperand(0).getValueType() == EVT && 5274193323Sed ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5275193323Sed LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5276193323Sed } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5277193323Sed // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5278193323Sed // => 5279193323Sed // (load $addr+1*size) 5280193323Sed 5281193323Sed // If the bit convert changed the number of elements, it is unsafe 5282193323Sed // to examine the mask. 5283193323Sed if (BCNumEltsChanged) 5284193323Sed return SDValue(); 5285193323Sed 5286193323Sed // Select the input vector, guarding against out of range extract vector. 5287193323Sed unsigned NumElems = VT.getVectorNumElements(); 5288193323Sed int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5289193323Sed InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5290193323Sed 5291193323Sed if (InVec.getOpcode() == ISD::BIT_CONVERT) 5292193323Sed InVec = InVec.getOperand(0); 5293193323Sed if (ISD::isNormalLoad(InVec.getNode())) { 5294193323Sed LN0 = cast<LoadSDNode>(InVec); 5295193323Sed Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5296193323Sed } 5297193323Sed } 5298193323Sed 5299193323Sed if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5300193323Sed return SDValue(); 5301193323Sed 5302193323Sed unsigned Align = LN0->getAlignment(); 5303193323Sed if (NewLoad) { 5304193323Sed // Check the resultant load doesn't need a higher alignment than the 5305193323Sed // original load. 5306193323Sed unsigned NewAlign = 5307193323Sed TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); 5308193323Sed 5309193323Sed if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5310193323Sed return SDValue(); 5311193323Sed 5312193323Sed Align = NewAlign; 5313193323Sed } 5314193323Sed 5315193323Sed SDValue NewPtr = LN0->getBasePtr(); 5316193323Sed if (Elt) { 5317193323Sed unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5318193323Sed MVT PtrType = NewPtr.getValueType(); 5319193323Sed if (TLI.isBigEndian()) 5320193323Sed PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5321193323Sed NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5322193323Sed DAG.getConstant(PtrOff, PtrType)); 5323193323Sed } 5324193323Sed 5325193323Sed return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5326193323Sed LN0->getSrcValue(), LN0->getSrcValueOffset(), 5327193323Sed LN0->isVolatile(), Align); 5328193323Sed } 5329193323Sed 5330193323Sed return SDValue(); 5331193323Sed} 5332193323Sed 5333193323SedSDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5334193323Sed unsigned NumInScalars = N->getNumOperands(); 5335193323Sed MVT VT = N->getValueType(0); 5336193323Sed MVT EltType = VT.getVectorElementType(); 5337193323Sed 5338193323Sed // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5339193323Sed // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5340193323Sed // at most two distinct vectors, turn this into a shuffle node. 5341193323Sed SDValue VecIn1, VecIn2; 5342193323Sed for (unsigned i = 0; i != NumInScalars; ++i) { 5343193323Sed // Ignore undef inputs. 5344193323Sed if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5345193323Sed 5346193323Sed // If this input is something other than a EXTRACT_VECTOR_ELT with a 5347193323Sed // constant index, bail out. 5348193323Sed if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5349193323Sed !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5350193323Sed VecIn1 = VecIn2 = SDValue(0, 0); 5351193323Sed break; 5352193323Sed } 5353193323Sed 5354193323Sed // If the input vector type disagrees with the result of the build_vector, 5355193323Sed // we can't make a shuffle. 5356193323Sed SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5357193323Sed if (ExtractedFromVec.getValueType() != VT) { 5358193323Sed VecIn1 = VecIn2 = SDValue(0, 0); 5359193323Sed break; 5360193323Sed } 5361193323Sed 5362193323Sed // Otherwise, remember this. We allow up to two distinct input vectors. 5363193323Sed if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5364193323Sed continue; 5365193323Sed 5366193323Sed if (VecIn1.getNode() == 0) { 5367193323Sed VecIn1 = ExtractedFromVec; 5368193323Sed } else if (VecIn2.getNode() == 0) { 5369193323Sed VecIn2 = ExtractedFromVec; 5370193323Sed } else { 5371193323Sed // Too many inputs. 5372193323Sed VecIn1 = VecIn2 = SDValue(0, 0); 5373193323Sed break; 5374193323Sed } 5375193323Sed } 5376193323Sed 5377193323Sed // If everything is good, we can make a shuffle operation. 5378193323Sed if (VecIn1.getNode()) { 5379193323Sed SmallVector<int, 8> Mask; 5380193323Sed for (unsigned i = 0; i != NumInScalars; ++i) { 5381193323Sed if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5382193323Sed Mask.push_back(-1); 5383193323Sed continue; 5384193323Sed } 5385193323Sed 5386193323Sed // If extracting from the first vector, just use the index directly. 5387193323Sed SDValue Extract = N->getOperand(i); 5388193323Sed SDValue ExtVal = Extract.getOperand(1); 5389193323Sed if (Extract.getOperand(0) == VecIn1) { 5390193323Sed unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5391193323Sed if (ExtIndex > VT.getVectorNumElements()) 5392193323Sed return SDValue(); 5393193323Sed 5394193323Sed Mask.push_back(ExtIndex); 5395193323Sed continue; 5396193323Sed } 5397193323Sed 5398193323Sed // Otherwise, use InIdx + VecSize 5399193323Sed unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5400193323Sed Mask.push_back(Idx+NumInScalars); 5401193323Sed } 5402193323Sed 5403193323Sed // Add count and size info. 5404193323Sed if (!TLI.isTypeLegal(VT) && LegalTypes) 5405193323Sed return SDValue(); 5406193323Sed 5407193323Sed // Return the new VECTOR_SHUFFLE node. 5408193323Sed SDValue Ops[2]; 5409193323Sed Ops[0] = VecIn1; 5410193323Sed Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5411193323Sed return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5412193323Sed } 5413193323Sed 5414193323Sed return SDValue(); 5415193323Sed} 5416193323Sed 5417193323SedSDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5418193323Sed // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5419193323Sed // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5420193323Sed // inputs come from at most two distinct vectors, turn this into a shuffle 5421193323Sed // node. 5422193323Sed 5423193323Sed // If we only have one input vector, we don't need to do any concatenation. 5424193323Sed if (N->getNumOperands() == 1) 5425193323Sed return N->getOperand(0); 5426193323Sed 5427193323Sed return SDValue(); 5428193323Sed} 5429193323Sed 5430193323SedSDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5431193323Sed return SDValue(); 5432193323Sed 5433193323Sed MVT VT = N->getValueType(0); 5434193323Sed unsigned NumElts = VT.getVectorNumElements(); 5435193323Sed 5436193323Sed SDValue N0 = N->getOperand(0); 5437193323Sed SDValue N1 = N->getOperand(1); 5438193323Sed 5439193323Sed assert(N0.getValueType().getVectorNumElements() == NumElts && 5440193323Sed "Vector shuffle must be normalized in DAG"); 5441193323Sed 5442193323Sed // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5443193323Sed 5444193323Sed // If it is a splat, check if the argument vector is a build_vector with 5445193323Sed // all scalar elements the same. 5446193323Sed if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5447193323Sed SDNode *V = N0.getNode(); 5448193323Sed 5449193323Sed 5450193323Sed // If this is a bit convert that changes the element type of the vector but 5451193323Sed // not the number of vector elements, look through it. Be careful not to 5452193323Sed // look though conversions that change things like v4f32 to v2f64. 5453193323Sed if (V->getOpcode() == ISD::BIT_CONVERT) { 5454193323Sed SDValue ConvInput = V->getOperand(0); 5455193323Sed if (ConvInput.getValueType().isVector() && 5456193323Sed ConvInput.getValueType().getVectorNumElements() == NumElts) 5457193323Sed V = ConvInput.getNode(); 5458193323Sed } 5459193323Sed 5460193323Sed if (V->getOpcode() == ISD::BUILD_VECTOR) { 5461193323Sed unsigned NumElems = V->getNumOperands(); 5462193323Sed unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5463193323Sed if (NumElems > BaseIdx) { 5464193323Sed SDValue Base; 5465193323Sed bool AllSame = true; 5466193323Sed for (unsigned i = 0; i != NumElems; ++i) { 5467193323Sed if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5468193323Sed Base = V->getOperand(i); 5469193323Sed break; 5470193323Sed } 5471193323Sed } 5472193323Sed // Splat of <u, u, u, u>, return <u, u, u, u> 5473193323Sed if (!Base.getNode()) 5474193323Sed return N0; 5475193323Sed for (unsigned i = 0; i != NumElems; ++i) { 5476193323Sed if (V->getOperand(i) != Base) { 5477193323Sed AllSame = false; 5478193323Sed break; 5479193323Sed } 5480193323Sed } 5481193323Sed // Splat of <x, x, x, x>, return <x, x, x, x> 5482193323Sed if (AllSame) 5483193323Sed return N0; 5484193323Sed } 5485193323Sed } 5486193323Sed } 5487193323Sed return SDValue(); 5488193323Sed} 5489193323Sed 5490193323Sed/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5491193323Sed/// an AND to a vector_shuffle with the destination vector and a zero vector. 5492193323Sed/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5493193323Sed/// vector_shuffle V, Zero, <0, 4, 2, 4> 5494193323SedSDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5495193323Sed MVT VT = N->getValueType(0); 5496193323Sed DebugLoc dl = N->getDebugLoc(); 5497193323Sed SDValue LHS = N->getOperand(0); 5498193323Sed SDValue RHS = N->getOperand(1); 5499193323Sed if (N->getOpcode() == ISD::AND) { 5500193323Sed if (RHS.getOpcode() == ISD::BIT_CONVERT) 5501193323Sed RHS = RHS.getOperand(0); 5502193323Sed if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5503193323Sed SmallVector<int, 8> Indices; 5504193323Sed unsigned NumElts = RHS.getNumOperands(); 5505193323Sed for (unsigned i = 0; i != NumElts; ++i) { 5506193323Sed SDValue Elt = RHS.getOperand(i); 5507193323Sed if (!isa<ConstantSDNode>(Elt)) 5508193323Sed return SDValue(); 5509193323Sed else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5510193323Sed Indices.push_back(i); 5511193323Sed else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5512193323Sed Indices.push_back(NumElts); 5513193323Sed else 5514193323Sed return SDValue(); 5515193323Sed } 5516193323Sed 5517193323Sed // Let's see if the target supports this vector_shuffle. 5518193323Sed MVT RVT = RHS.getValueType(); 5519193323Sed if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5520193323Sed return SDValue(); 5521193323Sed 5522193323Sed // Return the new VECTOR_SHUFFLE node. 5523193323Sed MVT EVT = RVT.getVectorElementType(); 5524193323Sed SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5525193323Sed DAG.getConstant(0, EVT)); 5526193323Sed SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5527193323Sed RVT, &ZeroOps[0], ZeroOps.size()); 5528193323Sed LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5529193323Sed SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5530193323Sed return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5531193323Sed } 5532193323Sed } 5533193323Sed 5534193323Sed return SDValue(); 5535193323Sed} 5536193323Sed 5537193323Sed/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5538193323SedSDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5539193323Sed // After legalize, the target may be depending on adds and other 5540193323Sed // binary ops to provide legal ways to construct constants or other 5541193323Sed // things. Simplifying them may result in a loss of legality. 5542193323Sed if (LegalOperations) return SDValue(); 5543193323Sed 5544193323Sed MVT VT = N->getValueType(0); 5545193323Sed assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5546193323Sed 5547193323Sed MVT EltType = VT.getVectorElementType(); 5548193323Sed SDValue LHS = N->getOperand(0); 5549193323Sed SDValue RHS = N->getOperand(1); 5550193323Sed SDValue Shuffle = XformToShuffleWithZero(N); 5551193323Sed if (Shuffle.getNode()) return Shuffle; 5552193323Sed 5553193323Sed // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5554193323Sed // this operation. 5555193323Sed if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5556193323Sed RHS.getOpcode() == ISD::BUILD_VECTOR) { 5557193323Sed SmallVector<SDValue, 8> Ops; 5558193323Sed for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5559193323Sed SDValue LHSOp = LHS.getOperand(i); 5560193323Sed SDValue RHSOp = RHS.getOperand(i); 5561193323Sed // If these two elements can't be folded, bail out. 5562193323Sed if ((LHSOp.getOpcode() != ISD::UNDEF && 5563193323Sed LHSOp.getOpcode() != ISD::Constant && 5564193323Sed LHSOp.getOpcode() != ISD::ConstantFP) || 5565193323Sed (RHSOp.getOpcode() != ISD::UNDEF && 5566193323Sed RHSOp.getOpcode() != ISD::Constant && 5567193323Sed RHSOp.getOpcode() != ISD::ConstantFP)) 5568193323Sed break; 5569193323Sed 5570193323Sed // Can't fold divide by zero. 5571193323Sed if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5572193323Sed N->getOpcode() == ISD::FDIV) { 5573193323Sed if ((RHSOp.getOpcode() == ISD::Constant && 5574193323Sed cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5575193323Sed (RHSOp.getOpcode() == ISD::ConstantFP && 5576193323Sed cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5577193323Sed break; 5578193323Sed } 5579193323Sed 5580193323Sed Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5581193323Sed EltType, LHSOp, RHSOp)); 5582193323Sed AddToWorkList(Ops.back().getNode()); 5583193323Sed assert((Ops.back().getOpcode() == ISD::UNDEF || 5584193323Sed Ops.back().getOpcode() == ISD::Constant || 5585193323Sed Ops.back().getOpcode() == ISD::ConstantFP) && 5586193323Sed "Scalar binop didn't fold!"); 5587193323Sed } 5588193323Sed 5589193323Sed if (Ops.size() == LHS.getNumOperands()) { 5590193323Sed MVT VT = LHS.getValueType(); 5591193323Sed return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5592193323Sed &Ops[0], Ops.size()); 5593193323Sed } 5594193323Sed } 5595193323Sed 5596193323Sed return SDValue(); 5597193323Sed} 5598193323Sed 5599193323SedSDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5600193323Sed SDValue N1, SDValue N2){ 5601193323Sed assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5602193323Sed 5603193323Sed SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5604193323Sed cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5605193323Sed 5606193323Sed // If we got a simplified select_cc node back from SimplifySelectCC, then 5607193323Sed // break it down into a new SETCC node, and a new SELECT node, and then return 5608193323Sed // the SELECT node, since we were called with a SELECT node. 5609193323Sed if (SCC.getNode()) { 5610193323Sed // Check to see if we got a select_cc back (to turn into setcc/select). 5611193323Sed // Otherwise, just return whatever node we got back, like fabs. 5612193323Sed if (SCC.getOpcode() == ISD::SELECT_CC) { 5613193323Sed SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5614193323Sed N0.getValueType(), 5615193323Sed SCC.getOperand(0), SCC.getOperand(1), 5616193323Sed SCC.getOperand(4)); 5617193323Sed AddToWorkList(SETCC.getNode()); 5618193323Sed return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5619193323Sed SCC.getOperand(2), SCC.getOperand(3), SETCC); 5620193323Sed } 5621193323Sed 5622193323Sed return SCC; 5623193323Sed } 5624193323Sed return SDValue(); 5625193323Sed} 5626193323Sed 5627193323Sed/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5628193323Sed/// are the two values being selected between, see if we can simplify the 5629193323Sed/// select. Callers of this should assume that TheSelect is deleted if this 5630193323Sed/// returns true. As such, they should return the appropriate thing (e.g. the 5631193323Sed/// node) back to the top-level of the DAG combiner loop to avoid it being 5632193323Sed/// looked at. 5633193323Sedbool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5634193323Sed SDValue RHS) { 5635193323Sed 5636193323Sed // If this is a select from two identical things, try to pull the operation 5637193323Sed // through the select. 5638193323Sed if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5639193323Sed // If this is a load and the token chain is identical, replace the select 5640193323Sed // of two loads with a load through a select of the address to load from. 5641193323Sed // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5642193323Sed // constants have been dropped into the constant pool. 5643193323Sed if (LHS.getOpcode() == ISD::LOAD && 5644193323Sed // Do not let this transformation reduce the number of volatile loads. 5645193323Sed !cast<LoadSDNode>(LHS)->isVolatile() && 5646193323Sed !cast<LoadSDNode>(RHS)->isVolatile() && 5647193323Sed // Token chains must be identical. 5648193323Sed LHS.getOperand(0) == RHS.getOperand(0)) { 5649193323Sed LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5650193323Sed LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5651193323Sed 5652193323Sed // If this is an EXTLOAD, the VT's must match. 5653193323Sed if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5654193323Sed // FIXME: this conflates two src values, discarding one. This is not 5655193323Sed // the right thing to do, but nothing uses srcvalues now. When they do, 5656193323Sed // turn SrcValue into a list of locations. 5657193323Sed SDValue Addr; 5658193323Sed if (TheSelect->getOpcode() == ISD::SELECT) { 5659193323Sed // Check that the condition doesn't reach either load. If so, folding 5660193323Sed // this will induce a cycle into the DAG. 5661193323Sed if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5662193323Sed !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5663193323Sed Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5664193323Sed LLD->getBasePtr().getValueType(), 5665193323Sed TheSelect->getOperand(0), LLD->getBasePtr(), 5666193323Sed RLD->getBasePtr()); 5667193323Sed } 5668193323Sed } else { 5669193323Sed // Check that the condition doesn't reach either load. If so, folding 5670193323Sed // this will induce a cycle into the DAG. 5671193323Sed if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5672193323Sed !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5673193323Sed !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5674193323Sed !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5675193323Sed Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5676193323Sed LLD->getBasePtr().getValueType(), 5677193323Sed TheSelect->getOperand(0), 5678193323Sed TheSelect->getOperand(1), 5679193323Sed LLD->getBasePtr(), RLD->getBasePtr(), 5680193323Sed TheSelect->getOperand(4)); 5681193323Sed } 5682193323Sed } 5683193323Sed 5684193323Sed if (Addr.getNode()) { 5685193323Sed SDValue Load; 5686193323Sed if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5687193323Sed Load = DAG.getLoad(TheSelect->getValueType(0), 5688193323Sed TheSelect->getDebugLoc(), 5689193323Sed LLD->getChain(), 5690193323Sed Addr,LLD->getSrcValue(), 5691193323Sed LLD->getSrcValueOffset(), 5692193323Sed LLD->isVolatile(), 5693193323Sed LLD->getAlignment()); 5694193323Sed } else { 5695193323Sed Load = DAG.getExtLoad(LLD->getExtensionType(), 5696193323Sed TheSelect->getDebugLoc(), 5697193323Sed TheSelect->getValueType(0), 5698193323Sed LLD->getChain(), Addr, LLD->getSrcValue(), 5699193323Sed LLD->getSrcValueOffset(), 5700193323Sed LLD->getMemoryVT(), 5701193323Sed LLD->isVolatile(), 5702193323Sed LLD->getAlignment()); 5703193323Sed } 5704193323Sed 5705193323Sed // Users of the select now use the result of the load. 5706193323Sed CombineTo(TheSelect, Load); 5707193323Sed 5708193323Sed // Users of the old loads now use the new load's chain. We know the 5709193323Sed // old-load value is dead now. 5710193323Sed CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5711193323Sed CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5712193323Sed return true; 5713193323Sed } 5714193323Sed } 5715193323Sed } 5716193323Sed } 5717193323Sed 5718193323Sed return false; 5719193323Sed} 5720193323Sed 5721193323Sed/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5722193323Sed/// where 'cond' is the comparison specified by CC. 5723193323SedSDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5724193323Sed SDValue N2, SDValue N3, 5725193323Sed ISD::CondCode CC, bool NotExtCompare) { 5726193323Sed // (x ? y : y) -> y. 5727193323Sed if (N2 == N3) return N2; 5728193323Sed 5729193323Sed MVT VT = N2.getValueType(); 5730193323Sed ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5731193323Sed ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5732193323Sed ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5733193323Sed 5734193323Sed // Determine if the condition we're dealing with is constant 5735193323Sed SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5736193323Sed N0, N1, CC, DL, false); 5737193323Sed if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5738193323Sed ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5739193323Sed 5740193323Sed // fold select_cc true, x, y -> x 5741193323Sed if (SCCC && !SCCC->isNullValue()) 5742193323Sed return N2; 5743193323Sed // fold select_cc false, x, y -> y 5744193323Sed if (SCCC && SCCC->isNullValue()) 5745193323Sed return N3; 5746193323Sed 5747193323Sed // Check to see if we can simplify the select into an fabs node 5748193323Sed if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5749193323Sed // Allow either -0.0 or 0.0 5750193323Sed if (CFP->getValueAPF().isZero()) { 5751193323Sed // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5752193323Sed if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5753193323Sed N0 == N2 && N3.getOpcode() == ISD::FNEG && 5754193323Sed N2 == N3.getOperand(0)) 5755193323Sed return DAG.getNode(ISD::FABS, DL, VT, N0); 5756193323Sed 5757193323Sed // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5758193323Sed if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5759193323Sed N0 == N3 && N2.getOpcode() == ISD::FNEG && 5760193323Sed N2.getOperand(0) == N3) 5761193323Sed return DAG.getNode(ISD::FABS, DL, VT, N3); 5762193323Sed } 5763193323Sed } 5764193323Sed 5765193323Sed // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5766193323Sed // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5767193323Sed // in it. This is a win when the constant is not otherwise available because 5768193323Sed // it replaces two constant pool loads with one. We only do this if the FP 5769193323Sed // type is known to be legal, because if it isn't, then we are before legalize 5770193323Sed // types an we want the other legalization to happen first (e.g. to avoid 5771193323Sed // messing with soft float) and if the ConstantFP is not legal, because if 5772193323Sed // it is legal, we may not need to store the FP constant in a constant pool. 5773193323Sed if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5774193323Sed if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5775193323Sed if (TLI.isTypeLegal(N2.getValueType()) && 5776193323Sed (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5777193323Sed TargetLowering::Legal) && 5778193323Sed // If both constants have multiple uses, then we won't need to do an 5779193323Sed // extra load, they are likely around in registers for other users. 5780193323Sed (TV->hasOneUse() || FV->hasOneUse())) { 5781193323Sed Constant *Elts[] = { 5782193323Sed const_cast<ConstantFP*>(FV->getConstantFPValue()), 5783193323Sed const_cast<ConstantFP*>(TV->getConstantFPValue()) 5784193323Sed }; 5785193323Sed const Type *FPTy = Elts[0]->getType(); 5786193323Sed const TargetData &TD = *TLI.getTargetData(); 5787193323Sed 5788193323Sed // Create a ConstantArray of the two constants. 5789193323Sed Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5790193323Sed SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5791193323Sed TD.getPrefTypeAlignment(FPTy)); 5792193323Sed unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5793193323Sed 5794193323Sed // Get the offsets to the 0 and 1 element of the array so that we can 5795193323Sed // select between them. 5796193323Sed SDValue Zero = DAG.getIntPtrConstant(0); 5797193323Sed unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5798193323Sed SDValue One = DAG.getIntPtrConstant(EltSize); 5799193323Sed 5800193323Sed SDValue Cond = DAG.getSetCC(DL, 5801193323Sed TLI.getSetCCResultType(N0.getValueType()), 5802193323Sed N0, N1, CC); 5803193323Sed SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5804193323Sed Cond, One, Zero); 5805193323Sed CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5806193323Sed CstOffset); 5807193323Sed return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5808193323Sed PseudoSourceValue::getConstantPool(), 0, false, 5809193323Sed Alignment); 5810193323Sed 5811193323Sed } 5812193323Sed } 5813193323Sed 5814193323Sed // Check to see if we can perform the "gzip trick", transforming 5815193323Sed // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5816193323Sed if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5817193323Sed N0.getValueType().isInteger() && 5818193323Sed N2.getValueType().isInteger() && 5819193323Sed (N1C->isNullValue() || // (a < 0) ? b : 0 5820193323Sed (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5821193323Sed MVT XType = N0.getValueType(); 5822193323Sed MVT AType = N2.getValueType(); 5823193323Sed if (XType.bitsGE(AType)) { 5824193323Sed // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5825193323Sed // single-bit constant. 5826193323Sed if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5827193323Sed unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5828193323Sed ShCtV = XType.getSizeInBits()-ShCtV-1; 5829193323Sed SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5830193323Sed SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5831193323Sed XType, N0, ShCt); 5832193323Sed AddToWorkList(Shift.getNode()); 5833193323Sed 5834193323Sed if (XType.bitsGT(AType)) { 5835193323Sed Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5836193323Sed AddToWorkList(Shift.getNode()); 5837193323Sed } 5838193323Sed 5839193323Sed return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5840193323Sed } 5841193323Sed 5842193323Sed SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5843193323Sed XType, N0, 5844193323Sed DAG.getConstant(XType.getSizeInBits()-1, 5845193323Sed getShiftAmountTy())); 5846193323Sed AddToWorkList(Shift.getNode()); 5847193323Sed 5848193323Sed if (XType.bitsGT(AType)) { 5849193323Sed Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5850193323Sed AddToWorkList(Shift.getNode()); 5851193323Sed } 5852193323Sed 5853193323Sed return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5854193323Sed } 5855193323Sed } 5856193323Sed 5857193323Sed // fold select C, 16, 0 -> shl C, 4 5858193323Sed if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5859193323Sed TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5860193323Sed 5861193323Sed // If the caller doesn't want us to simplify this into a zext of a compare, 5862193323Sed // don't do it. 5863193323Sed if (NotExtCompare && N2C->getAPIntValue() == 1) 5864193323Sed return SDValue(); 5865193323Sed 5866193323Sed // Get a SetCC of the condition 5867193323Sed // FIXME: Should probably make sure that setcc is legal if we ever have a 5868193323Sed // target where it isn't. 5869193323Sed SDValue Temp, SCC; 5870193323Sed // cast from setcc result type to select result type 5871193323Sed if (LegalTypes) { 5872193323Sed SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5873193323Sed N0, N1, CC); 5874193323Sed if (N2.getValueType().bitsLT(SCC.getValueType())) 5875193323Sed Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5876193323Sed else 5877193323Sed Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5878193323Sed N2.getValueType(), SCC); 5879193323Sed } else { 5880193323Sed SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5881193323Sed Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5882193323Sed N2.getValueType(), SCC); 5883193323Sed } 5884193323Sed 5885193323Sed AddToWorkList(SCC.getNode()); 5886193323Sed AddToWorkList(Temp.getNode()); 5887193323Sed 5888193323Sed if (N2C->getAPIntValue() == 1) 5889193323Sed return Temp; 5890193323Sed 5891193323Sed // shl setcc result by log2 n2c 5892193323Sed return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5893193323Sed DAG.getConstant(N2C->getAPIntValue().logBase2(), 5894193323Sed getShiftAmountTy())); 5895193323Sed } 5896193323Sed 5897193323Sed // Check to see if this is the equivalent of setcc 5898193323Sed // FIXME: Turn all of these into setcc if setcc if setcc is legal 5899193323Sed // otherwise, go ahead with the folds. 5900193323Sed if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5901193323Sed MVT XType = N0.getValueType(); 5902193323Sed if (!LegalOperations || 5903193323Sed TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5904193323Sed SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5905193323Sed if (Res.getValueType() != VT) 5906193323Sed Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5907193323Sed return Res; 5908193323Sed } 5909193323Sed 5910193323Sed // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5911193323Sed if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5912193323Sed (!LegalOperations || 5913193323Sed TLI.isOperationLegal(ISD::CTLZ, XType))) { 5914193323Sed SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5915193323Sed return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5916193323Sed DAG.getConstant(Log2_32(XType.getSizeInBits()), 5917193323Sed getShiftAmountTy())); 5918193323Sed } 5919193323Sed // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5920193323Sed if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5921193323Sed SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5922193323Sed XType, DAG.getConstant(0, XType), N0); 5923193323Sed SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5924193323Sed return DAG.getNode(ISD::SRL, DL, XType, 5925193323Sed DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5926193323Sed DAG.getConstant(XType.getSizeInBits()-1, 5927193323Sed getShiftAmountTy())); 5928193323Sed } 5929193323Sed // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5930193323Sed if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5931193323Sed SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5932193323Sed DAG.getConstant(XType.getSizeInBits()-1, 5933193323Sed getShiftAmountTy())); 5934193323Sed return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5935193323Sed } 5936193323Sed } 5937193323Sed 5938193323Sed // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5939193323Sed // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5940193323Sed if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5941193323Sed N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5942193323Sed N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5943193323Sed MVT XType = N0.getValueType(); 5944193323Sed SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5945193323Sed DAG.getConstant(XType.getSizeInBits()-1, 5946193323Sed getShiftAmountTy())); 5947193323Sed SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5948193323Sed N0, Shift); 5949193323Sed AddToWorkList(Shift.getNode()); 5950193323Sed AddToWorkList(Add.getNode()); 5951193323Sed return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5952193323Sed } 5953193323Sed // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5954193323Sed // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5955193323Sed if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5956193323Sed N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5957193323Sed if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5958193323Sed MVT XType = N0.getValueType(); 5959193323Sed if (SubC->isNullValue() && XType.isInteger()) { 5960193323Sed SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5961193323Sed N0, 5962193323Sed DAG.getConstant(XType.getSizeInBits()-1, 5963193323Sed getShiftAmountTy())); 5964193323Sed SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5965193323Sed XType, N0, Shift); 5966193323Sed AddToWorkList(Shift.getNode()); 5967193323Sed AddToWorkList(Add.getNode()); 5968193323Sed return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5969193323Sed } 5970193323Sed } 5971193323Sed } 5972193323Sed 5973193323Sed return SDValue(); 5974193323Sed} 5975193323Sed 5976193323Sed/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5977193323SedSDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5978193323Sed SDValue N1, ISD::CondCode Cond, 5979193323Sed DebugLoc DL, bool foldBooleans) { 5980193323Sed TargetLowering::DAGCombinerInfo 5981193323Sed DagCombineInfo(DAG, Level == Unrestricted, false, this); 5982193323Sed return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 5983193323Sed} 5984193323Sed 5985193323Sed/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5986193323Sed/// return a DAG expression to select that will generate the same value by 5987193323Sed/// multiplying by a magic number. See: 5988193323Sed/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5989193323SedSDValue DAGCombiner::BuildSDIV(SDNode *N) { 5990193323Sed std::vector<SDNode*> Built; 5991193323Sed SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5992193323Sed 5993193323Sed for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5994193323Sed ii != ee; ++ii) 5995193323Sed AddToWorkList(*ii); 5996193323Sed return S; 5997193323Sed} 5998193323Sed 5999193323Sed/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6000193323Sed/// return a DAG expression to select that will generate the same value by 6001193323Sed/// multiplying by a magic number. See: 6002193323Sed/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6003193323SedSDValue DAGCombiner::BuildUDIV(SDNode *N) { 6004193323Sed std::vector<SDNode*> Built; 6005193323Sed SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6006193323Sed 6007193323Sed for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6008193323Sed ii != ee; ++ii) 6009193323Sed AddToWorkList(*ii); 6010193323Sed return S; 6011193323Sed} 6012193323Sed 6013193323Sed/// FindBaseOffset - Return true if base is known not to alias with anything 6014193323Sed/// but itself. Provides base object and offset as results. 6015193323Sedstatic bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 6016193323Sed // Assume it is a primitive operation. 6017193323Sed Base = Ptr; Offset = 0; 6018193323Sed 6019193323Sed // If it's an adding a simple constant then integrate the offset. 6020193323Sed if (Base.getOpcode() == ISD::ADD) { 6021193323Sed if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6022193323Sed Base = Base.getOperand(0); 6023193323Sed Offset += C->getZExtValue(); 6024193323Sed } 6025193323Sed } 6026193323Sed 6027193323Sed // If it's any of the following then it can't alias with anything but itself. 6028193323Sed return isa<FrameIndexSDNode>(Base) || 6029193323Sed isa<ConstantPoolSDNode>(Base) || 6030193323Sed isa<GlobalAddressSDNode>(Base); 6031193323Sed} 6032193323Sed 6033193323Sed/// isAlias - Return true if there is any possibility that the two addresses 6034193323Sed/// overlap. 6035193323Sedbool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6036193323Sed const Value *SrcValue1, int SrcValueOffset1, 6037193323Sed SDValue Ptr2, int64_t Size2, 6038193323Sed const Value *SrcValue2, int SrcValueOffset2) const { 6039193323Sed // If they are the same then they must be aliases. 6040193323Sed if (Ptr1 == Ptr2) return true; 6041193323Sed 6042193323Sed // Gather base node and offset information. 6043193323Sed SDValue Base1, Base2; 6044193323Sed int64_t Offset1, Offset2; 6045193323Sed bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 6046193323Sed bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 6047193323Sed 6048193323Sed // If they have a same base address then... 6049193323Sed if (Base1 == Base2) 6050193323Sed // Check to see if the addresses overlap. 6051193323Sed return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6052193323Sed 6053193323Sed // If we know both bases then they can't alias. 6054193323Sed if (KnownBase1 && KnownBase2) return false; 6055193323Sed 6056193323Sed if (CombinerGlobalAA) { 6057193323Sed // Use alias analysis information. 6058193323Sed int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6059193323Sed int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6060193323Sed int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6061193323Sed AliasAnalysis::AliasResult AAResult = 6062193323Sed AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6063193323Sed if (AAResult == AliasAnalysis::NoAlias) 6064193323Sed return false; 6065193323Sed } 6066193323Sed 6067193323Sed // Otherwise we have to assume they alias. 6068193323Sed return true; 6069193323Sed} 6070193323Sed 6071193323Sed/// FindAliasInfo - Extracts the relevant alias information from the memory 6072193323Sed/// node. Returns true if the operand was a load. 6073193323Sedbool DAGCombiner::FindAliasInfo(SDNode *N, 6074193323Sed SDValue &Ptr, int64_t &Size, 6075193323Sed const Value *&SrcValue, int &SrcValueOffset) const { 6076193323Sed if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6077193323Sed Ptr = LD->getBasePtr(); 6078193323Sed Size = LD->getMemoryVT().getSizeInBits() >> 3; 6079193323Sed SrcValue = LD->getSrcValue(); 6080193323Sed SrcValueOffset = LD->getSrcValueOffset(); 6081193323Sed return true; 6082193323Sed } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6083193323Sed Ptr = ST->getBasePtr(); 6084193323Sed Size = ST->getMemoryVT().getSizeInBits() >> 3; 6085193323Sed SrcValue = ST->getSrcValue(); 6086193323Sed SrcValueOffset = ST->getSrcValueOffset(); 6087193323Sed } else { 6088193323Sed assert(0 && "FindAliasInfo expected a memory operand"); 6089193323Sed } 6090193323Sed 6091193323Sed return false; 6092193323Sed} 6093193323Sed 6094193323Sed/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6095193323Sed/// looking for aliasing nodes and adding them to the Aliases vector. 6096193323Sedvoid DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6097193323Sed SmallVector<SDValue, 8> &Aliases) { 6098193323Sed SmallVector<SDValue, 8> Chains; // List of chains to visit. 6099193323Sed std::set<SDNode *> Visited; // Visited node set. 6100193323Sed 6101193323Sed // Get alias information for node. 6102193323Sed SDValue Ptr; 6103193323Sed int64_t Size = 0; 6104193323Sed const Value *SrcValue = 0; 6105193323Sed int SrcValueOffset = 0; 6106193323Sed bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6107193323Sed 6108193323Sed // Starting off. 6109193323Sed Chains.push_back(OriginalChain); 6110193323Sed 6111193323Sed // Look at each chain and determine if it is an alias. If so, add it to the 6112193323Sed // aliases list. If not, then continue up the chain looking for the next 6113193323Sed // candidate. 6114193323Sed while (!Chains.empty()) { 6115193323Sed SDValue Chain = Chains.back(); 6116193323Sed Chains.pop_back(); 6117193323Sed 6118193323Sed // Don't bother if we've been before. 6119193323Sed if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6120193323Sed Visited.insert(Chain.getNode()); 6121193323Sed 6122193323Sed switch (Chain.getOpcode()) { 6123193323Sed case ISD::EntryToken: 6124193323Sed // Entry token is ideal chain operand, but handled in FindBetterChain. 6125193323Sed break; 6126193323Sed 6127193323Sed case ISD::LOAD: 6128193323Sed case ISD::STORE: { 6129193323Sed // Get alias information for Chain. 6130193323Sed SDValue OpPtr; 6131193323Sed int64_t OpSize = 0; 6132193323Sed const Value *OpSrcValue = 0; 6133193323Sed int OpSrcValueOffset = 0; 6134193323Sed bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6135193323Sed OpSrcValue, OpSrcValueOffset); 6136193323Sed 6137193323Sed // If chain is alias then stop here. 6138193323Sed if (!(IsLoad && IsOpLoad) && 6139193323Sed isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6140193323Sed OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6141193323Sed Aliases.push_back(Chain); 6142193323Sed } else { 6143193323Sed // Look further up the chain. 6144193323Sed Chains.push_back(Chain.getOperand(0)); 6145193323Sed // Clean up old chain. 6146193323Sed AddToWorkList(Chain.getNode()); 6147193323Sed } 6148193323Sed break; 6149193323Sed } 6150193323Sed 6151193323Sed case ISD::TokenFactor: 6152193323Sed // We have to check each of the operands of the token factor, so we queue 6153193323Sed // then up. Adding the operands to the queue (stack) in reverse order 6154193323Sed // maintains the original order and increases the likelihood that getNode 6155193323Sed // will find a matching token factor (CSE.) 6156193323Sed for (unsigned n = Chain.getNumOperands(); n;) 6157193323Sed Chains.push_back(Chain.getOperand(--n)); 6158193323Sed // Eliminate the token factor if we can. 6159193323Sed AddToWorkList(Chain.getNode()); 6160193323Sed break; 6161193323Sed 6162193323Sed default: 6163193323Sed // For all other instructions we will just have to take what we can get. 6164193323Sed Aliases.push_back(Chain); 6165193323Sed break; 6166193323Sed } 6167193323Sed } 6168193323Sed} 6169193323Sed 6170193323Sed/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6171193323Sed/// for a better chain (aliasing node.) 6172193323SedSDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6173193323Sed SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6174193323Sed 6175193323Sed // Accumulate all the aliases to this node. 6176193323Sed GatherAllAliases(N, OldChain, Aliases); 6177193323Sed 6178193323Sed if (Aliases.size() == 0) { 6179193323Sed // If no operands then chain to entry token. 6180193323Sed return DAG.getEntryNode(); 6181193323Sed } else if (Aliases.size() == 1) { 6182193323Sed // If a single operand then chain to it. We don't need to revisit it. 6183193323Sed return Aliases[0]; 6184193323Sed } 6185193323Sed 6186193323Sed // Construct a custom tailored token factor. 6187193323Sed SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6188193323Sed &Aliases[0], Aliases.size()); 6189193323Sed 6190193323Sed // Make sure the old chain gets cleaned up. 6191193323Sed if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6192193323Sed 6193193323Sed return NewChain; 6194193323Sed} 6195193323Sed 6196193323Sed// SelectionDAG::Combine - This is the entry point for the file. 6197193323Sed// 6198193323Sedvoid SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6199193323Sed CodeGenOpt::Level OptLevel) { 6200193323Sed /// run - This is the main entry point to this class. 6201193323Sed /// 6202193323Sed DAGCombiner(*this, AA, OptLevel).Run(Level); 6203193323Sed} 6204