TargetLowering.h revision 203954
1//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes how to lower LLVM code to machine code. This has two 11// main components: 12// 13// 1. Which ValueTypes are natively supported by the target. 14// 2. Which operations are supported for supported ValueTypes. 15// 3. Cost thresholds for alternative implementations of certain operations. 16// 17// In addition it has a few other components, like information about FP 18// immediates. 19// 20//===----------------------------------------------------------------------===// 21 22#ifndef LLVM_TARGET_TARGETLOWERING_H 23#define LLVM_TARGET_TARGETLOWERING_H 24 25#include "llvm/CallingConv.h" 26#include "llvm/InlineAsm.h" 27#include "llvm/CodeGen/SelectionDAGNodes.h" 28#include "llvm/CodeGen/RuntimeLibcalls.h" 29#include "llvm/ADT/APFloat.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallSet.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/STLExtras.h" 34#include "llvm/Support/DebugLoc.h" 35#include "llvm/Target/TargetMachine.h" 36#include <climits> 37#include <map> 38#include <vector> 39 40namespace llvm { 41 class AllocaInst; 42 class CallInst; 43 class Function; 44 class FastISel; 45 class MachineBasicBlock; 46 class MachineFunction; 47 class MachineFrameInfo; 48 class MachineInstr; 49 class MachineJumpTableInfo; 50 class MachineModuleInfo; 51 class MCContext; 52 class MCExpr; 53 class DwarfWriter; 54 class SDNode; 55 class SDValue; 56 class SelectionDAG; 57 class TargetData; 58 class TargetMachine; 59 class TargetRegisterClass; 60 class TargetSubtarget; 61 class TargetLoweringObjectFile; 62 class Value; 63 64 // FIXME: should this be here? 65 namespace TLSModel { 66 enum Model { 67 GeneralDynamic, 68 LocalDynamic, 69 InitialExec, 70 LocalExec 71 }; 72 } 73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 74 75 76//===----------------------------------------------------------------------===// 77/// TargetLowering - This class defines information used to lower LLVM code to 78/// legal SelectionDAG operators that the target instruction selector can accept 79/// natively. 80/// 81/// This class also defines callbacks that targets must implement to lower 82/// target-specific constructs to SelectionDAG operators. 83/// 84class TargetLowering { 85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 87public: 88 /// LegalizeAction - This enum indicates whether operations are valid for a 89 /// target, and if not, what action should be used to make them valid. 90 enum LegalizeAction { 91 Legal, // The target natively supports this operation. 92 Promote, // This operation should be executed in a larger type. 93 Expand, // Try to expand this to other ops, otherwise use a libcall. 94 Custom // Use the LowerOperation hook to implement custom lowering. 95 }; 96 97 enum BooleanContent { // How the target represents true/false values. 98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 99 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 101 }; 102 103 enum SchedPreference { 104 SchedulingForLatency, // Scheduling for shortest total latency. 105 SchedulingForRegPressure // Scheduling for lowest register pressure. 106 }; 107 108 /// NOTE: The constructor takes ownership of TLOF. 109 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF); 110 virtual ~TargetLowering(); 111 112 TargetMachine &getTargetMachine() const { return TM; } 113 const TargetData *getTargetData() const { return TD; } 114 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 115 116 bool isBigEndian() const { return !IsLittleEndian; } 117 bool isLittleEndian() const { return IsLittleEndian; } 118 MVT getPointerTy() const { return PointerTy; } 119 MVT getShiftAmountTy() const { return ShiftAmountTy; } 120 121 /// isSelectExpensive - Return true if the select operation is expensive for 122 /// this target. 123 bool isSelectExpensive() const { return SelectIsExpensive; } 124 125 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 126 /// a sequence of several shifts, adds, and multiplies for this target. 127 bool isIntDivCheap() const { return IntDivIsCheap; } 128 129 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 130 /// srl/add/sra. 131 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 132 133 /// getSetCCResultType - Return the ValueType of the result of SETCC 134 /// operations. Also used to obtain the target's preferred type for 135 /// the condition operand of SELECT and BRCOND nodes. In the case of 136 /// BRCOND the argument passed is MVT::Other since there are no other 137 /// operands to get a type hint from. 138 virtual 139 MVT::SimpleValueType getSetCCResultType(EVT VT) const; 140 141 /// getCmpLibcallReturnType - Return the ValueType for comparison 142 /// libcalls. Comparions libcalls include floating point comparion calls, 143 /// and Ordered/Unordered check calls on floating point numbers. 144 virtual 145 MVT::SimpleValueType getCmpLibcallReturnType() const; 146 147 /// getBooleanContents - For targets without i1 registers, this gives the 148 /// nature of the high-bits of boolean values held in types wider than i1. 149 /// "Boolean values" are special true/false values produced by nodes like 150 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 151 /// Not to be confused with general values promoted from i1. 152 BooleanContent getBooleanContents() const { return BooleanContents;} 153 154 /// getSchedulingPreference - Return target scheduling preference. 155 SchedPreference getSchedulingPreference() const { 156 return SchedPreferenceInfo; 157 } 158 159 /// getRegClassFor - Return the register class that should be used for the 160 /// specified value type. This may only be called on legal types. 161 TargetRegisterClass *getRegClassFor(EVT VT) const { 162 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 163 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 164 assert(RC && "This value type is not natively supported!"); 165 return RC; 166 } 167 168 /// isTypeLegal - Return true if the target has native support for the 169 /// specified value type. This means that it has a register that directly 170 /// holds it without promotions or expansions. 171 bool isTypeLegal(EVT VT) const { 172 assert(!VT.isSimple() || 173 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 174 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 175 } 176 177 class ValueTypeActionImpl { 178 /// ValueTypeActions - This is a bitvector that contains two bits for each 179 /// value type, where the two bits correspond to the LegalizeAction enum. 180 /// This can be queried with "getTypeAction(VT)". 181 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2 182 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2]; 183 public: 184 ValueTypeActionImpl() { 185 ValueTypeActions[0] = ValueTypeActions[1] = 0; 186 ValueTypeActions[2] = ValueTypeActions[3] = 0; 187 } 188 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) { 189 ValueTypeActions[0] = RHS.ValueTypeActions[0]; 190 ValueTypeActions[1] = RHS.ValueTypeActions[1]; 191 ValueTypeActions[2] = RHS.ValueTypeActions[2]; 192 ValueTypeActions[3] = RHS.ValueTypeActions[3]; 193 } 194 195 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 196 if (VT.isExtended()) { 197 if (VT.isVector()) { 198 return VT.isPow2VectorType() ? Expand : Promote; 199 } 200 if (VT.isInteger()) 201 // First promote to a power-of-two size, then expand if necessary. 202 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote; 203 assert(0 && "Unsupported extended type!"); 204 return Legal; 205 } 206 unsigned I = VT.getSimpleVT().SimpleTy; 207 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 208 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3); 209 } 210 void setTypeAction(EVT VT, LegalizeAction Action) { 211 unsigned I = VT.getSimpleVT().SimpleTy; 212 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0])); 213 ValueTypeActions[I>>4] |= Action << ((I*2) & 31); 214 } 215 }; 216 217 const ValueTypeActionImpl &getValueTypeActions() const { 218 return ValueTypeActions; 219 } 220 221 /// getTypeAction - Return how we should legalize values of this type, either 222 /// it is already legal (return 'Legal') or we need to promote it to a larger 223 /// type (return 'Promote'), or we need to expand it into multiple registers 224 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. 225 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { 226 return ValueTypeActions.getTypeAction(Context, VT); 227 } 228 229 /// getTypeToTransformTo - For types supported by the target, this is an 230 /// identity function. For types that must be promoted to larger types, this 231 /// returns the larger type to promote to. For integer types that are larger 232 /// than the largest integer register, this contains one step in the expansion 233 /// to get to the smaller register. For illegal floating point types, this 234 /// returns the integer type to transform to. 235 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 236 if (VT.isSimple()) { 237 assert((unsigned)VT.getSimpleVT().SimpleTy < 238 array_lengthof(TransformToType)); 239 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 240 assert(getTypeAction(Context, NVT) != Promote && 241 "Promote may not follow Expand or Promote"); 242 return NVT; 243 } 244 245 if (VT.isVector()) { 246 EVT NVT = VT.getPow2VectorType(Context); 247 if (NVT == VT) { 248 // Vector length is a power of 2 - split to half the size. 249 unsigned NumElts = VT.getVectorNumElements(); 250 EVT EltVT = VT.getVectorElementType(); 251 return (NumElts == 1) ? 252 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); 253 } 254 // Promote to a power of two size, avoiding multi-step promotion. 255 return getTypeAction(Context, NVT) == Promote ? 256 getTypeToTransformTo(Context, NVT) : NVT; 257 } else if (VT.isInteger()) { 258 EVT NVT = VT.getRoundIntegerType(Context); 259 if (NVT == VT) 260 // Size is a power of two - expand to half the size. 261 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); 262 else 263 // Promote to a power of two size, avoiding multi-step promotion. 264 return getTypeAction(Context, NVT) == Promote ? 265 getTypeToTransformTo(Context, NVT) : NVT; 266 } 267 assert(0 && "Unsupported extended type!"); 268 return MVT(MVT::Other); // Not reached 269 } 270 271 /// getTypeToExpandTo - For types supported by the target, this is an 272 /// identity function. For types that must be expanded (i.e. integer types 273 /// that are larger than the largest integer register or illegal floating 274 /// point types), this returns the largest legal type it will be expanded to. 275 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 276 assert(!VT.isVector()); 277 while (true) { 278 switch (getTypeAction(Context, VT)) { 279 case Legal: 280 return VT; 281 case Expand: 282 VT = getTypeToTransformTo(Context, VT); 283 break; 284 default: 285 assert(false && "Type is not legal nor is it to be expanded!"); 286 return VT; 287 } 288 } 289 return VT; 290 } 291 292 /// getVectorTypeBreakdown - Vector types are broken down into some number of 293 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 294 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 295 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 296 /// 297 /// This method returns the number of registers needed, and the VT for each 298 /// register. It also returns the VT and quantity of the intermediate values 299 /// before they are promoted/expanded. 300 /// 301 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 302 EVT &IntermediateVT, 303 unsigned &NumIntermediates, 304 EVT &RegisterVT) const; 305 306 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 307 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 308 /// this is the case, it returns true and store the intrinsic 309 /// information into the IntrinsicInfo that was passed to the function. 310 typedef struct IntrinsicInfo { 311 unsigned opc; // target opcode 312 EVT memVT; // memory VT 313 const Value* ptrVal; // value representing memory location 314 int offset; // offset off of ptrVal 315 unsigned align; // alignment 316 bool vol; // is volatile? 317 bool readMem; // reads memory? 318 bool writeMem; // writes memory? 319 } IntrinisicInfo; 320 321 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info, 322 CallInst &I, unsigned Intrinsic) { 323 return false; 324 } 325 326 /// getWidenVectorType: given a vector type, returns the type to widen to 327 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 328 /// If there is no vector type that we want to widen to, returns MVT::Other 329 /// When and were to widen is target dependent based on the cost of 330 /// scalarizing vs using the wider vector type. 331 virtual EVT getWidenVectorType(EVT VT) const; 332 333 /// isFPImmLegal - Returns true if the target can instruction select the 334 /// specified FP immediate natively. If false, the legalizer will materialize 335 /// the FP immediate as a load from a constant pool. 336 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const { 337 return false; 338 } 339 340 /// isShuffleMaskLegal - Targets can use this to indicate that they only 341 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 342 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 343 /// are assumed to be legal. 344 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 345 EVT VT) const { 346 return true; 347 } 348 349 /// canOpTrap - Returns true if the operation can trap for the value type. 350 /// VT must be a legal type. By default, we optimistically assume most 351 /// operations don't trap except for divide and remainder. 352 virtual bool canOpTrap(unsigned Op, EVT VT) const; 353 354 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 355 /// used by Targets can use this to indicate if there is a suitable 356 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 357 /// pool entry. 358 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 359 EVT VT) const { 360 return false; 361 } 362 363 /// getOperationAction - Return how this operation should be treated: either 364 /// it is legal, needs to be promoted to a larger size, needs to be 365 /// expanded to some other code sequence, or the target has a custom expander 366 /// for it. 367 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 368 if (VT.isExtended()) return Expand; 369 assert(Op < array_lengthof(OpActions[0]) && 370 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 && 371 "Table isn't big enough!"); 372 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 373 unsigned J = I & 31; 374 I = I >> 5; 375 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3); 376 } 377 378 /// isOperationLegalOrCustom - Return true if the specified operation is 379 /// legal on this target or can be made legal with custom lowering. This 380 /// is used to help guide high-level lowering decisions. 381 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 382 return (VT == MVT::Other || isTypeLegal(VT)) && 383 (getOperationAction(Op, VT) == Legal || 384 getOperationAction(Op, VT) == Custom); 385 } 386 387 /// isOperationLegal - Return true if the specified operation is legal on this 388 /// target. 389 bool isOperationLegal(unsigned Op, EVT VT) const { 390 return (VT == MVT::Other || isTypeLegal(VT)) && 391 getOperationAction(Op, VT) == Legal; 392 } 393 394 /// getLoadExtAction - Return how this load with extension should be treated: 395 /// either it is legal, needs to be promoted to a larger size, needs to be 396 /// expanded to some other code sequence, or the target has a custom expander 397 /// for it. 398 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const { 399 assert(LType < array_lengthof(LoadExtActions) && 400 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 && 401 "Table isn't big enough!"); 402 return (LegalizeAction)((LoadExtActions[LType] >> 403 (2*VT.getSimpleVT().SimpleTy)) & 3); 404 } 405 406 /// isLoadExtLegal - Return true if the specified load with extension is legal 407 /// on this target. 408 bool isLoadExtLegal(unsigned LType, EVT VT) const { 409 return VT.isSimple() && 410 (getLoadExtAction(LType, VT) == Legal || 411 getLoadExtAction(LType, VT) == Custom); 412 } 413 414 /// getTruncStoreAction - Return how this store with truncation should be 415 /// treated: either it is legal, needs to be promoted to a larger size, needs 416 /// to be expanded to some other code sequence, or the target has a custom 417 /// expander for it. 418 LegalizeAction getTruncStoreAction(EVT ValVT, 419 EVT MemVT) const { 420 assert((unsigned)ValVT.getSimpleVT().SimpleTy < 421 array_lengthof(TruncStoreActions) && 422 (unsigned)MemVT.getSimpleVT().SimpleTy < 423 sizeof(TruncStoreActions[0])*4 && 424 "Table isn't big enough!"); 425 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >> 426 (2*MemVT.getSimpleVT().SimpleTy)) & 3); 427 } 428 429 /// isTruncStoreLegal - Return true if the specified store with truncation is 430 /// legal on this target. 431 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 432 return isTypeLegal(ValVT) && MemVT.isSimple() && 433 (getTruncStoreAction(ValVT, MemVT) == Legal || 434 getTruncStoreAction(ValVT, MemVT) == Custom); 435 } 436 437 /// getIndexedLoadAction - Return how the indexed load should be treated: 438 /// either it is legal, needs to be promoted to a larger size, needs to be 439 /// expanded to some other code sequence, or the target has a custom expander 440 /// for it. 441 LegalizeAction 442 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 443 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) && 444 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE && 445 "Table isn't big enough!"); 446 return (LegalizeAction)((IndexedModeActions[ 447 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode])); 448 } 449 450 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 451 /// on this target. 452 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 453 return VT.isSimple() && 454 (getIndexedLoadAction(IdxMode, VT) == Legal || 455 getIndexedLoadAction(IdxMode, VT) == Custom); 456 } 457 458 /// getIndexedStoreAction - Return how the indexed store should be treated: 459 /// either it is legal, needs to be promoted to a larger size, needs to be 460 /// expanded to some other code sequence, or the target has a custom expander 461 /// for it. 462 LegalizeAction 463 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 464 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) && 465 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE && 466 "Table isn't big enough!"); 467 return (LegalizeAction)((IndexedModeActions[ 468 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode])); 469 } 470 471 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 472 /// on this target. 473 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 474 return VT.isSimple() && 475 (getIndexedStoreAction(IdxMode, VT) == Legal || 476 getIndexedStoreAction(IdxMode, VT) == Custom); 477 } 478 479 /// getConvertAction - Return how the conversion should be treated: 480 /// either it is legal, needs to be promoted to a larger size, needs to be 481 /// expanded to some other code sequence, or the target has a custom expander 482 /// for it. 483 LegalizeAction 484 getConvertAction(EVT FromVT, EVT ToVT) const { 485 assert((unsigned)FromVT.getSimpleVT().SimpleTy < 486 array_lengthof(ConvertActions) && 487 (unsigned)ToVT.getSimpleVT().SimpleTy < 488 sizeof(ConvertActions[0])*4 && 489 "Table isn't big enough!"); 490 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >> 491 (2*ToVT.getSimpleVT().SimpleTy)) & 3); 492 } 493 494 /// isConvertLegal - Return true if the specified conversion is legal 495 /// on this target. 496 bool isConvertLegal(EVT FromVT, EVT ToVT) const { 497 return isTypeLegal(FromVT) && isTypeLegal(ToVT) && 498 (getConvertAction(FromVT, ToVT) == Legal || 499 getConvertAction(FromVT, ToVT) == Custom); 500 } 501 502 /// getCondCodeAction - Return how the condition code should be treated: 503 /// either it is legal, needs to be expanded to some other code sequence, 504 /// or the target has a custom expander for it. 505 LegalizeAction 506 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 507 assert((unsigned)CC < array_lengthof(CondCodeActions) && 508 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 509 "Table isn't big enough!"); 510 LegalizeAction Action = (LegalizeAction) 511 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 512 assert(Action != Promote && "Can't promote condition code!"); 513 return Action; 514 } 515 516 /// isCondCodeLegal - Return true if the specified condition code is legal 517 /// on this target. 518 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 519 return getCondCodeAction(CC, VT) == Legal || 520 getCondCodeAction(CC, VT) == Custom; 521 } 522 523 524 /// getTypeToPromoteTo - If the action for this operation is to promote, this 525 /// method returns the ValueType to promote to. 526 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 527 assert(getOperationAction(Op, VT) == Promote && 528 "This operation isn't promoted!"); 529 530 // See if this has an explicit type specified. 531 std::map<std::pair<unsigned, MVT::SimpleValueType>, 532 MVT::SimpleValueType>::const_iterator PTTI = 533 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 534 if (PTTI != PromoteToType.end()) return PTTI->second; 535 536 assert((VT.isInteger() || VT.isFloatingPoint()) && 537 "Cannot autopromote this type, add it with AddPromotedToType."); 538 539 EVT NVT = VT; 540 do { 541 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 542 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 543 "Didn't find type to promote to!"); 544 } while (!isTypeLegal(NVT) || 545 getOperationAction(Op, NVT) == Promote); 546 return NVT; 547 } 548 549 /// getValueType - Return the EVT corresponding to this LLVM type. 550 /// This is fixed by the LLVM operations except for the pointer size. If 551 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 552 /// counterpart (e.g. structs), otherwise it will assert. 553 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const { 554 EVT VT = EVT::getEVT(Ty, AllowUnknown); 555 return VT == MVT:: iPTR ? PointerTy : VT; 556 } 557 558 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 559 /// function arguments in the caller parameter area. This is the actual 560 /// alignment, not its logarithm. 561 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 562 563 /// getRegisterType - Return the type of registers that this ValueType will 564 /// eventually require. 565 EVT getRegisterType(MVT VT) const { 566 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 567 return RegisterTypeForVT[VT.SimpleTy]; 568 } 569 570 /// getRegisterType - Return the type of registers that this ValueType will 571 /// eventually require. 572 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 573 if (VT.isSimple()) { 574 assert((unsigned)VT.getSimpleVT().SimpleTy < 575 array_lengthof(RegisterTypeForVT)); 576 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 577 } 578 if (VT.isVector()) { 579 EVT VT1, RegisterVT; 580 unsigned NumIntermediates; 581 (void)getVectorTypeBreakdown(Context, VT, VT1, 582 NumIntermediates, RegisterVT); 583 return RegisterVT; 584 } 585 if (VT.isInteger()) { 586 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 587 } 588 assert(0 && "Unsupported extended type!"); 589 return EVT(MVT::Other); // Not reached 590 } 591 592 /// getNumRegisters - Return the number of registers that this ValueType will 593 /// eventually require. This is one for any types promoted to live in larger 594 /// registers, but may be more than one for types (like i64) that are split 595 /// into pieces. For types like i140, which are first promoted then expanded, 596 /// it is the number of registers needed to hold all the bits of the original 597 /// type. For an i140 on a 32 bit machine this means 5 registers. 598 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 599 if (VT.isSimple()) { 600 assert((unsigned)VT.getSimpleVT().SimpleTy < 601 array_lengthof(NumRegistersForVT)); 602 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 603 } 604 if (VT.isVector()) { 605 EVT VT1, VT2; 606 unsigned NumIntermediates; 607 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 608 } 609 if (VT.isInteger()) { 610 unsigned BitWidth = VT.getSizeInBits(); 611 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 612 return (BitWidth + RegWidth - 1) / RegWidth; 613 } 614 assert(0 && "Unsupported extended type!"); 615 return 0; // Not reached 616 } 617 618 /// ShouldShrinkFPConstant - If true, then instruction selection should 619 /// seek to shrink the FP constant of the specified type to a smaller type 620 /// in order to save space and / or reduce runtime. 621 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; } 622 623 /// hasTargetDAGCombine - If true, the target has custom DAG combine 624 /// transformations that it can perform for the specified node. 625 bool hasTargetDAGCombine(ISD::NodeType NT) const { 626 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 627 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 628 } 629 630 /// This function returns the maximum number of store operations permitted 631 /// to replace a call to llvm.memset. The value is set by the target at the 632 /// performance threshold for such a replacement. 633 /// @brief Get maximum # of store operations permitted for llvm.memset 634 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; } 635 636 /// This function returns the maximum number of store operations permitted 637 /// to replace a call to llvm.memcpy. The value is set by the target at the 638 /// performance threshold for such a replacement. 639 /// @brief Get maximum # of store operations permitted for llvm.memcpy 640 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; } 641 642 /// This function returns the maximum number of store operations permitted 643 /// to replace a call to llvm.memmove. The value is set by the target at the 644 /// performance threshold for such a replacement. 645 /// @brief Get maximum # of store operations permitted for llvm.memmove 646 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; } 647 648 /// This function returns true if the target allows unaligned memory accesses. 649 /// of the specified type. This is used, for example, in situations where an 650 /// array copy/move/set is converted to a sequence of store operations. It's 651 /// use helps to ensure that such replacements don't generate code that causes 652 /// an alignment error (trap) on the target machine. 653 /// @brief Determine if the target supports unaligned memory accesses. 654 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 655 return false; 656 } 657 658 /// This function returns true if the target would benefit from code placement 659 /// optimization. 660 /// @brief Determine if the target should perform code placement optimization. 661 bool shouldOptimizeCodePlacement() const { 662 return benefitFromCodePlacementOpt; 663 } 664 665 /// getOptimalMemOpType - Returns the target specific optimal type for load 666 /// and store operations as a result of memset, memcpy, and memmove lowering. 667 /// It returns EVT::iAny if SelectionDAG should be responsible for 668 /// determining it. 669 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, 670 bool isSrcConst, bool isSrcStr, 671 SelectionDAG &DAG) const { 672 return MVT::iAny; 673 } 674 675 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 676 /// to implement llvm.setjmp. 677 bool usesUnderscoreSetJmp() const { 678 return UseUnderscoreSetJmp; 679 } 680 681 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 682 /// to implement llvm.longjmp. 683 bool usesUnderscoreLongJmp() const { 684 return UseUnderscoreLongJmp; 685 } 686 687 /// getStackPointerRegisterToSaveRestore - If a physical register, this 688 /// specifies the register that llvm.savestack/llvm.restorestack should save 689 /// and restore. 690 unsigned getStackPointerRegisterToSaveRestore() const { 691 return StackPointerRegisterToSaveRestore; 692 } 693 694 /// getExceptionAddressRegister - If a physical register, this returns 695 /// the register that receives the exception address on entry to a landing 696 /// pad. 697 unsigned getExceptionAddressRegister() const { 698 return ExceptionPointerRegister; 699 } 700 701 /// getExceptionSelectorRegister - If a physical register, this returns 702 /// the register that receives the exception typeid on entry to a landing 703 /// pad. 704 unsigned getExceptionSelectorRegister() const { 705 return ExceptionSelectorRegister; 706 } 707 708 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 709 /// set, the default is 200) 710 unsigned getJumpBufSize() const { 711 return JumpBufSize; 712 } 713 714 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 715 /// (if never set, the default is 0) 716 unsigned getJumpBufAlignment() const { 717 return JumpBufAlignment; 718 } 719 720 /// getIfCvtBlockLimit - returns the target specific if-conversion block size 721 /// limit. Any block whose size is greater should not be predicated. 722 unsigned getIfCvtBlockSizeLimit() const { 723 return IfCvtBlockSizeLimit; 724 } 725 726 /// getIfCvtDupBlockLimit - returns the target specific size limit for a 727 /// block to be considered for duplication. Any block whose size is greater 728 /// should not be duplicated to facilitate its predication. 729 unsigned getIfCvtDupBlockSizeLimit() const { 730 return IfCvtDupBlockSizeLimit; 731 } 732 733 /// getPrefLoopAlignment - return the preferred loop alignment. 734 /// 735 unsigned getPrefLoopAlignment() const { 736 return PrefLoopAlignment; 737 } 738 739 /// getPreIndexedAddressParts - returns true by value, base pointer and 740 /// offset pointer and addressing mode by reference if the node's address 741 /// can be legally represented as pre-indexed load / store address. 742 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 743 SDValue &Offset, 744 ISD::MemIndexedMode &AM, 745 SelectionDAG &DAG) const { 746 return false; 747 } 748 749 /// getPostIndexedAddressParts - returns true by value, base pointer and 750 /// offset pointer and addressing mode by reference if this node can be 751 /// combined with a load / store to form a post-indexed load / store. 752 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 753 SDValue &Base, SDValue &Offset, 754 ISD::MemIndexedMode &AM, 755 SelectionDAG &DAG) const { 756 return false; 757 } 758 759 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 760 /// current function. The returned value is a member of the 761 /// MachineJumpTableInfo::JTEntryKind enum. 762 virtual unsigned getJumpTableEncoding() const; 763 764 virtual const MCExpr * 765 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 766 const MachineBasicBlock *MBB, unsigned uid, 767 MCContext &Ctx) const { 768 assert(0 && "Need to implement this hook if target has custom JTIs"); 769 return 0; 770 } 771 772 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 773 /// jumptable. 774 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 775 SelectionDAG &DAG) const; 776 777 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 778 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 779 /// MCExpr. 780 virtual const MCExpr * 781 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 782 unsigned JTI, MCContext &Ctx) const; 783 784 /// isOffsetFoldingLegal - Return true if folding a constant offset 785 /// with the given GlobalAddress is legal. It is frequently not legal in 786 /// PIC relocation models. 787 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 788 789 /// getFunctionAlignment - Return the Log2 alignment of this function. 790 virtual unsigned getFunctionAlignment(const Function *) const = 0; 791 792 //===--------------------------------------------------------------------===// 793 // TargetLowering Optimization Methods 794 // 795 796 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 797 /// SDValues for returning information from TargetLowering to its clients 798 /// that want to combine 799 struct TargetLoweringOpt { 800 SelectionDAG &DAG; 801 bool ShrinkOps; 802 SDValue Old; 803 SDValue New; 804 805 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool Shrink = false) : 806 DAG(InDAG), ShrinkOps(Shrink) {} 807 808 bool CombineTo(SDValue O, SDValue N) { 809 Old = O; 810 New = N; 811 return true; 812 } 813 814 /// ShrinkDemandedConstant - Check to see if the specified operand of the 815 /// specified instruction is a constant integer. If so, check to see if 816 /// there are any bits set in the constant that are not demanded. If so, 817 /// shrink the constant and return true. 818 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 819 820 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 821 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 822 /// cast, but it could be generalized for targets with other types of 823 /// implicit widening casts. 824 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 825 DebugLoc dl); 826 }; 827 828 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 829 /// DemandedMask bits of the result of Op are ever used downstream. If we can 830 /// use this information to simplify Op, create a new simplified DAG node and 831 /// return true, returning the original and new nodes in Old and New. 832 /// Otherwise, analyze the expression and return a mask of KnownOne and 833 /// KnownZero bits for the expression (used to simplify the caller). 834 /// The KnownZero/One bits may only be accurate for those bits in the 835 /// DemandedMask. 836 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 837 APInt &KnownZero, APInt &KnownOne, 838 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 839 840 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 841 /// Mask are known to be either zero or one and return them in the 842 /// KnownZero/KnownOne bitsets. 843 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 844 const APInt &Mask, 845 APInt &KnownZero, 846 APInt &KnownOne, 847 const SelectionDAG &DAG, 848 unsigned Depth = 0) const; 849 850 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 851 /// targets that want to expose additional information about sign bits to the 852 /// DAG Combiner. 853 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 854 unsigned Depth = 0) const; 855 856 struct DAGCombinerInfo { 857 void *DC; // The DAG Combiner object. 858 bool BeforeLegalize; 859 bool BeforeLegalizeOps; 860 bool CalledByLegalizer; 861 public: 862 SelectionDAG &DAG; 863 864 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 865 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 866 CalledByLegalizer(cl), DAG(dag) {} 867 868 bool isBeforeLegalize() const { return BeforeLegalize; } 869 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } 870 bool isCalledByLegalizer() const { return CalledByLegalizer; } 871 872 void AddToWorklist(SDNode *N); 873 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 874 bool AddTo = true); 875 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 876 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 877 878 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 879 }; 880 881 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 882 /// and cc. If it is unable to simplify it, return a null SDValue. 883 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 884 ISD::CondCode Cond, bool foldBooleans, 885 DAGCombinerInfo &DCI, DebugLoc dl) const; 886 887 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 888 /// node is a GlobalAddress + offset. 889 virtual bool 890 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 891 892 /// PerformDAGCombine - This method will be invoked for all target nodes and 893 /// for any target-independent nodes that the target has registered with 894 /// invoke it for. 895 /// 896 /// The semantics are as follows: 897 /// Return Value: 898 /// SDValue.Val == 0 - No change was made 899 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 900 /// otherwise - N should be replaced by the returned Operand. 901 /// 902 /// In addition, methods provided by DAGCombinerInfo may be used to perform 903 /// more complex transformations. 904 /// 905 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 906 907 //===--------------------------------------------------------------------===// 908 // TargetLowering Configuration Methods - These methods should be invoked by 909 // the derived class constructor to configure this object for the target. 910 // 911 912protected: 913 /// setShiftAmountType - Describe the type that should be used for shift 914 /// amounts. This type defaults to the pointer type. 915 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; } 916 917 /// setBooleanContents - Specify how the target extends the result of a 918 /// boolean value from i1 to a wider type. See getBooleanContents. 919 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 920 921 /// setSchedulingPreference - Specify the target scheduling preference. 922 void setSchedulingPreference(SchedPreference Pref) { 923 SchedPreferenceInfo = Pref; 924 } 925 926 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 927 /// use _setjmp to implement llvm.setjmp or the non _ version. 928 /// Defaults to false. 929 void setUseUnderscoreSetJmp(bool Val) { 930 UseUnderscoreSetJmp = Val; 931 } 932 933 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 934 /// use _longjmp to implement llvm.longjmp or the non _ version. 935 /// Defaults to false. 936 void setUseUnderscoreLongJmp(bool Val) { 937 UseUnderscoreLongJmp = Val; 938 } 939 940 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 941 /// specifies the register that llvm.savestack/llvm.restorestack should save 942 /// and restore. 943 void setStackPointerRegisterToSaveRestore(unsigned R) { 944 StackPointerRegisterToSaveRestore = R; 945 } 946 947 /// setExceptionPointerRegister - If set to a physical register, this sets 948 /// the register that receives the exception address on entry to a landing 949 /// pad. 950 void setExceptionPointerRegister(unsigned R) { 951 ExceptionPointerRegister = R; 952 } 953 954 /// setExceptionSelectorRegister - If set to a physical register, this sets 955 /// the register that receives the exception typeid on entry to a landing 956 /// pad. 957 void setExceptionSelectorRegister(unsigned R) { 958 ExceptionSelectorRegister = R; 959 } 960 961 /// SelectIsExpensive - Tells the code generator not to expand operations 962 /// into sequences that use the select operations if possible. 963 void setSelectIsExpensive() { SelectIsExpensive = true; } 964 965 /// setIntDivIsCheap - Tells the code generator that integer divide is 966 /// expensive, and if possible, should be replaced by an alternate sequence 967 /// of instructions not containing an integer divide. 968 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 969 970 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 971 /// srl/add/sra for a signed divide by power of two, and let the target handle 972 /// it. 973 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 974 975 /// addRegisterClass - Add the specified register class as an available 976 /// regclass for the specified value type. This indicates the selector can 977 /// handle values of that class natively. 978 void addRegisterClass(EVT VT, TargetRegisterClass *RC) { 979 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 980 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 981 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 982 } 983 984 /// computeRegisterProperties - Once all of the register classes are added, 985 /// this allows us to compute derived properties we expose. 986 void computeRegisterProperties(); 987 988 /// setOperationAction - Indicate that the specified operation does not work 989 /// with the specified type and indicate what to do about it. 990 void setOperationAction(unsigned Op, MVT VT, 991 LegalizeAction Action) { 992 unsigned I = (unsigned)VT.SimpleTy; 993 unsigned J = I & 31; 994 I = I >> 5; 995 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2)); 996 OpActions[I][Op] |= (uint64_t)Action << (J*2); 997 } 998 999 /// setLoadExtAction - Indicate that the specified load with extension does 1000 /// not work with the with specified type and indicate what to do about it. 1001 void setLoadExtAction(unsigned ExtType, MVT VT, 1002 LegalizeAction Action) { 1003 assert((unsigned)VT.SimpleTy*2 < 63 && 1004 ExtType < array_lengthof(LoadExtActions) && 1005 "Table isn't big enough!"); 1006 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1007 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2; 1008 } 1009 1010 /// setTruncStoreAction - Indicate that the specified truncating store does 1011 /// not work with the with specified type and indicate what to do about it. 1012 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1013 LegalizeAction Action) { 1014 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) && 1015 (unsigned)MemVT.SimpleTy*2 < 63 && 1016 "Table isn't big enough!"); 1017 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2); 1018 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2; 1019 } 1020 1021 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1022 /// does not work with the with specified type and indicate what to do abort 1023 /// it. NOTE: All indexed mode loads are initialized to Expand in 1024 /// TargetLowering.cpp 1025 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1026 LegalizeAction Action) { 1027 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1028 IdxMode < array_lengthof(IndexedModeActions[0][0]) && 1029 "Table isn't big enough!"); 1030 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action; 1031 } 1032 1033 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1034 /// does not work with the with specified type and indicate what to do about 1035 /// it. NOTE: All indexed mode stores are initialized to Expand in 1036 /// TargetLowering.cpp 1037 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1038 LegalizeAction Action) { 1039 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1040 IdxMode < array_lengthof(IndexedModeActions[0][1] ) && 1041 "Table isn't big enough!"); 1042 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action; 1043 } 1044 1045 /// setConvertAction - Indicate that the specified conversion does or does 1046 /// not work with the with specified type and indicate what to do about it. 1047 void setConvertAction(MVT FromVT, MVT ToVT, 1048 LegalizeAction Action) { 1049 assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) && 1050 (unsigned)ToVT.SimpleTy < MVT::LAST_VALUETYPE && 1051 "Table isn't big enough!"); 1052 ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2); 1053 ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2; 1054 } 1055 1056 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1057 /// supported on the target and indicate what to do about it. 1058 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1059 LegalizeAction Action) { 1060 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE && 1061 (unsigned)CC < array_lengthof(CondCodeActions) && 1062 "Table isn't big enough!"); 1063 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1064 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1065 } 1066 1067 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1068 /// promotion code defaults to trying a larger integer/fp until it can find 1069 /// one that works. If that default is insufficient, this method can be used 1070 /// by the target to override the default. 1071 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1072 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1073 } 1074 1075 /// setTargetDAGCombine - Targets should invoke this method for each target 1076 /// independent node that they want to provide a custom DAG combiner for by 1077 /// implementing the PerformDAGCombine virtual method. 1078 void setTargetDAGCombine(ISD::NodeType NT) { 1079 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1080 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1081 } 1082 1083 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1084 /// bytes); default is 200 1085 void setJumpBufSize(unsigned Size) { 1086 JumpBufSize = Size; 1087 } 1088 1089 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1090 /// alignment (in bytes); default is 0 1091 void setJumpBufAlignment(unsigned Align) { 1092 JumpBufAlignment = Align; 1093 } 1094 1095 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size 1096 /// limit (in number of instructions); default is 2. 1097 void setIfCvtBlockSizeLimit(unsigned Limit) { 1098 IfCvtBlockSizeLimit = Limit; 1099 } 1100 1101 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number 1102 /// of instructions) to be considered for code duplication during 1103 /// if-conversion; default is 2. 1104 void setIfCvtDupBlockSizeLimit(unsigned Limit) { 1105 IfCvtDupBlockSizeLimit = Limit; 1106 } 1107 1108 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1109 /// alignment is zero, it means the target does not care about loop alignment. 1110 void setPrefLoopAlignment(unsigned Align) { 1111 PrefLoopAlignment = Align; 1112 } 1113 1114public: 1115 1116 virtual const TargetSubtarget *getSubtarget() { 1117 assert(0 && "Not Implemented"); 1118 return NULL; // this is here to silence compiler errors 1119 } 1120 1121 //===--------------------------------------------------------------------===// 1122 // Lowering methods - These methods must be implemented by targets so that 1123 // the SelectionDAGLowering code knows how to lower these. 1124 // 1125 1126 /// LowerFormalArguments - This hook must be implemented to lower the 1127 /// incoming (formal) arguments, described by the Ins array, into the 1128 /// specified DAG. The implementation should fill in the InVals array 1129 /// with legal-type argument values, and return the resulting token 1130 /// chain value. 1131 /// 1132 virtual SDValue 1133 LowerFormalArguments(SDValue Chain, 1134 CallingConv::ID CallConv, bool isVarArg, 1135 const SmallVectorImpl<ISD::InputArg> &Ins, 1136 DebugLoc dl, SelectionDAG &DAG, 1137 SmallVectorImpl<SDValue> &InVals) { 1138 assert(0 && "Not Implemented"); 1139 return SDValue(); // this is here to silence compiler errors 1140 } 1141 1142 /// LowerCallTo - This function lowers an abstract call to a function into an 1143 /// actual call. This returns a pair of operands. The first element is the 1144 /// return value for the function (if RetTy is not VoidTy). The second 1145 /// element is the outgoing token chain. It calls LowerCall to do the actual 1146 /// lowering. 1147 struct ArgListEntry { 1148 SDValue Node; 1149 const Type* Ty; 1150 bool isSExt : 1; 1151 bool isZExt : 1; 1152 bool isInReg : 1; 1153 bool isSRet : 1; 1154 bool isNest : 1; 1155 bool isByVal : 1; 1156 uint16_t Alignment; 1157 1158 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1159 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1160 }; 1161 typedef std::vector<ArgListEntry> ArgListTy; 1162 std::pair<SDValue, SDValue> 1163 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt, 1164 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1165 CallingConv::ID CallConv, bool isTailCall, 1166 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1167 SelectionDAG &DAG, DebugLoc dl, unsigned Order); 1168 1169 /// LowerCall - This hook must be implemented to lower calls into the 1170 /// the specified DAG. The outgoing arguments to the call are described 1171 /// by the Outs array, and the values to be returned by the call are 1172 /// described by the Ins array. The implementation should fill in the 1173 /// InVals array with legal-type return values from the call, and return 1174 /// the resulting token chain value. 1175 virtual SDValue 1176 LowerCall(SDValue Chain, SDValue Callee, 1177 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 1178 const SmallVectorImpl<ISD::OutputArg> &Outs, 1179 const SmallVectorImpl<ISD::InputArg> &Ins, 1180 DebugLoc dl, SelectionDAG &DAG, 1181 SmallVectorImpl<SDValue> &InVals) { 1182 assert(0 && "Not Implemented"); 1183 return SDValue(); // this is here to silence compiler errors 1184 } 1185 1186 /// CanLowerReturn - This hook should be implemented to check whether the 1187 /// return values described by the Outs array can fit into the return 1188 /// registers. If false is returned, an sret-demotion is performed. 1189 /// 1190 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 1191 const SmallVectorImpl<EVT> &OutTys, 1192 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 1193 SelectionDAG &DAG) 1194 { 1195 // Return true by default to get preexisting behavior. 1196 return true; 1197 } 1198 /// LowerReturn - This hook must be implemented to lower outgoing 1199 /// return values, described by the Outs array, into the specified 1200 /// DAG. The implementation should return the resulting token chain 1201 /// value. 1202 /// 1203 virtual SDValue 1204 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1205 const SmallVectorImpl<ISD::OutputArg> &Outs, 1206 DebugLoc dl, SelectionDAG &DAG) { 1207 assert(0 && "Not Implemented"); 1208 return SDValue(); // this is here to silence compiler errors 1209 } 1210 1211 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a 1212 /// memcpy. This can be used by targets to provide code sequences for cases 1213 /// that don't fit the target's parameters for simple loads/stores and can be 1214 /// more efficient than using a library call. This function can return a null 1215 /// SDValue if the target declines to use custom code and a different 1216 /// lowering strategy should be used. 1217 /// 1218 /// If AlwaysInline is true, the size is constant and the target should not 1219 /// emit any calls and is strongly encouraged to attempt to emit inline code 1220 /// even if it is beyond the usual threshold because this intrinsic is being 1221 /// expanded in a place where calls are not feasible (e.g. within the prologue 1222 /// for another call). If the target chooses to decline an AlwaysInline 1223 /// request here, legalize will resort to using simple loads and stores. 1224 virtual SDValue 1225 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1226 SDValue Chain, 1227 SDValue Op1, SDValue Op2, 1228 SDValue Op3, unsigned Align, 1229 bool AlwaysInline, 1230 const Value *DstSV, uint64_t DstOff, 1231 const Value *SrcSV, uint64_t SrcOff) { 1232 return SDValue(); 1233 } 1234 1235 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a 1236 /// memmove. This can be used by targets to provide code sequences for cases 1237 /// that don't fit the target's parameters for simple loads/stores and can be 1238 /// more efficient than using a library call. This function can return a null 1239 /// SDValue if the target declines to use custom code and a different 1240 /// lowering strategy should be used. 1241 virtual SDValue 1242 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, 1243 SDValue Chain, 1244 SDValue Op1, SDValue Op2, 1245 SDValue Op3, unsigned Align, 1246 const Value *DstSV, uint64_t DstOff, 1247 const Value *SrcSV, uint64_t SrcOff) { 1248 return SDValue(); 1249 } 1250 1251 /// EmitTargetCodeForMemset - Emit target-specific code that performs a 1252 /// memset. This can be used by targets to provide code sequences for cases 1253 /// that don't fit the target's parameters for simple stores and can be more 1254 /// efficient than using a library call. This function can return a null 1255 /// SDValue if the target declines to use custom code and a different 1256 /// lowering strategy should be used. 1257 virtual SDValue 1258 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 1259 SDValue Chain, 1260 SDValue Op1, SDValue Op2, 1261 SDValue Op3, unsigned Align, 1262 const Value *DstSV, uint64_t DstOff) { 1263 return SDValue(); 1264 } 1265 1266 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1267 /// to legalize nodes with an illegal operand type but legal result types. 1268 /// It replaces the LowerOperation callback in the type Legalizer. 1269 /// The reason we can not do away with LowerOperation entirely is that 1270 /// LegalizeDAG isn't yet ready to use this callback. 1271 /// TODO: Consider merging with ReplaceNodeResults. 1272 1273 /// The target places new result values for the node in Results (their number 1274 /// and types must exactly match those of the original return values of 1275 /// the node), or leaves Results empty, which indicates that the node is not 1276 /// to be custom lowered after all. 1277 /// The default implementation calls LowerOperation. 1278 virtual void LowerOperationWrapper(SDNode *N, 1279 SmallVectorImpl<SDValue> &Results, 1280 SelectionDAG &DAG); 1281 1282 /// LowerOperation - This callback is invoked for operations that are 1283 /// unsupported by the target, which are registered to use 'custom' lowering, 1284 /// and whose defined values are all legal. 1285 /// If the target has no operations that require custom lowering, it need not 1286 /// implement this. The default implementation of this aborts. 1287 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1288 1289 /// ReplaceNodeResults - This callback is invoked when a node result type is 1290 /// illegal for the target, and the operation was registered to use 'custom' 1291 /// lowering for that result type. The target places new result values for 1292 /// the node in Results (their number and types must exactly match those of 1293 /// the original return values of the node), or leaves Results empty, which 1294 /// indicates that the node is not to be custom lowered after all. 1295 /// 1296 /// If the target has no operations that require custom lowering, it need not 1297 /// implement this. The default implementation aborts. 1298 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1299 SelectionDAG &DAG) { 1300 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1301 } 1302 1303 /// getTargetNodeName() - This method returns the name of a target specific 1304 /// DAG node. 1305 virtual const char *getTargetNodeName(unsigned Opcode) const; 1306 1307 /// createFastISel - This method returns a target specific FastISel object, 1308 /// or null if the target does not support "fast" ISel. 1309 virtual FastISel * 1310 createFastISel(MachineFunction &, 1311 MachineModuleInfo *, DwarfWriter *, 1312 DenseMap<const Value *, unsigned> &, 1313 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 1314 DenseMap<const AllocaInst *, int> & 1315#ifndef NDEBUG 1316 , SmallSet<Instruction*, 8> &CatchInfoLost 1317#endif 1318 ) { 1319 return 0; 1320 } 1321 1322 //===--------------------------------------------------------------------===// 1323 // Inline Asm Support hooks 1324 // 1325 1326 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1327 /// call to be explicit llvm code if it wants to. This is useful for 1328 /// turning simple inline asms into LLVM intrinsics, which gives the 1329 /// compiler more information about the behavior of the code. 1330 virtual bool ExpandInlineAsm(CallInst *CI) const { 1331 return false; 1332 } 1333 1334 enum ConstraintType { 1335 C_Register, // Constraint represents specific register(s). 1336 C_RegisterClass, // Constraint represents any of register(s) in class. 1337 C_Memory, // Memory constraint. 1338 C_Other, // Something else. 1339 C_Unknown // Unsupported constraint. 1340 }; 1341 1342 /// AsmOperandInfo - This contains information for each constraint that we are 1343 /// lowering. 1344 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1345 /// ConstraintCode - This contains the actual string for the code, like "m". 1346 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1347 /// most closely matches the operand. 1348 std::string ConstraintCode; 1349 1350 /// ConstraintType - Information about the constraint code, e.g. Register, 1351 /// RegisterClass, Memory, Other, Unknown. 1352 TargetLowering::ConstraintType ConstraintType; 1353 1354 /// CallOperandval - If this is the result output operand or a 1355 /// clobber, this is null, otherwise it is the incoming operand to the 1356 /// CallInst. This gets modified as the asm is processed. 1357 Value *CallOperandVal; 1358 1359 /// ConstraintVT - The ValueType for the operand value. 1360 EVT ConstraintVT; 1361 1362 /// isMatchingInputConstraint - Return true of this is an input operand that 1363 /// is a matching constraint like "4". 1364 bool isMatchingInputConstraint() const; 1365 1366 /// getMatchedOperand - If this is an input matching constraint, this method 1367 /// returns the output operand it matches. 1368 unsigned getMatchedOperand() const; 1369 1370 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1371 : InlineAsm::ConstraintInfo(info), 1372 ConstraintType(TargetLowering::C_Unknown), 1373 CallOperandVal(0), ConstraintVT(MVT::Other) { 1374 } 1375 }; 1376 1377 /// ComputeConstraintToUse - Determines the constraint code and constraint 1378 /// type to use for the specific AsmOperandInfo, setting 1379 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1380 /// being passed in is available, it can be passed in as Op, otherwise an 1381 /// empty SDValue can be passed. If hasMemory is true it means one of the asm 1382 /// constraint of the inline asm instruction being processed is 'm'. 1383 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1384 SDValue Op, 1385 bool hasMemory, 1386 SelectionDAG *DAG = 0) const; 1387 1388 /// getConstraintType - Given a constraint, return the type of constraint it 1389 /// is for this target. 1390 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1391 1392 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), 1393 /// return a list of registers that can be used to satisfy the constraint. 1394 /// This should only be used for C_RegisterClass constraints. 1395 virtual std::vector<unsigned> 1396 getRegClassForInlineAsmConstraint(const std::string &Constraint, 1397 EVT VT) const; 1398 1399 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1400 /// {edx}), return the register number and the register class for the 1401 /// register. 1402 /// 1403 /// Given a register class constraint, like 'r', if this corresponds directly 1404 /// to an LLVM register class, return a register of 0 and the register class 1405 /// pointer. 1406 /// 1407 /// This should only be used for C_Register constraints. On error, 1408 /// this returns a register number of 0 and a null register class pointer.. 1409 virtual std::pair<unsigned, const TargetRegisterClass*> 1410 getRegForInlineAsmConstraint(const std::string &Constraint, 1411 EVT VT) const; 1412 1413 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1414 /// with another that has more specific requirements based on the type of the 1415 /// corresponding operand. This returns null if there is no replacement to 1416 /// make. 1417 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1418 1419 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1420 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true 1421 /// it means one of the asm constraint of the inline asm instruction being 1422 /// processed is 'm'. 1423 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, 1424 bool hasMemory, 1425 std::vector<SDValue> &Ops, 1426 SelectionDAG &DAG) const; 1427 1428 //===--------------------------------------------------------------------===// 1429 // Instruction Emitting Hooks 1430 // 1431 1432 // EmitInstrWithCustomInserter - This method should be implemented by targets 1433 // that mark instructions with the 'usesCustomInserter' flag. These 1434 // instructions are special in various ways, which require special support to 1435 // insert. The specified MachineInstr is created but not inserted into any 1436 // basic blocks, and this method is called to expand it into a sequence of 1437 // instructions, potentially also creating new basic blocks and control flow. 1438 // When new basic blocks are inserted and the edges from MBB to its successors 1439 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the 1440 // DenseMap. 1441 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1442 MachineBasicBlock *MBB, 1443 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 1444 1445 //===--------------------------------------------------------------------===// 1446 // Addressing mode description hooks (used by LSR etc). 1447 // 1448 1449 /// AddrMode - This represents an addressing mode of: 1450 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1451 /// If BaseGV is null, there is no BaseGV. 1452 /// If BaseOffs is zero, there is no base offset. 1453 /// If HasBaseReg is false, there is no base register. 1454 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1455 /// no scale. 1456 /// 1457 struct AddrMode { 1458 GlobalValue *BaseGV; 1459 int64_t BaseOffs; 1460 bool HasBaseReg; 1461 int64_t Scale; 1462 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1463 }; 1464 1465 /// isLegalAddressingMode - Return true if the addressing mode represented by 1466 /// AM is legal for this target, for a load/store of the specified type. 1467 /// The type may be VoidTy, in which case only return true if the addressing 1468 /// mode is legal for a load/store of any legal type. 1469 /// TODO: Handle pre/postinc as well. 1470 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const; 1471 1472 /// isTruncateFree - Return true if it's free to truncate a value of 1473 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1474 /// register EAX to i16 by referencing its sub-register AX. 1475 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const { 1476 return false; 1477 } 1478 1479 virtual bool isTruncateFree(EVT VT1, EVT VT2) const { 1480 return false; 1481 } 1482 1483 /// isZExtFree - Return true if any actual instruction that defines a 1484 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1485 /// register. This does not necessarily include registers defined in 1486 /// unknown ways, such as incoming arguments, or copies from unknown 1487 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1488 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1489 /// all instructions that define 32-bit values implicit zero-extend the 1490 /// result out to 64 bits. 1491 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const { 1492 return false; 1493 } 1494 1495 virtual bool isZExtFree(EVT VT1, EVT VT2) const { 1496 return false; 1497 } 1498 1499 /// isNarrowingProfitable - Return true if it's profitable to narrow 1500 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1501 /// from i32 to i8 but not from i32 to i16. 1502 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const { 1503 return false; 1504 } 1505 1506 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1507 /// icmp immediate, that is the target has icmp instructions which can compare 1508 /// a register against the immediate without having to materialize the 1509 /// immediate into a register. 1510 virtual bool isLegalICmpImmediate(int64_t Imm) const { 1511 return true; 1512 } 1513 1514 //===--------------------------------------------------------------------===// 1515 // Div utility functions 1516 // 1517 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1518 std::vector<SDNode*>* Created) const; 1519 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1520 std::vector<SDNode*>* Created) const; 1521 1522 1523 //===--------------------------------------------------------------------===// 1524 // Runtime Library hooks 1525 // 1526 1527 /// setLibcallName - Rename the default libcall routine name for the specified 1528 /// libcall. 1529 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1530 LibcallRoutineNames[Call] = Name; 1531 } 1532 1533 /// getLibcallName - Get the libcall routine name for the specified libcall. 1534 /// 1535 const char *getLibcallName(RTLIB::Libcall Call) const { 1536 return LibcallRoutineNames[Call]; 1537 } 1538 1539 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1540 /// result of the comparison libcall against zero. 1541 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1542 CmpLibcallCCs[Call] = CC; 1543 } 1544 1545 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1546 /// the comparison libcall against zero. 1547 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1548 return CmpLibcallCCs[Call]; 1549 } 1550 1551 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1552 /// specified libcall. 1553 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1554 LibcallCallingConvs[Call] = CC; 1555 } 1556 1557 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1558 /// specified libcall. 1559 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1560 return LibcallCallingConvs[Call]; 1561 } 1562 1563private: 1564 TargetMachine &TM; 1565 const TargetData *TD; 1566 TargetLoweringObjectFile &TLOF; 1567 1568 /// PointerTy - The type to use for pointers, usually i32 or i64. 1569 /// 1570 MVT PointerTy; 1571 1572 /// IsLittleEndian - True if this is a little endian target. 1573 /// 1574 bool IsLittleEndian; 1575 1576 /// SelectIsExpensive - Tells the code generator not to expand operations 1577 /// into sequences that use the select operations if possible. 1578 bool SelectIsExpensive; 1579 1580 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1581 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1582 /// a real cost model is in place. If we ever optimize for size, this will be 1583 /// set to true unconditionally. 1584 bool IntDivIsCheap; 1585 1586 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1587 /// srl/add/sra for a signed divide by power of two, and let the target handle 1588 /// it. 1589 bool Pow2DivIsCheap; 1590 1591 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1592 /// llvm.setjmp. Defaults to false. 1593 bool UseUnderscoreSetJmp; 1594 1595 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1596 /// llvm.longjmp. Defaults to false. 1597 bool UseUnderscoreLongJmp; 1598 1599 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever 1600 /// PointerTy is. 1601 MVT ShiftAmountTy; 1602 1603 /// BooleanContents - Information about the contents of the high-bits in 1604 /// boolean values held in a type wider than i1. See getBooleanContents. 1605 BooleanContent BooleanContents; 1606 1607 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1608 /// total cycles or lowest register usage. 1609 SchedPreference SchedPreferenceInfo; 1610 1611 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1612 unsigned JumpBufSize; 1613 1614 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1615 /// buffers 1616 unsigned JumpBufAlignment; 1617 1618 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be 1619 /// if-converted. 1620 unsigned IfCvtBlockSizeLimit; 1621 1622 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be 1623 /// duplicated during if-conversion. 1624 unsigned IfCvtDupBlockSizeLimit; 1625 1626 /// PrefLoopAlignment - The perferred loop alignment. 1627 /// 1628 unsigned PrefLoopAlignment; 1629 1630 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1631 /// specifies the register that llvm.savestack/llvm.restorestack should save 1632 /// and restore. 1633 unsigned StackPointerRegisterToSaveRestore; 1634 1635 /// ExceptionPointerRegister - If set to a physical register, this specifies 1636 /// the register that receives the exception address on entry to a landing 1637 /// pad. 1638 unsigned ExceptionPointerRegister; 1639 1640 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1641 /// the register that receives the exception typeid on entry to a landing 1642 /// pad. 1643 unsigned ExceptionSelectorRegister; 1644 1645 /// RegClassForVT - This indicates the default register class to use for 1646 /// each ValueType the target supports natively. 1647 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1648 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1649 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1650 1651 /// TransformToType - For any value types we are promoting or expanding, this 1652 /// contains the value type that we are changing to. For Expanded types, this 1653 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1654 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1655 /// by the system, this holds the same type (e.g. i32 -> i32). 1656 EVT TransformToType[MVT::LAST_VALUETYPE]; 1657 1658 /// OpActions - For each operation and each value type, keep a LegalizeAction 1659 /// that indicates how instruction selection should deal with the operation. 1660 /// Most operations are Legal (aka, supported natively by the target), but 1661 /// operations that are not should be described. Note that operations on 1662 /// non-legal value types are not described here. 1663 /// This array is accessed using VT.getSimpleVT(), so it is subject to 1664 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits. 1665 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END]; 1666 1667 /// LoadExtActions - For each load of load extension type and each value type, 1668 /// keep a LegalizeAction that indicates how instruction selection should deal 1669 /// with the load. 1670 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE]; 1671 1672 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that 1673 /// indicates how instruction selection should deal with the store. 1674 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE]; 1675 1676 /// IndexedModeActions - For each indexed mode and each value type, 1677 /// keep a pair of LegalizeAction that indicates how instruction 1678 /// selection should deal with the load / store. The first 1679 /// dimension is now the value_type for the reference. The second 1680 /// dimension is the load [0] vs. store[1]. The third dimension 1681 /// represents the various modes for load store. 1682 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE]; 1683 1684 /// ConvertActions - For each conversion from source type to destination type, 1685 /// keep a LegalizeAction that indicates how instruction selection should 1686 /// deal with the conversion. 1687 /// Currently, this is used only for floating->floating conversions 1688 /// (FP_EXTEND and FP_ROUND). 1689 uint64_t ConvertActions[MVT::LAST_VALUETYPE]; 1690 1691 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1692 /// LegalizeAction that indicates how instruction selection should 1693 /// deal with the condition code. 1694 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1695 1696 ValueTypeActionImpl ValueTypeActions; 1697 1698 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1699 1700 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1701 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1702 /// which sets a bit in this array. 1703 unsigned char 1704 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1705 1706 /// PromoteToType - For operations that must be promoted to a specific type, 1707 /// this holds the destination type. This map should be sparse, so don't hold 1708 /// it as an array. 1709 /// 1710 /// Targets add entries to this map with AddPromotedToType(..), clients access 1711 /// this with getTypeToPromoteTo(..). 1712 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1713 PromoteToType; 1714 1715 /// LibcallRoutineNames - Stores the name each libcall. 1716 /// 1717 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1718 1719 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1720 /// of each of the comparison libcall against zero. 1721 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1722 1723 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1724 /// libcall. 1725 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1726 1727protected: 1728 /// When lowering \@llvm.memset this field specifies the maximum number of 1729 /// store operations that may be substituted for the call to memset. Targets 1730 /// must set this value based on the cost threshold for that target. Targets 1731 /// should assume that the memset will be done using as many of the largest 1732 /// store operations first, followed by smaller ones, if necessary, per 1733 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1734 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1735 /// store. This only applies to setting a constant array of a constant size. 1736 /// @brief Specify maximum number of store instructions per memset call. 1737 unsigned maxStoresPerMemset; 1738 1739 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1740 /// store operations that may be substituted for a call to memcpy. Targets 1741 /// must set this value based on the cost threshold for that target. Targets 1742 /// should assume that the memcpy will be done using as many of the largest 1743 /// store operations first, followed by smaller ones, if necessary, per 1744 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1745 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1746 /// and one 1-byte store. This only applies to copying a constant array of 1747 /// constant size. 1748 /// @brief Specify maximum bytes of store instructions per memcpy call. 1749 unsigned maxStoresPerMemcpy; 1750 1751 /// When lowering \@llvm.memmove this field specifies the maximum number of 1752 /// store instructions that may be substituted for a call to memmove. Targets 1753 /// must set this value based on the cost threshold for that target. Targets 1754 /// should assume that the memmove will be done using as many of the largest 1755 /// store operations first, followed by smaller ones, if necessary, per 1756 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 1757 /// with 8-bit alignment would result in nine 1-byte stores. This only 1758 /// applies to copying a constant array of constant size. 1759 /// @brief Specify maximum bytes of store instructions per memmove call. 1760 unsigned maxStoresPerMemmove; 1761 1762 /// This field specifies whether the target can benefit from code placement 1763 /// optimization. 1764 bool benefitFromCodePlacementOpt; 1765}; 1766} // end llvm namespace 1767 1768#endif 1769