ScheduleDAGInstrs.h revision 234285 
1272343Sngie//==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
2272343Sngie//
3272343Sngie//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ScheduleDAGInstrs class, which implements
11// scheduling for a MachineInstr-based dependency graph.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SCHEDULEDAGINSTRS_H
16#define SCHEDULEDAGINSTRS_H
17
18#include "llvm/CodeGen/MachineDominators.h"
19#include "llvm/CodeGen/MachineLoopInfo.h"
20#include "llvm/CodeGen/ScheduleDAG.h"
21#include "llvm/Support/Compiler.h"
22#include "llvm/Target/TargetRegisterInfo.h"
23#include "llvm/ADT/SmallSet.h"
24#include "llvm/ADT/SparseSet.h"
25#include <map>
26
27namespace llvm {
28  class MachineLoopInfo;
29  class MachineDominatorTree;
30  class LiveIntervals;
31
32  /// LoopDependencies - This class analyzes loop-oriented register
33  /// dependencies, which are used to guide scheduling decisions.
34  /// For example, loop induction variable increments should be
35  /// scheduled as soon as possible after the variable's last use.
36  ///
37  class LoopDependencies {
38    const MachineLoopInfo &MLI;
39    const MachineDominatorTree &MDT;
40
41  public:
42    typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
43      LoopDeps;
44    LoopDeps Deps;
45
46    LoopDependencies(const MachineLoopInfo &mli,
47                     const MachineDominatorTree &mdt) :
48      MLI(mli), MDT(mdt) {}
49
50    /// VisitLoop - Clear out any previous state and analyze the given loop.
51    ///
52    void VisitLoop(const MachineLoop *Loop) {
53      assert(Deps.empty() && "stale loop dependencies");
54
55      MachineBasicBlock *Header = Loop->getHeader();
56      SmallSet<unsigned, 8> LoopLiveIns;
57      for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
58           LE = Header->livein_end(); LI != LE; ++LI)
59        LoopLiveIns.insert(*LI);
60
61      const MachineDomTreeNode *Node = MDT.getNode(Header);
62      const MachineBasicBlock *MBB = Node->getBlock();
63      assert(Loop->contains(MBB) &&
64             "Loop does not contain header!");
65      VisitRegion(Node, MBB, Loop, LoopLiveIns);
66    }
67
68  private:
69    void VisitRegion(const MachineDomTreeNode *Node,
70                     const MachineBasicBlock *MBB,
71                     const MachineLoop *Loop,
72                     const SmallSet<unsigned, 8> &LoopLiveIns) {
73      unsigned Count = 0;
74      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
75           I != E; ++I) {
76        const MachineInstr *MI = I;
77        if (MI->isDebugValue())
78          continue;
79        for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
80          const MachineOperand &MO = MI->getOperand(i);
81          if (!MO.isReg() || !MO.isUse())
82            continue;
83          unsigned MOReg = MO.getReg();
84          if (LoopLiveIns.count(MOReg))
85            Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
86        }
87        ++Count; // Not every iteration due to dbg_value above.
88      }
89
90      const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
91      for (std::vector<MachineDomTreeNode*>::const_iterator I =
92           Children.begin(), E = Children.end(); I != E; ++I) {
93        const MachineDomTreeNode *ChildNode = *I;
94        MachineBasicBlock *ChildBlock = ChildNode->getBlock();
95        if (Loop->contains(ChildBlock))
96          VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
97      }
98    }
99  };
100
101  /// An individual mapping from virtual register number to SUnit.
102  struct VReg2SUnit {
103    unsigned VirtReg;
104    SUnit *SU;
105
106    VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
107
108    unsigned getSparseSetKey() const {
109      return TargetRegisterInfo::virtReg2Index(VirtReg);
110    }
111  };
112
113  /// Combine a SparseSet with a 1x1 vector to track physical registers.
114  /// The SparseSet allows iterating over the (few) live registers for quickly
115  /// comparing against a regmask or clearing the set.
116  ///
117  /// Storage for the map is allocated once for the pass. The map can be
118  /// cleared between scheduling regions without freeing unused entries.
119  class Reg2SUnitsMap {
120    SparseSet<unsigned> PhysRegSet;
121    std::vector<std::vector<SUnit*> > SUnits;
122  public:
123    typedef SparseSet<unsigned>::const_iterator const_iterator;
124
125    // Allow iteration over register numbers (keys) in the map. If needed, we
126    // can provide an iterator over SUnits (values) as well.
127    const_iterator reg_begin() const { return PhysRegSet.begin(); }
128    const_iterator reg_end() const { return PhysRegSet.end(); }
129
130    /// Initialize the map with the number of registers.
131    /// If the map is already large enough, no allocation occurs.
132    /// For simplicity we expect the map to be empty().
133    void setRegLimit(unsigned Limit);
134
135    /// Returns true if the map is empty.
136    bool empty() const { return PhysRegSet.empty(); }
137
138    /// Clear the map without deallocating storage.
139    void clear();
140
141    bool contains(unsigned Reg) const { return PhysRegSet.count(Reg); }
142
143    /// If this register is mapped, return its existing SUnits vector.
144    /// Otherwise map the register and return an empty SUnits vector.
145    std::vector<SUnit *> &operator[](unsigned Reg) {
146      bool New = PhysRegSet.insert(Reg).second;
147      assert((!New || SUnits[Reg].empty()) && "stale SUnits vector");
148      (void)New;
149      return SUnits[Reg];
150    }
151
152    /// Erase an existing element without freeing memory.
153    void erase(unsigned Reg) {
154      PhysRegSet.erase(Reg);
155      SUnits[Reg].clear();
156    }
157  };
158
159  /// Use SparseSet as a SparseMap by relying on the fact that it never
160  /// compares ValueT's, only unsigned keys. This allows the set to be cleared
161  /// between scheduling regions in constant time as long as ValueT does not
162  /// require a destructor.
163  typedef SparseSet<VReg2SUnit> VReg2SUnitMap;
164
165  /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
166  /// MachineInstrs.
167  class ScheduleDAGInstrs : public ScheduleDAG {
168  protected:
169    const MachineLoopInfo &MLI;
170    const MachineDominatorTree &MDT;
171    const MachineFrameInfo *MFI;
172    const InstrItineraryData *InstrItins;
173
174    /// Live Intervals provides reaching defs in preRA scheduling.
175    LiveIntervals *LIS;
176
177    /// isPostRA flag indicates vregs cannot be present.
178    bool IsPostRA;
179
180    /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
181    /// the def-side latency only.
182    bool UnitLatencies;
183
184    /// State specific to the current scheduling region.
185    /// ------------------------------------------------
186
187    /// The block in which to insert instructions
188    MachineBasicBlock *BB;
189
190    /// The beginning of the range to be scheduled.
191    MachineBasicBlock::iterator RegionBegin;
192
193    /// The end of the range to be scheduled.
194    MachineBasicBlock::iterator RegionEnd;
195
196    /// The index in BB of RegionEnd.
197    unsigned EndIndex;
198
199    /// After calling BuildSchedGraph, each machine instruction in the current
200    /// scheduling region is mapped to an SUnit.
201    DenseMap<MachineInstr*, SUnit*> MISUnitMap;
202
203    /// State internal to DAG building.
204    /// -------------------------------
205
206    /// Defs, Uses - Remember where defs and uses of each register are as we
207    /// iterate upward through the instructions. This is allocated here instead
208    /// of inside BuildSchedGraph to avoid the need for it to be initialized and
209    /// destructed for each block.
210    Reg2SUnitsMap Defs;
211    Reg2SUnitsMap Uses;
212
213    /// Track the last instructon in this region defining each virtual register.
214    VReg2SUnitMap VRegDefs;
215
216    /// PendingLoads - Remember where unknown loads are after the most recent
217    /// unknown store, as we iterate. As with Defs and Uses, this is here
218    /// to minimize construction/destruction.
219    std::vector<SUnit *> PendingLoads;
220
221    /// LoopRegs - Track which registers are used for loop-carried dependencies.
222    ///
223    LoopDependencies LoopRegs;
224
225    /// DbgValues - Remember instruction that preceeds DBG_VALUE.
226    /// These are generated by buildSchedGraph but persist so they can be
227    /// referenced when emitting the final schedule.
228    typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
229      DbgValueVector;
230    DbgValueVector DbgValues;
231    MachineInstr *FirstDbgValue;
232
233  public:
234    explicit ScheduleDAGInstrs(MachineFunction &mf,
235                               const MachineLoopInfo &mli,
236                               const MachineDominatorTree &mdt,
237                               bool IsPostRAFlag,
238                               LiveIntervals *LIS = 0);
239
240    virtual ~ScheduleDAGInstrs() {}
241
242    /// begin - Return an iterator to the top of the current scheduling region.
243    MachineBasicBlock::iterator begin() const { return RegionBegin; }
244
245    /// end - Return an iterator to the bottom of the current scheduling region.
246    MachineBasicBlock::iterator end() const { return RegionEnd; }
247
248    /// newSUnit - Creates a new SUnit and return a ptr to it.
249    SUnit *newSUnit(MachineInstr *MI);
250
251    /// getSUnit - Return an existing SUnit for this MI, or NULL.
252    SUnit *getSUnit(MachineInstr *MI) const;
253
254    /// startBlock - Prepare to perform scheduling in the given block.
255    virtual void startBlock(MachineBasicBlock *BB);
256
257    /// finishBlock - Clean up after scheduling in the given block.
258    virtual void finishBlock();
259
260    /// Initialize the scheduler state for the next scheduling region.
261    virtual void enterRegion(MachineBasicBlock *bb,
262                             MachineBasicBlock::iterator begin,
263                             MachineBasicBlock::iterator end,
264                             unsigned endcount);
265
266    /// Notify that the scheduler has finished scheduling the current region.
267    virtual void exitRegion();
268
269    /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
270    /// input.
271    void buildSchedGraph(AliasAnalysis *AA);
272
273    /// addSchedBarrierDeps - Add dependencies from instructions in the current
274    /// list of instructions being scheduled to scheduling barrier. We want to
275    /// make sure instructions which define registers that are either used by
276    /// the terminator or are live-out are properly scheduled. This is
277    /// especially important when the definition latency of the return value(s)
278    /// are too high to be hidden by the branch or when the liveout registers
279    /// used by instructions in the fallthrough block.
280    void addSchedBarrierDeps();
281
282    /// computeLatency - Compute node latency.
283    ///
284    virtual void computeLatency(SUnit *SU);
285
286    /// computeOperandLatency - Override dependence edge latency using
287    /// operand use/def information
288    ///
289    virtual void computeOperandLatency(SUnit *Def, SUnit *Use,
290                                       SDep& dep) const;
291
292    /// schedule - Order nodes according to selected style, filling
293    /// in the Sequence member.
294    ///
295    /// Typically, a scheduling algorithm will implement schedule() without
296    /// overriding enterRegion() or exitRegion().
297    virtual void schedule() = 0;
298
299    /// finalizeSchedule - Allow targets to perform final scheduling actions at
300    /// the level of the whole MachineFunction. By default does nothing.
301    virtual void finalizeSchedule() {}
302
303    virtual void dumpNode(const SUnit *SU) const;
304
305    /// Return a label for a DAG node that points to an instruction.
306    virtual std::string getGraphNodeLabel(const SUnit *SU) const;
307
308    /// Return a label for the region of code covered by the DAG.
309    virtual std::string getDAGName() const;
310
311  protected:
312    void initSUnits();
313    void addPhysRegDataDeps(SUnit *SU, const MachineOperand &MO);
314    void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
315    void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
316    void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
317
318    VReg2SUnitMap::iterator findVRegDef(unsigned VirtReg) {
319      return VRegDefs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
320    }
321  };
322
323  /// newSUnit - Creates a new SUnit and return a ptr to it.
324  inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
325#ifndef NDEBUG
326    const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
327#endif
328    SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
329    assert((Addr == 0 || Addr == &SUnits[0]) &&
330           "SUnits std::vector reallocated on the fly!");
331    SUnits.back().OrigNode = &SUnits.back();
332    return &SUnits.back();
333  }
334
335  /// getSUnit - Return an existing SUnit for this MI, or NULL.
336  inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
337    DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
338    if (I == MISUnitMap.end())
339      return 0;
340    return I->second;
341  }
342} // namespace llvm
343
344#endif
345