ScheduleDAG.h revision 218893
1//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ScheduleDAG class, which is used as the common 11// base class for instruction schedulers. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SCHEDULEDAG_H 16#define LLVM_CODEGEN_SCHEDULEDAG_H 17 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Target/TargetMachine.h" 20#include "llvm/ADT/DenseMap.h" 21#include "llvm/ADT/BitVector.h" 22#include "llvm/ADT/GraphTraits.h" 23#include "llvm/ADT/SmallVector.h" 24#include "llvm/ADT/PointerIntPair.h" 25 26namespace llvm { 27 class AliasAnalysis; 28 class SUnit; 29 class MachineConstantPool; 30 class MachineFunction; 31 class MachineRegisterInfo; 32 class MachineInstr; 33 class TargetRegisterInfo; 34 class ScheduleDAG; 35 class SDNode; 36 class TargetInstrInfo; 37 class TargetInstrDesc; 38 class TargetMachine; 39 class TargetRegisterClass; 40 template<class Graph> class GraphWriter; 41 42 /// SDep - Scheduling dependency. This represents one direction of an 43 /// edge in the scheduling DAG. 44 class SDep { 45 public: 46 /// Kind - These are the different kinds of scheduling dependencies. 47 enum Kind { 48 Data, ///< Regular data dependence (aka true-dependence). 49 Anti, ///< A register anti-dependedence (aka WAR). 50 Output, ///< A register output-dependence (aka WAW). 51 Order ///< Any other ordering dependency. 52 }; 53 54 private: 55 /// Dep - A pointer to the depending/depended-on SUnit, and an enum 56 /// indicating the kind of the dependency. 57 PointerIntPair<SUnit *, 2, Kind> Dep; 58 59 /// Contents - A union discriminated by the dependence kind. 60 union { 61 /// Reg - For Data, Anti, and Output dependencies, the associated 62 /// register. For Data dependencies that don't currently have a register 63 /// assigned, this is set to zero. 64 unsigned Reg; 65 66 /// Order - Additional information about Order dependencies. 67 struct { 68 /// isNormalMemory - True if both sides of the dependence 69 /// access memory in non-volatile and fully modeled ways. 70 bool isNormalMemory : 1; 71 72 /// isMustAlias - True if both sides of the dependence are known to 73 /// access the same memory. 74 bool isMustAlias : 1; 75 76 /// isArtificial - True if this is an artificial dependency, meaning 77 /// it is not necessary for program correctness, and may be safely 78 /// deleted if necessary. 79 bool isArtificial : 1; 80 } Order; 81 } Contents; 82 83 /// Latency - The time associated with this edge. Often this is just 84 /// the value of the Latency field of the predecessor, however advanced 85 /// models may provide additional information about specific edges. 86 unsigned Latency; 87 88 public: 89 /// SDep - Construct a null SDep. This is only for use by container 90 /// classes which require default constructors. SUnits may not 91 /// have null SDep edges. 92 SDep() : Dep(0, Data) {} 93 94 /// SDep - Construct an SDep with the specified values. 95 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, 96 bool isNormalMemory = false, bool isMustAlias = false, 97 bool isArtificial = false) 98 : Dep(S, kind), Contents(), Latency(latency) { 99 switch (kind) { 100 case Anti: 101 case Output: 102 assert(Reg != 0 && 103 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 104 // fall through 105 case Data: 106 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!"); 107 assert(!isArtificial && "isArtificial only applies with SDep::Order!"); 108 Contents.Reg = Reg; 109 break; 110 case Order: 111 assert(Reg == 0 && "Reg given for non-register dependence!"); 112 Contents.Order.isNormalMemory = isNormalMemory; 113 Contents.Order.isMustAlias = isMustAlias; 114 Contents.Order.isArtificial = isArtificial; 115 break; 116 } 117 } 118 119 bool operator==(const SDep &Other) const { 120 if (Dep != Other.Dep || Latency != Other.Latency) return false; 121 switch (Dep.getInt()) { 122 case Data: 123 case Anti: 124 case Output: 125 return Contents.Reg == Other.Contents.Reg; 126 case Order: 127 return Contents.Order.isNormalMemory == 128 Other.Contents.Order.isNormalMemory && 129 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias && 130 Contents.Order.isArtificial == Other.Contents.Order.isArtificial; 131 } 132 assert(0 && "Invalid dependency kind!"); 133 return false; 134 } 135 136 bool operator!=(const SDep &Other) const { 137 return !operator==(Other); 138 } 139 140 /// getLatency - Return the latency value for this edge, which roughly 141 /// means the minimum number of cycles that must elapse between the 142 /// predecessor and the successor, given that they have this edge 143 /// between them. 144 unsigned getLatency() const { 145 return Latency; 146 } 147 148 /// setLatency - Set the latency for this edge. 149 void setLatency(unsigned Lat) { 150 Latency = Lat; 151 } 152 153 //// getSUnit - Return the SUnit to which this edge points. 154 SUnit *getSUnit() const { 155 return Dep.getPointer(); 156 } 157 158 //// setSUnit - Assign the SUnit to which this edge points. 159 void setSUnit(SUnit *SU) { 160 Dep.setPointer(SU); 161 } 162 163 /// getKind - Return an enum value representing the kind of the dependence. 164 Kind getKind() const { 165 return Dep.getInt(); 166 } 167 168 /// isCtrl - Shorthand for getKind() != SDep::Data. 169 bool isCtrl() const { 170 return getKind() != Data; 171 } 172 173 /// isNormalMemory - Test if this is an Order dependence between two 174 /// memory accesses where both sides of the dependence access memory 175 /// in non-volatile and fully modeled ways. 176 bool isNormalMemory() const { 177 return getKind() == Order && Contents.Order.isNormalMemory; 178 } 179 180 /// isMustAlias - Test if this is an Order dependence that is marked 181 /// as "must alias", meaning that the SUnits at either end of the edge 182 /// have a memory dependence on a known memory location. 183 bool isMustAlias() const { 184 return getKind() == Order && Contents.Order.isMustAlias; 185 } 186 187 /// isArtificial - Test if this is an Order dependence that is marked 188 /// as "artificial", meaning it isn't necessary for correctness. 189 bool isArtificial() const { 190 return getKind() == Order && Contents.Order.isArtificial; 191 } 192 193 /// isAssignedRegDep - Test if this is a Data dependence that is 194 /// associated with a register. 195 bool isAssignedRegDep() const { 196 return getKind() == Data && Contents.Reg != 0; 197 } 198 199 /// getReg - Return the register associated with this edge. This is 200 /// only valid on Data, Anti, and Output edges. On Data edges, this 201 /// value may be zero, meaning there is no associated register. 202 unsigned getReg() const { 203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 204 "getReg called on non-register dependence edge!"); 205 return Contents.Reg; 206 } 207 208 /// setReg - Assign the associated register for this edge. This is 209 /// only valid on Data, Anti, and Output edges. On Anti and Output 210 /// edges, this value must not be zero. On Data edges, the value may 211 /// be zero, which would mean that no specific register is associated 212 /// with this edge. 213 void setReg(unsigned Reg) { 214 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 215 "setReg called on non-register dependence edge!"); 216 assert((getKind() != Anti || Reg != 0) && 217 "SDep::Anti edge cannot use the zero register!"); 218 assert((getKind() != Output || Reg != 0) && 219 "SDep::Output edge cannot use the zero register!"); 220 Contents.Reg = Reg; 221 } 222 }; 223 224 template <> 225 struct isPodLike<SDep> { static const bool value = true; }; 226 227 /// SUnit - Scheduling unit. This is a node in the scheduling DAG. 228 class SUnit { 229 private: 230 SDNode *Node; // Representative node. 231 MachineInstr *Instr; // Alternatively, a MachineInstr. 232 public: 233 SUnit *OrigNode; // If not this, the node from which 234 // this node was cloned. 235 236 // Preds/Succs - The SUnits before/after us in the graph. 237 SmallVector<SDep, 4> Preds; // All sunit predecessors. 238 SmallVector<SDep, 4> Succs; // All sunit successors. 239 240 typedef SmallVector<SDep, 4>::iterator pred_iterator; 241 typedef SmallVector<SDep, 4>::iterator succ_iterator; 242 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; 243 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; 244 245 unsigned NodeNum; // Entry # of node in the node vector. 246 unsigned NodeQueueId; // Queue id of node. 247 unsigned NumPreds; // # of SDep::Data preds. 248 unsigned NumSuccs; // # of SDep::Data sucss. 249 unsigned NumPredsLeft; // # of preds not scheduled. 250 unsigned NumSuccsLeft; // # of succs not scheduled. 251 unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use. 252 unsigned short Latency; // Node latency. 253 bool isCall : 1; // Is a function call. 254 bool isTwoAddress : 1; // Is a two-address instruction. 255 bool isCommutable : 1; // Is a commutable instruction. 256 bool hasPhysRegDefs : 1; // Has physreg defs that are being used. 257 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not. 258 bool isPending : 1; // True once pending. 259 bool isAvailable : 1; // True once available. 260 bool isScheduled : 1; // True once scheduled. 261 bool isScheduleHigh : 1; // True if preferable to schedule high. 262 bool isCloned : 1; // True if this node has been cloned. 263 Sched::Preference SchedulingPref; // Scheduling preference. 264 265 SmallVector<MachineInstr*, 4> DbgInstrList; // dbg_values referencing this. 266 private: 267 bool isDepthCurrent : 1; // True if Depth is current. 268 bool isHeightCurrent : 1; // True if Height is current. 269 unsigned Depth; // Node depth. 270 unsigned Height; // Node height. 271 public: 272 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. 273 const TargetRegisterClass *CopySrcRC; 274 275 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent 276 /// an SDNode and any nodes flagged to it. 277 SUnit(SDNode *node, unsigned nodenum) 278 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), 279 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), 280 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0), 281 isCall(false), isTwoAddress(false), isCommutable(false), 282 hasPhysRegDefs(false), hasPhysRegClobbers(false), 283 isPending(false), isAvailable(false), isScheduled(false), 284 isScheduleHigh(false), isCloned(false), 285 SchedulingPref(Sched::None), 286 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 287 CopyDstRC(NULL), CopySrcRC(NULL) {} 288 289 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent 290 /// a MachineInstr. 291 SUnit(MachineInstr *instr, unsigned nodenum) 292 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), 293 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), 294 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0), 295 isCall(false), isTwoAddress(false), isCommutable(false), 296 hasPhysRegDefs(false), hasPhysRegClobbers(false), 297 isPending(false), isAvailable(false), isScheduled(false), 298 isScheduleHigh(false), isCloned(false), 299 SchedulingPref(Sched::None), 300 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 301 CopyDstRC(NULL), CopySrcRC(NULL) {} 302 303 /// SUnit - Construct a placeholder SUnit. 304 SUnit() 305 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), 306 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), 307 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0), 308 isCall(false), isTwoAddress(false), isCommutable(false), 309 hasPhysRegDefs(false), hasPhysRegClobbers(false), 310 isPending(false), isAvailable(false), isScheduled(false), 311 isScheduleHigh(false), isCloned(false), 312 SchedulingPref(Sched::None), 313 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 314 CopyDstRC(NULL), CopySrcRC(NULL) {} 315 316 /// setNode - Assign the representative SDNode for this SUnit. 317 /// This may be used during pre-regalloc scheduling. 318 void setNode(SDNode *N) { 319 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); 320 Node = N; 321 } 322 323 /// getNode - Return the representative SDNode for this SUnit. 324 /// This may be used during pre-regalloc scheduling. 325 SDNode *getNode() const { 326 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!"); 327 return Node; 328 } 329 330 /// isInstr - Return true if this SUnit refers to a machine instruction as 331 /// opposed to an SDNode. 332 bool isInstr() const { return Instr; } 333 334 /// setInstr - Assign the instruction for the SUnit. 335 /// This may be used during post-regalloc scheduling. 336 void setInstr(MachineInstr *MI) { 337 assert(!Node && "Setting MachineInstr of SUnit with SDNode!"); 338 Instr = MI; 339 } 340 341 /// getInstr - Return the representative MachineInstr for this SUnit. 342 /// This may be used during post-regalloc scheduling. 343 MachineInstr *getInstr() const { 344 assert(!Node && "Reading MachineInstr of SUnit with SDNode!"); 345 return Instr; 346 } 347 348 /// addPred - This adds the specified edge as a pred of the current node if 349 /// not already. It also adds the current node as a successor of the 350 /// specified node. 351 bool addPred(const SDep &D); 352 353 /// removePred - This removes the specified edge as a pred of the current 354 /// node if it exists. It also removes the current node as a successor of 355 /// the specified node. 356 void removePred(const SDep &D); 357 358 /// getDepth - Return the depth of this node, which is the length of the 359 /// maximum path up to any node with has no predecessors. 360 unsigned getDepth() const { 361 if (!isDepthCurrent) 362 const_cast<SUnit *>(this)->ComputeDepth(); 363 return Depth; 364 } 365 366 /// getHeight - Return the height of this node, which is the length of the 367 /// maximum path down to any node with has no successors. 368 unsigned getHeight() const { 369 if (!isHeightCurrent) 370 const_cast<SUnit *>(this)->ComputeHeight(); 371 return Height; 372 } 373 374 /// setDepthToAtLeast - If NewDepth is greater than this node's 375 /// depth value, set it to be the new depth value. This also 376 /// recursively marks successor nodes dirty. 377 void setDepthToAtLeast(unsigned NewDepth); 378 379 /// setDepthToAtLeast - If NewDepth is greater than this node's 380 /// depth value, set it to be the new height value. This also 381 /// recursively marks predecessor nodes dirty. 382 void setHeightToAtLeast(unsigned NewHeight); 383 384 /// setDepthDirty - Set a flag in this node to indicate that its 385 /// stored Depth value will require recomputation the next time 386 /// getDepth() is called. 387 void setDepthDirty(); 388 389 /// setHeightDirty - Set a flag in this node to indicate that its 390 /// stored Height value will require recomputation the next time 391 /// getHeight() is called. 392 void setHeightDirty(); 393 394 /// isPred - Test if node N is a predecessor of this node. 395 bool isPred(SUnit *N) { 396 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i) 397 if (Preds[i].getSUnit() == N) 398 return true; 399 return false; 400 } 401 402 /// isSucc - Test if node N is a successor of this node. 403 bool isSucc(SUnit *N) { 404 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i) 405 if (Succs[i].getSUnit() == N) 406 return true; 407 return false; 408 } 409 410 void dump(const ScheduleDAG *G) const; 411 void dumpAll(const ScheduleDAG *G) const; 412 void print(raw_ostream &O, const ScheduleDAG *G) const; 413 414 private: 415 void ComputeDepth(); 416 void ComputeHeight(); 417 }; 418 419 //===--------------------------------------------------------------------===// 420 /// SchedulingPriorityQueue - This interface is used to plug different 421 /// priorities computation algorithms into the list scheduler. It implements 422 /// the interface of a standard priority queue, where nodes are inserted in 423 /// arbitrary order and returned in priority order. The computation of the 424 /// priority and the representation of the queue are totally up to the 425 /// implementation to decide. 426 /// 427 class SchedulingPriorityQueue { 428 unsigned CurCycle; 429 bool HasReadyFilter; 430 public: 431 SchedulingPriorityQueue(bool rf = false): 432 CurCycle(0), HasReadyFilter(rf) {} 433 virtual ~SchedulingPriorityQueue() {} 434 435 virtual bool isBottomUp() const = 0; 436 437 virtual void initNodes(std::vector<SUnit> &SUnits) = 0; 438 virtual void addNode(const SUnit *SU) = 0; 439 virtual void updateNode(const SUnit *SU) = 0; 440 virtual void releaseState() = 0; 441 442 virtual bool empty() const = 0; 443 444 bool hasReadyFilter() const { return HasReadyFilter; } 445 446 virtual bool tracksRegPressure() const { return false; } 447 448 virtual bool isReady(SUnit *) const { 449 assert(!HasReadyFilter && "The ready filter must override isReady()"); 450 return true; 451 } 452 virtual void push(SUnit *U) = 0; 453 454 void push_all(const std::vector<SUnit *> &Nodes) { 455 for (std::vector<SUnit *>::const_iterator I = Nodes.begin(), 456 E = Nodes.end(); I != E; ++I) 457 push(*I); 458 } 459 460 virtual SUnit *pop() = 0; 461 462 virtual void remove(SUnit *SU) = 0; 463 464 virtual void dump(ScheduleDAG *) const {} 465 466 /// ScheduledNode - As each node is scheduled, this method is invoked. This 467 /// allows the priority function to adjust the priority of related 468 /// unscheduled nodes, for example. 469 /// 470 virtual void ScheduledNode(SUnit *) {} 471 472 virtual void UnscheduledNode(SUnit *) {} 473 474 void setCurCycle(unsigned Cycle) { 475 CurCycle = Cycle; 476 } 477 478 unsigned getCurCycle() const { 479 return CurCycle; 480 } 481 }; 482 483 class ScheduleDAG { 484 public: 485 MachineBasicBlock *BB; // The block in which to insert instructions 486 MachineBasicBlock::iterator InsertPos;// The position to insert instructions 487 const TargetMachine &TM; // Target processor 488 const TargetInstrInfo *TII; // Target instruction information 489 const TargetRegisterInfo *TRI; // Target processor register info 490 MachineFunction &MF; // Machine function 491 MachineRegisterInfo &MRI; // Virtual/real register map 492 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s 493 // represent noop instructions. 494 std::vector<SUnit> SUnits; // The scheduling units. 495 SUnit EntrySU; // Special node for the region entry. 496 SUnit ExitSU; // Special node for the region exit. 497 498 explicit ScheduleDAG(MachineFunction &mf); 499 500 virtual ~ScheduleDAG(); 501 502 /// getInstrDesc - Return the TargetInstrDesc of this SUnit. 503 /// Return NULL for SDNodes without a machine opcode. 504 const TargetInstrDesc *getInstrDesc(const SUnit *SU) const { 505 if (SU->isInstr()) return &SU->getInstr()->getDesc(); 506 return getNodeDesc(SU->getNode()); 507 } 508 509 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered 510 /// using 'dot'. 511 /// 512 void viewGraph(); 513 514 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock 515 /// according to the order specified in Sequence. 516 /// 517 virtual MachineBasicBlock *EmitSchedule() = 0; 518 519 void dumpSchedule() const; 520 521 virtual void dumpNode(const SUnit *SU) const = 0; 522 523 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization 524 /// of the ScheduleDAG. 525 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0; 526 527 /// addCustomGraphFeatures - Add custom features for a visualization of 528 /// the ScheduleDAG. 529 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {} 530 531#ifndef NDEBUG 532 /// VerifySchedule - Verify that all SUnits were scheduled and that 533 /// their state is consistent. 534 void VerifySchedule(bool isBottomUp); 535#endif 536 537 protected: 538 /// Run - perform scheduling. 539 /// 540 void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos); 541 542 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs 543 /// to form the scheduling dependency graph. 544 /// 545 virtual void BuildSchedGraph(AliasAnalysis *AA) = 0; 546 547 /// ComputeLatency - Compute node latency. 548 /// 549 virtual void ComputeLatency(SUnit *SU) = 0; 550 551 /// ComputeOperandLatency - Override dependence edge latency using 552 /// operand use/def information 553 /// 554 virtual void ComputeOperandLatency(SUnit *, SUnit *, 555 SDep&) const { } 556 557 /// Schedule - Order nodes according to selected style, filling 558 /// in the Sequence member. 559 /// 560 virtual void Schedule() = 0; 561 562 /// ForceUnitLatencies - Return true if all scheduling edges should be given 563 /// a latency value of one. The default is to return false; schedulers may 564 /// override this as needed. 565 virtual bool ForceUnitLatencies() const { return false; } 566 567 /// EmitNoop - Emit a noop instruction. 568 /// 569 void EmitNoop(); 570 571 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap); 572 573 private: 574 // Return the TargetInstrDesc of this SDNode or NULL. 575 const TargetInstrDesc *getNodeDesc(const SDNode *Node) const; 576 }; 577 578 class SUnitIterator : public std::iterator<std::forward_iterator_tag, 579 SUnit, ptrdiff_t> { 580 SUnit *Node; 581 unsigned Operand; 582 583 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {} 584 public: 585 bool operator==(const SUnitIterator& x) const { 586 return Operand == x.Operand; 587 } 588 bool operator!=(const SUnitIterator& x) const { return !operator==(x); } 589 590 const SUnitIterator &operator=(const SUnitIterator &I) { 591 assert(I.Node==Node && "Cannot assign iterators to two different nodes!"); 592 Operand = I.Operand; 593 return *this; 594 } 595 596 pointer operator*() const { 597 return Node->Preds[Operand].getSUnit(); 598 } 599 pointer operator->() const { return operator*(); } 600 601 SUnitIterator& operator++() { // Preincrement 602 ++Operand; 603 return *this; 604 } 605 SUnitIterator operator++(int) { // Postincrement 606 SUnitIterator tmp = *this; ++*this; return tmp; 607 } 608 609 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); } 610 static SUnitIterator end (SUnit *N) { 611 return SUnitIterator(N, (unsigned)N->Preds.size()); 612 } 613 614 unsigned getOperand() const { return Operand; } 615 const SUnit *getNode() const { return Node; } 616 /// isCtrlDep - Test if this is not an SDep::Data dependence. 617 bool isCtrlDep() const { 618 return getSDep().isCtrl(); 619 } 620 bool isArtificialDep() const { 621 return getSDep().isArtificial(); 622 } 623 const SDep &getSDep() const { 624 return Node->Preds[Operand]; 625 } 626 }; 627 628 template <> struct GraphTraits<SUnit*> { 629 typedef SUnit NodeType; 630 typedef SUnitIterator ChildIteratorType; 631 static inline NodeType *getEntryNode(SUnit *N) { return N; } 632 static inline ChildIteratorType child_begin(NodeType *N) { 633 return SUnitIterator::begin(N); 634 } 635 static inline ChildIteratorType child_end(NodeType *N) { 636 return SUnitIterator::end(N); 637 } 638 }; 639 640 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> { 641 typedef std::vector<SUnit>::iterator nodes_iterator; 642 static nodes_iterator nodes_begin(ScheduleDAG *G) { 643 return G->SUnits.begin(); 644 } 645 static nodes_iterator nodes_end(ScheduleDAG *G) { 646 return G->SUnits.end(); 647 } 648 }; 649 650 /// ScheduleDAGTopologicalSort is a class that computes a topological 651 /// ordering for SUnits and provides methods for dynamically updating 652 /// the ordering as new edges are added. 653 /// 654 /// This allows a very fast implementation of IsReachable, for example. 655 /// 656 class ScheduleDAGTopologicalSort { 657 /// SUnits - A reference to the ScheduleDAG's SUnits. 658 std::vector<SUnit> &SUnits; 659 660 /// Index2Node - Maps topological index to the node number. 661 std::vector<int> Index2Node; 662 /// Node2Index - Maps the node number to its topological index. 663 std::vector<int> Node2Index; 664 /// Visited - a set of nodes visited during a DFS traversal. 665 BitVector Visited; 666 667 /// DFS - make a DFS traversal and mark all nodes affected by the 668 /// edge insertion. These nodes will later get new topological indexes 669 /// by means of the Shift method. 670 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop); 671 672 /// Shift - reassign topological indexes for the nodes in the DAG 673 /// to preserve the topological ordering. 674 void Shift(BitVector& Visited, int LowerBound, int UpperBound); 675 676 /// Allocate - assign the topological index to the node n. 677 void Allocate(int n, int index); 678 679 public: 680 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits); 681 682 /// InitDAGTopologicalSorting - create the initial topological 683 /// ordering from the DAG to be scheduled. 684 void InitDAGTopologicalSorting(); 685 686 /// IsReachable - Checks if SU is reachable from TargetSU. 687 bool IsReachable(const SUnit *SU, const SUnit *TargetSU); 688 689 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU 690 /// will create a cycle. 691 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU); 692 693 /// AddPred - Updates the topological ordering to accomodate an edge 694 /// to be added from SUnit X to SUnit Y. 695 void AddPred(SUnit *Y, SUnit *X); 696 697 /// RemovePred - Updates the topological ordering to accomodate an 698 /// an edge to be removed from the specified node N from the predecessors 699 /// of the current node M. 700 void RemovePred(SUnit *M, SUnit *N); 701 702 typedef std::vector<int>::iterator iterator; 703 typedef std::vector<int>::const_iterator const_iterator; 704 iterator begin() { return Index2Node.begin(); } 705 const_iterator begin() const { return Index2Node.begin(); } 706 iterator end() { return Index2Node.end(); } 707 const_iterator end() const { return Index2Node.end(); } 708 709 typedef std::vector<int>::reverse_iterator reverse_iterator; 710 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator; 711 reverse_iterator rbegin() { return Index2Node.rbegin(); } 712 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); } 713 reverse_iterator rend() { return Index2Node.rend(); } 714 const_reverse_iterator rend() const { return Index2Node.rend(); } 715 }; 716} 717 718#endif 719