ScheduleDAG.h revision 198892
1//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ScheduleDAG class, which is used as the common 11// base class for instruction schedulers. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SCHEDULEDAG_H 16#define LLVM_CODEGEN_SCHEDULEDAG_H 17 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/ADT/BitVector.h" 21#include "llvm/ADT/GraphTraits.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/ADT/PointerIntPair.h" 24 25namespace llvm { 26 class AliasAnalysis; 27 class SUnit; 28 class MachineConstantPool; 29 class MachineFunction; 30 class MachineModuleInfo; 31 class MachineRegisterInfo; 32 class MachineInstr; 33 class TargetRegisterInfo; 34 class ScheduleDAG; 35 class SDNode; 36 class TargetInstrInfo; 37 class TargetInstrDesc; 38 class TargetLowering; 39 class TargetMachine; 40 class TargetRegisterClass; 41 template<class Graph> class GraphWriter; 42 43 /// SDep - Scheduling dependency. This represents one direction of an 44 /// edge in the scheduling DAG. 45 class SDep { 46 public: 47 /// Kind - These are the different kinds of scheduling dependencies. 48 enum Kind { 49 Data, ///< Regular data dependence (aka true-dependence). 50 Anti, ///< A register anti-dependedence (aka WAR). 51 Output, ///< A register output-dependence (aka WAW). 52 Order ///< Any other ordering dependency. 53 }; 54 55 private: 56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum 57 /// indicating the kind of the dependency. 58 PointerIntPair<SUnit *, 2, Kind> Dep; 59 60 /// Contents - A union discriminated by the dependence kind. 61 union { 62 /// Reg - For Data, Anti, and Output dependencies, the associated 63 /// register. For Data dependencies that don't currently have a register 64 /// assigned, this is set to zero. 65 unsigned Reg; 66 67 /// Order - Additional information about Order dependencies. 68 struct { 69 /// isNormalMemory - True if both sides of the dependence 70 /// access memory in non-volatile and fully modeled ways. 71 bool isNormalMemory : 1; 72 73 /// isMustAlias - True if both sides of the dependence are known to 74 /// access the same memory. 75 bool isMustAlias : 1; 76 77 /// isArtificial - True if this is an artificial dependency, meaning 78 /// it is not necessary for program correctness, and may be safely 79 /// deleted if necessary. 80 bool isArtificial : 1; 81 } Order; 82 } Contents; 83 84 /// Latency - The time associated with this edge. Often this is just 85 /// the value of the Latency field of the predecessor, however advanced 86 /// models may provide additional information about specific edges. 87 unsigned Latency; 88 89 public: 90 /// SDep - Construct a null SDep. This is only for use by container 91 /// classes which require default constructors. SUnits may not 92 /// have null SDep edges. 93 SDep() : Dep(0, Data) {} 94 95 /// SDep - Construct an SDep with the specified values. 96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, 97 bool isNormalMemory = false, bool isMustAlias = false, 98 bool isArtificial = false) 99 : Dep(S, kind), Contents(), Latency(latency) { 100 switch (kind) { 101 case Anti: 102 case Output: 103 assert(Reg != 0 && 104 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 105 // fall through 106 case Data: 107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!"); 108 assert(!isArtificial && "isArtificial only applies with SDep::Order!"); 109 Contents.Reg = Reg; 110 break; 111 case Order: 112 assert(Reg == 0 && "Reg given for non-register dependence!"); 113 Contents.Order.isNormalMemory = isNormalMemory; 114 Contents.Order.isMustAlias = isMustAlias; 115 Contents.Order.isArtificial = isArtificial; 116 break; 117 } 118 } 119 120 bool operator==(const SDep &Other) const { 121 if (Dep != Other.Dep || Latency != Other.Latency) return false; 122 switch (Dep.getInt()) { 123 case Data: 124 case Anti: 125 case Output: 126 return Contents.Reg == Other.Contents.Reg; 127 case Order: 128 return Contents.Order.isNormalMemory == 129 Other.Contents.Order.isNormalMemory && 130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias && 131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial; 132 } 133 assert(0 && "Invalid dependency kind!"); 134 return false; 135 } 136 137 bool operator!=(const SDep &Other) const { 138 return !operator==(Other); 139 } 140 141 /// getLatency - Return the latency value for this edge, which roughly 142 /// means the minimum number of cycles that must elapse between the 143 /// predecessor and the successor, given that they have this edge 144 /// between them. 145 unsigned getLatency() const { 146 return Latency; 147 } 148 149 /// setLatency - Set the latency for this edge. 150 void setLatency(unsigned Lat) { 151 Latency = Lat; 152 } 153 154 //// getSUnit - Return the SUnit to which this edge points. 155 SUnit *getSUnit() const { 156 return Dep.getPointer(); 157 } 158 159 //// setSUnit - Assign the SUnit to which this edge points. 160 void setSUnit(SUnit *SU) { 161 Dep.setPointer(SU); 162 } 163 164 /// getKind - Return an enum value representing the kind of the dependence. 165 Kind getKind() const { 166 return Dep.getInt(); 167 } 168 169 /// isCtrl - Shorthand for getKind() != SDep::Data. 170 bool isCtrl() const { 171 return getKind() != Data; 172 } 173 174 /// isNormalMemory - Test if this is an Order dependence between two 175 /// memory accesses where both sides of the dependence access memory 176 /// in non-volatile and fully modeled ways. 177 bool isNormalMemory() const { 178 return getKind() == Order && Contents.Order.isNormalMemory; 179 } 180 181 /// isMustAlias - Test if this is an Order dependence that is marked 182 /// as "must alias", meaning that the SUnits at either end of the edge 183 /// have a memory dependence on a known memory location. 184 bool isMustAlias() const { 185 return getKind() == Order && Contents.Order.isMustAlias; 186 } 187 188 /// isArtificial - Test if this is an Order dependence that is marked 189 /// as "artificial", meaning it isn't necessary for correctness. 190 bool isArtificial() const { 191 return getKind() == Order && Contents.Order.isArtificial; 192 } 193 194 /// isAssignedRegDep - Test if this is a Data dependence that is 195 /// associated with a register. 196 bool isAssignedRegDep() const { 197 return getKind() == Data && Contents.Reg != 0; 198 } 199 200 /// getReg - Return the register associated with this edge. This is 201 /// only valid on Data, Anti, and Output edges. On Data edges, this 202 /// value may be zero, meaning there is no associated register. 203 unsigned getReg() const { 204 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 205 "getReg called on non-register dependence edge!"); 206 return Contents.Reg; 207 } 208 209 /// setReg - Assign the associated register for this edge. This is 210 /// only valid on Data, Anti, and Output edges. On Anti and Output 211 /// edges, this value must not be zero. On Data edges, the value may 212 /// be zero, which would mean that no specific register is associated 213 /// with this edge. 214 void setReg(unsigned Reg) { 215 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 216 "setReg called on non-register dependence edge!"); 217 assert((getKind() != Anti || Reg != 0) && 218 "SDep::Anti edge cannot use the zero register!"); 219 assert((getKind() != Output || Reg != 0) && 220 "SDep::Output edge cannot use the zero register!"); 221 Contents.Reg = Reg; 222 } 223 }; 224 225 /// SUnit - Scheduling unit. This is a node in the scheduling DAG. 226 class SUnit { 227 private: 228 SDNode *Node; // Representative node. 229 MachineInstr *Instr; // Alternatively, a MachineInstr. 230 public: 231 SUnit *OrigNode; // If not this, the node from which 232 // this node was cloned. 233 234 // Preds/Succs - The SUnits before/after us in the graph. The boolean value 235 // is true if the edge is a token chain edge, false if it is a value edge. 236 SmallVector<SDep, 4> Preds; // All sunit predecessors. 237 SmallVector<SDep, 4> Succs; // All sunit successors. 238 239 typedef SmallVector<SDep, 4>::iterator pred_iterator; 240 typedef SmallVector<SDep, 4>::iterator succ_iterator; 241 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; 242 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; 243 244 unsigned NodeNum; // Entry # of node in the node vector. 245 unsigned NodeQueueId; // Queue id of node. 246 unsigned short Latency; // Node latency. 247 unsigned NumPreds; // # of SDep::Data preds. 248 unsigned NumSuccs; // # of SDep::Data sucss. 249 unsigned NumPredsLeft; // # of preds not scheduled. 250 unsigned NumSuccsLeft; // # of succs not scheduled. 251 bool isTwoAddress : 1; // Is a two-address instruction. 252 bool isCommutable : 1; // Is a commutable instruction. 253 bool hasPhysRegDefs : 1; // Has physreg defs that are being used. 254 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not. 255 bool isPending : 1; // True once pending. 256 bool isAvailable : 1; // True once available. 257 bool isScheduled : 1; // True once scheduled. 258 bool isScheduleHigh : 1; // True if preferable to schedule high. 259 bool isCloned : 1; // True if this node has been cloned. 260 private: 261 bool isDepthCurrent : 1; // True if Depth is current. 262 bool isHeightCurrent : 1; // True if Height is current. 263 unsigned Depth; // Node depth. 264 unsigned Height; // Node height. 265 public: 266 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. 267 const TargetRegisterClass *CopySrcRC; 268 269 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent 270 /// an SDNode and any nodes flagged to it. 271 SUnit(SDNode *node, unsigned nodenum) 272 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 273 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 274 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 275 hasPhysRegClobbers(false), 276 isPending(false), isAvailable(false), isScheduled(false), 277 isScheduleHigh(false), isCloned(false), 278 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 279 CopyDstRC(NULL), CopySrcRC(NULL) {} 280 281 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent 282 /// a MachineInstr. 283 SUnit(MachineInstr *instr, unsigned nodenum) 284 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 285 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 286 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 287 hasPhysRegClobbers(false), 288 isPending(false), isAvailable(false), isScheduled(false), 289 isScheduleHigh(false), isCloned(false), 290 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 291 CopyDstRC(NULL), CopySrcRC(NULL) {} 292 293 /// SUnit - Construct a placeholder SUnit. 294 SUnit() 295 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0), 296 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 297 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 298 hasPhysRegClobbers(false), 299 isPending(false), isAvailable(false), isScheduled(false), 300 isScheduleHigh(false), isCloned(false), 301 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 302 CopyDstRC(NULL), CopySrcRC(NULL) {} 303 304 /// setNode - Assign the representative SDNode for this SUnit. 305 /// This may be used during pre-regalloc scheduling. 306 void setNode(SDNode *N) { 307 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); 308 Node = N; 309 } 310 311 /// getNode - Return the representative SDNode for this SUnit. 312 /// This may be used during pre-regalloc scheduling. 313 SDNode *getNode() const { 314 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!"); 315 return Node; 316 } 317 318 /// setInstr - Assign the instruction for the SUnit. 319 /// This may be used during post-regalloc scheduling. 320 void setInstr(MachineInstr *MI) { 321 assert(!Node && "Setting MachineInstr of SUnit with SDNode!"); 322 Instr = MI; 323 } 324 325 /// getInstr - Return the representative MachineInstr for this SUnit. 326 /// This may be used during post-regalloc scheduling. 327 MachineInstr *getInstr() const { 328 assert(!Node && "Reading MachineInstr of SUnit with SDNode!"); 329 return Instr; 330 } 331 332 /// addPred - This adds the specified edge as a pred of the current node if 333 /// not already. It also adds the current node as a successor of the 334 /// specified node. 335 void addPred(const SDep &D); 336 337 /// removePred - This removes the specified edge as a pred of the current 338 /// node if it exists. It also removes the current node as a successor of 339 /// the specified node. 340 void removePred(const SDep &D); 341 342 /// getDepth - Return the depth of this node, which is the length of the 343 /// maximum path up to any node with has no predecessors. If IgnoreAntiDep 344 /// is true, ignore anti-dependence edges. 345 unsigned getDepth(bool IgnoreAntiDep=false) const { 346 if (!isDepthCurrent) 347 const_cast<SUnit *>(this)->ComputeDepth(IgnoreAntiDep); 348 return Depth; 349 } 350 351 /// getHeight - Return the height of this node, which is the length of the 352 /// maximum path down to any node with has no successors. If IgnoreAntiDep 353 /// is true, ignore anti-dependence edges. 354 unsigned getHeight(bool IgnoreAntiDep=false) const { 355 if (!isHeightCurrent) 356 const_cast<SUnit *>(this)->ComputeHeight(IgnoreAntiDep); 357 return Height; 358 } 359 360 /// setDepthToAtLeast - If NewDepth is greater than this node's 361 /// depth value, set it to be the new depth value. This also 362 /// recursively marks successor nodes dirty. If IgnoreAntiDep is 363 /// true, ignore anti-dependence edges. 364 void setDepthToAtLeast(unsigned NewDepth, bool IgnoreAntiDep=false); 365 366 /// setDepthToAtLeast - If NewDepth is greater than this node's 367 /// depth value, set it to be the new height value. This also 368 /// recursively marks predecessor nodes dirty. If IgnoreAntiDep is 369 /// true, ignore anti-dependence edges. 370 void setHeightToAtLeast(unsigned NewHeight, bool IgnoreAntiDep=false); 371 372 /// setDepthDirty - Set a flag in this node to indicate that its 373 /// stored Depth value will require recomputation the next time 374 /// getDepth() is called. 375 void setDepthDirty(); 376 377 /// setHeightDirty - Set a flag in this node to indicate that its 378 /// stored Height value will require recomputation the next time 379 /// getHeight() is called. 380 void setHeightDirty(); 381 382 /// isPred - Test if node N is a predecessor of this node. 383 bool isPred(SUnit *N) { 384 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i) 385 if (Preds[i].getSUnit() == N) 386 return true; 387 return false; 388 } 389 390 /// isSucc - Test if node N is a successor of this node. 391 bool isSucc(SUnit *N) { 392 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i) 393 if (Succs[i].getSUnit() == N) 394 return true; 395 return false; 396 } 397 398 void dump(const ScheduleDAG *G) const; 399 void dumpAll(const ScheduleDAG *G) const; 400 void print(raw_ostream &O, const ScheduleDAG *G) const; 401 402 private: 403 void ComputeDepth(bool IgnoreAntiDep); 404 void ComputeHeight(bool IgnoreAntiDep); 405 }; 406 407 //===--------------------------------------------------------------------===// 408 /// SchedulingPriorityQueue - This interface is used to plug different 409 /// priorities computation algorithms into the list scheduler. It implements 410 /// the interface of a standard priority queue, where nodes are inserted in 411 /// arbitrary order and returned in priority order. The computation of the 412 /// priority and the representation of the queue are totally up to the 413 /// implementation to decide. 414 /// 415 class SchedulingPriorityQueue { 416 public: 417 virtual ~SchedulingPriorityQueue() {} 418 419 virtual void initNodes(std::vector<SUnit> &SUnits) = 0; 420 virtual void addNode(const SUnit *SU) = 0; 421 virtual void updateNode(const SUnit *SU) = 0; 422 virtual void releaseState() = 0; 423 424 virtual unsigned size() const = 0; 425 virtual bool empty() const = 0; 426 virtual void push(SUnit *U) = 0; 427 428 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0; 429 virtual SUnit *pop() = 0; 430 431 virtual void remove(SUnit *SU) = 0; 432 433 /// ScheduledNode - As each node is scheduled, this method is invoked. This 434 /// allows the priority function to adjust the priority of related 435 /// unscheduled nodes, for example. 436 /// 437 virtual void ScheduledNode(SUnit *) {} 438 439 virtual void UnscheduledNode(SUnit *) {} 440 }; 441 442 class ScheduleDAG { 443 public: 444 MachineBasicBlock *BB; // The block in which to insert instructions 445 MachineBasicBlock::iterator InsertPos;// The position to insert instructions 446 const TargetMachine &TM; // Target processor 447 const TargetInstrInfo *TII; // Target instruction information 448 const TargetRegisterInfo *TRI; // Target processor register info 449 const TargetLowering *TLI; // Target lowering info 450 MachineFunction &MF; // Machine function 451 MachineRegisterInfo &MRI; // Virtual/real register map 452 MachineConstantPool *ConstPool; // Target constant pool 453 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s 454 // represent noop instructions. 455 std::vector<SUnit> SUnits; // The scheduling units. 456 SUnit EntrySU; // Special node for the region entry. 457 SUnit ExitSU; // Special node for the region exit. 458 459 explicit ScheduleDAG(MachineFunction &mf); 460 461 virtual ~ScheduleDAG(); 462 463 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered 464 /// using 'dot'. 465 /// 466 void viewGraph(); 467 468 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock 469 /// according to the order specified in Sequence. 470 /// 471 virtual MachineBasicBlock* 472 EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) = 0; 473 474 void dumpSchedule() const; 475 476 virtual void dumpNode(const SUnit *SU) const = 0; 477 478 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization 479 /// of the ScheduleDAG. 480 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0; 481 482 /// addCustomGraphFeatures - Add custom features for a visualization of 483 /// the ScheduleDAG. 484 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {} 485 486#ifndef NDEBUG 487 /// VerifySchedule - Verify that all SUnits were scheduled and that 488 /// their state is consistent. 489 void VerifySchedule(bool isBottomUp); 490#endif 491 492 protected: 493 /// Run - perform scheduling. 494 /// 495 void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos); 496 497 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs 498 /// to form the scheduling dependency graph. 499 /// 500 virtual void BuildSchedGraph(AliasAnalysis *AA) = 0; 501 502 /// ComputeLatency - Compute node latency. 503 /// 504 virtual void ComputeLatency(SUnit *SU) = 0; 505 506 /// ComputeOperandLatency - Override dependence edge latency using 507 /// operand use/def information 508 /// 509 virtual void ComputeOperandLatency(SUnit *, SUnit *, 510 SDep&) const { } 511 512 /// Schedule - Order nodes according to selected style, filling 513 /// in the Sequence member. 514 /// 515 virtual void Schedule() = 0; 516 517 /// ForceUnitLatencies - Return true if all scheduling edges should be given 518 /// a latency value of one. The default is to return false; schedulers may 519 /// override this as needed. 520 virtual bool ForceUnitLatencies() const { return false; } 521 522 /// EmitNoop - Emit a noop instruction. 523 /// 524 void EmitNoop(); 525 526 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap); 527 }; 528 529 class SUnitIterator : public std::iterator<std::forward_iterator_tag, 530 SUnit, ptrdiff_t> { 531 SUnit *Node; 532 unsigned Operand; 533 534 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {} 535 public: 536 bool operator==(const SUnitIterator& x) const { 537 return Operand == x.Operand; 538 } 539 bool operator!=(const SUnitIterator& x) const { return !operator==(x); } 540 541 const SUnitIterator &operator=(const SUnitIterator &I) { 542 assert(I.Node==Node && "Cannot assign iterators to two different nodes!"); 543 Operand = I.Operand; 544 return *this; 545 } 546 547 pointer operator*() const { 548 return Node->Preds[Operand].getSUnit(); 549 } 550 pointer operator->() const { return operator*(); } 551 552 SUnitIterator& operator++() { // Preincrement 553 ++Operand; 554 return *this; 555 } 556 SUnitIterator operator++(int) { // Postincrement 557 SUnitIterator tmp = *this; ++*this; return tmp; 558 } 559 560 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); } 561 static SUnitIterator end (SUnit *N) { 562 return SUnitIterator(N, (unsigned)N->Preds.size()); 563 } 564 565 unsigned getOperand() const { return Operand; } 566 const SUnit *getNode() const { return Node; } 567 /// isCtrlDep - Test if this is not an SDep::Data dependence. 568 bool isCtrlDep() const { 569 return getSDep().isCtrl(); 570 } 571 bool isArtificialDep() const { 572 return getSDep().isArtificial(); 573 } 574 const SDep &getSDep() const { 575 return Node->Preds[Operand]; 576 } 577 }; 578 579 template <> struct GraphTraits<SUnit*> { 580 typedef SUnit NodeType; 581 typedef SUnitIterator ChildIteratorType; 582 static inline NodeType *getEntryNode(SUnit *N) { return N; } 583 static inline ChildIteratorType child_begin(NodeType *N) { 584 return SUnitIterator::begin(N); 585 } 586 static inline ChildIteratorType child_end(NodeType *N) { 587 return SUnitIterator::end(N); 588 } 589 }; 590 591 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> { 592 typedef std::vector<SUnit>::iterator nodes_iterator; 593 static nodes_iterator nodes_begin(ScheduleDAG *G) { 594 return G->SUnits.begin(); 595 } 596 static nodes_iterator nodes_end(ScheduleDAG *G) { 597 return G->SUnits.end(); 598 } 599 }; 600 601 /// ScheduleDAGTopologicalSort is a class that computes a topological 602 /// ordering for SUnits and provides methods for dynamically updating 603 /// the ordering as new edges are added. 604 /// 605 /// This allows a very fast implementation of IsReachable, for example. 606 /// 607 class ScheduleDAGTopologicalSort { 608 /// SUnits - A reference to the ScheduleDAG's SUnits. 609 std::vector<SUnit> &SUnits; 610 611 /// Index2Node - Maps topological index to the node number. 612 std::vector<int> Index2Node; 613 /// Node2Index - Maps the node number to its topological index. 614 std::vector<int> Node2Index; 615 /// Visited - a set of nodes visited during a DFS traversal. 616 BitVector Visited; 617 618 /// DFS - make a DFS traversal and mark all nodes affected by the 619 /// edge insertion. These nodes will later get new topological indexes 620 /// by means of the Shift method. 621 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop); 622 623 /// Shift - reassign topological indexes for the nodes in the DAG 624 /// to preserve the topological ordering. 625 void Shift(BitVector& Visited, int LowerBound, int UpperBound); 626 627 /// Allocate - assign the topological index to the node n. 628 void Allocate(int n, int index); 629 630 public: 631 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits); 632 633 /// InitDAGTopologicalSorting - create the initial topological 634 /// ordering from the DAG to be scheduled. 635 void InitDAGTopologicalSorting(); 636 637 /// IsReachable - Checks if SU is reachable from TargetSU. 638 bool IsReachable(const SUnit *SU, const SUnit *TargetSU); 639 640 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU 641 /// will create a cycle. 642 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU); 643 644 /// AddPred - Updates the topological ordering to accomodate an edge 645 /// to be added from SUnit X to SUnit Y. 646 void AddPred(SUnit *Y, SUnit *X); 647 648 /// RemovePred - Updates the topological ordering to accomodate an 649 /// an edge to be removed from the specified node N from the predecessors 650 /// of the current node M. 651 void RemovePred(SUnit *M, SUnit *N); 652 653 typedef std::vector<int>::iterator iterator; 654 typedef std::vector<int>::const_iterator const_iterator; 655 iterator begin() { return Index2Node.begin(); } 656 const_iterator begin() const { return Index2Node.begin(); } 657 iterator end() { return Index2Node.end(); } 658 const_iterator end() const { return Index2Node.end(); } 659 660 typedef std::vector<int>::reverse_iterator reverse_iterator; 661 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator; 662 reverse_iterator rbegin() { return Index2Node.rbegin(); } 663 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); } 664 reverse_iterator rend() { return Index2Node.rend(); } 665 const_reverse_iterator rend() const { return Index2Node.rend(); } 666 }; 667} 668 669#endif 670