1193323Sed//===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines interfaces to access the target independent code generation 11193323Sed// passes provided by the LLVM backend. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#ifndef LLVM_CODEGEN_PASSES_H 16193323Sed#define LLVM_CODEGEN_PASSES_H 17193323Sed 18234353Sdim#include "llvm/Pass.h" 19198396Srdivacky#include "llvm/Target/TargetMachine.h" 20193323Sed#include <string> 21193323Sed 22193323Sednamespace llvm { 23193323Sed 24193323Sed class FunctionPass; 25206124Srdivacky class MachineFunctionPass; 26193323Sed class PassInfo; 27239462Sdim class PassManagerBase; 28249423Sdim class TargetLoweringBase; 29193323Sed class TargetLowering; 30226633Sdim class TargetRegisterClass; 31198090Srdivacky class raw_ostream; 32234353Sdim} 33193323Sed 34234353Sdimnamespace llvm { 35234353Sdim 36234353Sdimclass PassConfigImpl; 37234353Sdim 38251662Sdim/// Discriminated union of Pass ID types. 39251662Sdim/// 40251662Sdim/// The PassConfig API prefers dealing with IDs because they are safer and more 41251662Sdim/// efficient. IDs decouple configuration from instantiation. This way, when a 42251662Sdim/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to 43251662Sdim/// refer to a Pass pointer after adding it to a pass manager, which deletes 44251662Sdim/// redundant pass instances. 45251662Sdim/// 46251662Sdim/// However, it is convient to directly instantiate target passes with 47251662Sdim/// non-default ctors. These often don't have a registered PassInfo. Rather than 48251662Sdim/// force all target passes to implement the pass registry boilerplate, allow 49251662Sdim/// the PassConfig API to handle either type. 50251662Sdim/// 51251662Sdim/// AnalysisID is sadly char*, so PointerIntPair won't work. 52251662Sdimclass IdentifyingPassPtr { 53251662Sdim union { 54251662Sdim AnalysisID ID; 55251662Sdim Pass *P; 56251662Sdim }; 57251662Sdim bool IsInstance; 58251662Sdimpublic: 59251662Sdim IdentifyingPassPtr() : P(0), IsInstance(false) {} 60251662Sdim IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {} 61251662Sdim IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {} 62251662Sdim 63251662Sdim bool isValid() const { return P; } 64251662Sdim bool isInstance() const { return IsInstance; } 65251662Sdim 66251662Sdim AnalysisID getID() const { 67251662Sdim assert(!IsInstance && "Not a Pass ID"); 68251662Sdim return ID; 69251662Sdim } 70251662Sdim Pass *getInstance() const { 71251662Sdim assert(IsInstance && "Not a Pass Instance"); 72251662Sdim return P; 73251662Sdim } 74251662Sdim}; 75251662Sdim 76251662Sdimtemplate <> struct isPodLike<IdentifyingPassPtr> { 77251662Sdim static const bool value = true; 78251662Sdim}; 79251662Sdim 80234353Sdim/// Target-Independent Code Generator Pass Configuration Options. 81234353Sdim/// 82234353Sdim/// This is an ImmutablePass solely for the purpose of exposing CodeGen options 83234353Sdim/// to the internals of other CodeGen passes. 84234353Sdimclass TargetPassConfig : public ImmutablePass { 85234353Sdimpublic: 86234353Sdim /// Pseudo Pass IDs. These are defined within TargetPassConfig because they 87234353Sdim /// are unregistered pass IDs. They are only useful for use with 88234353Sdim /// TargetPassConfig APIs to identify multiple occurrences of the same pass. 89234353Sdim /// 90234353Sdim 91234353Sdim /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early 92234353Sdim /// during codegen, on SSA form. 93234353Sdim static char EarlyTailDuplicateID; 94234353Sdim 95234353Sdim /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine 96234353Sdim /// optimization after regalloc. 97234353Sdim static char PostRAMachineLICMID; 98234353Sdim 99239462Sdimprivate: 100239462Sdim PassManagerBase *PM; 101239462Sdim AnalysisID StartAfter; 102239462Sdim AnalysisID StopAfter; 103239462Sdim bool Started; 104239462Sdim bool Stopped; 105239462Sdim 106234353Sdimprotected: 107234353Sdim TargetMachine *TM; 108234353Sdim PassConfigImpl *Impl; // Internal data structures 109234353Sdim bool Initialized; // Flagged after all passes are configured. 110234353Sdim 111234353Sdim // Target Pass Options 112234353Sdim // Targets provide a default setting, user flags override. 113234353Sdim // 114234353Sdim bool DisableVerify; 115234353Sdim 116234353Sdim /// Default setting for -enable-tail-merge on this target. 117234353Sdim bool EnableTailMerge; 118234353Sdim 119234353Sdimpublic: 120234353Sdim TargetPassConfig(TargetMachine *tm, PassManagerBase &pm); 121234353Sdim // Dummy constructor. 122234353Sdim TargetPassConfig(); 123234353Sdim 124234353Sdim virtual ~TargetPassConfig(); 125234353Sdim 126234353Sdim static char ID; 127234353Sdim 128234353Sdim /// Get the right type of TargetMachine for this target. 129234353Sdim template<typename TMC> TMC &getTM() const { 130234353Sdim return *static_cast<TMC*>(TM); 131234353Sdim } 132234353Sdim 133234353Sdim const TargetLowering *getTargetLowering() const { 134234353Sdim return TM->getTargetLowering(); 135234353Sdim } 136234353Sdim 137234353Sdim // 138234353Sdim void setInitialized() { Initialized = true; } 139234353Sdim 140234353Sdim CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } 141234353Sdim 142239462Sdim /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow 143239462Sdim /// running only a portion of the normal code-gen pass sequence. If the 144239462Sdim /// Start pass ID is zero, then compilation will begin at the normal point; 145239462Sdim /// otherwise, clear the Started flag to indicate that passes should not be 146239462Sdim /// added until the starting pass is seen. If the Stop pass ID is zero, 147239462Sdim /// then compilation will continue to the end. 148239462Sdim void setStartStopPasses(AnalysisID Start, AnalysisID Stop) { 149239462Sdim StartAfter = Start; 150239462Sdim StopAfter = Stop; 151239462Sdim Started = (StartAfter == 0); 152239462Sdim } 153239462Sdim 154234353Sdim void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } 155234353Sdim 156234353Sdim bool getEnableTailMerge() const { return EnableTailMerge; } 157234353Sdim void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } 158234353Sdim 159234353Sdim /// Allow the target to override a specific pass without overriding the pass 160234353Sdim /// pipeline. When passes are added to the standard pipeline at the 161239462Sdim /// point where StandardID is expected, add TargetID in its place. 162251662Sdim void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID); 163234353Sdim 164239462Sdim /// Insert InsertedPassID pass after TargetPassID pass. 165251662Sdim void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID); 166239462Sdim 167234353Sdim /// Allow the target to enable a specific standard pass by default. 168239462Sdim void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); } 169234353Sdim 170234353Sdim /// Allow the target to disable a specific standard pass by default. 171251662Sdim void disablePass(AnalysisID PassID) { 172251662Sdim substitutePass(PassID, IdentifyingPassPtr()); 173251662Sdim } 174234353Sdim 175239462Sdim /// Return the pass substituted for StandardID by the target. 176234353Sdim /// If no substitution exists, return StandardID. 177251662Sdim IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const; 178234353Sdim 179234353Sdim /// Return true if the optimized regalloc pipeline is enabled. 180234353Sdim bool getOptimizeRegAlloc() const; 181234353Sdim 182234353Sdim /// Add common target configurable passes that perform LLVM IR to IR 183234353Sdim /// transforms following machine independent optimization. 184234353Sdim virtual void addIRPasses(); 185234353Sdim 186239462Sdim /// Add passes to lower exception handling for the code generator. 187239462Sdim void addPassesToHandleExceptions(); 188239462Sdim 189249423Sdim /// Add pass to prepare the LLVM IR for code generation. This should be done 190249423Sdim /// before exception handling preparation passes. 191249423Sdim virtual void addCodeGenPrepare(); 192249423Sdim 193234353Sdim /// Add common passes that perform LLVM IR to IR transforms in preparation for 194234353Sdim /// instruction selection. 195234353Sdim virtual void addISelPrepare(); 196234353Sdim 197234353Sdim /// addInstSelector - This method should install an instruction selector pass, 198234353Sdim /// which converts from LLVM code to machine instructions. 199234353Sdim virtual bool addInstSelector() { 200234353Sdim return true; 201234353Sdim } 202234353Sdim 203234353Sdim /// Add the complete, standard set of LLVM CodeGen passes. 204234353Sdim /// Fully developed targets will not generally override this. 205234353Sdim virtual void addMachinePasses(); 206234353Sdim 207234353Sdimprotected: 208234353Sdim // Helper to verify the analysis is really immutable. 209234353Sdim void setOpt(bool &Opt, bool Val); 210234353Sdim 211234353Sdim /// Methods with trivial inline returns are convenient points in the common 212234353Sdim /// codegen pass pipeline where targets may insert passes. Methods with 213234353Sdim /// out-of-line standard implementations are major CodeGen stages called by 214234353Sdim /// addMachinePasses. Some targets may override major stages when inserting 215234353Sdim /// passes is insufficient, but maintaining overriden stages is more work. 216234353Sdim /// 217234353Sdim 218234353Sdim /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 219234353Sdim /// passes (which are run just before instruction selector). 220234353Sdim virtual bool addPreISel() { 221234353Sdim return true; 222234353Sdim } 223234353Sdim 224234353Sdim /// addMachineSSAOptimization - Add standard passes that optimize machine 225234353Sdim /// instructions in SSA form. 226234353Sdim virtual void addMachineSSAOptimization(); 227234353Sdim 228249423Sdim /// Add passes that optimize instruction level parallelism for out-of-order 229249423Sdim /// targets. These passes are run while the machine code is still in SSA 230249423Sdim /// form, so they can use MachineTraceMetrics to control their heuristics. 231249423Sdim /// 232249423Sdim /// All passes added here should preserve the MachineDominatorTree, 233249423Sdim /// MachineLoopInfo, and MachineTraceMetrics analyses. 234249423Sdim virtual bool addILPOpts() { 235249423Sdim return false; 236249423Sdim } 237249423Sdim 238234353Sdim /// addPreRegAlloc - This method may be implemented by targets that want to 239234353Sdim /// run passes immediately before register allocation. This should return 240234353Sdim /// true if -print-machineinstrs should print after these passes. 241234353Sdim virtual bool addPreRegAlloc() { 242234353Sdim return false; 243234353Sdim } 244234353Sdim 245234353Sdim /// createTargetRegisterAllocator - Create the register allocator pass for 246234353Sdim /// this target at the current optimization level. 247234353Sdim virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); 248234353Sdim 249234353Sdim /// addFastRegAlloc - Add the minimum set of target-independent passes that 250234353Sdim /// are required for fast register allocation. 251234353Sdim virtual void addFastRegAlloc(FunctionPass *RegAllocPass); 252234353Sdim 253234353Sdim /// addOptimizedRegAlloc - Add passes related to register allocation. 254234353Sdim /// LLVMTargetMachine provides standard regalloc passes for most targets. 255234353Sdim virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); 256234353Sdim 257239462Sdim /// addPreRewrite - Add passes to the optimized register allocation pipeline 258239462Sdim /// after register allocation is complete, but before virtual registers are 259239462Sdim /// rewritten to physical registers. 260239462Sdim /// 261239462Sdim /// These passes must preserve VirtRegMap and LiveIntervals, and when running 262239462Sdim /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. 263239462Sdim /// When these passes run, VirtRegMap contains legal physreg assignments for 264239462Sdim /// all virtual registers. 265239462Sdim virtual bool addPreRewrite() { 266239462Sdim return false; 267239462Sdim } 268239462Sdim 269234353Sdim /// addPostRegAlloc - This method may be implemented by targets that want to 270234353Sdim /// run passes after register allocation pass pipeline but before 271234353Sdim /// prolog-epilog insertion. This should return true if -print-machineinstrs 272234353Sdim /// should print after these passes. 273234353Sdim virtual bool addPostRegAlloc() { 274234353Sdim return false; 275234353Sdim } 276234353Sdim 277234353Sdim /// Add passes that optimize machine instructions after register allocation. 278234353Sdim virtual void addMachineLateOptimization(); 279234353Sdim 280234353Sdim /// addPreSched2 - This method may be implemented by targets that want to 281234353Sdim /// run passes after prolog-epilog insertion and before the second instruction 282234353Sdim /// scheduling pass. This should return true if -print-machineinstrs should 283234353Sdim /// print after these passes. 284234353Sdim virtual bool addPreSched2() { 285234353Sdim return false; 286234353Sdim } 287234353Sdim 288249423Sdim /// addGCPasses - Add late codegen passes that analyze code for garbage 289249423Sdim /// collection. This should return true if GC info should be printed after 290249423Sdim /// these passes. 291249423Sdim virtual bool addGCPasses(); 292249423Sdim 293234353Sdim /// Add standard basic block placement passes. 294234353Sdim virtual void addBlockPlacement(); 295234353Sdim 296234353Sdim /// addPreEmitPass - This pass may be implemented by targets that want to run 297234353Sdim /// passes immediately before machine code is emitted. This should return 298234353Sdim /// true if -print-machineinstrs should print out the code after the passes. 299234353Sdim virtual bool addPreEmitPass() { 300234353Sdim return false; 301234353Sdim } 302234353Sdim 303234353Sdim /// Utilities for targets to add passes to the pass manager. 304234353Sdim /// 305234353Sdim 306234353Sdim /// Add a CodeGen pass at this point in the pipeline after checking overrides. 307239462Sdim /// Return the pass that was added, or zero if no pass was added. 308239462Sdim AnalysisID addPass(AnalysisID PassID); 309234353Sdim 310239462Sdim /// Add a pass to the PassManager if that pass is supposed to be run, as 311239462Sdim /// determined by the StartAfter and StopAfter options. 312239462Sdim void addPass(Pass *P); 313239462Sdim 314234353Sdim /// addMachinePasses helper to create the target-selected or overriden 315234353Sdim /// regalloc pass. 316234353Sdim FunctionPass *createRegAllocPass(bool Optimized); 317234353Sdim 318234353Sdim /// printAndVerify - Add a pass to dump then verify the machine function, if 319234353Sdim /// those steps are enabled. 320234353Sdim /// 321239462Sdim void printAndVerify(const char *Banner); 322234353Sdim}; 323234353Sdim} // namespace llvm 324234353Sdim 325234353Sdim/// List of target independent CodeGen pass IDs. 326234353Sdimnamespace llvm { 327249423Sdim /// \brief Create a basic TargetTransformInfo analysis pass. 328249423Sdim /// 329249423Sdim /// This pass implements the target transform info analysis using the target 330249423Sdim /// independent information available to the LLVM code generator. 331249423Sdim ImmutablePass * 332249423Sdim createBasicTargetTransformInfoPass(const TargetLoweringBase *TLI); 333249423Sdim 334193323Sed /// createUnreachableBlockEliminationPass - The LLVM code generator does not 335193323Sed /// work well with unreachable basic blocks (what live ranges make sense for a 336193323Sed /// block that cannot be reached?). As such, a code generator should either 337212904Sdim /// not instruction select unreachable blocks, or run this pass as its 338193323Sed /// last LLVM modifying pass to clean up blocks that are not reachable from 339193323Sed /// the entry block. 340193323Sed FunctionPass *createUnreachableBlockEliminationPass(); 341193323Sed 342193323Sed /// MachineFunctionPrinter pass - This pass prints out the machine function to 343212904Sdim /// the given stream as a debugging tool. 344206124Srdivacky MachineFunctionPass * 345206124Srdivacky createMachineFunctionPrinterPass(raw_ostream &OS, 346206124Srdivacky const std::string &Banner =""); 347193323Sed 348234353Sdim /// MachineLoopInfo - This pass is a loop analysis pass. 349212904Sdim extern char &MachineLoopInfoID; 350193323Sed 351234353Sdim /// MachineDominators - This pass is a machine dominators analysis pass. 352212904Sdim extern char &MachineDominatorsID; 353193323Sed 354218893Sdim /// EdgeBundles analysis - Bundle machine CFG edges. 355218893Sdim extern char &EdgeBundlesID; 356218893Sdim 357234353Sdim /// LiveVariables pass - This pass computes the set of blocks in which each 358234353Sdim /// variable is life and sets machine operand kill flags. 359234353Sdim extern char &LiveVariablesID; 360234353Sdim 361234353Sdim /// PHIElimination - This pass eliminates machine instruction PHI nodes 362193323Sed /// by inserting copy instructions. This destroys SSA information, but is the 363193323Sed /// desired input for some register allocators. This pass is "required" by 364193323Sed /// these register allocator like this: AU.addRequiredID(PHIEliminationID); 365212904Sdim extern char &PHIEliminationID; 366212904Sdim 367234353Sdim /// StrongPHIElimination - This pass eliminates machine instruction PHI 368193323Sed /// nodes by inserting copy instructions. This destroys SSA information, but 369193323Sed /// is the desired input for some register allocators. This pass is 370193323Sed /// "required" by these register allocator like this: 371193323Sed /// AU.addRequiredID(PHIEliminationID); 372193323Sed /// This pass is still in development 373212904Sdim extern char &StrongPHIEliminationID; 374193323Sed 375239462Sdim /// LiveIntervals - This analysis keeps track of the live ranges of virtual 376239462Sdim /// and physical registers. 377239462Sdim extern char &LiveIntervalsID; 378239462Sdim 379218893Sdim /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. 380218893Sdim extern char &LiveStacksID; 381218893Sdim 382234353Sdim /// TwoAddressInstruction - This pass reduces two-address instructions to 383193323Sed /// use two operands. This destroys SSA information but it is desired by 384193323Sed /// register allocators. 385212904Sdim extern char &TwoAddressInstructionPassID; 386193323Sed 387234353Sdim /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. 388234353Sdim extern char &ProcessImplicitDefsID; 389226633Sdim 390234353Sdim /// RegisterCoalescer - This pass merges live ranges to eliminate copies. 391234353Sdim extern char &RegisterCoalescerID; 392234353Sdim 393234353Sdim /// MachineScheduler - This pass schedules machine instructions. 394234353Sdim extern char &MachineSchedulerID; 395234353Sdim 396218893Sdim /// SpillPlacement analysis. Suggest optimal placement of spill code between 397218893Sdim /// basic blocks. 398218893Sdim extern char &SpillPlacementID; 399218893Sdim 400239462Sdim /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as 401239462Sdim /// assigned in VirtRegMap. 402239462Sdim extern char &VirtRegRewriterID; 403239462Sdim 404234353Sdim /// UnreachableMachineBlockElimination - This pass removes unreachable 405193323Sed /// machine basic blocks. 406212904Sdim extern char &UnreachableMachineBlockElimID; 407193323Sed 408234353Sdim /// DeadMachineInstructionElim - This pass removes dead machine instructions. 409234353Sdim extern char &DeadMachineInstructionElimID; 410193323Sed 411207618Srdivacky /// FastRegisterAllocation Pass - This pass register allocates as fast as 412207618Srdivacky /// possible. It is best suited for debug code where live ranges are short. 413207618Srdivacky /// 414207618Srdivacky FunctionPass *createFastRegisterAllocator(); 415207618Srdivacky 416218893Sdim /// BasicRegisterAllocation Pass - This pass implements a degenerate global 417218893Sdim /// register allocator using the basic regalloc framework. 418218893Sdim /// 419218893Sdim FunctionPass *createBasicRegisterAllocator(); 420218893Sdim 421218893Sdim /// Greedy register allocation pass - This pass implements a global register 422218893Sdim /// allocator for optimized builds. 423218893Sdim /// 424218893Sdim FunctionPass *createGreedyRegisterAllocator(); 425218893Sdim 426193323Sed /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean 427193323Sed /// Quadratic Prograaming (PBQP) based register allocator. 428193323Sed /// 429218893Sdim FunctionPass *createDefaultPBQPRegisterAllocator(); 430193323Sed 431234353Sdim /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, 432193323Sed /// and eliminates abstract frame references. 433234353Sdim extern char &PrologEpilogCodeInserterID; 434212904Sdim 435234353Sdim /// ExpandPostRAPseudos - This pass expands pseudo instructions after 436226633Sdim /// register allocation. 437234353Sdim extern char &ExpandPostRAPseudosID; 438193323Sed 439198396Srdivacky /// createPostRAScheduler - This pass performs post register allocation 440198396Srdivacky /// scheduling. 441234353Sdim extern char &PostRASchedulerID; 442193323Sed 443234353Sdim /// BranchFolding - This pass performs machine code CFG based 444193323Sed /// optimizations to delete branches to branches, eliminate branches to 445193323Sed /// successor blocks (creating fall throughs), and eliminating branches over 446193323Sed /// branches. 447234353Sdim extern char &BranchFolderPassID; 448193323Sed 449239462Sdim /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. 450239462Sdim extern char &MachineFunctionPrinterPassID; 451239462Sdim 452234353Sdim /// TailDuplicate - Duplicate blocks with unconditional branches 453199989Srdivacky /// into tails of their predecessors. 454234353Sdim extern char &TailDuplicateID; 455199989Srdivacky 456239462Sdim /// MachineTraceMetrics - This pass computes critical path and CPU resource 457239462Sdim /// usage in an ensemble of traces. 458239462Sdim extern char &MachineTraceMetricsID; 459239462Sdim 460239462Sdim /// EarlyIfConverter - This pass performs if-conversion on SSA form by 461239462Sdim /// inserting cmov instructions. 462239462Sdim extern char &EarlyIfConverterID; 463239462Sdim 464243830Sdim /// StackSlotColoring - This pass performs stack coloring and merging. 465243830Sdim /// It merges disjoint allocas to reduce the stack size. 466243830Sdim extern char &StackColoringID; 467243830Sdim 468234353Sdim /// IfConverter - This pass performs machine code if conversion. 469234353Sdim extern char &IfConverterID; 470193323Sed 471234353Sdim /// MachineBlockPlacement - This pass places basic blocks based on branch 472234353Sdim /// probabilities. 473234353Sdim extern char &MachineBlockPlacementID; 474234353Sdim 475234353Sdim /// MachineBlockPlacementStats - This pass collects statistics about the 476234353Sdim /// basic block placement using branch probabilities and block frequency 477234353Sdim /// information. 478234353Sdim extern char &MachineBlockPlacementStatsID; 479234353Sdim 480234353Sdim /// GCLowering Pass - Performs target-independent LLVM IR transformations for 481234353Sdim /// highly portable strategies. 482234353Sdim /// 483193323Sed FunctionPass *createGCLoweringPass(); 484212904Sdim 485234353Sdim /// GCMachineCodeAnalysis - Target-independent pass to mark safe points 486234353Sdim /// in machine code. Must be added very late during code generation, just 487234353Sdim /// prior to output, and importantly after all CFG transformations (such as 488234353Sdim /// branch folding). 489234353Sdim extern char &GCMachineCodeAnalysisID; 490212904Sdim 491193323Sed /// Creates a pass to print GC metadata. 492212904Sdim /// 493198090Srdivacky FunctionPass *createGCInfoPrinter(raw_ostream &OS); 494212904Sdim 495234353Sdim /// MachineCSE - This pass performs global CSE on machine instructions. 496234353Sdim extern char &MachineCSEID; 497204642Srdivacky 498234353Sdim /// MachineLICM - This pass performs LICM on machine instructions. 499234353Sdim extern char &MachineLICMID; 500193323Sed 501234353Sdim /// MachineSinking - This pass performs sinking on machine instructions. 502234353Sdim extern char &MachineSinkingID; 503193323Sed 504234353Sdim /// MachineCopyPropagation - This pass performs copy propagation on 505234353Sdim /// machine instructions. 506234353Sdim extern char &MachineCopyPropagationID; 507234353Sdim 508234353Sdim /// PeepholeOptimizer - This pass performs peephole optimizations - 509212904Sdim /// like extension and comparison eliminations. 510234353Sdim extern char &PeepholeOptimizerID; 511202375Srdivacky 512234353Sdim /// OptimizePHIs - This pass optimizes machine instruction PHIs 513203954Srdivacky /// to take advantage of opportunities created during DAG legalization. 514234353Sdim extern char &OptimizePHIsID; 515203954Srdivacky 516234353Sdim /// StackSlotColoring - This pass performs stack slot coloring. 517234353Sdim extern char &StackSlotColoringID; 518193323Sed 519193323Sed /// createStackProtectorPass - This pass adds stack protectors to functions. 520234353Sdim /// 521249423Sdim FunctionPass *createStackProtectorPass(const TargetLoweringBase *tli); 522193323Sed 523193323Sed /// createMachineVerifierPass - This pass verifies cenerated machine code 524193323Sed /// instructions for correctness. 525234353Sdim /// 526218893Sdim FunctionPass *createMachineVerifierPass(const char *Banner = 0); 527193323Sed 528193323Sed /// createDwarfEHPass - This pass mulches exception handling code into a form 529193323Sed /// adapted to code generation. Required if using dwarf exception handling. 530212904Sdim FunctionPass *createDwarfEHPass(const TargetMachine *tm); 531193323Sed 532234353Sdim /// createSjLjEHPreparePass - This pass adapts exception handling code to use 533198090Srdivacky /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. 534234353Sdim /// 535249423Sdim FunctionPass *createSjLjEHPreparePass(const TargetLoweringBase *tli); 536198090Srdivacky 537234353Sdim /// LocalStackSlotAllocation - This pass assigns local frame indices to stack 538234353Sdim /// slots relative to one another and allocates base registers to access them 539234353Sdim /// when it is estimated by the target to be out of range of normal frame 540234353Sdim /// pointer or stack pointer index addressing. 541234353Sdim extern char &LocalStackSlotAllocationID; 542212904Sdim 543234353Sdim /// ExpandISelPseudos - This pass expands pseudo-instructions. 544234353Sdim extern char &ExpandISelPseudosID; 545218893Sdim 546226633Sdim /// createExecutionDependencyFixPass - This pass fixes execution time 547226633Sdim /// problems with dependent instructions, such as switching execution 548226633Sdim /// domains to match. 549226633Sdim /// 550226633Sdim /// The pass will examine instructions using and defining registers in RC. 551226633Sdim /// 552226633Sdim FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); 553226633Sdim 554234353Sdim /// UnpackMachineBundles - This pass unpack machine instruction bundles. 555234353Sdim extern char &UnpackMachineBundlesID; 556234353Sdim 557234353Sdim /// FinalizeMachineBundles - This pass finalize machine instruction 558234353Sdim /// bundles (created earlier, e.g. during pre-RA scheduling). 559234353Sdim extern char &FinalizeMachineBundlesID; 560234353Sdim 561193323Sed} // End llvm namespace 562193323Sed 563193323Sed#endif 564