MachineRegisterInfo.h revision 208599
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include <vector> 20 21namespace llvm { 22 23/// MachineRegisterInfo - Keep track of information for virtual and physical 24/// registers, including vreg register classes, use/def chains for registers, 25/// etc. 26class MachineRegisterInfo { 27 /// VRegInfo - Information we keep for each virtual register. The entries in 28 /// this vector are actually converted to vreg numbers by adding the 29 /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 30 /// 31 /// Each element in this list contains the register class of the vreg and the 32 /// start of the use/def list for the register. 33 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 34 35 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 36 /// virtual registers. For each target register class, it keeps a list of 37 /// virtual registers belonging to the class. 38 std::vector<std::vector<unsigned> > RegClass2VRegMap; 39 40 /// RegAllocHints - This vector records register allocation hints for virtual 41 /// registers. For each virtual register, it keeps a register and hint type 42 /// pair making up the allocation hint. Hint type is target specific except 43 /// for the value 0 which means the second value of the pair is the preferred 44 /// register for allocation. For example, if the hint is <0, 1024>, it means 45 /// the allocator should prefer the physical register allocated to the virtual 46 /// register of the hint. 47 std::vector<std::pair<unsigned, unsigned> > RegAllocHints; 48 49 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 50 /// physical registers. 51 MachineOperand **PhysRegUseDefLists; 52 53 /// UsedPhysRegs - This is a bit vector that is computed and set by the 54 /// register allocator, and must be kept up to date by passes that run after 55 /// register allocation (though most don't modify this). This is used 56 /// so that the code generator knows which callee save registers to save and 57 /// for other target specific uses. 58 BitVector UsedPhysRegs; 59 60 /// LiveIns/LiveOuts - Keep track of the physical registers that are 61 /// livein/liveout of the function. Live in values are typically arguments in 62 /// registers, live out values are typically return values in registers. 63 /// LiveIn values are allowed to have virtual registers associated with them, 64 /// stored in the second element. 65 std::vector<std::pair<unsigned, unsigned> > LiveIns; 66 std::vector<unsigned> LiveOuts; 67 68 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 69 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 70public: 71 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 72 ~MachineRegisterInfo(); 73 74 //===--------------------------------------------------------------------===// 75 // Register Info 76 //===--------------------------------------------------------------------===// 77 78 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 79 /// and uses of a register within the MachineFunction that corresponds to this 80 /// MachineRegisterInfo object. 81 template<bool Uses, bool Defs, bool SkipDebug> 82 class defusechain_iterator; 83 84 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 85 /// register. 86 typedef defusechain_iterator<true,true,false> reg_iterator; 87 reg_iterator reg_begin(unsigned RegNo) const { 88 return reg_iterator(getRegUseDefListHead(RegNo)); 89 } 90 static reg_iterator reg_end() { return reg_iterator(0); } 91 92 /// reg_empty - Return true if there are no instructions using or defining the 93 /// specified register (it may be live-in). 94 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 95 96 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 97 /// of the specified register, skipping those marked as Debug. 98 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 99 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 100 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 101 } 102 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 103 104 /// reg_nodbg_empty - Return true if the only instructions using or defining 105 /// Reg are Debug instructions. 106 bool reg_nodbg_empty(unsigned RegNo) const { 107 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 108 } 109 110 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 111 typedef defusechain_iterator<false,true,false> def_iterator; 112 def_iterator def_begin(unsigned RegNo) const { 113 return def_iterator(getRegUseDefListHead(RegNo)); 114 } 115 static def_iterator def_end() { return def_iterator(0); } 116 117 /// def_empty - Return true if there are no instructions defining the 118 /// specified register (it may be live-in). 119 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 120 121 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 122 typedef defusechain_iterator<true,false,false> use_iterator; 123 use_iterator use_begin(unsigned RegNo) const { 124 return use_iterator(getRegUseDefListHead(RegNo)); 125 } 126 static use_iterator use_end() { return use_iterator(0); } 127 128 /// use_empty - Return true if there are no instructions using the specified 129 /// register. 130 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 131 132 /// hasOneUse - Return true if there is exactly one instruction using the 133 /// specified register. 134 bool hasOneUse(unsigned RegNo) const; 135 136 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 137 /// specified register, skipping those marked as Debug. 138 typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 139 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 140 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 141 } 142 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 143 144 /// use_nodbg_empty - Return true if there are no non-Debug instructions 145 /// using the specified register. 146 bool use_nodbg_empty(unsigned RegNo) const { 147 return use_nodbg_begin(RegNo) == use_nodbg_end(); 148 } 149 150 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 151 /// instruction using the specified register. 152 bool hasOneNonDBGUse(unsigned RegNo) const; 153 154 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 155 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 156 /// except that it also changes any definitions of the register as well. 157 void replaceRegWith(unsigned FromReg, unsigned ToReg); 158 159 /// getRegUseDefListHead - Return the head pointer for the register use/def 160 /// list for the specified virtual or physical register. 161 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 162 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 163 return PhysRegUseDefLists[RegNo]; 164 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 165 return VRegInfo[RegNo].second; 166 } 167 168 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 169 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 170 return PhysRegUseDefLists[RegNo]; 171 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 172 return VRegInfo[RegNo].second; 173 } 174 175 /// getVRegDef - Return the machine instr that defines the specified virtual 176 /// register or null if none is found. This assumes that the code is in SSA 177 /// form, so there should only be one definition. 178 MachineInstr *getVRegDef(unsigned Reg) const; 179 180 /// clearKillFlags - Iterate over all the uses of the given register and 181 /// clear the kill flag from the MachineOperand. This function is used by 182 /// optimization passes which extend register lifetimes and need only 183 /// preserve conservative kill flag information. 184 void clearKillFlags(unsigned Reg) const; 185 186#ifndef NDEBUG 187 void dumpUses(unsigned RegNo) const; 188#endif 189 190 //===--------------------------------------------------------------------===// 191 // Virtual Register Info 192 //===--------------------------------------------------------------------===// 193 194 /// getRegClass - Return the register class of the specified virtual register. 195 /// 196 const TargetRegisterClass *getRegClass(unsigned Reg) const { 197 Reg -= TargetRegisterInfo::FirstVirtualRegister; 198 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 199 return VRegInfo[Reg].first; 200 } 201 202 /// setRegClass - Set the register class of the specified virtual register. 203 /// 204 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 205 206 /// createVirtualRegister - Create and return a new virtual register in the 207 /// function with the specified register class. 208 /// 209 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 210 211 /// getLastVirtReg - Return the highest currently assigned virtual register. 212 /// 213 unsigned getLastVirtReg() const { 214 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 215 } 216 217 /// getRegClassVirtRegs - Return the list of virtual registers of the given 218 /// target register class. 219 const std::vector<unsigned> & 220 getRegClassVirtRegs(const TargetRegisterClass *RC) const { 221 return RegClass2VRegMap[RC->getID()]; 222 } 223 224 /// setRegAllocationHint - Specify a register allocation hint for the 225 /// specified virtual register. 226 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 227 Reg -= TargetRegisterInfo::FirstVirtualRegister; 228 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 229 RegAllocHints[Reg].first = Type; 230 RegAllocHints[Reg].second = PrefReg; 231 } 232 233 /// getRegAllocationHint - Return the register allocation hint for the 234 /// specified virtual register. 235 std::pair<unsigned, unsigned> 236 getRegAllocationHint(unsigned Reg) const { 237 Reg -= TargetRegisterInfo::FirstVirtualRegister; 238 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 239 return RegAllocHints[Reg]; 240 } 241 242 //===--------------------------------------------------------------------===// 243 // Physical Register Use Info 244 //===--------------------------------------------------------------------===// 245 246 /// isPhysRegUsed - Return true if the specified register is used in this 247 /// function. This only works after register allocation. 248 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 249 250 /// setPhysRegUsed - Mark the specified register used in this function. 251 /// This should only be called during and after register allocation. 252 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 253 254 /// addPhysRegsUsed - Mark the specified registers used in this function. 255 /// This should only be called during and after register allocation. 256 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 257 258 /// setPhysRegUnused - Mark the specified register unused in this function. 259 /// This should only be called during and after register allocation. 260 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 261 262 /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 263 /// subregisters. That means that if R is used, so are all subregisters. 264 void closePhysRegsUsed(const TargetRegisterInfo&); 265 266 //===--------------------------------------------------------------------===// 267 // LiveIn/LiveOut Management 268 //===--------------------------------------------------------------------===// 269 270 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 271 /// is an error to add the same register to the same set more than once. 272 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 273 LiveIns.push_back(std::make_pair(Reg, vreg)); 274 } 275 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 276 277 // Iteration support for live in/out sets. These sets are kept in sorted 278 // order by their register number. 279 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 280 livein_iterator; 281 typedef std::vector<unsigned>::const_iterator liveout_iterator; 282 livein_iterator livein_begin() const { return LiveIns.begin(); } 283 livein_iterator livein_end() const { return LiveIns.end(); } 284 bool livein_empty() const { return LiveIns.empty(); } 285 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 286 liveout_iterator liveout_end() const { return LiveOuts.end(); } 287 bool liveout_empty() const { return LiveOuts.empty(); } 288 289 bool isLiveIn(unsigned Reg) const; 290 bool isLiveOut(unsigned Reg) const; 291 292 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 293 /// corresponding live-in physical register. 294 unsigned getLiveInPhysReg(unsigned VReg) const; 295 296 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 297 /// corresponding live-in physical register. 298 unsigned getLiveInVirtReg(unsigned PReg) const; 299 300 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 301 /// into the given entry block. 302 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 303 const TargetRegisterInfo &TRI, 304 const TargetInstrInfo &TII); 305 306private: 307 void HandleVRegListReallocation(); 308 309public: 310 /// defusechain_iterator - This class provides iterator support for machine 311 /// operands in the function that use or define a specific register. If 312 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 313 /// returns defs. If neither are true then you are silly and it always 314 /// returns end(). If SkipDebug is true it skips uses marked Debug 315 /// when incrementing. 316 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 317 class defusechain_iterator 318 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 319 MachineOperand *Op; 320 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 321 // If the first node isn't one we're interested in, advance to one that 322 // we are interested in. 323 if (op) { 324 if ((!ReturnUses && op->isUse()) || 325 (!ReturnDefs && op->isDef()) || 326 (SkipDebug && op->isDebug())) 327 ++*this; 328 } 329 } 330 friend class MachineRegisterInfo; 331 public: 332 typedef std::iterator<std::forward_iterator_tag, 333 MachineInstr, ptrdiff_t>::reference reference; 334 typedef std::iterator<std::forward_iterator_tag, 335 MachineInstr, ptrdiff_t>::pointer pointer; 336 337 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 338 defusechain_iterator() : Op(0) {} 339 340 bool operator==(const defusechain_iterator &x) const { 341 return Op == x.Op; 342 } 343 bool operator!=(const defusechain_iterator &x) const { 344 return !operator==(x); 345 } 346 347 /// atEnd - return true if this iterator is equal to reg_end() on the value. 348 bool atEnd() const { return Op == 0; } 349 350 // Iterator traversal: forward iteration only 351 defusechain_iterator &operator++() { // Preincrement 352 assert(Op && "Cannot increment end iterator!"); 353 Op = Op->getNextOperandForReg(); 354 355 // If this is an operand we don't care about, skip it. 356 while (Op && ((!ReturnUses && Op->isUse()) || 357 (!ReturnDefs && Op->isDef()) || 358 (SkipDebug && Op->isDebug()))) 359 Op = Op->getNextOperandForReg(); 360 361 return *this; 362 } 363 defusechain_iterator operator++(int) { // Postincrement 364 defusechain_iterator tmp = *this; ++*this; return tmp; 365 } 366 367 MachineOperand &getOperand() const { 368 assert(Op && "Cannot dereference end iterator!"); 369 return *Op; 370 } 371 372 /// getOperandNo - Return the operand # of this MachineOperand in its 373 /// MachineInstr. 374 unsigned getOperandNo() const { 375 assert(Op && "Cannot dereference end iterator!"); 376 return Op - &Op->getParent()->getOperand(0); 377 } 378 379 // Retrieve a reference to the current operand. 380 MachineInstr &operator*() const { 381 assert(Op && "Cannot dereference end iterator!"); 382 return *Op->getParent(); 383 } 384 385 MachineInstr *operator->() const { 386 assert(Op && "Cannot dereference end iterator!"); 387 return Op->getParent(); 388 } 389 }; 390 391}; 392 393} // End llvm namespace 394 395#endif 396