MachineRegisterInfo.h revision 203954
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include <vector> 20 21namespace llvm { 22 23/// MachineRegisterInfo - Keep track of information for virtual and physical 24/// registers, including vreg register classes, use/def chains for registers, 25/// etc. 26class MachineRegisterInfo { 27 /// VRegInfo - Information we keep for each virtual register. The entries in 28 /// this vector are actually converted to vreg numbers by adding the 29 /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 30 /// 31 /// Each element in this list contains the register class of the vreg and the 32 /// start of the use/def list for the register. 33 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 34 35 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 36 /// virtual registers. For each target register class, it keeps a list of 37 /// virtual registers belonging to the class. 38 std::vector<std::vector<unsigned> > RegClass2VRegMap; 39 40 /// RegAllocHints - This vector records register allocation hints for virtual 41 /// registers. For each virtual register, it keeps a register and hint type 42 /// pair making up the allocation hint. Hint type is target specific except 43 /// for the value 0 which means the second value of the pair is the preferred 44 /// register for allocation. For example, if the hint is <0, 1024>, it means 45 /// the allocator should prefer the physical register allocated to the virtual 46 /// register of the hint. 47 std::vector<std::pair<unsigned, unsigned> > RegAllocHints; 48 49 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 50 /// physical registers. 51 MachineOperand **PhysRegUseDefLists; 52 53 /// UsedPhysRegs - This is a bit vector that is computed and set by the 54 /// register allocator, and must be kept up to date by passes that run after 55 /// register allocation (though most don't modify this). This is used 56 /// so that the code generator knows which callee save registers to save and 57 /// for other target specific uses. 58 BitVector UsedPhysRegs; 59 60 /// LiveIns/LiveOuts - Keep track of the physical registers that are 61 /// livein/liveout of the function. Live in values are typically arguments in 62 /// registers, live out values are typically return values in registers. 63 /// LiveIn values are allowed to have virtual registers associated with them, 64 /// stored in the second element. 65 std::vector<std::pair<unsigned, unsigned> > LiveIns; 66 std::vector<unsigned> LiveOuts; 67 68 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 69 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 70public: 71 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 72 ~MachineRegisterInfo(); 73 74 //===--------------------------------------------------------------------===// 75 // Register Info 76 //===--------------------------------------------------------------------===// 77 78 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 79 /// and uses of a register within the MachineFunction that corresponds to this 80 /// MachineRegisterInfo object. 81 template<bool Uses, bool Defs, bool SkipDebug> 82 class defusechain_iterator; 83 84 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 85 /// register. 86 typedef defusechain_iterator<true,true,false> reg_iterator; 87 reg_iterator reg_begin(unsigned RegNo) const { 88 return reg_iterator(getRegUseDefListHead(RegNo)); 89 } 90 static reg_iterator reg_end() { return reg_iterator(0); } 91 92 /// reg_empty - Return true if there are no instructions using or defining the 93 /// specified register (it may be live-in). 94 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 95 96 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 97 typedef defusechain_iterator<false,true,false> def_iterator; 98 def_iterator def_begin(unsigned RegNo) const { 99 return def_iterator(getRegUseDefListHead(RegNo)); 100 } 101 static def_iterator def_end() { return def_iterator(0); } 102 103 /// def_empty - Return true if there are no instructions defining the 104 /// specified register (it may be live-in). 105 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 106 107 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 108 typedef defusechain_iterator<true,false,false> use_iterator; 109 use_iterator use_begin(unsigned RegNo) const { 110 return use_iterator(getRegUseDefListHead(RegNo)); 111 } 112 static use_iterator use_end() { return use_iterator(0); } 113 114 /// use_empty - Return true if there are no instructions using the specified 115 /// register. 116 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 117 118 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 119 /// specified register, skipping those marked as Debug. 120 typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 121 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 122 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 123 } 124 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 125 126 /// use_nodbg_empty - Return true if there are no non-Debug instructions 127 /// using the specified register. 128 bool use_nodbg_empty(unsigned RegNo) const { 129 return use_nodbg_begin(RegNo) == use_nodbg_end(); 130 } 131 132 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 133 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 134 /// except that it also changes any definitions of the register as well. 135 void replaceRegWith(unsigned FromReg, unsigned ToReg); 136 137 /// getRegUseDefListHead - Return the head pointer for the register use/def 138 /// list for the specified virtual or physical register. 139 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 140 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 141 return PhysRegUseDefLists[RegNo]; 142 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 143 return VRegInfo[RegNo].second; 144 } 145 146 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 147 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 148 return PhysRegUseDefLists[RegNo]; 149 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 150 return VRegInfo[RegNo].second; 151 } 152 153 /// getVRegDef - Return the machine instr that defines the specified virtual 154 /// register or null if none is found. This assumes that the code is in SSA 155 /// form, so there should only be one definition. 156 MachineInstr *getVRegDef(unsigned Reg) const; 157 158#ifndef NDEBUG 159 void dumpUses(unsigned RegNo) const; 160#endif 161 162 //===--------------------------------------------------------------------===// 163 // Virtual Register Info 164 //===--------------------------------------------------------------------===// 165 166 /// getRegClass - Return the register class of the specified virtual register. 167 /// 168 const TargetRegisterClass *getRegClass(unsigned Reg) const { 169 Reg -= TargetRegisterInfo::FirstVirtualRegister; 170 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 171 return VRegInfo[Reg].first; 172 } 173 174 /// setRegClass - Set the register class of the specified virtual register. 175 /// 176 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 177 178 /// createVirtualRegister - Create and return a new virtual register in the 179 /// function with the specified register class. 180 /// 181 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 182 183 /// getLastVirtReg - Return the highest currently assigned virtual register. 184 /// 185 unsigned getLastVirtReg() const { 186 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 187 } 188 189 /// getRegClassVirtRegs - Return the list of virtual registers of the given 190 /// target register class. 191 std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) { 192 return RegClass2VRegMap[RC->getID()]; 193 } 194 195 /// setRegAllocationHint - Specify a register allocation hint for the 196 /// specified virtual register. 197 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 198 Reg -= TargetRegisterInfo::FirstVirtualRegister; 199 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 200 RegAllocHints[Reg].first = Type; 201 RegAllocHints[Reg].second = PrefReg; 202 } 203 204 /// getRegAllocationHint - Return the register allocation hint for the 205 /// specified virtual register. 206 std::pair<unsigned, unsigned> 207 getRegAllocationHint(unsigned Reg) const { 208 Reg -= TargetRegisterInfo::FirstVirtualRegister; 209 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 210 return RegAllocHints[Reg]; 211 } 212 213 //===--------------------------------------------------------------------===// 214 // Physical Register Use Info 215 //===--------------------------------------------------------------------===// 216 217 /// isPhysRegUsed - Return true if the specified register is used in this 218 /// function. This only works after register allocation. 219 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 220 221 /// setPhysRegUsed - Mark the specified register used in this function. 222 /// This should only be called during and after register allocation. 223 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 224 225 /// setPhysRegUnused - Mark the specified register unused in this function. 226 /// This should only be called during and after register allocation. 227 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 228 229 230 //===--------------------------------------------------------------------===// 231 // LiveIn/LiveOut Management 232 //===--------------------------------------------------------------------===// 233 234 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 235 /// is an error to add the same register to the same set more than once. 236 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 237 LiveIns.push_back(std::make_pair(Reg, vreg)); 238 } 239 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 240 241 // Iteration support for live in/out sets. These sets are kept in sorted 242 // order by their register number. 243 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 244 livein_iterator; 245 typedef std::vector<unsigned>::const_iterator liveout_iterator; 246 livein_iterator livein_begin() const { return LiveIns.begin(); } 247 livein_iterator livein_end() const { return LiveIns.end(); } 248 bool livein_empty() const { return LiveIns.empty(); } 249 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 250 liveout_iterator liveout_end() const { return LiveOuts.end(); } 251 bool liveout_empty() const { return LiveOuts.empty(); } 252 253 bool isLiveIn(unsigned Reg) const { 254 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 255 if (I->first == Reg || I->second == Reg) 256 return true; 257 return false; 258 } 259 bool isLiveOut(unsigned Reg) const { 260 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 261 if (*I == Reg) 262 return true; 263 return false; 264 } 265 266private: 267 void HandleVRegListReallocation(); 268 269public: 270 /// defusechain_iterator - This class provides iterator support for machine 271 /// operands in the function that use or define a specific register. If 272 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 273 /// returns defs. If neither are true then you are silly and it always 274 /// returns end(). If SkipDebug is true it skips uses marked Debug 275 /// when incrementing. 276 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 277 class defusechain_iterator 278 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 279 MachineOperand *Op; 280 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 281 // If the first node isn't one we're interested in, advance to one that 282 // we are interested in. 283 if (op) { 284 if ((!ReturnUses && op->isUse()) || 285 (!ReturnDefs && op->isDef()) || 286 (SkipDebug && op->isDebug())) 287 ++*this; 288 } 289 } 290 friend class MachineRegisterInfo; 291 public: 292 typedef std::iterator<std::forward_iterator_tag, 293 MachineInstr, ptrdiff_t>::reference reference; 294 typedef std::iterator<std::forward_iterator_tag, 295 MachineInstr, ptrdiff_t>::pointer pointer; 296 297 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 298 defusechain_iterator() : Op(0) {} 299 300 bool operator==(const defusechain_iterator &x) const { 301 return Op == x.Op; 302 } 303 bool operator!=(const defusechain_iterator &x) const { 304 return !operator==(x); 305 } 306 307 /// atEnd - return true if this iterator is equal to reg_end() on the value. 308 bool atEnd() const { return Op == 0; } 309 310 // Iterator traversal: forward iteration only 311 defusechain_iterator &operator++() { // Preincrement 312 assert(Op && "Cannot increment end iterator!"); 313 Op = Op->getNextOperandForReg(); 314 315 // If this is an operand we don't care about, skip it. 316 while (Op && ((!ReturnUses && Op->isUse()) || 317 (!ReturnDefs && Op->isDef()) || 318 (SkipDebug && Op->isDebug()))) 319 Op = Op->getNextOperandForReg(); 320 321 return *this; 322 } 323 defusechain_iterator operator++(int) { // Postincrement 324 defusechain_iterator tmp = *this; ++*this; return tmp; 325 } 326 327 MachineOperand &getOperand() const { 328 assert(Op && "Cannot dereference end iterator!"); 329 return *Op; 330 } 331 332 /// getOperandNo - Return the operand # of this MachineOperand in its 333 /// MachineInstr. 334 unsigned getOperandNo() const { 335 assert(Op && "Cannot dereference end iterator!"); 336 return Op - &Op->getParent()->getOperand(0); 337 } 338 339 // Retrieve a reference to the current operand. 340 MachineInstr &operator*() const { 341 assert(Op && "Cannot dereference end iterator!"); 342 return *Op->getParent(); 343 } 344 345 MachineInstr *operator->() const { 346 assert(Op && "Cannot dereference end iterator!"); 347 return Op->getParent(); 348 } 349 }; 350 351}; 352 353} // End llvm namespace 354 355#endif 356