1169689Skan;; Scheduling description for Niagara. 2169689Skan;; Copyright (C) 2006 Free Software Foundation, Inc. 3169689Skan;; 4169689Skan;; This file is part of GCC. 5169689Skan;; 6169689Skan;; GCC is free software; you can redistribute it and/or modify 7169689Skan;; it under the terms of the GNU General Public License as published by 8169689Skan;; the Free Software Foundation; either version 2, or (at your option) 9169689Skan;; any later version. 10169689Skan;; 11169689Skan;; GCC is distributed in the hope that it will be useful, 12169689Skan;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13169689Skan;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14169689Skan;; GNU General Public License for more details. 15169689Skan;; 16169689Skan;; You should have received a copy of the GNU General Public License 17169689Skan;; along with GCC; see the file COPYING. If not, write to 18169689Skan;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19169689Skan;; Boston, MA 02110-1301, USA. 20169689Skan 21169689Skan;; Niagara is a single-issue processor. 22169689Skan 23169689Skan(define_automaton "niagara_0") 24169689Skan 25169689Skan(define_cpu_unit "niag_pipe" "niagara_0") 26169689Skan 27169689Skan(define_insn_reservation "niag_5cycle" 5 28169689Skan (and (eq_attr "cpu" "niagara") 29169689Skan (eq_attr "type" "multi,flushw,iflush,trap")) 30169689Skan "niag_pipe*5") 31169689Skan 32169689Skan(define_insn_reservation "niag_4cycle" 4 33169689Skan (and (eq_attr "cpu" "niagara") 34169689Skan (eq_attr "type" "savew")) 35169689Skan "niag_pipe*4") 36169689Skan 37169689Skan/* Most basic operations are single-cycle. */ 38169689Skan(define_insn_reservation "niag_ialu" 1 39169689Skan (and (eq_attr "cpu" "niagara") 40169689Skan (eq_attr "type" "ialu,shift,compare,cmove")) 41169689Skan "niag_pipe") 42169689Skan 43169689Skan(define_insn_reservation "niag_imul" 11 44169689Skan (and (eq_attr "cpu" "niagara") 45169689Skan (eq_attr "type" "imul")) 46169689Skan "niag_pipe*11") 47169689Skan 48169689Skan(define_insn_reservation "niag_idiv" 72 49169689Skan (and (eq_attr "cpu" "niagara") 50169689Skan (eq_attr "type" "idiv")) 51169689Skan "niag_pipe*72") 52169689Skan 53169689Skan(define_insn_reservation "niag_branch" 3 54169689Skan (and (eq_attr "cpu" "niagara") 55169689Skan (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch")) 56169689Skan "niag_pipe*3") 57169689Skan 58169689Skan(define_insn_reservation "niag_3cycle_load" 3 59169689Skan (and (eq_attr "cpu" "niagara") 60169689Skan (eq_attr "type" "load")) 61169689Skan "niag_pipe*3") 62169689Skan 63169689Skan(define_insn_reservation "niag_9cycle_load" 9 64169689Skan (and (eq_attr "cpu" "niagara") 65169689Skan (eq_attr "type" "fpload")) 66169689Skan "niag_pipe*9") 67169689Skan 68169689Skan(define_insn_reservation "niag_1cycle_store" 1 69169689Skan (and (eq_attr "cpu" "niagara") 70169689Skan (eq_attr "type" "store")) 71169689Skan "niag_pipe") 72169689Skan 73169689Skan(define_insn_reservation "niag_8cycle_store" 8 74169689Skan (and (eq_attr "cpu" "niagara") 75169689Skan (eq_attr "type" "fpstore")) 76169689Skan "niag_pipe*8") 77169689Skan 78169689Skan/* Things incorrectly modelled here: 79169689Skan * FPADD{s,d}: 26 cycles 80169689Skan * FPSUB{s,d}: 26 cycles 81169689Skan * FABSD: 26 cycles 82169689Skan * F{s,d}TO{s,d}: 26 cycles 83169689Skan * F{s,d}TO{i,x}: 26 cycles 84169689Skan * FSMULD: 29 cycles 85169689Skan */ 86169689Skan(define_insn_reservation "niag_fmov" 8 87169689Skan (and (eq_attr "cpu" "niagara") 88169689Skan (eq_attr "type" "fpmove,fpcmove,fpcrmove")) 89169689Skan "niag_pipe*8") 90169689Skan 91169689Skan(define_insn_reservation "niag_fpcmp" 26 92169689Skan (and (eq_attr "cpu" "niagara") 93169689Skan (eq_attr "type" "fpcmp")) 94169689Skan "niag_pipe*26") 95169689Skan 96169689Skan(define_insn_reservation "niag_fmult" 29 97169689Skan (and (eq_attr "cpu" "niagara") 98169689Skan (eq_attr "type" "fpmul")) 99169689Skan "niag_pipe*29") 100169689Skan 101169689Skan(define_insn_reservation "niag_fdivs" 54 102169689Skan (and (eq_attr "cpu" "niagara") 103169689Skan (eq_attr "type" "fpdivs")) 104169689Skan "niag_pipe*54") 105169689Skan 106169689Skan(define_insn_reservation "niag_fdivd" 83 107169689Skan (and (eq_attr "cpu" "niagara") 108169689Skan (eq_attr "type" "fpdivd")) 109169689Skan "niag_pipe*83") 110169689Skan 111169689Skan/* Things incorrectly modelled here: 112169689Skan * FPADD{16,32}: 10 cycles 113169689Skan * FPSUB{16,32}: 10 cycles 114169689Skan * FALIGNDATA: 10 cycles 115169689Skan */ 116169689Skan(define_insn_reservation "niag_vis" 8 117169689Skan (and (eq_attr "cpu" "niagara") 118169689Skan (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist")) 119169689Skan "niag_pipe*8") 120