1132718Skan;; Scheduling description for z900 (cpu 2064). 2169689Skan;; Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc. 3132718Skan;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4132718Skan;; Ulrich Weigand (uweigand@de.ibm.com). 5132718Skan 6132718Skan;; This file is part of GCC. 7132718Skan 8132718Skan;; GCC is free software; you can redistribute it and/or modify it under 9132718Skan;; the terms of the GNU General Public License as published by the Free 10132718Skan;; Software Foundation; either version 2, or (at your option) any later 11132718Skan;; version. 12132718Skan 13132718Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14132718Skan;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 15132718Skan;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16132718Skan;; for more details. 17132718Skan 18132718Skan;; You should have received a copy of the GNU General Public License 19132718Skan;; along with GCC; see the file COPYING. If not, write to the Free 20169689Skan;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 21169689Skan;; 02110-1301, USA. 22132718Skan 23132718Skan;; 24132718Skan;; References: 25132718Skan;; The microarchitecture of the IBM eServer z900 processor. 26132718Skan;; E.M. Schwarz et al. 27132718Skan;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002. 28132718Skan;; 29132718Skan;; z900 (cpu 2064) pipeline 30132718Skan;; 31132718Skan;; dec 32132718Skan;; --> | <--- 33132718Skan;; LA bypass | agen | 34132718Skan;; | | | 35132718Skan;; --- c1 | Load bypass 36132718Skan;; | | 37132718Skan;; c2---- 38132718Skan;; | 39132718Skan;; e1 40132718Skan;; | 41132718Skan;; wr 42132718Skan 43169689Skan;; This scheduler description is also used for the g5 and g6. 44169689Skan 45132718Skan(define_automaton "z_ipu") 46132718Skan(define_cpu_unit "z_e1" "z_ipu") 47132718Skan(define_cpu_unit "z_wr" "z_ipu") 48132718Skan 49132718Skan 50132718Skan(define_insn_reservation "z_la" 1 51169689Skan (and (eq_attr "cpu" "z900,g5,g6") 52132718Skan (eq_attr "type" "la")) 53132718Skan "z_e1,z_wr") 54132718Skan 55132718Skan(define_insn_reservation "z_larl" 1 56169689Skan (and (eq_attr "cpu" "z900,g5,g6") 57132718Skan (eq_attr "type" "larl")) 58132718Skan "z_e1,z_wr") 59132718Skan 60132718Skan(define_insn_reservation "z_load" 1 61169689Skan (and (eq_attr "cpu" "z900,g5,g6") 62132718Skan (eq_attr "type" "load")) 63132718Skan "z_e1,z_wr") 64132718Skan 65132718Skan(define_insn_reservation "z_store" 1 66169689Skan (and (eq_attr "cpu" "z900,g5,g6") 67132718Skan (eq_attr "type" "store")) 68132718Skan "z_e1,z_wr") 69132718Skan 70169689Skan(define_insn_reservation "z_sem" 2 71169689Skan (and (eq_attr "cpu" "z900,g5,g6") 72169689Skan (eq_attr "type" "sem")) 73169689Skan "z_e1*2,z_wr") 74169689Skan 75132718Skan(define_insn_reservation "z_call" 5 76169689Skan (and (eq_attr "cpu" "z900,g5,g6") 77132718Skan (eq_attr "type" "jsr")) 78132718Skan "z_e1*5,z_wr") 79132718Skan 80169689Skan(define_insn_reservation "z_mul" 5 81169689Skan (and (eq_attr "cpu" "g5,g6,z900") 82169689Skan (eq_attr "type" "imulsi,imulhi")) 83169689Skan "z_e1*5,z_wr") 84132718Skan 85169689Skan(define_insn_reservation "z_inf" 10 86169689Skan (and (eq_attr "cpu" "g5,g6,z900") 87169689Skan (eq_attr "type" "idiv,imuldi")) 88169689Skan "z_e1*10,z_wr") 89132718Skan 90169689Skan;; For everything else we check the atype flag. 91132718Skan 92132718Skan(define_insn_reservation "z_int" 1 93169689Skan (and (eq_attr "cpu" "z900,g5,g6") 94169689Skan (and (not (eq_attr "type" "la,larl,load,store,jsr")) 95169689Skan (eq_attr "atype" "reg"))) 96132718Skan "z_e1,z_wr") 97132718Skan 98132718Skan(define_insn_reservation "z_agen" 1 99169689Skan (and (eq_attr "cpu" "z900,g5,g6") 100169689Skan (and (not (eq_attr "type" "la,larl,load,store,jsr")) 101169689Skan (eq_attr "atype" "agen"))) 102132718Skan "z_e1,z_wr") 103132718Skan 104132718Skan;; 105132718Skan;; s390_agen_dep_p returns 1, if a register is set in the 106132718Skan;; first insn and used in the dependent insn to form a address. 107132718Skan;; 108132718Skan 109132718Skan;; 110132718Skan;; If an instruction uses a register to address memory, it needs 111132718Skan;; to be set 5 cycles in advance. 112132718Skan;; 113132718Skan 114132718Skan(define_bypass 5 "z_int,z_agen" 115132718Skan "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 116132718Skan 117132718Skan;; 118132718Skan;; A load type instruction uses a bypass to feed the result back 119132718Skan;; to the address generation pipeline stage. 120132718Skan;; 121132718Skan 122132718Skan(define_bypass 3 "z_load" 123132718Skan "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 124132718Skan 125132718Skan;; 126132718Skan;; A load address type instruction uses a bypass to feed the 127132718Skan;; result back to the address generation pipeline stage. 128132718Skan;; 129132718Skan 130132718Skan(define_bypass 2 "z_larl,z_la" 131132718Skan "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") 132132718Skan 133132718Skan 134132718Skan 135132718Skan 136132718Skan 137