mpc.md revision 169689
1193323Sed;; Scheduling description for Motorola PowerPC processor cores. 2193323Sed;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 3193323Sed;; 4193323Sed;; This file is part of GCC. 5193323Sed;; 6193323Sed;; GCC is free software; you can redistribute it and/or modify it 7193323Sed;; under the terms of the GNU General Public License as published 8193323Sed;; by the Free Software Foundation; either version 2, or (at your 9193323Sed;; option) any later version. 10239462Sdim;; 11193323Sed;; GCC is distributed in the hope that it will be useful, but WITHOUT 12221345Sdim;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13193323Sed;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14193323Sed;; License for more details. 15193323Sed;; 16193323Sed;; You should have received a copy of the GNU General Public License 17193323Sed;; along with GCC; see the file COPYING. If not, write to the 18193323Sed;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19193323Sed;; MA 02110-1301, USA. 20193323Sed 21249423Sdim(define_automaton "mpc,mpcfp") 22249423Sdim(define_cpu_unit "iu_mpc,mciu_mpc" "mpc") 23249423Sdim(define_cpu_unit "fpu_mpc" "mpcfp") 24249423Sdim(define_cpu_unit "lsu_mpc,bpu_mpc" "mpc") 25249423Sdim 26249423Sdim;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU 27193323Sed;; 505/801/821/823 28193323Sed 29249423Sdim(define_insn_reservation "mpccore-load" 2 30193323Sed (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ 31193323Sed load_l,store_c,sync") 32193323Sed (eq_attr "cpu" "mpccore")) 33193323Sed "lsu_mpc") 34193323Sed 35193323Sed(define_insn_reservation "mpccore-store" 2 36193323Sed (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") 37198090Srdivacky (eq_attr "cpu" "mpccore")) 38193323Sed "lsu_mpc") 39218893Sdim 40218893Sdim(define_insn_reservation "mpccore-fpload" 2 41218893Sdim (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 42193323Sed (eq_attr "cpu" "mpccore")) 43193323Sed "lsu_mpc") 44193323Sed 45193323Sed(define_insn_reservation "mpccore-integer" 1 46193323Sed (and (eq_attr "type" "integer,insert_word") 47193323Sed (eq_attr "cpu" "mpccore")) 48198090Srdivacky "iu_mpc") 49198090Srdivacky 50206083Srdivacky(define_insn_reservation "mpccore-two" 1 51207618Srdivacky (and (eq_attr "type" "two") 52207618Srdivacky (eq_attr "cpu" "mpccore")) 53207618Srdivacky "iu_mpc,iu_mpc") 54193323Sed 55207618Srdivacky(define_insn_reservation "mpccore-three" 1 56193323Sed (and (eq_attr "type" "three") 57193323Sed (eq_attr "cpu" "mpccore")) 58193323Sed "iu_mpc,iu_mpc,iu_mpc") 59198090Srdivacky 60193323Sed(define_insn_reservation "mpccore-imul" 2 61193323Sed (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 62239462Sdim (eq_attr "cpu" "mpccore")) 63193323Sed "mciu_mpc") 64218893Sdim 65218893Sdim; Divide latency varies greatly from 2-11, use 6 as average 66218893Sdim(define_insn_reservation "mpccore-idiv" 6 67218893Sdim (and (eq_attr "type" "idiv") 68218893Sdim (eq_attr "cpu" "mpccore")) 69193323Sed "mciu_mpc*6") 70198090Srdivacky 71239462Sdim(define_insn_reservation "mpccore-compare" 3 72198090Srdivacky (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare") 73239462Sdim (eq_attr "cpu" "mpccore")) 74198090Srdivacky "iu_mpc,nothing,bpu_mpc") 75198090Srdivacky 76198090Srdivacky(define_insn_reservation "mpccore-fpcompare" 2 77198090Srdivacky (and (eq_attr "type" "fpcompare") 78239462Sdim (eq_attr "cpu" "mpccore")) 79198090Srdivacky "fpu_mpc,bpu_mpc") 80198090Srdivacky 81198090Srdivacky(define_insn_reservation "mpccore-fp" 4 82198090Srdivacky (and (eq_attr "type" "fp") 83198090Srdivacky (eq_attr "cpu" "mpccore")) 84239462Sdim "fpu_mpc*2") 85198090Srdivacky 86198090Srdivacky(define_insn_reservation "mpccore-dmul" 5 87198090Srdivacky (and (eq_attr "type" "dmul") 88198090Srdivacky (eq_attr "cpu" "mpccore")) 89239462Sdim "fpu_mpc*5") 90198090Srdivacky 91198090Srdivacky(define_insn_reservation "mpccore-sdiv" 10 92198090Srdivacky (and (eq_attr "type" "sdiv") 93198090Srdivacky (eq_attr "cpu" "mpccore")) 94198090Srdivacky "fpu_mpc*10") 95198090Srdivacky 96198090Srdivacky(define_insn_reservation "mpccore-ddiv" 17 97198090Srdivacky (and (eq_attr "type" "ddiv") 98198090Srdivacky (eq_attr "cpu" "mpccore")) 99198090Srdivacky "fpu_mpc*17") 100198090Srdivacky 101198090Srdivacky(define_insn_reservation "mpccore-mtjmpr" 4 102239462Sdim (and (eq_attr "type" "mtjmpr,mfjmpr") 103198090Srdivacky (eq_attr "cpu" "mpccore")) 104198090Srdivacky "bpu_mpc") 105239462Sdim 106198090Srdivacky(define_insn_reservation "mpccore-jmpreg" 1 107198090Srdivacky (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync") 108239462Sdim (eq_attr "cpu" "mpccore")) 109198090Srdivacky "bpu_mpc") 110239462Sdim 111198090Srdivacky