603.md revision 132718 
1;; Scheduling description for PowerPC 603 processor.
2;;   Copyright (C) 2003 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5
6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published
8;; by the Free Software Foundation; either version 2, or (at your
9;; option) any later version.
10
11;; GCC is distributed in the hope that it will be useful, but WITHOUT
12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14;; License for more details.
15
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING.  If not, write to the
18;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19;; MA 02111-1307, USA.
20
21(define_automaton "ppc603,ppc603fp")
22(define_cpu_unit "iu_603" "ppc603")
23(define_cpu_unit "fpu_603" "ppc603fp")
24(define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603")
25
26;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU
27;; Max issue 3 insns/clock cycle (includes 1 branch)
28
29;; Branches go straight to the BPU.  All other insns are handled
30;; by a dispatch unit which can issue a max of 2 insns per cycle.
31
32;; The PPC603e user's manual recommends that to reduce branch mispredictions,
33;; the insn that sets CR bits should be separated from the branch insn
34;; that evaluates them; separation by more than 9 insns ensures that the CR
35;; bits will be immediately available for execution.
36;; This could be artificially achieved by exaggerating the latency of
37;; compare insns but at the expense of a poorer schedule.
38
39;; CR insns get executed in the SRU.  Not modelled.
40
41(define_insn_reservation "ppc603-load" 2
42  (and (eq_attr "type" "load,load_ext,load_ux,load_u")
43       (eq_attr "cpu" "ppc603"))
44  "lsu_603")
45
46(define_insn_reservation "ppc603-store" 1
47  (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
48       (eq_attr "cpu" "ppc603"))
49  "lsu_603")
50
51(define_insn_reservation "ppc603-fpload" 2
52  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
53       (eq_attr "cpu" "ppc603"))
54  "lsu_603")
55
56(define_insn_reservation "ppc603-integer" 1
57  (and (eq_attr "type" "integer,insert_word")
58       (eq_attr "cpu" "ppc603"))
59  "iu_603")
60
61; This takes 2 or 3 cycles
62(define_insn_reservation "ppc603-imul" 3
63  (and (eq_attr "type" "imul,imul_compare")
64       (eq_attr "cpu" "ppc603"))
65  "iu_603*2")
66
67(define_insn_reservation "ppc603-imul2" 2
68  (and (eq_attr "type" "imul2,imul3")
69       (eq_attr "cpu" "ppc603"))
70  "iu_603*2")
71
72(define_insn_reservation "ppc603-idiv" 37
73  (and (eq_attr "type" "idiv")
74       (eq_attr "cpu" "ppc603"))
75  "iu_603*37")
76
77(define_insn_reservation "ppc603-compare" 3
78  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
79       (eq_attr "cpu" "ppc603"))
80  "iu_603,nothing,bpu_603")
81
82(define_insn_reservation "ppc603-fpcompare" 3
83  (and (eq_attr "type" "fpcompare")
84       (eq_attr "cpu" "ppc603"))
85  "(fpu_603+iu_603*2),bpu_603")
86
87(define_insn_reservation "ppc603-fp" 3
88  (and (eq_attr "type" "fp")
89       (eq_attr "cpu" "ppc603"))
90  "fpu_603")
91
92(define_insn_reservation "ppc603-dmul" 4
93  (and (eq_attr "type" "dmul")
94       (eq_attr "cpu" "ppc603"))
95  "fpu_603*2")
96
97; Divides are not pipelined
98(define_insn_reservation "ppc603-sdiv" 18
99  (and (eq_attr "type" "sdiv")
100       (eq_attr "cpu" "ppc603"))
101  "fpu_603*18")
102
103(define_insn_reservation "ppc603-ddiv" 33
104  (and (eq_attr "type" "ddiv")
105       (eq_attr "cpu" "ppc603"))
106  "fpu_603*33")
107
108(define_insn_reservation "ppc603-crlogical" 2
109  (and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr")
110       (eq_attr "cpu" "ppc603"))
111  "sru_603")
112
113(define_insn_reservation "ppc603-mtjmpr" 4
114  (and (eq_attr "type" "mtjmpr")
115       (eq_attr "cpu" "ppc603"))
116  "sru_603")
117
118(define_insn_reservation "ppc603-mfjmpr" 2
119  (and (eq_attr "type" "mfjmpr")
120       (eq_attr "cpu" "ppc603"))
121  "sru_603")
122
123(define_insn_reservation "ppc603-jmpreg" 1
124  (and (eq_attr "type" "jmpreg,branch")
125       (eq_attr "cpu" "ppc603"))
126  "bpu_603")
127
128