mips-ps-3d.md revision 169690
16548Ssherman;; MIPS Paired-Single Floating and MIPS-3D Instructions. 26548Ssherman;; Copyright (C) 2004 Free Software Foundation, Inc. 36548Ssherman;; 46548Ssherman;; This file is part of GCC. 56548Ssherman;; 66548Ssherman;; GCC is free software; you can redistribute it and/or modify 76548Ssherman;; it under the terms of the GNU General Public License as published by 86548Ssherman;; the Free Software Foundation; either version 2, or (at your option) 96548Ssherman;; any later version. 106548Ssherman;; 116548Ssherman;; GCC is distributed in the hope that it will be useful, 126548Ssherman;; but WITHOUT ANY WARRANTY; without even the implied warranty of 136548Ssherman;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 146548Ssherman;; GNU General Public License for more details. 156548Ssherman;; 166548Ssherman;; You should have received a copy of the GNU General Public License 176548Ssherman;; along with GCC; see the file COPYING. If not, write to 186548Ssherman;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 196548Ssherman;; Boston, MA 02110-1301, USA. 206548Ssherman 216548Ssherman(define_insn "*movcc_v2sf_<mode>" 226548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f,f") 236548Ssherman (if_then_else:V2SF 246548Ssherman (match_operator:GPR 4 "equality_operator" 256548Ssherman [(match_operand:GPR 1 "register_operand" "d,d") 266548Ssherman (const_int 0)]) 276548Ssherman (match_operand:V2SF 2 "register_operand" "f,0") 286548Ssherman (match_operand:V2SF 3 "register_operand" "0,f")))] 296548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 306548Ssherman "@ 316548Ssherman mov%T4.ps\t%0,%2,%1 326548Ssherman mov%t4.ps\t%0,%3,%1" 336548Ssherman [(set_attr "type" "condmove") 346548Ssherman (set_attr "mode" "SF")]) 356548Ssherman 366548Ssherman(define_insn "mips_cond_move_tf_ps" 376548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f,f") 386548Ssherman (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f,0") 396548Ssherman (match_operand:V2SF 2 "register_operand" "0,f") 406548Ssherman (match_operand:CCV2 3 "register_operand" "z,z")] 416548Ssherman UNSPEC_MOVE_TF_PS))] 426548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 436548Ssherman "@ 446548Ssherman movt.ps\t%0,%1,%3 456548Ssherman movf.ps\t%0,%2,%3" 466548Ssherman [(set_attr "type" "condmove") 476548Ssherman (set_attr "mode" "SF")]) 486548Ssherman 496548Ssherman(define_expand "movv2sfcc" 506548Ssherman [(set (match_dup 4) (match_operand 1 "comparison_operator")) 516548Ssherman (set (match_operand:V2SF 0 "register_operand") 526548Ssherman (if_then_else:V2SF (match_dup 5) 536548Ssherman (match_operand:V2SF 2 "register_operand") 546548Ssherman (match_operand:V2SF 3 "register_operand")))] 556548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 566548Ssherman{ 576548Ssherman /* We can only support MOVN.PS and MOVZ.PS. 586548Ssherman NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and 596548Ssherman MOVZ.PS. MOVT.PS and MOVF.PS depend on two CC values and move 606548Ssherman each item independently. */ 616548Ssherman 626897Ssherman if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT) 636897Ssherman FAIL; 646548Ssherman 656548Ssherman gen_conditional_move (operands); 666548Ssherman DONE; 676548Ssherman}) 686548Ssherman 696548Ssherman; pul.ps - Pair Upper Lower 706548Ssherman(define_insn "mips_pul_ps" 716548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 726548Ssherman (vec_merge:V2SF 736548Ssherman (match_operand:V2SF 1 "register_operand" "f") 746548Ssherman (match_operand:V2SF 2 "register_operand" "f") 756548Ssherman (const_int 2)))] 766897Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 776897Ssherman "pul.ps\t%0,%1,%2" 786548Ssherman [(set_attr "type" "fmove") 796897Ssherman (set_attr "mode" "SF")]) 806548Ssherman 816897Ssherman; puu.ps - Pair upper upper 826897Ssherman(define_insn "mips_puu_ps" 838390Srriggs [(set (match_operand:V2SF 0 "register_operand" "=f") 846548Ssherman (vec_merge:V2SF 856548Ssherman (match_operand:V2SF 1 "register_operand" "f") 866548Ssherman (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f") 876548Ssherman (parallel [(const_int 1) 886548Ssherman (const_int 0)])) 896548Ssherman (const_int 2)))] 906548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 916548Ssherman "puu.ps\t%0,%1,%2" 926548Ssherman [(set_attr "type" "fmove") 936548Ssherman (set_attr "mode" "SF")]) 946548Ssherman 956548Ssherman; pll.ps - Pair Lower Lower 966548Ssherman(define_insn "mips_pll_ps" 976548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 986897Ssherman (vec_merge:V2SF 996548Ssherman (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f") 1006548Ssherman (parallel [(const_int 1) 1016548Ssherman (const_int 0)])) 1026548Ssherman (match_operand:V2SF 2 "register_operand" "f") 1036548Ssherman (const_int 2)))] 1046548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 1056548Ssherman "pll.ps\t%0,%1,%2" 1066548Ssherman [(set_attr "type" "fmove") 1076548Ssherman (set_attr "mode" "SF")]) 1086548Ssherman 1096548Ssherman; plu.ps - Pair Lower Upper 1106548Ssherman(define_insn "mips_plu_ps" 1116897Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 1126548Ssherman (vec_merge:V2SF 1136548Ssherman (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f") 1146548Ssherman (parallel [(const_int 1) 1156548Ssherman (const_int 0)])) 1166548Ssherman (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f") 1176548Ssherman (parallel [(const_int 1) 1186548Ssherman (const_int 0)])) 1196897Ssherman (const_int 2)))] 1206548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 1216897Ssherman "plu.ps\t%0,%1,%2" 1226897Ssherman [(set_attr "type" "fmove") 1236548Ssherman (set_attr "mode" "SF")]) 1246548Ssherman 1256548Ssherman; vec_init 1266548Ssherman(define_expand "vec_initv2sf" 1276548Ssherman [(match_operand:V2SF 0 "register_operand") 1286548Ssherman (match_operand:V2SF 1 "")] 1296548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 1306548Ssherman{ 1316548Ssherman rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0)); 1326548Ssherman rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1)); 1336548Ssherman emit_insn (gen_vec_initv2sf_internal (operands[0], op0, op1)); 1346548Ssherman DONE; 1356548Ssherman}) 1366548Ssherman 1376548Ssherman(define_insn "vec_initv2sf_internal" 1386548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 1396548Ssherman (vec_concat:V2SF 1406548Ssherman (match_operand:SF 1 "register_operand" "f") 1416548Ssherman (match_operand:SF 2 "register_operand" "f")))] 1426548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 1436548Ssherman{ 1446548Ssherman if (BYTES_BIG_ENDIAN) 1456548Ssherman return "cvt.ps.s\t%0,%1,%2"; 1466548Ssherman else 1476548Ssherman return "cvt.ps.s\t%0,%2,%1"; 1486897Ssherman} 1496548Ssherman [(set_attr "type" "fcvt") 1506548Ssherman (set_attr "mode" "SF")]) 1516548Ssherman 1526548Ssherman;; ??? This is only generated if we perform a vector operation that has to be 1536897Ssherman;; emulated. There is no other way to get a vector mode bitfield extract 1546548Ssherman;; currently. 1556548Ssherman 1566548Ssherman(define_insn "vec_extractv2sf" 1576548Ssherman [(set (match_operand:SF 0 "register_operand" "=f") 1586548Ssherman (vec_select:SF (match_operand:V2SF 1 "register_operand" "f") 1596548Ssherman (parallel 1606548Ssherman [(match_operand 2 "const_0_or_1_operand" "")])))] 1616548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 1626548Ssherman{ 1636548Ssherman if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN) 1646548Ssherman return "cvt.s.pu\t%0,%1"; 1656548Ssherman else 1666548Ssherman return "cvt.s.pl\t%0,%1"; 1676548Ssherman} 1686548Ssherman [(set_attr "type" "fcvt") 1696548Ssherman (set_attr "mode" "SF")]) 1706548Ssherman 1716548Ssherman;; ??? This is only generated if we disable the vec_init pattern. There is 1726548Ssherman;; no other way to get a vector mode bitfield store currently. 1736548Ssherman 1746548Ssherman(define_expand "vec_setv2sf" 1756548Ssherman [(match_operand:V2SF 0 "register_operand") 1766548Ssherman (match_operand:SF 1 "register_operand") 1776548Ssherman (match_operand 2 "const_0_or_1_operand")] 1786897Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 1796548Ssherman{ 1806548Ssherman rtx temp; 1816548Ssherman 1826548Ssherman /* We don't have an insert instruction, so we duplicate the float, and 1836897Ssherman then use a PUL instruction. */ 1846548Ssherman temp = gen_reg_rtx (V2SFmode); 1856548Ssherman emit_insn (gen_mips_cvt_ps_s (temp, operands[1], operands[1])); 1866548Ssherman if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN) 1876548Ssherman emit_insn (gen_mips_pul_ps (operands[0], temp, operands[0])); 1886897Ssherman else 1896897Ssherman emit_insn (gen_mips_pul_ps (operands[0], operands[0], temp)); 1906548Ssherman DONE; 1916548Ssherman}) 1926548Ssherman 1936548Ssherman; cvt.ps.s - Floating Point Convert Pair to Paired Single 1946548Ssherman(define_expand "mips_cvt_ps_s" 1956548Ssherman [(match_operand:V2SF 0 "register_operand") 1966548Ssherman (match_operand:SF 1 "register_operand") 1976548Ssherman (match_operand:SF 2 "register_operand")] 1986548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 1996548Ssherman{ 2006897Ssherman if (BYTES_BIG_ENDIAN) 2016548Ssherman emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1], 2026897Ssherman operands[2])); 2036548Ssherman else 2046548Ssherman emit_insn (gen_vec_initv2sf_internal (operands[0], operands[2], 2056548Ssherman operands[1])); 2066548Ssherman DONE; 2076548Ssherman}) 2086897Ssherman 2096548Ssherman; cvt.s.pl - Floating Point Convert Pair Lower to Single Floating Point 2106548Ssherman(define_expand "mips_cvt_s_pl" 2118390Srriggs [(set (match_operand:SF 0 "register_operand") 2126548Ssherman (vec_select:SF (match_operand:V2SF 1 "register_operand") 2136548Ssherman (parallel [(match_dup 2)])))] 2146548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 2156897Ssherman { operands[2] = GEN_INT (BYTES_BIG_ENDIAN); }) 2166548Ssherman 2176548Ssherman; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point 2188390Srriggs(define_expand "mips_cvt_s_pu" 2196548Ssherman [(set (match_operand:SF 0 "register_operand") 2206548Ssherman (vec_select:SF (match_operand:V2SF 1 "register_operand") 2216548Ssherman (parallel [(match_dup 2)])))] 2226548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 2236548Ssherman { operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); }) 2246548Ssherman 2256897Ssherman; alnv.ps - Floating Point Align Variable 2266548Ssherman(define_insn "mips_alnv_ps" 2276548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 2286548Ssherman (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") 2296548Ssherman (match_operand:V2SF 2 "register_operand" "f") 2306548Ssherman (match_operand:SI 3 "register_operand" "d")] 2316548Ssherman UNSPEC_ALNV_PS))] 2326897Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 2336548Ssherman "alnv.ps\t%0,%1,%2,%3" 2346548Ssherman [(set_attr "type" "fmove") 2356548Ssherman (set_attr "mode" "SF")]) 2366548Ssherman 2376548Ssherman; addr.ps - Floating Point Reduction Add 2386548Ssherman(define_insn "mips_addr_ps" 2396548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 2406548Ssherman (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") 2416897Ssherman (match_operand:V2SF 2 "register_operand" "f")] 2426548Ssherman UNSPEC_ADDR_PS))] 2436548Ssherman "TARGET_MIPS3D" 2446548Ssherman "addr.ps\t%0,%1,%2" 2456548Ssherman [(set_attr "type" "fadd") 2466548Ssherman (set_attr "mode" "SF")]) 2476548Ssherman 2486897Ssherman; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word 2496548Ssherman(define_insn "mips_cvt_pw_ps" 2506548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 2516548Ssherman (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] 2526548Ssherman UNSPEC_CVT_PW_PS))] 2536548Ssherman "TARGET_MIPS3D" 2546548Ssherman "cvt.pw.ps\t%0,%1" 2556548Ssherman [(set_attr "type" "fcvt") 2566548Ssherman (set_attr "mode" "SF")]) 2576548Ssherman 2586548Ssherman; cvt.ps.pw - Floating Point Convert Paired Word to Paired Single 2596548Ssherman(define_insn "mips_cvt_ps_pw" 2606548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 2616548Ssherman (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] 2626548Ssherman UNSPEC_CVT_PS_PW))] 2636548Ssherman "TARGET_MIPS3D" 2646548Ssherman "cvt.ps.pw\t%0,%1" 2656548Ssherman [(set_attr "type" "fcvt") 2666548Ssherman (set_attr "mode" "SF")]) 2676548Ssherman 2686548Ssherman; mulr.ps - Floating Point Reduction Multiply 2696548Ssherman(define_insn "mips_mulr_ps" 2706897Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 2716548Ssherman (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") 2726548Ssherman (match_operand:V2SF 2 "register_operand" "f")] 2736548Ssherman UNSPEC_MULR_PS))] 2746548Ssherman "TARGET_MIPS3D" 2756548Ssherman "mulr.ps\t%0,%1,%2" 2766548Ssherman [(set_attr "type" "fmul") 2776548Ssherman (set_attr "mode" "SF")]) 2786897Ssherman 2796548Ssherman; abs.ps 2806548Ssherman(define_expand "mips_abs_ps" 2816548Ssherman [(set (match_operand:V2SF 0 "register_operand") 2826548Ssherman (unspec:V2SF [(match_operand:V2SF 1 "register_operand")] 2836548Ssherman UNSPEC_ABS_PS))] 2846548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 2856548Ssherman{ 2866548Ssherman /* If we can ignore NaNs, this operation is equivalent to the 2876548Ssherman rtl ABS code. */ 2886548Ssherman if (!HONOR_NANS (V2SFmode)) 2896548Ssherman { 2906548Ssherman emit_insn (gen_absv2sf2 (operands[0], operands[1])); 2916548Ssherman DONE; 2926548Ssherman } 2936548Ssherman}) 2946548Ssherman 2956548Ssherman(define_insn "*mips_abs_ps" 2966548Ssherman [(set (match_operand:V2SF 0 "register_operand" "=f") 2976897Ssherman (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] 2986548Ssherman UNSPEC_ABS_PS))] 2996548Ssherman "TARGET_PAIRED_SINGLE_FLOAT" 3006548Ssherman "abs.ps\t%0,%1" 3016548Ssherman [(set_attr "type" "fabs") 3026548Ssherman (set_attr "mode" "SF")]) 3036548Ssherman 3046548Ssherman;---------------------------------------------------------------------------- 3056897Ssherman; Floating Point Comparisons for Scalars 3066548Ssherman;---------------------------------------------------------------------------- 3076548Ssherman 3086548Ssherman(define_insn "mips_cabs_cond_<fmt>" 3096548Ssherman [(set (match_operand:CC 0 "register_operand" "=z") 3106897Ssherman (unspec:CC [(match_operand:SCALARF 1 "register_operand" "f") 3116548Ssherman (match_operand:SCALARF 2 "register_operand" "f") 3126548Ssherman (match_operand 3 "const_int_operand" "")] 3136548Ssherman UNSPEC_CABS))] 3146548Ssherman "TARGET_MIPS3D" 3156548Ssherman "cabs.%Y3.<fmt>\t%0,%1,%2" 316 [(set_attr "type" "fcmp") 317 (set_attr "mode" "FPSW")]) 318 319 320;---------------------------------------------------------------------------- 321; Floating Point Comparisons for Four Singles 322;---------------------------------------------------------------------------- 323 324(define_insn_and_split "mips_c_cond_4s" 325 [(set (match_operand:CCV4 0 "register_operand" "=z") 326 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f") 327 (match_operand:V2SF 2 "register_operand" "f") 328 (match_operand:V2SF 3 "register_operand" "f") 329 (match_operand:V2SF 4 "register_operand" "f") 330 (match_operand 5 "const_int_operand" "")] 331 UNSPEC_C))] 332 "TARGET_PAIRED_SINGLE_FLOAT" 333 "#" 334 "&& reload_completed" 335 [(set (match_dup 6) 336 (unspec:CCV2 [(match_dup 1) 337 (match_dup 2) 338 (match_dup 5)] 339 UNSPEC_C)) 340 (set (match_dup 7) 341 (unspec:CCV2 [(match_dup 3) 342 (match_dup 4) 343 (match_dup 5)] 344 UNSPEC_C))] 345{ 346 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0); 347 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8); 348} 349 [(set_attr "type" "fcmp") 350 (set_attr "length" "8") 351 (set_attr "mode" "FPSW")]) 352 353(define_insn_and_split "mips_cabs_cond_4s" 354 [(set (match_operand:CCV4 0 "register_operand" "=z") 355 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f") 356 (match_operand:V2SF 2 "register_operand" "f") 357 (match_operand:V2SF 3 "register_operand" "f") 358 (match_operand:V2SF 4 "register_operand" "f") 359 (match_operand 5 "const_int_operand" "")] 360 UNSPEC_CABS))] 361 "TARGET_MIPS3D" 362 "#" 363 "&& reload_completed" 364 [(set (match_dup 6) 365 (unspec:CCV2 [(match_dup 1) 366 (match_dup 2) 367 (match_dup 5)] 368 UNSPEC_CABS)) 369 (set (match_dup 7) 370 (unspec:CCV2 [(match_dup 3) 371 (match_dup 4) 372 (match_dup 5)] 373 UNSPEC_CABS))] 374{ 375 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0); 376 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8); 377} 378 [(set_attr "type" "fcmp") 379 (set_attr "length" "8") 380 (set_attr "mode" "FPSW")]) 381 382 383;---------------------------------------------------------------------------- 384; Floating Point Comparisons for Paired Singles 385;---------------------------------------------------------------------------- 386 387(define_insn "mips_c_cond_ps" 388 [(set (match_operand:CCV2 0 "register_operand" "=z") 389 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f") 390 (match_operand:V2SF 2 "register_operand" "f") 391 (match_operand 3 "const_int_operand" "")] 392 UNSPEC_C))] 393 "TARGET_PAIRED_SINGLE_FLOAT" 394 "c.%Y3.ps\t%0,%1,%2" 395 [(set_attr "type" "fcmp") 396 (set_attr "mode" "FPSW")]) 397 398(define_insn "mips_cabs_cond_ps" 399 [(set (match_operand:CCV2 0 "register_operand" "=z") 400 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f") 401 (match_operand:V2SF 2 "register_operand" "f") 402 (match_operand 3 "const_int_operand" "")] 403 UNSPEC_CABS))] 404 "TARGET_MIPS3D" 405 "cabs.%Y3.ps\t%0,%1,%2" 406 [(set_attr "type" "fcmp") 407 (set_attr "mode" "FPSW")]) 408 409;; An expander for generating an scc operation. 410(define_expand "scc_ps" 411 [(set (match_operand:CCV2 0) 412 (unspec:CCV2 [(match_operand 1)] UNSPEC_SCC))]) 413 414(define_insn "s<code>_ps" 415 [(set (match_operand:CCV2 0 "register_operand" "=z") 416 (unspec:CCV2 417 [(fcond (match_operand:V2SF 1 "register_operand" "f") 418 (match_operand:V2SF 2 "register_operand" "f"))] 419 UNSPEC_SCC))] 420 "TARGET_PAIRED_SINGLE_FLOAT" 421 "c.<fcond>.ps\t%0,%1,%2" 422 [(set_attr "type" "fcmp") 423 (set_attr "mode" "FPSW")]) 424 425(define_insn "s<code>_ps" 426 [(set (match_operand:CCV2 0 "register_operand" "=z") 427 (unspec:CCV2 428 [(swapped_fcond (match_operand:V2SF 1 "register_operand" "f") 429 (match_operand:V2SF 2 "register_operand" "f"))] 430 UNSPEC_SCC))] 431 "TARGET_PAIRED_SINGLE_FLOAT" 432 "c.<swapped_fcond>.ps\t%0,%2,%1" 433 [(set_attr "type" "fcmp") 434 (set_attr "mode" "FPSW")]) 435 436;---------------------------------------------------------------------------- 437; Floating Point Branch Instructions. 438;---------------------------------------------------------------------------- 439 440; Branch on Any of Four Floating Point Condition Codes True 441(define_insn "bc1any4t" 442 [(set (pc) 443 (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z") 444 (const_int 0)) 445 (label_ref (match_operand 1 "" "")) 446 (pc)))] 447 "TARGET_MIPS3D" 448 "%*bc1any4t\t%0,%1%/" 449 [(set_attr "type" "branch") 450 (set_attr "mode" "none")]) 451 452; Branch on Any of Four Floating Point Condition Codes False 453(define_insn "bc1any4f" 454 [(set (pc) 455 (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z") 456 (const_int -1)) 457 (label_ref (match_operand 1 "" "")) 458 (pc)))] 459 "TARGET_MIPS3D" 460 "%*bc1any4f\t%0,%1%/" 461 [(set_attr "type" "branch") 462 (set_attr "mode" "none")]) 463 464; Branch on Any of Two Floating Point Condition Codes True 465(define_insn "bc1any2t" 466 [(set (pc) 467 (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z") 468 (const_int 0)) 469 (label_ref (match_operand 1 "" "")) 470 (pc)))] 471 "TARGET_MIPS3D" 472 "%*bc1any2t\t%0,%1%/" 473 [(set_attr "type" "branch") 474 (set_attr "mode" "none")]) 475 476; Branch on Any of Two Floating Point Condition Codes False 477(define_insn "bc1any2f" 478 [(set (pc) 479 (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z") 480 (const_int -1)) 481 (label_ref (match_operand 1 "" "")) 482 (pc)))] 483 "TARGET_MIPS3D" 484 "%*bc1any2f\t%0,%1%/" 485 [(set_attr "type" "branch") 486 (set_attr "mode" "none")]) 487 488; Used to access one register in a CCV2 pair. Operand 0 is the register 489; pair and operand 1 is the index of the register we want (a CONST_INT). 490(define_expand "single_cc" 491 [(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC) 492 (const_int 0))]) 493 494; This is a normal floating-point branch pattern, but rather than check 495; a single CCmode register, it checks one register in a CCV2 pair. 496; Operand 2 is the register pair and operand 3 is the index of the 497; register we want. 498(define_insn "*branch_upper_lower" 499 [(set (pc) 500 (if_then_else 501 (match_operator 0 "equality_operator" 502 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z") 503 (match_operand 3 "const_int_operand")] 504 UNSPEC_SINGLE_CC) 505 (const_int 0)]) 506 (label_ref (match_operand 1 "" "")) 507 (pc)))] 508 "TARGET_HARD_FLOAT" 509{ 510 operands[2] 511 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3])); 512 return mips_output_conditional_branch (insn, operands, 513 MIPS_BRANCH ("b%F0", "%2,%1"), 514 MIPS_BRANCH ("b%W0", "%2,%1")); 515} 516 [(set_attr "type" "branch") 517 (set_attr "mode" "none")]) 518 519; As above, but with the sense of the condition reversed. 520(define_insn "*branch_upper_lower_inverted" 521 [(set (pc) 522 (if_then_else 523 (match_operator 0 "equality_operator" 524 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z") 525 (match_operand 3 "const_int_operand")] 526 UNSPEC_SINGLE_CC) 527 (const_int 0)]) 528 (pc) 529 (label_ref (match_operand 1 "" ""))))] 530 "TARGET_HARD_FLOAT" 531{ 532 operands[2] 533 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3])); 534 return mips_output_conditional_branch (insn, operands, 535 MIPS_BRANCH ("b%W0", "%2,%1"), 536 MIPS_BRANCH ("b%F0", "%2,%1")); 537} 538 [(set_attr "type" "branch") 539 (set_attr "mode" "none")]) 540 541;---------------------------------------------------------------------------- 542; Floating Point Reduced Precision Reciprocal Square Root Instructions. 543;---------------------------------------------------------------------------- 544 545(define_insn "mips_rsqrt1_<fmt>" 546 [(set (match_operand:ANYF 0 "register_operand" "=f") 547 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] 548 UNSPEC_RSQRT1))] 549 "TARGET_MIPS3D" 550 "rsqrt1.<fmt>\t%0,%1" 551 [(set_attr "type" "frsqrt1") 552 (set_attr "mode" "<UNITMODE>")]) 553 554(define_insn "mips_rsqrt2_<fmt>" 555 [(set (match_operand:ANYF 0 "register_operand" "=f") 556 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") 557 (match_operand:ANYF 2 "register_operand" "f")] 558 UNSPEC_RSQRT2))] 559 "TARGET_MIPS3D" 560 "rsqrt2.<fmt>\t%0,%1,%2" 561 [(set_attr "type" "frsqrt2") 562 (set_attr "mode" "<UNITMODE>")]) 563 564(define_insn "mips_recip1_<fmt>" 565 [(set (match_operand:ANYF 0 "register_operand" "=f") 566 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] 567 UNSPEC_RECIP1))] 568 "TARGET_MIPS3D" 569 "recip1.<fmt>\t%0,%1" 570 [(set_attr "type" "frdiv1") 571 (set_attr "mode" "<UNITMODE>")]) 572 573(define_insn "mips_recip2_<fmt>" 574 [(set (match_operand:ANYF 0 "register_operand" "=f") 575 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") 576 (match_operand:ANYF 2 "register_operand" "f")] 577 UNSPEC_RECIP2))] 578 "TARGET_MIPS3D" 579 "recip2.<fmt>\t%0,%1,%2" 580 [(set_attr "type" "frdiv2") 581 (set_attr "mode" "<UNITMODE>")]) 582 583(define_expand "vcondv2sf" 584 [(set (match_operand:V2SF 0 "register_operand") 585 (if_then_else:V2SF 586 (match_operator 3 "" 587 [(match_operand:V2SF 4 "register_operand") 588 (match_operand:V2SF 5 "register_operand")]) 589 (match_operand:V2SF 1 "register_operand") 590 (match_operand:V2SF 2 "register_operand")))] 591 "TARGET_PAIRED_SINGLE_FLOAT" 592{ 593 mips_expand_vcondv2sf (operands[0], operands[1], operands[2], 594 GET_CODE (operands[3]), operands[4], operands[5]); 595 DONE; 596}) 597 598(define_expand "sminv2sf3" 599 [(set (match_operand:V2SF 0 "register_operand") 600 (smin:V2SF (match_operand:V2SF 1 "register_operand") 601 (match_operand:V2SF 2 "register_operand")))] 602 "TARGET_PAIRED_SINGLE_FLOAT" 603{ 604 mips_expand_vcondv2sf (operands[0], operands[1], operands[2], 605 LE, operands[1], operands[2]); 606 DONE; 607}) 608 609(define_expand "smaxv2sf3" 610 [(set (match_operand:V2SF 0 "register_operand") 611 (smax:V2SF (match_operand:V2SF 1 "register_operand") 612 (match_operand:V2SF 2 "register_operand")))] 613 "TARGET_PAIRED_SINGLE_FLOAT" 614{ 615 mips_expand_vcondv2sf (operands[0], operands[1], operands[2], 616 LE, operands[2], operands[1]); 617 DONE; 618}) 619