1169689Skan;; GCC machine description for IA-64 synchronization instructions. 2169689Skan;; Copyright (C) 2005 3169689Skan;; Free Software Foundation, Inc. 4169689Skan;; 5169689Skan;; This file is part of GCC. 6169689Skan;; 7169689Skan;; GCC is free software; you can redistribute it and/or modify 8169689Skan;; it under the terms of the GNU General Public License as published by 9169689Skan;; the Free Software Foundation; either version 2, or (at your option) 10169689Skan;; any later version. 11169689Skan;; 12169689Skan;; GCC is distributed in the hope that it will be useful, 13169689Skan;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14169689Skan;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15169689Skan;; GNU General Public License for more details. 16169689Skan;; 17169689Skan;; You should have received a copy of the GNU General Public License 18169689Skan;; along with GCC; see the file COPYING. If not, write to 19169689Skan;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20169689Skan;; Boston, MA 02110-1301, USA. 21169689Skan 22169689Skan(define_mode_macro IMODE [QI HI SI DI]) 23169689Skan(define_mode_macro I124MODE [QI HI SI]) 24169689Skan(define_mode_macro I48MODE [SI DI]) 25169689Skan(define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")]) 26169689Skan 27169689Skan(define_code_macro FETCHOP [plus minus ior xor and]) 28169689Skan(define_code_attr fetchop_name 29169689Skan [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")]) 30169689Skan 31169689Skan(define_insn "memory_barrier" 32169689Skan [(set (mem:BLK (match_scratch:DI 0 "X")) 33169689Skan (unspec:BLK [(mem:BLK (match_scratch:DI 1 "X"))] UNSPEC_MF))] 34169689Skan "" 35169689Skan "mf" 36169689Skan [(set_attr "itanium_class" "syst_m")]) 37169689Skan 38169689Skan(define_insn "fetchadd_acq_<mode>" 39169689Skan [(set (match_operand:I48MODE 0 "gr_register_operand" "=r") 40169689Skan (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S")) 41169689Skan (set (match_dup 1) 42169689Skan (unspec:I48MODE [(match_dup 1) 43169689Skan (match_operand:I48MODE 2 "fetchadd_operand" "n")] 44169689Skan UNSPEC_FETCHADD_ACQ))] 45169689Skan "" 46169689Skan "fetchadd<modesuffix>.acq %0 = %1, %2" 47169689Skan [(set_attr "itanium_class" "sem")]) 48169689Skan 49169689Skan(define_expand "sync_<fetchop_name><mode>" 50169689Skan [(set (match_operand:IMODE 0 "memory_operand" "") 51169689Skan (FETCHOP:IMODE (match_dup 0) 52169689Skan (match_operand:IMODE 1 "general_operand" "")))] 53169689Skan "" 54169689Skan{ 55169689Skan ia64_expand_atomic_op (<CODE>, operands[0], operands[1], NULL, NULL); 56169689Skan DONE; 57169689Skan}) 58169689Skan 59169689Skan(define_expand "sync_nand<mode>" 60169689Skan [(set (match_operand:IMODE 0 "memory_operand" "") 61169689Skan (and:IMODE (not:IMODE (match_dup 0)) 62169689Skan (match_operand:IMODE 1 "general_operand" "")))] 63169689Skan "" 64169689Skan{ 65169689Skan ia64_expand_atomic_op (NOT, operands[0], operands[1], NULL, NULL); 66169689Skan DONE; 67169689Skan}) 68169689Skan 69169689Skan(define_expand "sync_old_<fetchop_name><mode>" 70169689Skan [(set (match_operand:IMODE 0 "gr_register_operand" "") 71169689Skan (FETCHOP:IMODE 72169689Skan (match_operand:IMODE 1 "memory_operand" "") 73169689Skan (match_operand:IMODE 2 "general_operand" "")))] 74169689Skan "" 75169689Skan{ 76169689Skan ia64_expand_atomic_op (<CODE>, operands[1], operands[2], operands[0], NULL); 77169689Skan DONE; 78169689Skan}) 79169689Skan 80169689Skan(define_expand "sync_old_nand<mode>" 81169689Skan [(set (match_operand:IMODE 0 "gr_register_operand" "") 82169689Skan (and:IMODE 83169689Skan (not:IMODE (match_operand:IMODE 1 "memory_operand" "")) 84169689Skan (match_operand:IMODE 2 "general_operand" "")))] 85169689Skan "" 86169689Skan{ 87169689Skan ia64_expand_atomic_op (NOT, operands[1], operands[2], operands[0], NULL); 88169689Skan DONE; 89169689Skan}) 90169689Skan 91169689Skan(define_expand "sync_new_<fetchop_name><mode>" 92169689Skan [(set (match_operand:IMODE 0 "gr_register_operand" "") 93169689Skan (FETCHOP:IMODE 94169689Skan (match_operand:IMODE 1 "memory_operand" "") 95169689Skan (match_operand:IMODE 2 "general_operand" "")))] 96169689Skan "" 97169689Skan{ 98169689Skan ia64_expand_atomic_op (<CODE>, operands[1], operands[2], NULL, operands[0]); 99169689Skan DONE; 100169689Skan}) 101169689Skan 102169689Skan(define_expand "sync_new_nand<mode>" 103169689Skan [(set (match_operand:IMODE 0 "gr_register_operand" "") 104169689Skan (and:IMODE 105169689Skan (not:IMODE (match_operand:IMODE 1 "memory_operand" "")) 106169689Skan (match_operand:IMODE 2 "general_operand" "")))] 107169689Skan "" 108169689Skan{ 109169689Skan ia64_expand_atomic_op (NOT, operands[1], operands[2], NULL, operands[0]); 110169689Skan DONE; 111169689Skan}) 112169689Skan 113169689Skan(define_expand "sync_compare_and_swap<mode>" 114169689Skan [(match_operand:IMODE 0 "gr_register_operand" "") 115169689Skan (match_operand:IMODE 1 "memory_operand" "") 116169689Skan (match_operand:IMODE 2 "gr_register_operand" "") 117169689Skan (match_operand:IMODE 3 "gr_register_operand" "")] 118169689Skan "" 119169689Skan{ 120169689Skan rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM); 121169689Skan rtx dst; 122169689Skan 123169689Skan convert_move (ccv, operands[2], 1); 124169689Skan 125169689Skan dst = operands[0]; 126169689Skan if (GET_MODE (dst) != DImode) 127169689Skan dst = gen_reg_rtx (DImode); 128169689Skan 129169689Skan emit_insn (gen_memory_barrier ()); 130169689Skan emit_insn (gen_cmpxchg_rel_<mode> (dst, operands[1], ccv, operands[3])); 131169689Skan 132169689Skan if (dst != operands[0]) 133169689Skan emit_move_insn (operands[0], gen_lowpart (<MODE>mode, dst)); 134169689Skan DONE; 135169689Skan}) 136169689Skan 137169689Skan(define_insn "cmpxchg_rel_<mode>" 138169689Skan [(set (match_operand:DI 0 "gr_register_operand" "=r") 139169689Skan (zero_extend:DI 140169689Skan (match_operand:I124MODE 1 "not_postinc_memory_operand" "+S"))) 141169689Skan (set (match_dup 1) 142169689Skan (unspec:I124MODE 143169689Skan [(match_dup 1) 144169689Skan (match_operand:DI 2 "ar_ccv_reg_operand" "") 145169689Skan (match_operand:I124MODE 3 "gr_register_operand" "r")] 146169689Skan UNSPEC_CMPXCHG_ACQ))] 147169689Skan "" 148169689Skan "cmpxchg<modesuffix>.rel %0 = %1, %3, %2" 149169689Skan [(set_attr "itanium_class" "sem")]) 150169689Skan 151169689Skan(define_insn "cmpxchg_rel_di" 152169689Skan [(set (match_operand:DI 0 "gr_register_operand" "=r") 153169689Skan (match_operand:DI 1 "not_postinc_memory_operand" "+S")) 154169689Skan (set (match_dup 1) 155169689Skan (unspec:DI [(match_dup 1) 156169689Skan (match_operand:DI 2 "ar_ccv_reg_operand" "") 157169689Skan (match_operand:DI 3 "gr_register_operand" "r")] 158169689Skan UNSPEC_CMPXCHG_ACQ))] 159169689Skan "" 160169689Skan "cmpxchg8.rel %0 = %1, %3, %2" 161169689Skan [(set_attr "itanium_class" "sem")]) 162169689Skan 163169689Skan(define_insn "sync_lock_test_and_set<mode>" 164169689Skan [(set (match_operand:IMODE 0 "gr_register_operand" "=r") 165169689Skan (match_operand:IMODE 1 "not_postinc_memory_operand" "+S")) 166169689Skan (set (match_dup 1) 167169689Skan (match_operand:IMODE 2 "gr_register_operand" "r"))] 168169689Skan "" 169169689Skan "xchg<modesuffix> %0 = %1, %2" 170169689Skan [(set_attr "itanium_class" "sem")]) 171169689Skan 172169689Skan(define_expand "sync_lock_release<mode>" 173169689Skan [(set (match_operand:IMODE 0 "memory_operand" "") 174169689Skan (match_operand:IMODE 1 "gr_reg_or_0_operand" ""))] 175169689Skan "" 176169689Skan{ 177169689Skan gcc_assert (MEM_VOLATILE_P (operands[0])); 178169689Skan}) 179