itanium1.md revision 132718
1;; Itanium1 (original Itanium) DFA descriptions for insn scheduling 2;; and bundling. 3;; Copyright (C) 2002 Free Software Foundation, Inc. 4;; Contributed by Vladimir Makarov <vmakarov@redhat.com>. 5;; 6;; This file is part of GCC. 7;; 8;; GCC is free software; you can redistribute it and/or modify 9;; it under the terms of the GNU General Public License as published by 10;; the Free Software Foundation; either version 2, or (at your option) 11;; any later version. 12;; 13;; GCC is distributed in the hope that it will be useful, 14;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16;; GNU General Public License for more details. 17;; 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING. If not, write to 20;; the Free Software Foundation, 59 Temple Place - Suite 330, 21;; Boston, MA 02111-1307, USA. */ 22;; 23 24 25/* This is description of pipeline hazards based on DFA. The 26 following constructions can be used for this: 27 28 o define_cpu_unit string [string]) describes a cpu functional unit 29 (separated by comma). 30 31 1st operand: Names of cpu function units. 32 2nd operand: Name of automaton (see comments for 33 DEFINE_AUTOMATON). 34 35 All define_reservations and define_cpu_units should have unique 36 names which can not be "nothing". 37 38 o (exclusion_set string string) means that each CPU function unit 39 in the first string can not be reserved simultaneously with each 40 unit whose name is in the second string and vise versa. CPU 41 units in the string are separated by commas. For example, it is 42 useful for description CPU with fully pipelined floating point 43 functional unit which can execute simultaneously only single 44 floating point insns or only double floating point insns. 45 46 o (presence_set string string) means that each CPU function unit in 47 the first string can not be reserved unless at least one of 48 pattern of units whose names are in the second string is 49 reserved. This is an asymmetric relation. CPU units or unit 50 patterns in the strings are separated by commas. Pattern is one 51 unit name or unit names separated by white-spaces. 52 53 For example, it is useful for description that slot1 is reserved 54 after slot0 reservation for a VLIW processor. We could describe 55 it by the following construction 56 57 (presence_set "slot1" "slot0") 58 59 Or slot1 is reserved only after slot0 and unit b0 reservation. 60 In this case we could write 61 62 (presence_set "slot1" "slot0 b0") 63 64 All CPU functional units in a set should belong to the same 65 automaton. 66 67 o (final_presence_set string string) is analogous to 68 `presence_set'. The difference between them is when checking is 69 done. When an instruction is issued in given automaton state 70 reflecting all current and planned unit reservations, the 71 automaton state is changed. The first state is a source state, 72 the second one is a result state. Checking for `presence_set' is 73 done on the source state reservation, checking for 74 `final_presence_set' is done on the result reservation. This 75 construction is useful to describe a reservation which is 76 actually two subsequent reservations. For example, if we use 77 78 (presence_set "slot1" "slot0") 79 80 the following insn will be never issued (because slot1 requires 81 slot0 which is absent in the source state). 82 83 (define_reservation "insn_and_nop" "slot0 + slot1") 84 85 but it can be issued if we use analogous `final_presence_set'. 86 87 o (absence_set string string) means that each CPU function unit in 88 the first string can be reserved only if each pattern of units 89 whose names are in the second string is not reserved. This is an 90 asymmetric relation (actually exclusion set is analogous to this 91 one but it is symmetric). CPU units or unit patterns in the 92 string are separated by commas. Pattern is one unit name or unit 93 names separated by white-spaces. 94 95 For example, it is useful for description that slot0 can not be 96 reserved after slot1 or slot2 reservation for a VLIW processor. 97 We could describe it by the following construction 98 99 (absence_set "slot2" "slot0, slot1") 100 101 Or slot2 can not be reserved if slot0 and unit b0 are reserved or 102 slot1 and unit b1 are reserved . In this case we could write 103 104 (absence_set "slot2" "slot0 b0, slot1 b1") 105 106 All CPU functional units in a set should to belong the same 107 automaton. 108 109 o (final_absence_set string string) is analogous to `absence_set' but 110 checking is done on the result (state) reservation. See comments 111 for final_presence_set. 112 113 o (define_bypass number out_insn_names in_insn_names) names bypass with 114 given latency (the first number) from insns given by the first 115 string (see define_insn_reservation) into insns given by the 116 second string. Insn names in the strings are separated by 117 commas. 118 119 o (define_automaton string) describes names of an automaton 120 generated and used for pipeline hazards recognition. The names 121 are separated by comma. Actually it is possibly to generate the 122 single automaton but unfortunately it can be very large. If we 123 use more one automata, the summary size of the automata usually 124 is less than the single one. The automaton name is used in 125 define_cpu_unit. All automata should have unique names. 126 127 o (automata_option string) describes option for generation of 128 automata. Currently there are the following options: 129 130 o "no-minimization" which makes no minimization of automata. 131 This is only worth to do when we are debugging the description 132 and need to look more accurately at reservations of states. 133 134 o "ndfa" which makes automata with nondetermenistic reservation 135 by insns. 136 137 o (define_reservation string string) names reservation (the first 138 string) of cpu functional units (the 2nd string). Sometimes unit 139 reservations for different insns contain common parts. In such 140 case, you describe common part and use one its name (the 1st 141 parameter) in regular expression in define_insn_reservation. All 142 define_reservations, define results and define_cpu_units should 143 have unique names which can not be "nothing". 144 145 o (define_insn_reservation name default_latency condition regexpr) 146 describes reservation of cpu functional units (the 3nd operand) 147 for instruction which is selected by the condition (the 2nd 148 parameter). The first parameter is used for output of debugging 149 information. The reservations are described by a regular 150 expression according the following syntax: 151 152 regexp = regexp "," oneof 153 | oneof 154 155 oneof = oneof "|" allof 156 | allof 157 158 allof = allof "+" repeat 159 | repeat 160 161 repeat = element "*" number 162 | element 163 164 element = cpu_function_name 165 | reservation_name 166 | result_name 167 | "nothing" 168 | "(" regexp ")" 169 170 1. "," is used for describing start of the next cycle in 171 reservation. 172 173 2. "|" is used for describing the reservation described by the 174 first regular expression *or* the reservation described by 175 the second regular expression *or* etc. 176 177 3. "+" is used for describing the reservation described by the 178 first regular expression *and* the reservation described by 179 the second regular expression *and* etc. 180 181 4. "*" is used for convenience and simply means sequence in 182 which the regular expression are repeated NUMBER times with 183 cycle advancing (see ","). 184 185 5. cpu function unit name which means reservation. 186 187 6. reservation name -- see define_reservation. 188 189 7. string "nothing" means no units reservation. 190 191*/ 192 193(define_automaton "one") 194 195;; All possible combinations of bundles/syllables 196(define_cpu_unit "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 197 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx" "one") 198(define_cpu_unit "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b,\ 199 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx." "one") 200(define_cpu_unit "1_0mii., 1_0mmi., 1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb.,\ 201 1_0mib., 1_0mmb., 1_0mfb." "one") 202 203(define_cpu_unit "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb,\ 204 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx" "one") 205(define_cpu_unit "1_1mi.i, 1_1mm.i, 1_1mf.i, 1_1bb.b, 1_1mb.b,\ 206 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx." "one") 207(define_cpu_unit "1_1mii., 1_1mmi., 1_1mfi., 1_1bbb., 1_1mbb.,\ 208 1_1mib., 1_1mmb., 1_1mfb." "one") 209 210;; Slot 1 211(exclusion_set "1_0m.ii" 212 "1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb,\ 213 1_0m.lx") 214(exclusion_set "1_0m.mi" 215 "1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 216(exclusion_set "1_0m.fi" 217 "1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 218(exclusion_set "1_0m.mf" 219 "1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 220(exclusion_set "1_0b.bb" "1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 221(exclusion_set "1_0m.bb" "1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 222(exclusion_set "1_0m.ib" "1_0m.mb, 1_0m.fb, 1_0m.lx") 223(exclusion_set "1_0m.mb" "1_0m.fb, 1_0m.lx") 224(exclusion_set "1_0m.fb" "1_0m.lx") 225 226;; Slot 2 227(exclusion_set "1_0mi.i" 228 "1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b,\ 229 1_0mlx.") 230(exclusion_set "1_0mm.i" 231 "1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 232(exclusion_set "1_0mf.i" 233 "1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 234(exclusion_set "1_0mm.f" 235 "1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 236(exclusion_set "1_0bb.b" "1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 237(exclusion_set "1_0mb.b" "1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 238(exclusion_set "1_0mi.b" "1_0mm.b, 1_0mf.b, 1_0mlx.") 239(exclusion_set "1_0mm.b" "1_0mf.b, 1_0mlx.") 240(exclusion_set "1_0mf.b" "1_0mlx.") 241 242;; Slot 3 243(exclusion_set "1_0mii." 244 "1_0mmi., 1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb.,\ 245 1_0mlx.") 246(exclusion_set "1_0mmi." 247 "1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 248(exclusion_set "1_0mfi." 249 "1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 250(exclusion_set "1_0mmf." 251 "1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 252(exclusion_set "1_0bbb." "1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 253(exclusion_set "1_0mbb." "1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 254(exclusion_set "1_0mib." "1_0mmb., 1_0mfb., 1_0mlx.") 255(exclusion_set "1_0mmb." "1_0mfb., 1_0mlx.") 256(exclusion_set "1_0mfb." "1_0mlx.") 257 258;; Slot 4 259(exclusion_set "1_1m.ii" 260 "1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 261(exclusion_set "1_1m.mi" 262 "1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 263(exclusion_set "1_1m.fi" 264 "1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 265(exclusion_set "1_1b.bb" "1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 266(exclusion_set "1_1m.bb" "1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 267(exclusion_set "1_1m.ib" "1_1m.mb, 1_1m.fb, 1_1m.lx") 268(exclusion_set "1_1m.mb" "1_1m.fb, 1_1m.lx") 269(exclusion_set "1_1m.fb" "1_1m.lx") 270 271;; Slot 5 272(exclusion_set "1_1mi.i" 273 "1_1mm.i, 1_1mf.i, 1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 274(exclusion_set "1_1mm.i" 275 "1_1mf.i, 1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 276(exclusion_set "1_1mf.i" 277 "1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 278(exclusion_set "1_1bb.b" "1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 279(exclusion_set "1_1mb.b" "1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 280(exclusion_set "1_1mi.b" "1_1mm.b, 1_1mf.b, 1_1mlx.") 281(exclusion_set "1_1mm.b" "1_1mf.b, 1_1mlx.") 282(exclusion_set "1_1mf.b" "1_1mlx.") 283 284;; Slot 6 285(exclusion_set "1_1mii." 286 "1_1mmi., 1_1mfi., 1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 287(exclusion_set "1_1mmi." 288 "1_1mfi., 1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 289(exclusion_set "1_1mfi." 290 "1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 291(exclusion_set "1_1bbb." "1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 292(exclusion_set "1_1mbb." "1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 293(exclusion_set "1_1mib." "1_1mmb., 1_1mfb., 1_1mlx.") 294(exclusion_set "1_1mmb." "1_1mfb., 1_1mlx.") 295(exclusion_set "1_1mfb." "1_1mlx.") 296 297(final_presence_set "1_0mi.i" "1_0m.ii") 298(final_presence_set "1_0mii." "1_0mi.i") 299(final_presence_set "1_1mi.i" "1_1m.ii") 300(final_presence_set "1_1mii." "1_1mi.i") 301 302(final_presence_set "1_0mm.i" "1_0m.mi") 303(final_presence_set "1_0mmi." "1_0mm.i") 304(final_presence_set "1_1mm.i" "1_1m.mi") 305(final_presence_set "1_1mmi." "1_1mm.i") 306 307(final_presence_set "1_0mf.i" "1_0m.fi") 308(final_presence_set "1_0mfi." "1_0mf.i") 309(final_presence_set "1_1mf.i" "1_1m.fi") 310(final_presence_set "1_1mfi." "1_1mf.i") 311 312(final_presence_set "1_0mm.f" "1_0m.mf") 313(final_presence_set "1_0mmf." "1_0mm.f") 314 315(final_presence_set "1_0bb.b" "1_0b.bb") 316(final_presence_set "1_0bbb." "1_0bb.b") 317(final_presence_set "1_1bb.b" "1_1b.bb") 318(final_presence_set "1_1bbb." "1_1bb.b") 319 320(final_presence_set "1_0mb.b" "1_0m.bb") 321(final_presence_set "1_0mbb." "1_0mb.b") 322(final_presence_set "1_1mb.b" "1_1m.bb") 323(final_presence_set "1_1mbb." "1_1mb.b") 324 325(final_presence_set "1_0mi.b" "1_0m.ib") 326(final_presence_set "1_0mib." "1_0mi.b") 327(final_presence_set "1_1mi.b" "1_1m.ib") 328(final_presence_set "1_1mib." "1_1mi.b") 329 330(final_presence_set "1_0mm.b" "1_0m.mb") 331(final_presence_set "1_0mmb." "1_0mm.b") 332(final_presence_set "1_1mm.b" "1_1m.mb") 333(final_presence_set "1_1mmb." "1_1mm.b") 334 335(final_presence_set "1_0mf.b" "1_0m.fb") 336(final_presence_set "1_0mfb." "1_0mf.b") 337(final_presence_set "1_1mf.b" "1_1m.fb") 338(final_presence_set "1_1mfb." "1_1mf.b") 339 340(final_presence_set "1_0mlx." "1_0m.lx") 341(final_presence_set "1_1mlx." "1_1m.lx") 342 343(final_presence_set 344 "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx" 345 "1_0mii.,1_0mmi.,1_0mfi.,1_0mmf.,1_0bbb.,1_0mbb.,1_0mib.,1_0mmb.,1_0mfb.,\ 346 1_0mlx.") 347 348;; Microarchitecture units: 349(define_cpu_unit 350 "1_um0, 1_um1, 1_ui0, 1_ui1, 1_uf0, 1_uf1, 1_ub0, 1_ub1, 1_ub2,\ 351 1_unb0, 1_unb1, 1_unb2" "one") 352 353(exclusion_set "1_ub0" "1_unb0") 354(exclusion_set "1_ub1" "1_unb1") 355(exclusion_set "1_ub2" "1_unb2") 356 357;; The following rules are used to decrease number of alternatives. 358;; They are consequences of Itanium microarchitecture. They also 359;; describe the following rules mentioned in Itanium 360;; microarchitecture: rules mentioned in Itanium microarchitecture: 361;; o "MMF: Always splits issue before the first M and after F regardless 362;; of surrounding bundles and stops". 363;; o "BBB/MBB: Always splits issue after either of these bundles". 364;; o "MIB BBB: Split issue after the first bundle in this pair". 365 366(exclusion_set "1_0m.mf,1_0mm.f,1_0mmf." 367 "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx") 368(exclusion_set "1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb." 369 "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx") 370(exclusion_set "1_0m.ib,1_0mi.b,1_0mib." "1_1b.bb") 371 372;; For exceptions of M, I, B, F insns: 373(define_cpu_unit "1_not_um1, 1_not_ui1, 1_not_uf1" "one") 374 375(final_absence_set "1_not_um1" "1_um1") 376(final_absence_set "1_not_ui1" "1_ui1") 377(final_absence_set "1_not_uf1" "1_uf1") 378 379;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 380;;; B-slot contains a nop.b or a brp instruction". 381;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 382;;; nop.b, otherwise it disperses to B2". 383(final_absence_set 384 "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb,\ 385 1_1m.lx" 386 "1_0mib. 1_ub2, 1_0mfb. 1_ub2, 1_0mmb. 1_ub2") 387 388;; This is necessary to start new processor cycle when we meet stop bit. 389(define_cpu_unit "1_stop" "one") 390(final_absence_set 391 "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\ 392 1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\ 393 1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\ 394 1_0m.lx,1_0mlx., \ 395 1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\ 396 1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,1_1m.ib,1_1mi.b,1_1mib.,\ 397 1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,1_1m.lx,1_1mlx." 398 "1_stop") 399 400;; M and I instruction is dispersed to the lowest numbered M or I unit 401;; not already in use. An I slot in the 3rd position of 2nd bundle is 402;; always dispersed to I1 403(final_presence_set "1_um1" "1_um0") 404(final_presence_set "1_ui1" "1_ui0, 1_1mii., 1_1mmi., 1_1mfi.") 405 406;; Insns 407 408;; M and I instruction is dispersed to the lowest numbered M or I unit 409;; not already in use. An I slot in the 3rd position of 2nd bundle is 410;; always dispersed to I1 411(define_reservation "1_M0" 412 "1_0m.ii+1_um0|1_0m.mi+1_um0|1_0mm.i+(1_um0|1_um1)\ 413 |1_0m.fi+1_um0|1_0m.mf+1_um0|1_0mm.f+1_um1\ 414 |1_0m.bb+1_um0|1_0m.ib+1_um0|1_0m.mb+1_um0\ 415 |1_0mm.b+1_um1|1_0m.fb+1_um0|1_0m.lx+1_um0\ 416 |1_1mm.i+1_um1|1_1mm.b+1_um1\ 417 |(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\ 418 +(1_um0|1_um1)") 419 420(define_reservation "1_M1" 421 "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 422 |1_0mib.+1_unb0|1_0mfb.+1_unb0|1_0mmb.+1_unb0)\ 423 +(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\ 424 +(1_um0|1_um1)") 425 426(define_reservation "1_M" "1_M0|1_M1") 427 428;; Exceptions for dispersal rules. 429;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1". 430(define_reservation "1_I0" 431 "1_0mi.i+1_ui0|1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 432 |1_0mi.b+1_ui0|(1_1mi.i|1_1mi.b)+(1_ui0|1_ui1)\ 433 |1_1mii.+1_ui1|1_1mmi.+1_ui1|1_1mfi.+1_ui1") 434 435(define_reservation "1_I1" 436 "1_0m.ii+1_um0+1_0mi.i+1_ui0|1_0mm.i+(1_um0|1_um1)+1_0mmi.+1_ui0\ 437 |1_0mf.i+1_uf0+1_0mfi.+1_ui0|1_0m.ib+1_um0+1_0mi.b+1_ui0\ 438 |(1_1m.ii+(1_um0|1_um1)+1_1mi.i\ 439 |1_1m.ib+(1_um0|1_um1)+1_1mi.b)+(1_ui0|1_ui1)\ 440 |1_1mm.i+1_um1+1_1mmi.+1_ui1|1_1mf.i+1_uf1+1_1mfi.+1_ui1") 441 442(define_reservation "1_I" "1_I0|1_I1") 443 444;; "An F slot in the 1st bundle disperses to F0". 445;; "An F slot in the 2st bundle disperses to F1". 446(define_reservation "1_F0" 447 "1_0mf.i+1_uf0|1_0mmf.+1_uf0|1_0mf.b+1_uf0|1_1mf.i+1_uf1|1_1mf.b+1_uf1") 448 449(define_reservation "1_F1" 450 "1_0m.fi+1_um0+1_0mf.i+1_uf0|1_0mm.f+(1_um0|1_um1)+1_0mmf.+1_uf0\ 451 |1_0m.fb+1_um0+1_0mf.b+1_uf0|1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\ 452 |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1") 453 454(define_reservation "1_F2" 455 "1_0m.mf+1_um0+1_0mm.f+1_um1+1_0mmf.+1_uf0\ 456 |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 457 |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0)\ 458 +(1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\ 459 |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1)") 460 461(define_reservation "1_F" "1_F0|1_F1|1_F2") 462 463;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 464;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 465;;; 2nd position it is dispersed to B2". 466(define_reservation "1_NB" 467 "1_0b.bb+1_unb0|1_0bb.b+1_unb1|1_0bbb.+1_unb2\ 468 |1_0mb.b+1_unb1|1_0mbb.+1_unb2\ 469 |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0\ 470 |1_1b.bb+1_unb0|1_1bb.b+1_unb1\ 471 |1_1bbb.+1_unb2|1_1mb.b+1_unb1|1_1mbb.+1_unb2|1_1mib.+1_unb0\ 472 |1_1mmb.+1_unb0|1_1mfb.+1_unb0") 473 474(define_reservation "1_B0" 475 "1_0b.bb+1_ub0|1_0bb.b+1_ub1|1_0bbb.+1_ub2\ 476 |1_0mb.b+1_ub1|1_0mbb.+1_ub2|1_0mib.+1_ub2\ 477 |1_0mfb.+1_ub2|1_1b.bb+1_ub0|1_1bb.b+1_ub1\ 478 |1_1bbb.+1_ub2|1_1mb.b+1_ub1\ 479 |1_1mib.+1_ub2|1_1mmb.+1_ub2|1_1mfb.+1_ub2") 480 481(define_reservation "1_B1" 482 "1_0m.bb+1_um0+1_0mb.b+1_ub1|1_0mi.b+1_ui0+1_0mib.+1_ub2\ 483 |1_0mf.b+1_uf0+1_0mfb.+1_ub2\ 484 |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0)+1_1b.bb+1_ub0\ 485 |1_1m.bb+(1_um0|1_um1)+1_1mb.b+1_ub1\ 486 |1_1mi.b+(1_ui0|1_ui1)+1_1mib.+1_ub2\ 487 |1_1mm.b+1_um1+1_1mmb.+1_ub2\ 488 |1_1mf.b+1_uf1+1_1mfb.+1_ub2") 489 490(define_reservation "1_B" "1_B0|1_B1") 491 492;; MLX bunlde uses ports equivalent to MFI bundles. 493(define_reservation "1_L0" "1_0mlx.+1_ui0+1_uf0|1_1mlx.+(1_ui0|1_ui1)+1_uf1") 494(define_reservation "1_L1" 495 "1_0m.lx+1_um0+1_0mlx.+1_ui0+1_uf0\ 496 |1_1m.lx+(1_um0|1_um1)+1_1mlx.+(1_ui0|1_ui1)+1_uf1") 497(define_reservation "1_L2" 498 "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 499 |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0) 500 +1_1m.lx+(1_um0|1_um1)+1_1mlx.+1_ui1+1_uf1") 501(define_reservation "1_L" "1_L0|1_L1|1_L2") 502 503(define_reservation "1_A" "1_M|1_I") 504 505(define_insn_reservation "1_stop_bit" 0 506 (and (and (eq_attr "cpu" "itanium") 507 (eq_attr "itanium_class" "stop_bit")) 508 (eq (symbol_ref "bundling_p") (const_int 0))) 509 "1_stop|1_m0_stop|1_m1_stop|1_mi0_stop|1_mi1_stop") 510 511(define_insn_reservation "1_br" 0 512 (and (and (eq_attr "cpu" "itanium") 513 (eq_attr "itanium_class" "br")) 514 (eq (symbol_ref "bundling_p") (const_int 0))) "1_B") 515(define_insn_reservation "1_scall" 0 516 (and (and (eq_attr "cpu" "itanium") 517 (eq_attr "itanium_class" "scall")) 518 (eq (symbol_ref "bundling_p") (const_int 0))) "1_B") 519(define_insn_reservation "1_fcmp" 2 520 (and (and (eq_attr "cpu" "itanium") 521 (eq_attr "itanium_class" "fcmp")) 522 (eq (symbol_ref "bundling_p") (const_int 0))) 523 "1_F+1_not_uf1") 524(define_insn_reservation "1_fcvtfx" 7 525 (and (and (eq_attr "cpu" "itanium") 526 (eq_attr "itanium_class" "fcvtfx")) 527 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F") 528(define_insn_reservation "1_fld" 9 529 (and (and (eq_attr "cpu" "itanium") 530 (eq_attr "itanium_class" "fld")) 531 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 532(define_insn_reservation "1_fmac" 5 533 (and (and (eq_attr "cpu" "itanium") 534 (eq_attr "itanium_class" "fmac")) 535 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F") 536(define_insn_reservation "1_fmisc" 5 537 (and (and (eq_attr "cpu" "itanium") 538 (eq_attr "itanium_class" "fmisc")) 539 (eq (symbol_ref "bundling_p") (const_int 0))) 540 "1_F+1_not_uf1") 541 542;; There is only one insn `mov = ar.bsp' for frar_i: 543(define_insn_reservation "1_frar_i" 13 544 (and (and (eq_attr "cpu" "itanium") 545 (eq_attr "itanium_class" "frar_i")) 546 (eq (symbol_ref "bundling_p") (const_int 0))) 547 "1_I+1_not_ui1") 548;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m: 549(define_insn_reservation "1_frar_m" 6 550 (and (and (eq_attr "cpu" "itanium") 551 (eq_attr "itanium_class" "frar_m")) 552 (eq (symbol_ref "bundling_p") (const_int 0))) 553 "1_M+1_not_um1") 554(define_insn_reservation "1_frbr" 2 555 (and (and (eq_attr "cpu" "itanium") 556 (eq_attr "itanium_class" "frbr")) 557 (eq (symbol_ref "bundling_p") (const_int 0))) 558 "1_I+1_not_ui1") 559(define_insn_reservation "1_frfr" 2 560 (and (and (eq_attr "cpu" "itanium") 561 (eq_attr "itanium_class" "frfr")) 562 (eq (symbol_ref "bundling_p") (const_int 0))) 563 "1_M+1_not_um1") 564(define_insn_reservation "1_frpr" 2 565 (and (and (eq_attr "cpu" "itanium") 566 (eq_attr "itanium_class" "frpr")) 567 (eq (symbol_ref "bundling_p") (const_int 0))) 568 "1_I+1_not_ui1") 569 570(define_insn_reservation "1_ialu" 1 571 (and (and (eq_attr "cpu" "itanium") 572 (eq_attr "itanium_class" "ialu")) 573 (eq (symbol_ref 574 "bundling_p || ia64_produce_address_p (insn)") 575 (const_int 0))) 576 "1_A") 577(define_insn_reservation "1_ialu_addr" 1 578 (and (and (eq_attr "cpu" "itanium") 579 (eq_attr "itanium_class" "ialu")) 580 (eq (symbol_ref 581 "!bundling_p && ia64_produce_address_p (insn)") 582 (const_int 1))) 583 "1_M") 584(define_insn_reservation "1_icmp" 1 585 (and (and (eq_attr "cpu" "itanium") 586 (eq_attr "itanium_class" "icmp")) 587 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A") 588(define_insn_reservation "1_ilog" 1 589 (and (and (eq_attr "cpu" "itanium") 590 (eq_attr "itanium_class" "ilog")) 591 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A") 592(define_insn_reservation "1_ishf" 1 593 (and (and (eq_attr "cpu" "itanium") 594 (eq_attr "itanium_class" "ishf")) 595 (eq (symbol_ref "bundling_p") (const_int 0))) 596 "1_I+1_not_ui1") 597(define_insn_reservation "1_ld" 2 598 (and (and (eq_attr "cpu" "itanium") 599 (eq_attr "itanium_class" "ld")) 600 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 601(define_insn_reservation "1_long_i" 1 602 (and (and (eq_attr "cpu" "itanium") 603 (eq_attr "itanium_class" "long_i")) 604 (eq (symbol_ref "bundling_p") (const_int 0))) "1_L") 605(define_insn_reservation "1_mmmul" 2 606 (and (and (eq_attr "cpu" "itanium") 607 (eq_attr "itanium_class" "mmmul")) 608 (eq (symbol_ref "bundling_p") (const_int 0))) 609 "1_I+1_not_ui1") 610(define_insn_reservation "1_mmshf" 2 611 (and (and (eq_attr "cpu" "itanium") 612 (eq_attr "itanium_class" "mmshf")) 613 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I") 614(define_insn_reservation "1_mmshfi" 1 615 (and (and (eq_attr "cpu" "itanium") 616 (eq_attr "itanium_class" "mmshfi")) 617 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I") 618 619;; Now we have only one insn (flushrs) of such class. We assume that flushrs 620;; is the 1st syllable of the bundle after stop bit. 621(define_insn_reservation "1_rse_m" 0 622 (and (and (eq_attr "cpu" "itanium") 623 (eq_attr "itanium_class" "rse_m")) 624 (eq (symbol_ref "bundling_p") (const_int 0))) 625 "(1_0m.ii|1_0m.mi|1_0m.fi|1_0m.mf|1_0b.bb|1_0m.bb\ 626 |1_0m.ib|1_0m.mb|1_0m.fb|1_0m.lx)+1_um0") 627(define_insn_reservation "1_sem" 0 628 (and (and (eq_attr "cpu" "itanium") 629 (eq_attr "itanium_class" "sem")) 630 (eq (symbol_ref "bundling_p") (const_int 0))) 631 "1_M+1_not_um1") 632(define_insn_reservation "1_stf" 1 633 (and (and (eq_attr "cpu" "itanium") 634 (eq_attr "itanium_class" "stf")) 635 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 636(define_insn_reservation "1_st" 1 637 (and (and (eq_attr "cpu" "itanium") 638 (eq_attr "itanium_class" "st")) 639 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 640(define_insn_reservation "1_syst_m0" 0 641 (and (and (eq_attr "cpu" "itanium") 642 (eq_attr "itanium_class" "syst_m0")) 643 (eq (symbol_ref "bundling_p") (const_int 0))) 644 "1_M+1_not_um1") 645(define_insn_reservation "1_syst_m" 0 646 (and (and (eq_attr "cpu" "itanium") 647 (eq_attr "itanium_class" "syst_m")) 648 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 649(define_insn_reservation "1_tbit" 1 650 (and (and (eq_attr "cpu" "itanium") 651 (eq_attr "itanium_class" "tbit")) 652 (eq (symbol_ref "bundling_p") (const_int 0))) 653 "1_I+1_not_ui1") 654 655;; There is only ony insn `mov ar.pfs =' for toar_i: 656(define_insn_reservation "1_toar_i" 0 657 (and (and (eq_attr "cpu" "itanium") 658 (eq_attr "itanium_class" "toar_i")) 659 (eq (symbol_ref "bundling_p") (const_int 0))) 660 "1_I+1_not_ui1") 661;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: 662(define_insn_reservation "1_toar_m" 5 663 (and (and (eq_attr "cpu" "itanium") 664 (eq_attr "itanium_class" "toar_m")) 665 (eq (symbol_ref "bundling_p") (const_int 0))) 666 "1_M+1_not_um1") 667(define_insn_reservation "1_tobr" 1 668 (and (and (eq_attr "cpu" "itanium") 669 (eq_attr "itanium_class" "tobr")) 670 (eq (symbol_ref "bundling_p") (const_int 0))) 671 "1_I+1_not_ui1") 672(define_insn_reservation "1_tofr" 9 673 (and (and (eq_attr "cpu" "itanium") 674 (eq_attr "itanium_class" "tofr")) 675 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 676(define_insn_reservation "1_topr" 1 677 (and (and (eq_attr "cpu" "itanium") 678 (eq_attr "itanium_class" "topr")) 679 (eq (symbol_ref "bundling_p") (const_int 0))) 680 "1_I+1_not_ui1") 681(define_insn_reservation "1_xmpy" 7 682 (and (and (eq_attr "cpu" "itanium") 683 (eq_attr "itanium_class" "xmpy")) 684 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F") 685(define_insn_reservation "1_xtd" 1 686 (and (and (eq_attr "cpu" "itanium") 687 (eq_attr "itanium_class" "xtd")) 688 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I") 689 690(define_insn_reservation "1_chk_s" 0 691 (and (and (eq_attr "cpu" "itanium") 692 (eq_attr "itanium_class" "chk_s")) 693 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A") 694(define_insn_reservation "1_lfetch" 0 695 (and (and (eq_attr "cpu" "itanium") 696 (eq_attr "itanium_class" "lfetch")) 697 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 698 699(define_insn_reservation "1_nop_m" 0 700 (and (and (eq_attr "cpu" "itanium") 701 (eq_attr "itanium_class" "nop_m")) 702 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M0") 703(define_insn_reservation "1_nop_b" 0 704 (and (and (eq_attr "cpu" "itanium") 705 (eq_attr "itanium_class" "nop_b")) 706 (eq (symbol_ref "bundling_p") (const_int 0))) "1_NB") 707(define_insn_reservation "1_nop_i" 0 708 (and (and (eq_attr "cpu" "itanium") 709 (eq_attr "itanium_class" "nop_i")) 710 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I0") 711(define_insn_reservation "1_nop_f" 0 712 (and (and (eq_attr "cpu" "itanium") 713 (eq_attr "itanium_class" "nop_f")) 714 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F0") 715(define_insn_reservation "1_nop_x" 0 716 (and (and (eq_attr "cpu" "itanium") 717 (eq_attr "itanium_class" "nop_x")) 718 (eq (symbol_ref "bundling_p") (const_int 0))) "1_L0") 719 720;; We assume that there is no insn issued on the same cycle as unknown insn. 721(define_cpu_unit "1_empty" "one") 722(exclusion_set "1_empty" 723 "1_0m.ii,1_0m.mi,1_0m.fi,1_0m.mf,1_0b.bb,1_0m.bb,1_0m.ib,1_0m.mb,1_0m.fb,\ 724 1_0m.lx") 725 726(define_insn_reservation "1_unknown" 1 727 (and (and (eq_attr "cpu" "itanium") 728 (eq_attr "itanium_class" "unknown")) 729 (eq (symbol_ref "bundling_p") (const_int 0))) "1_empty") 730 731(define_insn_reservation "1_nop" 1 732 (and (and (eq_attr "cpu" "itanium") 733 (eq_attr "itanium_class" "nop")) 734 (eq (symbol_ref "bundling_p") (const_int 0))) 735 "1_M0|1_NB|1_I0|1_F0") 736 737(define_insn_reservation "1_ignore" 0 738 (and (and (eq_attr "cpu" "itanium") 739 (eq_attr "itanium_class" "ignore")) 740 (eq (symbol_ref "bundling_p") (const_int 0))) "nothing") 741 742 743(define_cpu_unit 744 "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs" 745 "one") 746(define_cpu_unit 747 "1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs" 748 "one") 749 750(define_cpu_unit "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont, 1_mb_cont,\ 751 1_b_cont, 1_bb_cont" "one") 752 753;; For stop in the middle of the bundles. 754(define_cpu_unit "1_m_stop, 1_m0_stop, 1_m1_stop, 1_0mmi_cont" "one") 755(define_cpu_unit "1_mi_stop, 1_mi0_stop, 1_mi1_stop, 1_0mii_cont" "one") 756 757(final_presence_set "1_0m_bs" 758 "1_0m.ii, 1_0m.mi, 1_0m.mf, 1_0m.fi, 1_0m.bb,\ 759 1_0m.ib, 1_0m.fb, 1_0m.mb, 1_0m.lx") 760(final_presence_set "1_1m_bs" 761 "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1m.bb, 1_1m.ib, 1_1m.fb, 1_1m.mb,\ 762 1_1m.lx") 763(final_presence_set "1_0mi_bs" "1_0mi.i, 1_0mi.i") 764(final_presence_set "1_1mi_bs" "1_1mi.i, 1_1mi.i") 765(final_presence_set "1_0mm_bs" "1_0mm.i, 1_0mm.f, 1_0mm.b") 766(final_presence_set "1_1mm_bs" "1_1mm.i, 1_1mm.b") 767(final_presence_set "1_0mf_bs" "1_0mf.i, 1_0mf.b") 768(final_presence_set "1_1mf_bs" "1_1mf.i, 1_1mf.b") 769(final_presence_set "1_0b_bs" "1_0b.bb") 770(final_presence_set "1_1b_bs" "1_1b.bb") 771(final_presence_set "1_0bb_bs" "1_0bb.b") 772(final_presence_set "1_1bb_bs" "1_1bb.b") 773(final_presence_set "1_0mb_bs" "1_0mb.b") 774(final_presence_set "1_1mb_bs" "1_1mb.b") 775 776(exclusion_set "1_0m_bs" 777 "1_0mi.i, 1_0mm.i, 1_0mm.f, 1_0mf.i, 1_0mb.b,\ 778 1_0mi.b, 1_0mf.b, 1_0mm.b, 1_0mlx., 1_m0_stop") 779(exclusion_set "1_1m_bs" 780 "1_1mi.i, 1_1mm.i, 1_1mf.i, 1_1mb.b, 1_1mi.b, 1_1mf.b, 1_1mm.b,\ 781 1_1mlx., 1_m1_stop") 782(exclusion_set "1_0mi_bs" "1_0mii., 1_0mib., 1_mi0_stop") 783(exclusion_set "1_1mi_bs" "1_1mii., 1_1mib., 1_mi1_stop") 784(exclusion_set "1_0mm_bs" "1_0mmi., 1_0mmf., 1_0mmb.") 785(exclusion_set "1_1mm_bs" "1_1mmi., 1_1mmb.") 786(exclusion_set "1_0mf_bs" "1_0mfi., 1_0mfb.") 787(exclusion_set "1_1mf_bs" "1_1mfi., 1_1mfb.") 788(exclusion_set "1_0b_bs" "1_0bb.b") 789(exclusion_set "1_1b_bs" "1_1bb.b") 790(exclusion_set "1_0bb_bs" "1_0bbb.") 791(exclusion_set "1_1bb_bs" "1_1bbb.") 792(exclusion_set "1_0mb_bs" "1_0mbb.") 793(exclusion_set "1_1mb_bs" "1_1mbb.") 794 795(exclusion_set 796 "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs, 797 1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs" 798 "1_stop") 799 800(final_presence_set 801 "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\ 802 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx." 803 "1_m_cont") 804(final_presence_set "1_0mii., 1_0mib." "1_mi_cont") 805(final_presence_set "1_0mmi., 1_0mmf., 1_0mmb." "1_mm_cont") 806(final_presence_set "1_0mfi., 1_0mfb." "1_mf_cont") 807(final_presence_set "1_0bb.b" "1_b_cont") 808(final_presence_set "1_0bbb." "1_bb_cont") 809(final_presence_set "1_0mbb." "1_mb_cont") 810 811(exclusion_set 812 "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 813 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx" 814 "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont,\ 815 1_mb_cont, 1_b_cont, 1_bb_cont") 816 817(exclusion_set "1_empty" 818 "1_m_cont,1_mi_cont,1_mm_cont,1_mf_cont,\ 819 1_mb_cont,1_b_cont,1_bb_cont") 820 821;; For m;mi bundle 822(final_presence_set "1_m0_stop" "1_0m.mi") 823(final_presence_set "1_0mm.i" "1_0mmi_cont") 824(exclusion_set "1_0mmi_cont" 825 "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 826 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 827(exclusion_set "1_m0_stop" "1_0mm.i") 828(final_presence_set "1_m1_stop" "1_1m.mi") 829(exclusion_set "1_m1_stop" "1_1mm.i") 830(final_presence_set "1_m_stop" "1_m0_stop, 1_m1_stop") 831 832;; For mi;i bundle 833(final_presence_set "1_mi0_stop" "1_0mi.i") 834(final_presence_set "1_0mii." "1_0mii_cont") 835(exclusion_set "1_0mii_cont" 836 "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 837 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 838(exclusion_set "1_mi0_stop" "1_0mii.") 839(final_presence_set "1_mi1_stop" "1_1mi.i") 840(exclusion_set "1_mi1_stop" "1_1mii.") 841(final_presence_set "1_mi_stop" "1_mi0_stop, 1_mi1_stop") 842 843(final_absence_set 844 "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\ 845 1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\ 846 1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\ 847 1_0m.lx,1_0mlx., \ 848 1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\ 849 1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,\ 850 1_1m.ib,1_1mi.b,1_1mib.,1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,\ 851 1_1m.lx,1_1mlx." 852 "1_m0_stop,1_m1_stop,1_mi0_stop,1_mi1_stop") 853 854(define_cpu_unit "1_m_cont_only, 1_b_cont_only" "one") 855(define_cpu_unit "1_mi_cont_only, 1_mm_cont_only, 1_mf_cont_only" "one") 856(define_cpu_unit "1_mb_cont_only, 1_bb_cont_only" "one") 857 858(final_presence_set "1_m_cont_only" "1_m_cont") 859(exclusion_set "1_m_cont_only" 860 "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\ 861 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 862 863(final_presence_set "1_b_cont_only" "1_b_cont") 864(exclusion_set "1_b_cont_only" "1_0bb.b") 865 866(final_presence_set "1_mi_cont_only" "1_mi_cont") 867(exclusion_set "1_mi_cont_only" "1_0mii., 1_0mib.") 868 869(final_presence_set "1_mm_cont_only" "1_mm_cont") 870(exclusion_set "1_mm_cont_only" "1_0mmi., 1_0mmf., 1_0mmb.") 871 872(final_presence_set "1_mf_cont_only" "1_mf_cont") 873(exclusion_set "1_mf_cont_only" "1_0mfi., 1_0mfb.") 874 875(final_presence_set "1_mb_cont_only" "1_mb_cont") 876(exclusion_set "1_mb_cont_only" "1_0mbb.") 877 878(final_presence_set "1_bb_cont_only" "1_bb_cont") 879(exclusion_set "1_bb_cont_only" "1_0bbb.") 880 881(define_insn_reservation "1_pre_cycle" 0 882 (and (and (eq_attr "cpu" "itanium") 883 (eq_attr "itanium_class" "pre_cycle")) 884 (eq (symbol_ref "bundling_p") (const_int 0))) 885 "(1_0m_bs, 1_m_cont) \ 886 | (1_0mi_bs, (1_mi_cont|nothing)) \ 887 | (1_0mm_bs, 1_mm_cont) \ 888 | (1_0mf_bs, (1_mf_cont|nothing)) \ 889 | (1_0b_bs, (1_b_cont|nothing)) \ 890 | (1_0bb_bs, (1_bb_cont|nothing)) \ 891 | (1_0mb_bs, (1_mb_cont|nothing)) \ 892 | (1_1m_bs, 1_m_cont) \ 893 | (1_1mi_bs, (1_mi_cont|nothing)) \ 894 | (1_1mm_bs, 1_mm_cont) \ 895 | (1_1mf_bs, (1_mf_cont|nothing)) \ 896 | (1_1b_bs, (1_b_cont|nothing)) \ 897 | (1_1bb_bs, (1_bb_cont|nothing)) \ 898 | (1_1mb_bs, (1_mb_cont|nothing)) \ 899 | (1_m_cont_only, (1_m_cont|nothing)) \ 900 | (1_b_cont_only, (1_b_cont|nothing)) \ 901 | (1_mi_cont_only, (1_mi_cont|nothing)) \ 902 | (1_mm_cont_only, (1_mm_cont|nothing)) \ 903 | (1_mf_cont_only, (1_mf_cont|nothing)) \ 904 | (1_mb_cont_only, (1_mb_cont|nothing)) \ 905 | (1_bb_cont_only, (1_bb_cont|nothing)) \ 906 | (1_m_stop, (1_0mmi_cont|nothing)) \ 907 | (1_mi_stop, (1_0mii_cont|nothing))") 908 909;; Bypasses: 910(define_bypass 1 "1_fcmp" "1_br,1_scall") 911;; ??? I found 7 cycle delay for 1_fmac -> 1_fcmp for Itanium1 912(define_bypass 7 "1_fmac" "1_fmisc,1_fcvtfx,1_xmpy,1_fcmp") 913 914;; ??? 915(define_bypass 3 "1_frbr" "1_mmmul,1_mmshf") 916(define_bypass 14 "1_frar_i" "1_mmmul,1_mmshf") 917(define_bypass 7 "1_frar_m" "1_mmmul,1_mmshf") 918 919;; ???? 920;; There is only one insn `mov ar.pfs =' for toar_i. 921(define_bypass 0 "1_tobr,1_topr,1_toar_i" "1_br,1_scall") 922 923(define_bypass 3 "1_ialu,1_ialu_addr" "1_mmmul,1_mmshf") 924;; ??? howto describe ialu for I slot only. We use ialu_addr for that 925;;(define_bypass 2 "1_ialu" "1_ld" "ia64_ld_address_bypass_p") 926;; ??? howto describe ialu st/address for I slot only. We use ialu_addr 927;; for that. 928;;(define_bypass 2 "1_ialu" "1_st" "ia64_st_address_bypass_p") 929 930(define_bypass 0 "1_icmp" "1_br,1_scall") 931 932(define_bypass 3 "1_ilog" "1_mmmul,1_mmshf") 933 934(define_bypass 2 "1_ilog,1_xtd" "1_ld" "ia64_ld_address_bypass_p") 935(define_bypass 2 "1_ilog,1_xtd" "1_st" "ia64_st_address_bypass_p") 936 937(define_bypass 3 "1_ld" "1_mmmul,1_mmshf") 938(define_bypass 3 "1_ld" "1_ld" "ia64_ld_address_bypass_p") 939(define_bypass 3 "1_ld" "1_st" "ia64_st_address_bypass_p") 940 941;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4, 942;; but HP engineers say any non-MM operation. 943(define_bypass 4 "1_mmmul,1_mmshf" 944 "1_br,1_fcmp,1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\ 945 1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_chk_s,\ 946 1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\ 947 1_tbit,1_toar_i,1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd") 948 949;; ??? how to describe that if scheduled < 4 cycle then latency is 10 cycles. 950;; (define_bypass 10 "1_mmmul,1_mmshf" "1_ialu,1_ilog,1_ishf,1_st,1_ld") 951 952(define_bypass 0 "1_tbit" "1_br,1_scall") 953 954(define_bypass 8 "1_tofr" "1_frfr,1_stf") 955(define_bypass 7 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_frfr") 956(define_bypass 8 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_stf") 957 958;; We don't use here fcmp because scall may be predicated. 959(define_bypass 0 "1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\ 960 1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\ 961 1_ld,1_long_i,1_mmmul,1_mmshf,1_mmshfi,1_toar_m,1_tofr,\ 962 1_xmpy,1_xtd" "1_scall") 963 964(define_bypass 0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\ 965 1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\ 966 1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,\ 967 1_chk_s,1_long_i,1_mmmul,1_mmshf,1_mmshfi,1_nop,\ 968 1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\ 969 1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\ 970 1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch" 971 "1_ignore") 972 973 974;; Bundling 975 976(define_automaton "oneb") 977 978;; Pseudo units for quicker searching for position in two packet window. */ 979(define_query_cpu_unit "1_1,1_2,1_3,1_4,1_5,1_6" "oneb") 980 981;; All possible combinations of bundles/syllables 982(define_cpu_unit 983 "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 984 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx" "oneb") 985(define_cpu_unit 986 "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\ 987 1b_0mi.b, 1b_0mm.b, 1b_0mf.b" "oneb") 988(define_query_cpu_unit 989 "1b_0mii., 1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\ 990 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx." "oneb") 991 992(define_cpu_unit "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\ 993 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx" "oneb") 994(define_cpu_unit "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\ 995 1b_1mi.b, 1b_1mm.b, 1b_1mf.b" "oneb") 996(define_query_cpu_unit "1b_1mii., 1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\ 997 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx." "oneb") 998 999;; Slot 1 1000(exclusion_set "1b_0m.ii" 1001 "1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1002 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1003(exclusion_set "1b_0m.mi" 1004 "1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib,\ 1005 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1006(exclusion_set "1b_0m.fi" 1007 "1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1008(exclusion_set "1b_0m.mf" 1009 "1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1010(exclusion_set "1b_0b.bb" "1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1011(exclusion_set "1b_0m.bb" "1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1012(exclusion_set "1b_0m.ib" "1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1013(exclusion_set "1b_0m.mb" "1b_0m.fb, 1b_0m.lx") 1014(exclusion_set "1b_0m.fb" "1b_0m.lx") 1015 1016;; Slot 2 1017(exclusion_set "1b_0mi.i" 1018 "1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\ 1019 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1020(exclusion_set "1b_0mm.i" 1021 "1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\ 1022 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1023(exclusion_set "1b_0mf.i" 1024 "1b_0mm.f, 1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1025(exclusion_set "1b_0mm.f" 1026 "1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1027(exclusion_set "1b_0bb.b" "1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1028(exclusion_set "1b_0mb.b" "1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1029(exclusion_set "1b_0mi.b" "1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1030(exclusion_set "1b_0mm.b" "1b_0mf.b, 1b_0mlx.") 1031(exclusion_set "1b_0mf.b" "1b_0mlx.") 1032 1033;; Slot 3 1034(exclusion_set "1b_0mii." 1035 "1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\ 1036 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1037(exclusion_set "1b_0mmi." 1038 "1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\ 1039 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1040(exclusion_set "1b_0mfi." 1041 "1b_0mmf., 1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1042(exclusion_set "1b_0mmf." 1043 "1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1044(exclusion_set "1b_0bbb." "1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1045(exclusion_set "1b_0mbb." "1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1046(exclusion_set "1b_0mib." "1b_0mmb., 1b_0mfb., 1b_0mlx.") 1047(exclusion_set "1b_0mmb." "1b_0mfb., 1b_0mlx.") 1048(exclusion_set "1b_0mfb." "1b_0mlx.") 1049 1050;; Slot 4 1051(exclusion_set "1b_1m.ii" 1052 "1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\ 1053 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1054(exclusion_set "1b_1m.mi" 1055 "1b_1m.fi, 1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1056(exclusion_set "1b_1m.fi" 1057 "1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1058(exclusion_set "1b_1b.bb" "1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1059(exclusion_set "1b_1m.bb" "1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1060(exclusion_set "1b_1m.ib" "1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1061(exclusion_set "1b_1m.mb" "1b_1m.fb, 1b_1m.lx") 1062(exclusion_set "1b_1m.fb" "1b_1m.lx") 1063 1064;; Slot 5 1065(exclusion_set "1b_1mi.i" 1066 "1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\ 1067 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1068(exclusion_set "1b_1mm.i" 1069 "1b_1mf.i, 1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1070(exclusion_set "1b_1mf.i" 1071 "1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1072(exclusion_set "1b_1bb.b" "1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1073(exclusion_set "1b_1mb.b" "1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1074(exclusion_set "1b_1mi.b" "1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1075(exclusion_set "1b_1mm.b" "1b_1mf.b, 1b_1mlx.") 1076(exclusion_set "1b_1mf.b" "1b_1mlx.") 1077 1078;; Slot 6 1079(exclusion_set "1b_1mii." 1080 "1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\ 1081 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1082(exclusion_set "1b_1mmi." 1083 "1b_1mfi., 1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1084(exclusion_set "1b_1mfi." 1085 "1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1086(exclusion_set "1b_1bbb." "1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1087(exclusion_set "1b_1mbb." "1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1088(exclusion_set "1b_1mib." "1b_1mmb., 1b_1mfb., 1b_1mlx.") 1089(exclusion_set "1b_1mmb." "1b_1mfb., 1b_1mlx.") 1090(exclusion_set "1b_1mfb." "1b_1mlx.") 1091 1092(final_presence_set "1b_0mi.i" "1b_0m.ii") 1093(final_presence_set "1b_0mii." "1b_0mi.i") 1094(final_presence_set "1b_1mi.i" "1b_1m.ii") 1095(final_presence_set "1b_1mii." "1b_1mi.i") 1096 1097(final_presence_set "1b_0mm.i" "1b_0m.mi") 1098(final_presence_set "1b_0mmi." "1b_0mm.i") 1099(final_presence_set "1b_1mm.i" "1b_1m.mi") 1100(final_presence_set "1b_1mmi." "1b_1mm.i") 1101 1102(final_presence_set "1b_0mf.i" "1b_0m.fi") 1103(final_presence_set "1b_0mfi." "1b_0mf.i") 1104(final_presence_set "1b_1mf.i" "1b_1m.fi") 1105(final_presence_set "1b_1mfi." "1b_1mf.i") 1106 1107(final_presence_set "1b_0mm.f" "1b_0m.mf") 1108(final_presence_set "1b_0mmf." "1b_0mm.f") 1109 1110(final_presence_set "1b_0bb.b" "1b_0b.bb") 1111(final_presence_set "1b_0bbb." "1b_0bb.b") 1112(final_presence_set "1b_1bb.b" "1b_1b.bb") 1113(final_presence_set "1b_1bbb." "1b_1bb.b") 1114 1115(final_presence_set "1b_0mb.b" "1b_0m.bb") 1116(final_presence_set "1b_0mbb." "1b_0mb.b") 1117(final_presence_set "1b_1mb.b" "1b_1m.bb") 1118(final_presence_set "1b_1mbb." "1b_1mb.b") 1119 1120(final_presence_set "1b_0mi.b" "1b_0m.ib") 1121(final_presence_set "1b_0mib." "1b_0mi.b") 1122(final_presence_set "1b_1mi.b" "1b_1m.ib") 1123(final_presence_set "1b_1mib." "1b_1mi.b") 1124 1125(final_presence_set "1b_0mm.b" "1b_0m.mb") 1126(final_presence_set "1b_0mmb." "1b_0mm.b") 1127(final_presence_set "1b_1mm.b" "1b_1m.mb") 1128(final_presence_set "1b_1mmb." "1b_1mm.b") 1129 1130(final_presence_set "1b_0mf.b" "1b_0m.fb") 1131(final_presence_set "1b_0mfb." "1b_0mf.b") 1132(final_presence_set "1b_1mf.b" "1b_1m.fb") 1133(final_presence_set "1b_1mfb." "1b_1mf.b") 1134 1135(final_presence_set "1b_0mlx." "1b_0m.lx") 1136(final_presence_set "1b_1mlx." "1b_1m.lx") 1137 1138(final_presence_set 1139 "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\ 1140 1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx" 1141 "1b_0mii.,1b_0mmi.,1b_0mfi.,1b_0mmf.,1b_0bbb.,1b_0mbb.,\ 1142 1b_0mib.,1b_0mmb.,1b_0mfb.,1b_0mlx.") 1143 1144;; Microarchitecture units: 1145(define_cpu_unit 1146 "1b_um0, 1b_um1, 1b_ui0, 1b_ui1, 1b_uf0, 1b_uf1, 1b_ub0, 1b_ub1, 1b_ub2,\ 1147 1b_unb0, 1b_unb1, 1b_unb2" "oneb") 1148 1149(exclusion_set "1b_ub0" "1b_unb0") 1150(exclusion_set "1b_ub1" "1b_unb1") 1151(exclusion_set "1b_ub2" "1b_unb2") 1152 1153;; The following rules are used to decrease number of alternatives. 1154;; They are consequences of Itanium microarchitecture. They also 1155;; describe the following rules mentioned in Itanium 1156;; microarchitecture: rules mentioned in Itanium microarchitecture: 1157;; o "MMF: Always splits issue before the first M and after F regardless 1158;; of surrounding bundles and stops". 1159;; o "BBB/MBB: Always splits issue after either of these bundles". 1160;; o "MIB BBB: Split issue after the first bundle in this pair". 1161 1162(exclusion_set "1b_0m.mf,1b_0mm.f,1b_0mmf." 1163 "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\ 1164 1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx") 1165(exclusion_set "1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb." 1166 "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\ 1167 1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx") 1168(exclusion_set "1b_0m.ib,1b_0mi.b,1b_0mib." "1b_1b.bb") 1169 1170;; For exceptions of M, I, B, F insns: 1171(define_cpu_unit "1b_not_um1, 1b_not_ui1, 1b_not_uf1" "oneb") 1172 1173(final_absence_set "1b_not_um1" "1b_um1") 1174(final_absence_set "1b_not_ui1" "1b_ui1") 1175(final_absence_set "1b_not_uf1" "1b_uf1") 1176 1177;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 1178;;; B-slot contains a nop.b or a brp instruction". 1179;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 1180;;; nop.b, otherwise it disperses to B2". 1181(final_absence_set 1182 "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\ 1183 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx" 1184 "1b_0mib. 1b_ub2, 1b_0mfb. 1b_ub2, 1b_0mmb. 1b_ub2") 1185 1186;; This is necessary to start new processor cycle when we meet stop bit. 1187(define_cpu_unit "1b_stop" "oneb") 1188(final_absence_set 1189 "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\ 1190 1b_0m.fi,1b_0mf.i,1b_0mfi.,\ 1191 1b_0m.mf,1b_0mm.f,1b_0mmf.,1b_0b.bb,1b_0bb.b,1b_0bbb.,\ 1192 1b_0m.bb,1b_0mb.b,1b_0mbb.,\ 1193 1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\ 1194 1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \ 1195 1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\ 1196 1b_1m.fi,1b_1mf.i,1b_1mfi.,\ 1197 1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\ 1198 1b_1m.ib,1b_1mi.b,1b_1mib.,\ 1199 1b_1m.mb,1b_1mm.b,1b_1mmb.,1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx." 1200 "1b_stop") 1201 1202;; M and I instruction is dispersed to the lowest numbered M or I unit 1203;; not already in use. An I slot in the 3rd position of 2nd bundle is 1204;; always dispersed to I1 1205(final_presence_set "1b_um1" "1b_um0") 1206(final_presence_set "1b_ui1" "1b_ui0, 1b_1mii., 1b_1mmi., 1b_1mfi.") 1207 1208;; Insns 1209 1210;; M and I instruction is dispersed to the lowest numbered M or I unit 1211;; not already in use. An I slot in the 3rd position of 2nd bundle is 1212;; always dispersed to I1 1213(define_reservation "1b_M" 1214 "1b_0m.ii+1_1+1b_um0|1b_0m.mi+1_1+1b_um0|1b_0mm.i+1_2+(1b_um0|1b_um1)\ 1215 |1b_0m.fi+1_1+1b_um0|1b_0m.mf+1_1+1b_um0|1b_0mm.f+1_2+1b_um1\ 1216 |1b_0m.bb+1_1+1b_um0|1b_0m.ib+1_1+1b_um0|1b_0m.mb+1_1+1b_um0\ 1217 |1b_0mm.b+1_2+1b_um1|1b_0m.fb+1_1+1b_um0|1b_0m.lx+1_1+1b_um0\ 1218 |1b_1mm.i+1_5+1b_um1|1b_1mm.b+1_5+1b_um1\ 1219 |(1b_1m.ii+1_4|1b_1m.mi+1_4|1b_1m.fi+1_4|1b_1m.bb+1_4|1b_1m.ib+1_4\ 1220 |1b_1m.mb+1_4|1b_1m.fb+1_4|1b_1m.lx+1_4)\ 1221 +(1b_um0|1b_um1)") 1222 1223;; Exceptions for dispersal rules. 1224;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1". 1225(define_reservation "1b_I" 1226 "1b_0mi.i+1_2+1b_ui0|1b_0mii.+1_3+(1b_ui0|1b_ui1)|1b_0mmi.+1_3+1b_ui0\ 1227 |1b_0mfi.+1_3+1b_ui0|1b_0mi.b+1_2+1b_ui0\ 1228 |(1b_1mi.i+1_5|1b_1mi.b+1_5)+(1b_ui0|1b_ui1)\ 1229 |1b_1mii.+1_6+1b_ui1|1b_1mmi.+1_6+1b_ui1|1b_1mfi.+1_6+1b_ui1") 1230 1231;; "An F slot in the 1st bundle disperses to F0". 1232;; "An F slot in the 2st bundle disperses to F1". 1233(define_reservation "1b_F" 1234 "1b_0mf.i+1_2+1b_uf0|1b_0mmf.+1_3+1b_uf0|1b_0mf.b+1_2+1b_uf0\ 1235 |1b_1mf.i+1_5+1b_uf1|1b_1mf.b+1_5+1b_uf1") 1236 1237;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 1238;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 1239;;; 2nd position it is dispersed to B2". 1240(define_reservation "1b_NB" 1241 "1b_0b.bb+1_1+1b_unb0|1b_0bb.b+1_2+1b_unb1|1b_0bbb.+1_3+1b_unb2\ 1242 |1b_0mb.b+1_2+1b_unb1|1b_0mbb.+1_3+1b_unb2\ 1243 |1b_0mib.+1_3+1b_unb0|1b_0mmb.+1_3+1b_unb0|1b_0mfb.+1_3+1b_unb0\ 1244 |1b_1b.bb+1_4+1b_unb0|1b_1bb.b+1_5+1b_unb1\ 1245 |1b_1bbb.+1_6+1b_unb2|1b_1mb.b+1_5+1b_unb1|1b_1mbb.+1_6+1b_unb2\ 1246 |1b_1mib.+1_6+1b_unb0|1b_1mmb.+1_6+1b_unb0|1b_1mfb.+1_6+1b_unb0") 1247 1248(define_reservation "1b_B" 1249 "1b_0b.bb+1_1+1b_ub0|1b_0bb.b+1_2+1b_ub1|1b_0bbb.+1_3+1b_ub2\ 1250 |1b_0mb.b+1_2+1b_ub1|1b_0mbb.+1_3+1b_ub2|1b_0mib.+1_3+1b_ub2\ 1251 |1b_0mfb.+1_3+1b_ub2|1b_1b.bb+1_4+1b_ub0|1b_1bb.b+1_5+1b_ub1\ 1252 |1b_1bbb.+1_6+1b_ub2|1b_1mb.b+1_5+1b_ub1\ 1253 |1b_1mib.+1_6+1b_ub2|1b_1mmb.+1_6+1b_ub2|1b_1mfb.+1_6+1b_ub2") 1254 1255(define_reservation "1b_L" "1b_0mlx.+1_3+1b_ui0+1b_uf0\ 1256 |1b_1mlx.+1_6+(1b_ui0|1b_ui1)+1b_uf1") 1257 1258;; We assume that there is no insn issued on the same cycle as unknown insn. 1259(define_cpu_unit "1b_empty" "oneb") 1260(exclusion_set "1b_empty" 1261 "1b_0m.ii,1b_0m.mi,1b_0m.fi,1b_0m.mf,1b_0b.bb,1b_0m.bb,\ 1262 1b_0m.ib,1b_0m.mb,1b_0m.fb,1b_0m.lx") 1263 1264(define_cpu_unit 1265 "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs" 1266 "oneb") 1267(define_cpu_unit 1268 "1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs" 1269 "oneb") 1270 1271(define_cpu_unit "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont, 1b_mb_cont,\ 1272 1b_b_cont, 1b_bb_cont" "oneb") 1273 1274;; For stop in the middle of the bundles. 1275(define_cpu_unit "1b_m_stop, 1b_m0_stop, 1b_m1_stop, 1b_0mmi_cont" "oneb") 1276(define_cpu_unit "1b_mi_stop, 1b_mi0_stop, 1b_mi1_stop, 1b_0mii_cont" "oneb") 1277 1278(final_presence_set "1b_0m_bs" 1279 "1b_0m.ii, 1b_0m.mi, 1b_0m.mf, 1b_0m.fi, 1b_0m.bb,\ 1280 1b_0m.ib, 1b_0m.fb, 1b_0m.mb, 1b_0m.lx") 1281(final_presence_set "1b_1m_bs" 1282 "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1m.bb, 1b_1m.ib, 1b_1m.fb, 1b_1m.mb,\ 1283 1b_1m.lx") 1284(final_presence_set "1b_0mi_bs" "1b_0mi.i, 1b_0mi.i") 1285(final_presence_set "1b_1mi_bs" "1b_1mi.i, 1b_1mi.i") 1286(final_presence_set "1b_0mm_bs" "1b_0mm.i, 1b_0mm.f, 1b_0mm.b") 1287(final_presence_set "1b_1mm_bs" "1b_1mm.i, 1b_1mm.b") 1288(final_presence_set "1b_0mf_bs" "1b_0mf.i, 1b_0mf.b") 1289(final_presence_set "1b_1mf_bs" "1b_1mf.i, 1b_1mf.b") 1290(final_presence_set "1b_0b_bs" "1b_0b.bb") 1291(final_presence_set "1b_1b_bs" "1b_1b.bb") 1292(final_presence_set "1b_0bb_bs" "1b_0bb.b") 1293(final_presence_set "1b_1bb_bs" "1b_1bb.b") 1294(final_presence_set "1b_0mb_bs" "1b_0mb.b") 1295(final_presence_set "1b_1mb_bs" "1b_1mb.b") 1296 1297(exclusion_set "1b_0m_bs" 1298 "1b_0mi.i, 1b_0mm.i, 1b_0mm.f, 1b_0mf.i, 1b_0mb.b,\ 1299 1b_0mi.b, 1b_0mf.b, 1b_0mm.b, 1b_0mlx., 1b_m0_stop") 1300(exclusion_set "1b_1m_bs" 1301 "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1mb.b, 1b_1mi.b, 1b_1mf.b, 1b_1mm.b,\ 1302 1b_1mlx., 1b_m1_stop") 1303(exclusion_set "1b_0mi_bs" "1b_0mii., 1b_0mib., 1b_mi0_stop") 1304(exclusion_set "1b_1mi_bs" "1b_1mii., 1b_1mib., 1b_mi1_stop") 1305(exclusion_set "1b_0mm_bs" "1b_0mmi., 1b_0mmf., 1b_0mmb.") 1306(exclusion_set "1b_1mm_bs" "1b_1mmi., 1b_1mmb.") 1307(exclusion_set "1b_0mf_bs" "1b_0mfi., 1b_0mfb.") 1308(exclusion_set "1b_1mf_bs" "1b_1mfi., 1b_1mfb.") 1309(exclusion_set "1b_0b_bs" "1b_0bb.b") 1310(exclusion_set "1b_1b_bs" "1b_1bb.b") 1311(exclusion_set "1b_0bb_bs" "1b_0bbb.") 1312(exclusion_set "1b_1bb_bs" "1b_1bbb.") 1313(exclusion_set "1b_0mb_bs" "1b_0mbb.") 1314(exclusion_set "1b_1mb_bs" "1b_1mbb.") 1315 1316(exclusion_set 1317 "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs, 1318 1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs" 1319 "1b_stop") 1320 1321(final_presence_set 1322 "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0mb.b,\ 1323 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx." 1324 "1b_m_cont") 1325(final_presence_set "1b_0mii., 1b_0mib." "1b_mi_cont") 1326(final_presence_set "1b_0mmi., 1b_0mmf., 1b_0mmb." "1b_mm_cont") 1327(final_presence_set "1b_0mfi., 1b_0mfb." "1b_mf_cont") 1328(final_presence_set "1b_0bb.b" "1b_b_cont") 1329(final_presence_set "1b_0bbb." "1b_bb_cont") 1330(final_presence_set "1b_0mbb." "1b_mb_cont") 1331 1332(exclusion_set 1333 "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1334 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx" 1335 "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont,\ 1336 1b_mb_cont, 1b_b_cont, 1b_bb_cont") 1337 1338(exclusion_set "1b_empty" 1339 "1b_m_cont,1b_mi_cont,1b_mm_cont,1b_mf_cont,\ 1340 1b_mb_cont,1b_b_cont,1b_bb_cont") 1341 1342;; For m;mi bundle 1343(final_presence_set "1b_m0_stop" "1b_0m.mi") 1344(final_presence_set "1b_0mm.i" "1b_0mmi_cont") 1345(exclusion_set "1b_0mmi_cont" 1346 "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1347 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1348(exclusion_set "1b_m0_stop" "1b_0mm.i") 1349(final_presence_set "1b_m1_stop" "1b_1m.mi") 1350(exclusion_set "1b_m1_stop" "1b_1mm.i") 1351(final_presence_set "1b_m_stop" "1b_m0_stop, 1b_m1_stop") 1352 1353;; For mi;i bundle 1354(final_presence_set "1b_mi0_stop" "1b_0mi.i") 1355(final_presence_set "1b_0mii." "1b_0mii_cont") 1356(exclusion_set "1b_0mii_cont" 1357 "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1358 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1359(exclusion_set "1b_mi0_stop" "1b_0mii.") 1360(final_presence_set "1b_mi1_stop" "1b_1mi.i") 1361(exclusion_set "1b_mi1_stop" "1b_1mii.") 1362(final_presence_set "1b_mi_stop" "1b_mi0_stop, 1b_mi1_stop") 1363 1364(final_absence_set 1365 "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\ 1366 1b_0m.fi,1b_0mf.i,1b_0mfi.,1b_0m.mf,1b_0mm.f,1b_0mmf.,\ 1367 1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb.,\ 1368 1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\ 1369 1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \ 1370 1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\ 1371 1b_1m.fi,1b_1mf.i,1b_1mfi.,\ 1372 1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\ 1373 1b_1m.ib,1b_1mi.b,1b_1mib.,1b_1m.mb,1b_1mm.b,1b_1mmb.,\ 1374 1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx." 1375 "1b_m0_stop,1b_m1_stop,1b_mi0_stop,1b_mi1_stop") 1376 1377(define_reservation "1b_A" "1b_M|1b_I") 1378 1379(define_insn_reservation "1b_stop_bit" 0 1380 (and (and (eq_attr "cpu" "itanium") 1381 (eq_attr "itanium_class" "stop_bit")) 1382 (ne (symbol_ref "bundling_p") (const_int 0))) 1383 "1b_stop|1b_m0_stop|1b_m1_stop|1b_mi0_stop|1b_mi1_stop") 1384(define_insn_reservation "1b_br" 0 1385 (and (and (eq_attr "cpu" "itanium") 1386 (eq_attr "itanium_class" "br")) 1387 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B") 1388(define_insn_reservation "1b_scall" 0 1389 (and (and (eq_attr "cpu" "itanium") 1390 (eq_attr "itanium_class" "scall")) 1391 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B") 1392(define_insn_reservation "1b_fcmp" 2 1393 (and (and (eq_attr "cpu" "itanium") 1394 (eq_attr "itanium_class" "fcmp")) 1395 (ne (symbol_ref "bundling_p") (const_int 0))) 1396 "1b_F+1b_not_uf1") 1397(define_insn_reservation "1b_fcvtfx" 7 1398 (and (and (eq_attr "cpu" "itanium") 1399 (eq_attr "itanium_class" "fcvtfx")) 1400 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1401(define_insn_reservation "1b_fld" 9 1402 (and (and (eq_attr "cpu" "itanium") 1403 (eq_attr "itanium_class" "fld")) 1404 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1405(define_insn_reservation "1b_fmac" 5 1406 (and (and (eq_attr "cpu" "itanium") 1407 (eq_attr "itanium_class" "fmac")) 1408 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1409(define_insn_reservation "1b_fmisc" 5 1410 (and (and (eq_attr "cpu" "itanium") 1411 (eq_attr "itanium_class" "fmisc")) 1412 (ne (symbol_ref "bundling_p") (const_int 0))) 1413 "1b_F+1b_not_uf1") 1414(define_insn_reservation "1b_frar_i" 13 1415 (and (and (eq_attr "cpu" "itanium") 1416 (eq_attr "itanium_class" "frar_i")) 1417 (ne (symbol_ref "bundling_p") (const_int 0))) 1418 "1b_I+1b_not_ui1") 1419(define_insn_reservation "1b_frar_m" 6 1420 (and (and (eq_attr "cpu" "itanium") 1421 (eq_attr "itanium_class" "frar_m")) 1422 (ne (symbol_ref "bundling_p") (const_int 0))) 1423 "1b_M+1b_not_um1") 1424(define_insn_reservation "1b_frbr" 2 1425 (and (and (eq_attr "cpu" "itanium") 1426 (eq_attr "itanium_class" "frbr")) 1427 (ne (symbol_ref "bundling_p") (const_int 0))) 1428 "1b_I+1b_not_ui1") 1429(define_insn_reservation "1b_frfr" 2 1430 (and (and (eq_attr "cpu" "itanium") 1431 (eq_attr "itanium_class" "frfr")) 1432 (ne (symbol_ref "bundling_p") (const_int 0))) 1433 "1b_M+1b_not_um1") 1434(define_insn_reservation "1b_frpr" 2 1435 (and (and (eq_attr "cpu" "itanium") 1436 (eq_attr "itanium_class" "frpr")) 1437 (ne (symbol_ref "bundling_p") (const_int 0))) 1438 "1b_I+1b_not_ui1") 1439(define_insn_reservation "1b_ialu" 1 1440 (and (and (eq_attr "cpu" "itanium") 1441 (eq_attr "itanium_class" "ialu")) 1442 (ne (symbol_ref 1443 "bundling_p && !ia64_produce_address_p (insn)") 1444 (const_int 0))) 1445 "1b_A") 1446(define_insn_reservation "1b_ialu_addr" 1 1447 (and (and (eq_attr "cpu" "itanium") 1448 (eq_attr "itanium_class" "ialu")) 1449 (eq (symbol_ref 1450 "bundling_p && ia64_produce_address_p (insn)") 1451 (const_int 1))) 1452 "1b_M") 1453(define_insn_reservation "1b_icmp" 1 1454 (and (and (eq_attr "cpu" "itanium") 1455 (eq_attr "itanium_class" "icmp")) 1456 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1457(define_insn_reservation "1b_ilog" 1 1458 (and (and (eq_attr "cpu" "itanium") 1459 (eq_attr "itanium_class" "ilog")) 1460 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1461(define_insn_reservation "1b_ishf" 1 1462 (and (and (eq_attr "cpu" "itanium") 1463 (eq_attr "itanium_class" "ishf")) 1464 (ne (symbol_ref "bundling_p") (const_int 0))) 1465 "1b_I+1b_not_ui1") 1466(define_insn_reservation "1b_ld" 2 1467 (and (and (eq_attr "cpu" "itanium") 1468 (eq_attr "itanium_class" "ld")) 1469 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1470(define_insn_reservation "1b_long_i" 1 1471 (and (and (eq_attr "cpu" "itanium") 1472 (eq_attr "itanium_class" "long_i")) 1473 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L") 1474(define_insn_reservation "1b_mmmul" 2 1475 (and (and (eq_attr "cpu" "itanium") 1476 (eq_attr "itanium_class" "mmmul")) 1477 (ne (symbol_ref "bundling_p") (const_int 0))) 1478 "1b_I+1b_not_ui1") 1479(define_insn_reservation "1b_mmshf" 2 1480 (and (and (eq_attr "cpu" "itanium") 1481 (eq_attr "itanium_class" "mmshf")) 1482 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1483(define_insn_reservation "1b_mmshfi" 2 1484 (and (and (eq_attr "cpu" "itanium") 1485 (eq_attr "itanium_class" "mmshfi")) 1486 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1487(define_insn_reservation "1b_rse_m" 0 1488 (and (and (eq_attr "cpu" "itanium") 1489 (eq_attr "itanium_class" "rse_m")) 1490 (ne (symbol_ref "bundling_p") (const_int 0))) 1491 "(1b_0m.ii|1b_0m.mi|1b_0m.fi|1b_0m.mf|1b_0b.bb|1b_0m.bb\ 1492 |1b_0m.ib|1b_0m.mb|1b_0m.fb|1b_0m.lx)+1_1+1b_um0") 1493(define_insn_reservation "1b_sem" 0 1494 (and (and (eq_attr "cpu" "itanium") 1495 (eq_attr "itanium_class" "sem")) 1496 (ne (symbol_ref "bundling_p") (const_int 0))) 1497 "1b_M+1b_not_um1") 1498(define_insn_reservation "1b_stf" 1 1499 (and (and (eq_attr "cpu" "itanium") 1500 (eq_attr "itanium_class" "stf")) 1501 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1502(define_insn_reservation "1b_st" 1 1503 (and (and (eq_attr "cpu" "itanium") 1504 (eq_attr "itanium_class" "st")) 1505 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1506(define_insn_reservation "1b_syst_m0" 0 1507 (and (and (eq_attr "cpu" "itanium") 1508 (eq_attr "itanium_class" "syst_m0")) 1509 (ne (symbol_ref "bundling_p") (const_int 0))) 1510 "1b_M+1b_not_um1") 1511(define_insn_reservation "1b_syst_m" 0 1512 (and (and (eq_attr "cpu" "itanium") 1513 (eq_attr "itanium_class" "syst_m")) 1514 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1515(define_insn_reservation "1b_tbit" 1 1516 (and (and (eq_attr "cpu" "itanium") 1517 (eq_attr "itanium_class" "tbit")) 1518 (ne (symbol_ref "bundling_p") (const_int 0))) 1519 "1b_I+1b_not_ui1") 1520(define_insn_reservation "1b_toar_i" 0 1521 (and (and (eq_attr "cpu" "itanium") 1522 (eq_attr "itanium_class" "toar_i")) 1523 (ne (symbol_ref "bundling_p") (const_int 0))) 1524 "1b_I+1b_not_ui1") 1525(define_insn_reservation "1b_toar_m" 5 1526 (and (and (eq_attr "cpu" "itanium") 1527 (eq_attr "itanium_class" "toar_m")) 1528 (ne (symbol_ref "bundling_p") (const_int 0))) 1529 "1b_M+1b_not_um1") 1530(define_insn_reservation "1b_tobr" 1 1531 (and (and (eq_attr "cpu" "itanium") 1532 (eq_attr "itanium_class" "tobr")) 1533 (ne (symbol_ref "bundling_p") (const_int 0))) 1534 "1b_I+1b_not_ui1") 1535(define_insn_reservation "1b_tofr" 9 1536 (and (and (eq_attr "cpu" "itanium") 1537 (eq_attr "itanium_class" "tofr")) 1538 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1539(define_insn_reservation "1b_topr" 1 1540 (and (and (eq_attr "cpu" "itanium") 1541 (eq_attr "itanium_class" "topr")) 1542 (ne (symbol_ref "bundling_p") (const_int 0))) 1543 "1b_I+1b_not_ui1") 1544(define_insn_reservation "1b_xmpy" 7 1545 (and (and (eq_attr "cpu" "itanium") 1546 (eq_attr "itanium_class" "xmpy")) 1547 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1548(define_insn_reservation "1b_xtd" 1 1549 (and (and (eq_attr "cpu" "itanium") 1550 (eq_attr "itanium_class" "xtd")) 1551 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1552(define_insn_reservation "1b_chk_s" 0 1553 (and (and (eq_attr "cpu" "itanium") 1554 (eq_attr "itanium_class" "chk_s")) 1555 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1556(define_insn_reservation "1b_lfetch" 0 1557 (and (and (eq_attr "cpu" "itanium") 1558 (eq_attr "itanium_class" "lfetch")) 1559 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1560(define_insn_reservation "1b_nop_m" 0 1561 (and (and (eq_attr "cpu" "itanium") 1562 (eq_attr "itanium_class" "nop_m")) 1563 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1564(define_insn_reservation "1b_nop_b" 0 1565 (and (and (eq_attr "cpu" "itanium") 1566 (eq_attr "itanium_class" "nop_b")) 1567 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_NB") 1568(define_insn_reservation "1b_nop_i" 0 1569 (and (and (eq_attr "cpu" "itanium") 1570 (eq_attr "itanium_class" "nop_i")) 1571 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1572(define_insn_reservation "1b_nop_f" 0 1573 (and (and (eq_attr "cpu" "itanium") 1574 (eq_attr "itanium_class" "nop_f")) 1575 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1576(define_insn_reservation "1b_nop_x" 0 1577 (and (and (eq_attr "cpu" "itanium") 1578 (eq_attr "itanium_class" "nop_x")) 1579 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L") 1580(define_insn_reservation "1b_unknown" 1 1581 (and (and (eq_attr "cpu" "itanium") 1582 (eq_attr "itanium_class" "unknown")) 1583 (ne (symbol_ref "bundling_p") (const_int 0))) 1584 "1b_empty") 1585(define_insn_reservation "1b_nop" 1 1586 (and (and (eq_attr "cpu" "itanium") 1587 (eq_attr "itanium_class" "nop")) 1588 (ne (symbol_ref "bundling_p") (const_int 0))) 1589 "1b_M|1b_NB|1b_I|1b_F") 1590(define_insn_reservation "1b_ignore" 0 1591 (and (and (eq_attr "cpu" "itanium") 1592 (eq_attr "itanium_class" "ignore")) 1593 (ne (symbol_ref "bundling_p") (const_int 0))) 1594 "nothing") 1595 1596(define_insn_reservation "1b_pre_cycle" 0 1597 (and (and (eq_attr "cpu" "itanium") 1598 (eq_attr "itanium_class" "pre_cycle")) 1599 (ne (symbol_ref "bundling_p") (const_int 0))) 1600 "(1b_0m_bs, 1b_m_cont) \ 1601 | (1b_0mi_bs, 1b_mi_cont) \ 1602 | (1b_0mm_bs, 1b_mm_cont) \ 1603 | (1b_0mf_bs, 1b_mf_cont) \ 1604 | (1b_0b_bs, 1b_b_cont) \ 1605 | (1b_0bb_bs, 1b_bb_cont) \ 1606 | (1b_0mb_bs, 1b_mb_cont) \ 1607 | (1b_1m_bs, 1b_m_cont) \ 1608 | (1b_1mi_bs, 1b_mi_cont) \ 1609 | (1b_1mm_bs, 1b_mm_cont) \ 1610 | (1b_1mf_bs, 1b_mf_cont) \ 1611 | (1b_1b_bs, 1b_b_cont) \ 1612 | (1b_1bb_bs, 1b_bb_cont) \ 1613 | (1b_1mb_bs, 1b_mb_cont) \ 1614 | (1b_m_stop, 1b_0mmi_cont) \ 1615 | (1b_mi_stop, 1b_0mii_cont)") 1616 1617