s390-opc.c revision 99461
1104349Sphk/* s390-opc.c -- S390 opcode list 2178848Scokane Copyright 2000, 2001 Free Software Foundation, Inc. 3178848Scokane Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). 4178848Scokane 5178848Scokane This file is part of GDB, GAS, and the GNU binutils. 6104349Sphk 7104349Sphk This program is free software; you can redistribute it and/or modify 8178848Scokane it under the terms of the GNU General Public License as published by 9178848Scokane the Free Software Foundation; either version 2 of the License, or 10178848Scokane (at your option) any later version. 11178848Scokane 12178848Scokane This program is distributed in the hope that it will be useful, 13178848Scokane but WITHOUT ANY WARRANTY; without even the implied warranty of 14178848Scokane MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15178848Scokane GNU General Public License for more details. 16178848Scokane 17178848Scokane You should have received a copy of the GNU General Public License 18178848Scokane along with this program; if not, write to the Free Software 19178848Scokane Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 20178848Scokane 02111-1307, USA. */ 21178848Scokane 22178848Scokane#include <stdio.h> 23178848Scokane#include "ansidecl.h" 24178848Scokane#include "opcode/s390.h" 25178848Scokane 26178848Scokane/* This file holds the S390 opcode table. The opcode table 27178848Scokane includes almost all of the extended instruction mnemonics. This 28178848Scokane permits the disassembler to use them, and simplifies the assembler 29178848Scokane logic, at the cost of increasing the table size. The table is 30178848Scokane strictly constant data, so the compiler should be able to put it in 31178848Scokane the .text section. 32178848Scokane 33178848Scokane This file also holds the operand table. All knowledge about 34178848Scokane inserting operands into instructions and vice-versa is kept in this 35178848Scokane file. */ 36178848Scokane 37104349Sphk/* The operands table. 38104349Sphk The fields are bits, shift, insert, extract, flags. */ 39104349Sphk 40104349Sphkconst struct s390_operand s390_operands[] = 41104349Sphk{ 42104349Sphk#define UNUSED 0 43104349Sphk { 0, 0, 0 }, /* Indicates the end of the operand list */ 44104349Sphk 45104349Sphk#define R_8 1 /* GPR starting at position 8 */ 46104349Sphk { 4, 8, S390_OPERAND_GPR }, 47104349Sphk#define R_12 2 /* GPR starting at position 12 */ 48104349Sphk { 4, 12, S390_OPERAND_GPR }, 49104349Sphk#define R_16 3 /* GPR starting at position 16 */ 50104349Sphk { 4, 16, S390_OPERAND_GPR }, 51104349Sphk#define R_20 4 /* GPR starting at position 20 */ 52178848Scokane { 4, 20, S390_OPERAND_GPR }, 53178848Scokane#define R_24 5 /* GPR starting at position 24 */ 54178848Scokane { 4, 24, S390_OPERAND_GPR }, 55178848Scokane#define R_28 6 /* GPR starting at position 28 */ 56178848Scokane { 4, 28, S390_OPERAND_GPR }, 57178848Scokane#define R_32 7 /* GPR starting at position 32 */ 58178848Scokane { 4, 32, S390_OPERAND_GPR }, 59178848Scokane 60178848Scokane#define F_8 8 /* FPR starting at position 8 */ 61178848Scokane { 4, 8, S390_OPERAND_FPR }, 62178848Scokane#define F_12 9 /* FPR starting at position 12 */ 63104349Sphk { 4, 12, S390_OPERAND_FPR }, 64104349Sphk#define F_16 10 /* FPR starting at position 16 */ 65104349Sphk { 4, 16, S390_OPERAND_FPR }, 66104349Sphk#define F_20 11 /* FPR starting at position 16 */ 67104349Sphk { 4, 16, S390_OPERAND_FPR }, 68104349Sphk#define F_24 12 /* FPR starting at position 24 */ 69104349Sphk { 4, 24, S390_OPERAND_FPR }, 70104349Sphk#define F_28 13 /* FPR starting at position 28 */ 71104349Sphk { 4, 28, S390_OPERAND_FPR }, 72104349Sphk#define F_32 14 /* FPR starting at position 32 */ 73104349Sphk { 4, 32, S390_OPERAND_FPR }, 74104349Sphk 75104349Sphk#define A_8 15 /* Access reg. starting at position 8 */ 76104349Sphk { 4, 8, S390_OPERAND_AR }, 77104349Sphk#define A_12 16 /* Access reg. starting at position 12 */ 78104349Sphk { 4, 12, S390_OPERAND_AR }, 79104349Sphk#define A_24 17 /* Access reg. starting at position 24 */ 80104349Sphk { 4, 24, S390_OPERAND_AR }, 81104349Sphk#define A_28 18 /* Access reg. starting at position 28 */ 82104349Sphk { 4, 28, S390_OPERAND_AR }, 83104349Sphk 84104349Sphk#define C_8 19 /* Control reg. starting at position 8 */ 85104349Sphk { 4, 8, S390_OPERAND_CR }, 86104349Sphk#define C_12 20 /* Control reg. starting at position 12 */ 87104349Sphk { 4, 12, S390_OPERAND_CR }, 88104349Sphk 89104349Sphk#define B_16 21 /* Base register starting at position 16 */ 90104349Sphk { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, 91104349Sphk#define B_32 22 /* Base register starting at position 32 */ 92104349Sphk { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, 93104349Sphk 94104349Sphk#define X_12 23 /* Index register starting at position 12 */ 95178848Scokane { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, 96178848Scokane 97178848Scokane#define D_20 24 /* Displacement starting at position 20 */ 98178848Scokane { 12, 20, S390_OPERAND_DISP }, 99178848Scokane#define D_36 25 /* Displacement starting at position 36 */ 100178848Scokane { 12, 36, S390_OPERAND_DISP }, 101178848Scokane 102#define L4_8 26 /* 4 bit length starting at position 8 */ 103 { 4, 8, S390_OPERAND_LENGTH }, 104#define L4_12 27 /* 4 bit length starting at position 12 */ 105 { 4, 12, S390_OPERAND_LENGTH }, 106#define L8_8 28 /* 8 bit length starting at position 8 */ 107 { 8, 8, S390_OPERAND_LENGTH }, 108 109#define U4_8 29 /* 4 bit unsigned value starting at 8 */ 110 { 4, 8, 0 }, 111#define U4_12 30 /* 4 bit unsigned value starting at 12 */ 112 { 4, 12, 0 }, 113#define U4_16 31 /* 4 bit unsigned value starting at 16 */ 114 { 4, 16, 0 }, 115#define U4_20 32 /* 4 bit unsigned value starting at 20 */ 116 { 4, 20, 0 }, 117#define U8_8 33 /* 8 bit unsigned value starting at 8 */ 118 { 8, 8, 0 }, 119#define U8_16 34 /* 8 bit unsigned value starting at 16 */ 120 { 8, 16, 0 }, 121#define I16_16 35 /* 16 bit signed value starting at 16 */ 122 { 16, 16, S390_OPERAND_SIGNED }, 123#define U16_16 36 /* 16 bit unsigned value starting at 16 */ 124 { 16, 16, 0 }, 125#define J16_16 37 /* PC relative jump offset at 16 */ 126 { 16, 16, S390_OPERAND_PCREL }, 127#define J32_16 38 /* PC relative long offset at 16 */ 128 { 32, 16, S390_OPERAND_PCREL } 129}; 130 131 132/* Macros used to form opcodes. */ 133 134/* 8/16/48 bit opcodes. */ 135#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } 136#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } 137#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ 138 (x >> 16) & 255, (x >> 8) & 255, x & 255} 139 140/* The new format of the INSTR_x_y and MASK_x_y defines is based 141 on the following rules: 142 1) the middle part of the definition (x in INSTR_x_y) is the official 143 names of the instruction format that you can find in the principals 144 of operation. 145 2) the last part of the definition (y in INSTR_x_y) gives you an idea 146 which operands the binary represenation of the instruction has. 147 The meanings of the letters in y are: 148 a - access register 149 c - control register 150 d - displacement, 12 bit 151 f - floating pointer register 152 i - signed integer, 4 or 8 bit 153 l - length, 4 or 8 bit 154 p - pc relative 155 r - general purpose register 156 u - unsigned integer, 4 or 8 bit 157 0 - operand skipped. 158 The order of the letters reflects the layout of the format in 159 storage and not the order of the paramaters of the instructions. 160 The use of the letters is not a 100% match with the PoP but it is 161 quite close. 162 163 For example the instruction "mvo" is defined in the PoP as follows: 164 165 MVO D1(L1,B1),D2(L2,B2) [SS] 166 167 -------------------------------------- 168 | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | 169 -------------------------------------- 170 0 8 12 16 20 32 36 171 172 The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ 173 174#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ 175#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ 176#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ 177#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ 178#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ 179#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ 180#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ 181#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ 182#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ 183#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ 184#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ 185#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ 186#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ 187#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ 188#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ 189#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ 190#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ 191#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ 192#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ 193#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ 194#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ 195#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 196#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 197#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */ 198#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */ 199#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */ 200#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ 201#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ 202#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ 203#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ 204#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ 205#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ 206#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 207#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 208#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ 209#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ 210#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ 211#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ 212#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ 213#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ 214#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ 215#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ 216#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ 217#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ 218#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ 219#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ 220#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ 221#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ 222#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ 223#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ 224#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ 225#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ 226#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ 227#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ 228#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ 229#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ 230#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ 231#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ 232 233#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 234#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 235#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 236#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 237#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 238#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 239#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 240#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 241#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 242#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 243#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } 244#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } 245#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 246#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 247#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } 248#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 249#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } 250#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 251#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 252#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 253#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 254#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 255#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 256#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 257#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 258#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 259#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } 260#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 261#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 262#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 263#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 264#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 265#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 266#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 267#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 268#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 269#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 270#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 271#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 272#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 273#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 274#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 275#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 276#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 277#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } 278#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 279#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 280#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 281#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 282#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 283#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 284#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 285#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 286#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 287#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 288#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 289#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } 290#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 291 292/* The opcode formats table (blueprints for .insn pseudo mnemonic). */ 293 294const struct s390_opcode s390_opformats[] = 295 { 296 { "e", OP8(0x00LL), MASK_E, INSTR_E, 3 }, 297 { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3 }, 298 { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3 }, 299 { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3 }, 300 { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3 }, 301 { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3 }, 302 { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3 }, 303 { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3 }, 304 { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3 }, 305 { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3 }, 306 { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3 }, 307 { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3 }, 308 { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3 }, 309 { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3 }, 310 { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3 }, 311 { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3 }, 312 { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3 }, 313}; 314 315const int s390_num_opformats = 316 sizeof (s390_opformats) / sizeof (s390_opformats[0]); 317 318#include "s390-opc.tab" 319