1214571Sdim/* CPU data header for mep. 2214571Sdim 3214571SdimTHIS FILE IS MACHINE GENERATED WITH CGEN. 4214571Sdim 5214571SdimCopyright 1996-2005 Free Software Foundation, Inc. 6214571Sdim 7214571SdimThis file is part of the GNU Binutils and/or GDB, the GNU debugger. 8214571Sdim 9214571SdimThis program is free software; you can redistribute it and/or modify 10214571Sdimit under the terms of the GNU General Public License as published by 11214571Sdimthe Free Software Foundation; either version 2, or (at your option) 12214571Sdimany later version. 13214571Sdim 14214571SdimThis program is distributed in the hope that it will be useful, 15214571Sdimbut WITHOUT ANY WARRANTY; without even the implied warranty of 16214571SdimMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17214571SdimGNU General Public License for more details. 18214571Sdim 19214571SdimYou should have received a copy of the GNU General Public License along 20214571Sdimwith this program; if not, write to the Free Software Foundation, Inc., 21214571Sdim51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22214571Sdim 23214571Sdim*/ 24214571Sdim 25214571Sdim#ifndef MEP_CPU_H 26214571Sdim#define MEP_CPU_H 27214571Sdim 28214571Sdim#include "opcode/cgen-bitset.h" 29214571Sdim 30214571Sdim#define CGEN_ARCH mep 31214571Sdim 32214571Sdim/* Given symbol S, return mep_cgen_<S>. */ 33214571Sdim#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 34214571Sdim#define CGEN_SYM(s) mep##_cgen_##s 35214571Sdim#else 36214571Sdim#define CGEN_SYM(s) mep/**/_cgen_/**/s 37214571Sdim#endif 38214571Sdim 39214571Sdim 40214571Sdim/* Selected cpu families. */ 41214571Sdim#define HAVE_CPU_MEPF 42214571Sdim 43214571Sdim#define CGEN_INSN_LSB0_P 0 44214571Sdim 45214571Sdim/* Minimum size of any insn (in bytes). */ 46214571Sdim#define CGEN_MIN_INSN_SIZE 2 47214571Sdim 48214571Sdim/* Maximum size of any insn (in bytes). */ 49214571Sdim#define CGEN_MAX_INSN_SIZE 4 50214571Sdim 51214571Sdim#define CGEN_INT_INSN_P 1 52214571Sdim 53214571Sdim/* Maximum number of syntax elements in an instruction. */ 54214571Sdim#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17 55214571Sdim 56214571Sdim/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 57214571Sdim e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 58214571Sdim we can't hash on everything up to the space. */ 59214571Sdim#define CGEN_MNEMONIC_OPERANDS 60214571Sdim 61214571Sdim/* Maximum number of fields in an instruction. */ 62214571Sdim#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 11 63214571Sdim 64214571Sdim/* Enums. */ 65214571Sdim 66214571Sdim/* Enum declaration for major opcodes. */ 67214571Sdimtypedef enum major { 68214571Sdim MAJ_0, MAJ_1, MAJ_2, MAJ_3 69214571Sdim , MAJ_4, MAJ_5, MAJ_6, MAJ_7 70214571Sdim , MAJ_8, MAJ_9, MAJ_10, MAJ_11 71214571Sdim , MAJ_12, MAJ_13, MAJ_14, MAJ_15 72214571Sdim} MAJOR; 73214571Sdim 74214571Sdim/* Enum declaration for condition opcode enum. */ 75214571Sdimtypedef enum fmax_cond { 76214571Sdim FMAX_F, FMAX_U, FMAX_E, FMAX_UE 77214571Sdim , FMAX_L, FMAX_UL, FMAX_LE, FMAX_ULE 78214571Sdim , FMAX_FI, FMAX_UI, FMAX_EI, FMAX_UEI 79214571Sdim , FMAX_LI, FMAX_ULI, FMAX_LEI, FMAX_ULEI 80214571Sdim} FMAX_COND; 81214571Sdim 82214571Sdim/* Attributes. */ 83214571Sdim 84214571Sdim/* Enum declaration for machine type selection. */ 85214571Sdimtypedef enum mach_attr { 86214571Sdim MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX 87214571Sdim} MACH_ATTR; 88214571Sdim 89214571Sdim/* Enum declaration for instruction set selection. */ 90214571Sdimtypedef enum isa_attr { 91214571Sdim ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2, ISA_EXT_COP2_16 92214571Sdim , ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64, ISA_MAX 93214571Sdim} ISA_ATTR; 94214571Sdim 95214571Sdim/* Enum declaration for datatype to use for C intrinsics mapping. */ 96214571Sdimtypedef enum cdata_attr { 97214571Sdim CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT 98214571Sdim , CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT 99214571Sdim , CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT 100214571Sdim} CDATA_ATTR; 101214571Sdim 102214571Sdim/* Enum declaration for . */ 103214571Sdimtypedef enum config_attr { 104214571Sdim CONFIG_NONE, CONFIG_SIMPLE, CONFIG_FMAX 105214571Sdim} CONFIG_ATTR; 106214571Sdim 107214571Sdim/* Number of architecture variants. */ 108214571Sdim#define MAX_ISAS ((int) ISA_MAX) 109214571Sdim#define MAX_MACHS ((int) MACH_MAX) 110214571Sdim 111214571Sdim/* Ifield support. */ 112214571Sdim 113214571Sdim/* Ifield attribute indices. */ 114214571Sdim 115214571Sdim/* Enum declaration for cgen_ifld attrs. */ 116214571Sdimtypedef enum cgen_ifld_attr { 117214571Sdim CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 118214571Sdim , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 119214571Sdim , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS 120214571Sdim} CGEN_IFLD_ATTR; 121214571Sdim 122214571Sdim/* Number of non-boolean elements in cgen_ifld_attr. */ 123214571Sdim#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 124214571Sdim 125214571Sdim/* cgen_ifld attribute accessor macros. */ 126214571Sdim#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 127214571Sdim#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) 128214571Sdim#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) 129214571Sdim#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 130214571Sdim#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 131214571Sdim#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) 132214571Sdim#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 133214571Sdim#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) 134214571Sdim 135214571Sdim/* Enum declaration for mep ifield types. */ 136214571Sdimtypedef enum ifield_type { 137214571Sdim MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN 138214571Sdim , MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2 139214571Sdim , MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN 140214571Sdim , MEP_F_CSRN_HI, MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI 141214571Sdim , MEP_F_CRNX_LO, MEP_F_CRNX, MEP_F_0, MEP_F_1 142214571Sdim , MEP_F_2, MEP_F_3, MEP_F_4, MEP_F_5 143214571Sdim , MEP_F_6, MEP_F_7, MEP_F_8, MEP_F_9 144214571Sdim , MEP_F_10, MEP_F_11, MEP_F_12, MEP_F_13 145214571Sdim , MEP_F_14, MEP_F_15, MEP_F_16, MEP_F_17 146214571Sdim , MEP_F_18, MEP_F_19, MEP_F_20, MEP_F_21 147214571Sdim , MEP_F_22, MEP_F_23, MEP_F_24, MEP_F_25 148214571Sdim , MEP_F_26, MEP_F_27, MEP_F_28, MEP_F_29 149214571Sdim , MEP_F_30, MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2 150214571Sdim , MEP_F_17S16A2, MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N 151214571Sdim , MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6 152214571Sdim , MEP_F_7U9, MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16 153214571Sdim , MEP_F_2U10, MEP_F_3U5, MEP_F_4U8, MEP_F_5U8 154214571Sdim , MEP_F_5U24, MEP_F_6S8, MEP_F_8S8, MEP_F_16U16 155214571Sdim , MEP_F_12U16, MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2 156214571Sdim , MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO 157214571Sdim , MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N 158214571Sdim , MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM 159214571Sdim , MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_FMAX_0_4 160214571Sdim , MEP_F_FMAX_4_4, MEP_F_FMAX_8_4, MEP_F_FMAX_12_4, MEP_F_FMAX_16_4 161214571Sdim , MEP_F_FMAX_20_4, MEP_F_FMAX_24_4, MEP_F_FMAX_28_1, MEP_F_FMAX_29_1 162214571Sdim , MEP_F_FMAX_30_1, MEP_F_FMAX_31_1, MEP_F_FMAX_FRD, MEP_F_FMAX_FRN 163214571Sdim , MEP_F_FMAX_FRM, MEP_F_FMAX_RM, MEP_F_MAX 164214571Sdim} IFIELD_TYPE; 165214571Sdim 166214571Sdim#define MAX_IFLD ((int) MEP_F_MAX) 167214571Sdim 168214571Sdim/* Hardware attribute indices. */ 169214571Sdim 170214571Sdim/* Enum declaration for cgen_hw attrs. */ 171214571Sdimtypedef enum cgen_hw_attr { 172214571Sdim CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 173214571Sdim , CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH 174214571Sdim , CGEN_HW_ISA, CGEN_HW_END_NBOOLS 175214571Sdim} CGEN_HW_ATTR; 176214571Sdim 177214571Sdim/* Number of non-boolean elements in cgen_hw_attr. */ 178214571Sdim#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 179214571Sdim 180214571Sdim/* cgen_hw attribute accessor macros. */ 181214571Sdim#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 182214571Sdim#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) 183214571Sdim#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) 184214571Sdim#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) 185214571Sdim#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) 186214571Sdim#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) 187214571Sdim#define CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_IS_FLOAT)) != 0) 188214571Sdim 189214571Sdim/* Enum declaration for mep hardware types. */ 190214571Sdimtypedef enum cgen_hw_type { 191214571Sdim HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 192214571Sdim , HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR 193214571Sdim , HW_H_CR64, HW_H_CR, HW_H_CCR, HW_H_CR_FMAX 194214571Sdim , HW_H_CCR_FMAX, HW_H_FMAX_COMPARE_I_P, HW_MAX 195214571Sdim} CGEN_HW_TYPE; 196214571Sdim 197214571Sdim#define MAX_HW ((int) HW_MAX) 198214571Sdim 199214571Sdim/* Operand attribute indices. */ 200214571Sdim 201214571Sdim/* Enum declaration for cgen_operand attrs. */ 202214571Sdimtypedef enum cgen_operand_attr { 203214571Sdim CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 204214571Sdim , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 205214571Sdim , CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH 206214571Sdim , CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA, CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS 207214571Sdim} CGEN_OPERAND_ATTR; 208214571Sdim 209214571Sdim/* Number of non-boolean elements in cgen_operand_attr. */ 210214571Sdim#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 211214571Sdim 212214571Sdim/* cgen_operand attribute accessor macros. */ 213214571Sdim#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 214214571Sdim#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) 215214571Sdim#define CGEN_ATTR_CGEN_OPERAND_CDATA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_CDATA-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 216214571Sdim#define CGEN_ATTR_CGEN_OPERAND_ALIGN_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ALIGN-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 217214571Sdim#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 218214571Sdim#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 219214571Sdim#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 220214571Sdim#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 221214571Sdim#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) 222214571Sdim#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 223214571Sdim#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) 224214571Sdim#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 225214571Sdim#define CGEN_ATTR_CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW)) != 0) 226214571Sdim 227214571Sdim/* Enum declaration for mep operand types. */ 228214571Sdimtypedef enum cgen_operand_type { 229214571Sdim MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM 230214571Sdim , MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC 231214571Sdim , MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL 232214571Sdim , MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S 233214571Sdim , MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP 234214571Sdim , MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0 235214571Sdim , MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW 236214571Sdim , MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG 237214571Sdim , MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP 238214571Sdim , MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN 239214571Sdim , MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64 240214571Sdim , MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2 241214571Sdim , MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2 242214571Sdim , MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16 243214571Sdim , MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8 244214571Sdim , MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3 245214571Sdim , MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2 246214571Sdim , MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4 247214571Sdim , MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4 248214571Sdim , MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD 249214571Sdim , MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT 250214571Sdim , MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR 251214571Sdim , MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX 252214571Sdim} CGEN_OPERAND_TYPE; 253214571Sdim 254214571Sdim/* Number of operands types. */ 255214571Sdim#define MAX_OPERANDS 90 256214571Sdim 257214571Sdim/* Maximum number of operands referenced by any insn. */ 258214571Sdim#define MAX_OPERAND_INSTANCES 8 259214571Sdim 260214571Sdim/* Insn attribute indices. */ 261214571Sdim 262214571Sdim/* Enum declaration for cgen_insn attrs. */ 263214571Sdimtypedef enum cgen_insn_attr { 264214571Sdim CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 265214571Sdim , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 266214571Sdim , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN 267214571Sdim , CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN, CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN 268214571Sdim , CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN 269214571Sdim , CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN 270214571Sdim , CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP 271214571Sdim , CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE 272214571Sdim , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA 273214571Sdim , CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_END_NBOOLS 274214571Sdim} CGEN_INSN_ATTR; 275214571Sdim 276214571Sdim/* Number of non-boolean elements in cgen_insn_attr. */ 277214571Sdim#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 278214571Sdim 279214571Sdim/* cgen_insn attribute accessor macros. */ 280214571Sdim#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 281214571Sdim#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) 282214571Sdim#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset) 283214571Sdim#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset) 284214571Sdim#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) 285214571Sdim#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) 286214571Sdim#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 287214571Sdim#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) 288214571Sdim#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) 289214571Sdim#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 290214571Sdim#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) 291214571Sdim#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) 292214571Sdim#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) 293214571Sdim#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) 294214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_BIT_INSN)) != 0) 295214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MUL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MUL_INSN)) != 0) 296214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DIV_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)) != 0) 297214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DEBUG_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN)) != 0) 298214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_LDZ_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)) != 0) 299214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_ABS_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_ABS_INSN)) != 0) 300214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_AVE_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_AVE_INSN)) != 0) 301214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MINMAX_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)) != 0) 302214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CLIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)) != 0) 303214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_SAT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_SAT_INSN)) != 0) 304214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_UCI_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_UCI_INSN)) != 0) 305214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DSP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DSP_INSN)) != 0) 306214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP_INSN)) != 0) 307214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP64_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) != 0) 308214571Sdim#define CGEN_ATTR_CGEN_INSN_OPTIONAL_VLIW64_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_VLIW64)) != 0) 309214571Sdim#define CGEN_ATTR_CGEN_INSN_MAY_TRAP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MAY_TRAP)) != 0) 310214571Sdim#define CGEN_ATTR_CGEN_INSN_VLIW_ALONE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_ALONE)) != 0) 311214571Sdim#define CGEN_ATTR_CGEN_INSN_VLIW_NO_CORE_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_CORE_NOP)) != 0) 312214571Sdim#define CGEN_ATTR_CGEN_INSN_VLIW_NO_COP_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_COP_NOP)) != 0) 313214571Sdim#define CGEN_ATTR_CGEN_INSN_VLIW64_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW64_NO_MATCHING_NOP)) != 0) 314214571Sdim#define CGEN_ATTR_CGEN_INSN_VLIW32_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW32_NO_MATCHING_NOP)) != 0) 315214571Sdim#define CGEN_ATTR_CGEN_INSN_VOLATILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VOLATILE)) != 0) 316214571Sdim 317214571Sdim/* cgen.h uses things we just defined. */ 318214571Sdim#include "opcode/cgen.h" 319214571Sdim 320214571Sdimextern const struct cgen_ifld mep_cgen_ifld_table[]; 321214571Sdim 322214571Sdim/* Attributes. */ 323214571Sdimextern const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[]; 324214571Sdimextern const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[]; 325214571Sdimextern const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[]; 326214571Sdimextern const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[]; 327214571Sdim 328214571Sdim/* Hardware decls. */ 329214571Sdim 330214571Sdimextern CGEN_KEYWORD mep_cgen_opval_h_gpr; 331214571Sdimextern CGEN_KEYWORD mep_cgen_opval_h_csr; 332214571Sdimextern CGEN_KEYWORD mep_cgen_opval_h_cr64; 333214571Sdimextern CGEN_KEYWORD mep_cgen_opval_h_cr; 334214571Sdimextern CGEN_KEYWORD mep_cgen_opval_h_ccr; 335214571Sdimextern CGEN_KEYWORD mep_cgen_opval_h_cr_fmax; 336214571Sdimextern CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax; 337214571Sdim 338214571Sdimextern const CGEN_HW_ENTRY mep_cgen_hw_table[]; 339214571Sdim 340214571Sdim 341214571Sdim 342214571Sdim#endif /* MEP_CPU_H */ 343