i386.h revision 33965
1/* i386-opcode.h -- Intel 80386 opcode table 2 Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation. 3 4This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. 5 6This program is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2 of the License, or 9(at your option) any later version. 10 11This program is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with this program; if not, write to the Free Software 18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 19 20/* The NON_BROKEN_OPCODES cases use the operands in the reverse order 21 from that documented in the Intel manuals. The opcode values are 22 such that they actually generate different instructions. These 23 values must not be changed, as they are the values generated by the 24 UnixWare assembler, and possibly other ix86 assemblers. */ 25 26static const template i386_optab[] = { 27 28#define _ None 29/* move instructions */ 30#define MOV_AX_DISP32 0xa0 31{ "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } }, 32{ "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } }, 33{ "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } }, 34{ "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } }, 35{ "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, Reg16|Mem, 0 } }, 36/* move to/from control debug registers */ 37{ "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} }, 38{ "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} }, 39{ "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} }, 40 41/* move with sign extend */ 42/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid 43 conflict with the "movs" string move instruction. Thus, 44 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, 45 is not kosher; we must seperate the two instructions. */ 46{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32, 0} }, 47{"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16, 0} }, 48{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, 49 50/* move with zero extend */ 51{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, 52{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, 53 54/* push instructions */ 55{"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } }, 56{"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } }, 57{"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} }, 58{"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} }, 59{"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } }, 60{"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } }, 61/* push all */ 62{"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } }, 63 64/* pop instructions */ 65{"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } }, 66{"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } }, 67#define POP_SEG_SHORT 0x7 68{"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } }, 69{"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } }, 70/* pop all */ 71{"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } }, 72 73/* xchg exchange instructions 74 xchg commutes: we allow both operand orders */ 75{"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } }, 76{"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } }, 77{"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } }, 78{"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } }, 79 80/* in/out from ports */ 81{"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } }, 82{"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } }, 83{"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } }, 84{"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } }, 85{"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } }, 86{"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } }, 87{"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } }, 88{"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } }, 89 90/* load effective address */ 91{"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } }, 92 93/* load segment registers from memory */ 94{"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} }, 95{"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} }, 96{"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} }, 97{"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} }, 98{"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} }, 99 100/* flags register instructions */ 101{"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} }, 102{"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} }, 103{"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} }, 104{"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} }, 105{"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} }, 106{"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} }, 107{"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} }, 108{"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} }, 109{"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} }, 110{"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} }, 111{"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} }, 112{"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} }, 113{"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} }, 114{"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} }, 115{"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} }, 116{"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} }, 117 118{"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 119{"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} }, 120{"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} }, 121{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} }, 122 123{"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} }, 124{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} }, 125 126{"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 127{"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} }, 128{"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} }, 129{"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} }, 130 131{"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} }, 132{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} }, 133 134{"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 135{"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} }, 136{"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} }, 137{"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} }, 138 139{"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 140{"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} }, 141{"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} }, 142{"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} }, 143 144{"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} }, 145{"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} }, 146{"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} }, 147{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} }, 148 149{"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 150{"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} }, 151{"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} }, 152{"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} }, 153 154{"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 155{"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} }, 156{"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} }, 157{"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} }, 158 159{"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 160{"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} }, 161{"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} }, 162{"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} }, 163 164/* iclr with 1 operand is really xor with 2 operands. */ 165{"clr", 1, 0x30, _, W|Modrm|iclrKludge, { Reg } }, 166 167{"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 168{"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} }, 169{"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} }, 170{"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} }, 171 172{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} }, 173{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} }, 174 175{"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} }, 176{"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} }, 177{"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} }, 178{"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} }, 179{"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} }, 180{"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} }, 181 182/* conversion insns */ 183/* conversion: intel naming */ 184{"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, 185{"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, 186{"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, 187{"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, 188/* att naming */ 189{"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, 190{"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, 191{"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, 192{"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, 193 194/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are 195 expanding 64-bit multiplies, and *cannot* be selected to accomplish 196 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) 197 These multiplies can only be selected with single operand forms. */ 198{"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} }, 199{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} }, 200 201 202 203 204/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields. 205 These instructions are exceptions: 'imul $2, %eax, %ecx' would put 206 '%eax' in the reg field and '%ecx' in the regmem field if we did not 207 switch them. */ 208{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, 209{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} }, 210{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} }, 211/* 212 imul with 2 operands mimicks imul with 3 by puting register both 213 in i.rm.reg & i.rm.regmem fields 214*/ 215{"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} }, 216{"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} }, 217{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} }, 218{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} }, 219{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} }, 220{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} }, 221 222{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} }, 223{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} }, 224{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 225{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} }, 226 227{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} }, 228{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} }, 229{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 230{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} }, 231 232{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} }, 233{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} }, 234{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 235{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} }, 236 237{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} }, 238{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} }, 239{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 240{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} }, 241 242{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, 243{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, 244{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 245{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, 246{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, 247{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, 248{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 249{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, 250 251{"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, 252{"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, 253{"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} }, 254 255{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} }, 256{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} }, 257{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 258{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} }, 259 260{"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, 261{"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, 262{"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} }, 263 264{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} }, 265{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} }, 266{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 267{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} }, 268 269/* control transfer instructions */ 270#define CALL_PC_RELATIVE 0xe8 271{"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} }, 272{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} }, 273{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} }, 274#define CALL_FAR_IMMEDIATE 0x9a 275{"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Imm32, 0} }, 276{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} }, 277{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} }, 278 279#define JUMP_PC_RELATIVE 0xeb 280{"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} }, 281{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} }, 282#define JUMP_FAR_IMMEDIATE 0xea 283{"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} }, 284{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} }, 285 286{"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} }, 287{"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} }, 288{"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} }, 289{"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} }, 290{"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} }, 291{"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} }, 292{"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} }, 293{"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} }, 294{"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} }, 295{"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} }, 296{"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} }, 297{"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} }, 298 299/* conditional jumps */ 300{"jo", 1, 0x70, _, Jump, { Disp, 0, 0} }, 301 302{"jno", 1, 0x71, _, Jump, { Disp, 0, 0} }, 303 304{"jb", 1, 0x72, _, Jump, { Disp, 0, 0} }, 305{"jc", 1, 0x72, _, Jump, { Disp, 0, 0} }, 306{"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} }, 307 308{"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} }, 309{"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} }, 310{"jae", 1, 0x73, _, Jump, { Disp, 0, 0} }, 311 312{"je", 1, 0x74, _, Jump, { Disp, 0, 0} }, 313{"jz", 1, 0x74, _, Jump, { Disp, 0, 0} }, 314 315{"jne", 1, 0x75, _, Jump, { Disp, 0, 0} }, 316{"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} }, 317 318{"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} }, 319{"jna", 1, 0x76, _, Jump, { Disp, 0, 0} }, 320 321{"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} }, 322{"ja", 1, 0x77, _, Jump, { Disp, 0, 0} }, 323 324{"js", 1, 0x78, _, Jump, { Disp, 0, 0} }, 325 326{"jns", 1, 0x79, _, Jump, { Disp, 0, 0} }, 327 328{"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} }, 329{"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} }, 330 331{"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} }, 332{"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} }, 333 334{"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} }, 335{"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} }, 336 337{"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} }, 338{"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} }, 339 340{"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} }, 341{"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} }, 342 343{"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} }, 344{"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} }, 345 346#if 0 /* XXX where are these macros used? 347 To get them working again, they need to take 348 an entire template as the parameter, 349 and check for Data16/Data32 flags. */ 350/* these turn into pseudo operations when disp is larger than 8 bits */ 351#define IS_JUMP_ON_CX_ZERO(o) \ 352 (o == 0x66e3) 353#define IS_JUMP_ON_ECX_ZERO(o) \ 354 (o == 0xe3) 355#endif 356 357{"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} }, 358{"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} }, 359 360#define IS_LOOP_ECX_TIMES(o) \ 361 (o == 0xe2 || o == 0xe1 || o == 0xe0) 362 363{"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} }, 364 365{"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, 366{"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, 367 368{"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, 369{"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, 370 371/* set byte on flag instructions */ 372{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} }, 373 374{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} }, 375 376{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, 377{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, 378{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, 379 380{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, 381{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, 382{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, 383 384{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, 385{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, 386 387{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, 388{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, 389 390{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, 391{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, 392 393{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, 394{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, 395 396{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} }, 397 398{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} }, 399 400{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, 401{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, 402 403{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, 404{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, 405 406{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, 407{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, 408 409{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, 410{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, 411 412{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, 413{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, 414 415{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, 416{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, 417 418#define IS_STRING_INSTRUCTION(o) \ 419 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \ 420 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \ 421 (o) == 0xd7) 422 423/* string manipulation */ 424{"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, 425{"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, 426{"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} }, 427{"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} }, 428{"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, 429{"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, 430{"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, 431{"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, 432{"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, 433{"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, 434{"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, 435{"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, 436{"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} }, 437 438/* bit manipulation */ 439{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, 440{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, 441{"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} }, 442{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} }, 443{"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} }, 444{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} }, 445{"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} }, 446{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} }, 447{"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} }, 448{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} }, 449 450/* interrupts & op. sys insns */ 451/* See gas/config/tc-i386.c for conversion of 'int $3' into the special 452 int 3 insn. */ 453#define INT_OPCODE 0xcd 454#define INT3_OPCODE 0xcc 455{"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} }, 456{"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} }, 457{"into", 0, 0xce, _, NoModrm, { 0, 0, 0} }, 458{"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} }, 459{"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} }, 460/* i386sl, i486sl, later 486, and Pentium */ 461{"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} }, 462 463{"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} }, 464{"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} }, 465 466{"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} }, 467{"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, 468/* nop is actually 'xchgl %eax, %eax' */ 469{"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} }, 470 471/* protection control */ 472{"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} }, 473{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, 474{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} }, 475{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} }, 476{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} }, 477{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} }, 478{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, 479{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} }, 480 481{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} }, 482{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} }, 483{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} }, 484{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} }, 485{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} }, 486 487{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} }, 488{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} }, 489 490/* floating point instructions */ 491 492/* load */ 493{"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 494{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */ 495{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */ 496{"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 497{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */ 498{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */ 499{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ 500{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ 501{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */ 502{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */ 503 504/* store (no pop) */ 505{"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 506{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ 507{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ 508{"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 509{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ 510{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ 511 512/* store (with pop) */ 513{"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 514{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ 515{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ 516{"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 517{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ 518{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ 519{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ 520{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ 521{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */ 522{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */ 523 524/* exchange %st<n> with %st0 */ 525{"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} }, 526{"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */ 527 528/* comparison (without pop) */ 529{"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, 530{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ 531{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ 532{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ 533{"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, 534{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ 535 536/* comparison (with pop) */ 537{"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, 538{"fcomp", 0, 0xd8d9, _, NoModrm, {0, 0, 0} }, /* fcomp %st, %st(1) */ 539{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ 540{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ 541{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ 542{"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, 543{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ 544{"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */ 545 546/* unordered comparison (with pop) */ 547{"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} }, 548{"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} }, 549{"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */ 550 551{"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */ 552{"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */ 553 554/* load constants into %st0 */ 555{"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */ 556{"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */ 557{"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */ 558{"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */ 559{"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */ 560{"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */ 561{"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */ 562 563/* arithmetic */ 564 565/* add */ 566{"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} }, 567{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 568{"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */ 569{"faddp", 1, 0xdec0, _, ShortForm, { FloatReg, 0, 0} }, 570{"faddp", 2, 0xdec0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 571{"faddp", 2, 0xdec0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 572{"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */ 573{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} }, 574{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} }, 575{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} }, 576{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} }, 577 578/* sub */ 579/* Note: intel has decided that certain of these operations are reversed 580 in assembler syntax. */ 581{"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} }, 582{"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 583#ifdef NON_BROKEN_OPCODES 584{"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 585#else 586{"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 587#endif 588{"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} }, 589{"fsubp", 1, 0xdee8, _, ShortForm, { FloatReg, 0, 0} }, 590{"fsubp", 2, 0xdee8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 591#ifdef NON_BROKEN_OPCODES 592{"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 593{"fsubp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, 594#else 595{"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 596{"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, 597#endif 598{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} }, 599{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} }, 600{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} }, 601{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} }, 602 603/* sub reverse */ 604{"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} }, 605{"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 606#ifdef NON_BROKEN_OPCODES 607{"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 608#else 609{"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 610#endif 611{"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} }, 612{"fsubrp", 1, 0xdee0, _, ShortForm, { FloatReg, 0, 0} }, 613{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 614#ifdef NON_BROKEN_OPCODES 615{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 616{"fsubrp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, 617#else 618{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 619{"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, 620#endif 621{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} }, 622{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} }, 623{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} }, 624{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} }, 625 626/* mul */ 627{"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} }, 628{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 629{"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} }, 630{"fmulp", 1, 0xdec8, _, ShortForm, { FloatReg, 0, 0} }, 631{"fmulp", 2, 0xdec8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 632{"fmulp", 2, 0xdec8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 633{"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} }, 634{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} }, 635{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} }, 636{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} }, 637{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} }, 638 639/* div */ 640/* Note: intel has decided that certain of these operations are reversed 641 in assembler syntax. */ 642{"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} }, 643{"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 644#ifdef NON_BROKEN_OPCODES 645{"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 646#else 647{"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 648#endif 649{"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} }, 650{"fdivp", 1, 0xdef8, _, ShortForm, { FloatReg, 0, 0} }, 651{"fdivp", 2, 0xdef8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 652#ifdef NON_BROKEN_OPCODES 653{"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 654{"fdivp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, 655#else 656{"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 657{"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, 658#endif 659{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} }, 660{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} }, 661{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} }, 662{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} }, 663 664/* div reverse */ 665{"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} }, 666{"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 667#ifdef NON_BROKEN_OPCODES 668{"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 669#else 670{"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 671#endif 672{"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} }, 673{"fdivrp", 1, 0xdef0, _, ShortForm, { FloatReg, 0, 0} }, 674{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 675#ifdef NON_BROKEN_OPCODES 676{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 677{"fdivrp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, 678#else 679{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 680{"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, 681#endif 682{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} }, 683{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} }, 684{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} }, 685{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} }, 686 687{"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} }, 688{"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} }, 689{"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} }, 690{"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} }, 691{"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} }, 692{"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} }, 693{"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} }, 694{"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} }, 695{"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} }, 696{"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} }, 697{"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} }, 698{"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} }, 699{"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} }, 700{"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} }, 701{"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} }, 702{"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} }, 703 704{"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} }, 705{"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} }, 706 707/* processor control */ 708{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} }, 709{"finit", 0, 0x9bdbe3, _, NoModrm, { 0, 0, 0} }, 710{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} }, 711{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} }, 712{"fstcw", 1, 0x9bd9, 7, Modrm, { Mem, 0, 0} }, 713{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} }, 714{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} }, 715{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} }, 716{"fstsw", 1, 0x9bdfe0, _, NoModrm, { Acc, 0, 0} }, 717{"fstsw", 1, 0x9bdd, 7, Modrm, { Mem, 0, 0} }, 718{"fstsw", 0, 0x9bdfe0, _, NoModrm, { 0, 0, 0} }, 719{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} }, 720{"fclex", 0, 0x9bdbe2, _, NoModrm, { 0, 0, 0} }, 721/* 722 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor 723 instructions; i'm not sure how to add them or how they are different. 724 My 386/387 book offers no details about this. 725*/ 726{"fnstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} }, 727{"fstenv", 1, 0x9bd9, 6, Modrm, { Mem, 0, 0} }, 728{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} }, 729{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} }, 730{"fsave", 1, 0x9bdd, 6, Modrm, { Mem, 0, 0} }, 731{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} }, 732 733{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} }, 734/* P6:free st(i), pop st */ 735{"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} }, 736{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} }, 737{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, 738 739/* 740 opcode prefixes; we allow them as seperate insns too 741 (see prefix table below) 742*/ 743{"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} }, 744{"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} }, 745{"word", 0, 0x66, _, NoModrm, { 0, 0, 0} }, 746{"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} }, 747{"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} }, 748{"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} }, 749{"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} }, 750{"es", 0, 0x26, _, NoModrm, { 0, 0, 0} }, 751{"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} }, 752{"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} }, 753{"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} }, 754{"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, 755{"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, 756{"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, 757{"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, 758{"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, 759 760/* 486 extensions */ 761 762{"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } }, 763{"xadd", 2, 0x0fc0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, 764{"cmpxchg", 2, 0x0fb0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, 765{"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} }, 766{"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} }, 767{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} }, 768 769/* 586 and late 486 extensions */ 770{"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} }, 771 772/* Pentium extensions */ 773{"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} }, 774{"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} }, 775{"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} }, 776{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} }, 777 778/* Pentium Pro extensions */ 779{"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} }, 780 781{"ud2", 0, 0x0fff, _, NoModrm, {0, 0, 0} }, /* official undefined instr. */ 782 783{"cmovo", 2, 0x0f40, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 784{"cmovno", 2, 0x0f41, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 785{"cmovb", 2, 0x0f42, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 786{"cmovae", 2, 0x0f43, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 787{"cmove", 2, 0x0f44, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 788{"cmovne", 2, 0x0f45, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 789{"cmovbe", 2, 0x0f46, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 790{"cmova", 2, 0x0f47, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 791{"cmovs", 2, 0x0f48, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 792{"cmovns", 2, 0x0f49, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 793{"cmovp", 2, 0x0f4a, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 794{"cmovnp", 2, 0x0f4b, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 795{"cmovl", 2, 0x0f4c, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 796{"cmovge", 2, 0x0f4d, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 797{"cmovle", 2, 0x0f4e, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 798{"cmovg", 2, 0x0f4f, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 799 800{"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 801{"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 802{"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 803{"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 804{"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 805{"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 806{"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 807{"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 808 809{"fcomi", 2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 810{"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 811{"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 812{"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 813 814/* MMX instructions. */ 815 816{"emms", 0, 0x0f77, _, NoModrm, { 0, 0, 0 } }, 817{"movd", 2, 0x0f6e, _, Modrm, { Reg32|WordMem, RegMMX, 0 } }, 818{"movd", 2, 0x0f7e, _, Modrm, { RegMMX, Reg32|WordMem, 0 } }, 819{"movq", 2, 0x0f6f, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 820{"movq", 2, 0x0f7f, _, Modrm, { RegMMX, RegMMX|WordMem, 0 } }, 821{"packssdw", 2, 0x0f6b, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 822{"packsswb", 2, 0x0f63, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 823{"packuswb", 2, 0x0f67, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 824{"paddb", 2, 0x0ffc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 825{"paddw", 2, 0x0ffd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 826{"paddd", 2, 0x0ffe, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 827{"paddsb", 2, 0x0fec, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 828{"paddsw", 2, 0x0fed, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 829{"paddusb", 2, 0x0fdc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 830{"paddusw", 2, 0x0fdd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 831{"pand", 2, 0x0fda, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 832{"pandn", 2, 0x0fdf, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 833{"pcmpeqb", 2, 0x0f74, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 834{"pcmpeqw", 2, 0x0f75, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 835{"pcmpeqd", 2, 0x0f76, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 836{"pcmpgtb", 2, 0x0f64, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 837{"pcmpgtw", 2, 0x0f65, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 838{"pcmpgtd", 2, 0x0f66, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 839{"pmaddwd", 2, 0x0ff5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 840{"pmulhw", 2, 0x0fe5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 841{"pmullw", 2, 0x0fd5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 842{"por", 2, 0x0feb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 843{"psllw", 2, 0x0ff1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 844{"psllw", 2, 0x0f71, 6, Modrm, { Imm8, RegMMX, 0 } }, 845{"pslld", 2, 0x0ff2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 846{"pslld", 2, 0x0f72, 6, Modrm, { Imm8, RegMMX, 0 } }, 847{"psllq", 2, 0x0ff3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 848{"psllq", 2, 0x0f73, 6, Modrm, { Imm8, RegMMX, 0 } }, 849{"psraw", 2, 0x0fe1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 850{"psraw", 2, 0x0f71, 4, Modrm, { Imm8, RegMMX, 0 } }, 851{"psrad", 2, 0x0fe2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 852{"psrad", 2, 0x0f72, 4, Modrm, { Imm8, RegMMX, 0 } }, 853{"psrlw", 2, 0x0fd1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 854{"psrlw", 2, 0x0f71, 2, Modrm, { Imm8, RegMMX, 0 } }, 855{"psrld", 2, 0x0fd2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 856{"psrld", 2, 0x0f72, 2, Modrm, { Imm8, RegMMX, 0 } }, 857{"psrlq", 2, 0x0fd3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 858{"psrlq", 2, 0x0f73, 2, Modrm, { Imm8, RegMMX, 0 } }, 859{"psubb", 2, 0x0ff8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 860{"psubw", 2, 0x0ff9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 861{"psubd", 2, 0x0ffa, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 862{"psubsb", 2, 0x0fe8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 863{"psubsw", 2, 0x0fe9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 864{"psubusb", 2, 0x0fd8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 865{"psubusw", 2, 0x0fd9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 866{"punpckhbw", 2, 0x0f68, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 867{"punpckhwd", 2, 0x0f69, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 868{"punpckhdq", 2, 0x0f6a, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 869{"punpcklbw", 2, 0x0f60, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 870{"punpcklwd", 2, 0x0f61, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 871{"punpckldq", 2, 0x0f62, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 872{"pxor", 2, 0x0fef, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 873 874{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ 875}; 876#undef _ 877 878static const template *const i386_optab_end 879 = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]); 880 881/* 386 register table */ 882 883static const reg_entry i386_regtab[] = { 884 /* 8 bit regs */ 885 {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2}, 886 {"bl", Reg8, 3}, 887 {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7}, 888 /* 16 bit regs */ 889 {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3}, 890 {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7}, 891 /* 32 bit regs */ 892 {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3}, 893 {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7}, 894 /* segment registers */ 895 {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2}, 896 {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5}, 897 /* control registers */ 898 {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3}, 899 {"cr4", Control, 4}, 900 /* debug registers */ 901 {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2}, 902 {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7}, 903 {"dr0", Debug, 0}, {"dr1", Debug, 1}, {"dr2", Debug, 2}, 904 {"dr3", Debug, 3}, {"dr6", Debug, 6}, {"dr7", Debug, 7}, 905 /* test registers */ 906 {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5}, 907 {"tr6", Test, 6}, {"tr7", Test, 7}, 908 /* float registers */ 909 {"st(0)", FloatReg|FloatAcc, 0}, 910 {"st", FloatReg|FloatAcc, 0}, 911 {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, 912 {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, 913 {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}, 914 {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2}, 915 {"mm3", RegMMX, 3}, {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5}, 916 {"mm6", RegMMX, 6}, {"mm7", RegMMX, 7} 917}; 918 919#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ 920 921static const reg_entry *const i386_regtab_end 922 = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]); 923 924/* segment stuff */ 925static const seg_entry cs = { "cs", 0x2e }; 926static const seg_entry ds = { "ds", 0x3e }; 927static const seg_entry ss = { "ss", 0x36 }; 928static const seg_entry es = { "es", 0x26 }; 929static const seg_entry fs = { "fs", 0x64 }; 930static const seg_entry gs = { "gs", 0x65 }; 931static const seg_entry null = { "", 0x0 }; 932 933/* 934 This table is used to store the default segment register implied by all 935 possible memory addressing modes. 936 It is indexed by the mode & modrm entries of the modrm byte as follows: 937 index = (mode<<3) | modrm; 938*/ 939static const seg_entry *const one_byte_segment_defaults[] = { 940 /* mode 0 */ 941 &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds, 942 /* mode 1 */ 943 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 944 /* mode 2 */ 945 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 946 /* mode 3 --- not a memory reference; never referenced */ 947}; 948 949static const seg_entry *const two_byte_segment_defaults[] = { 950 /* mode 0 */ 951 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 952 /* mode 1 */ 953 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 954 /* mode 2 */ 955 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 956 /* mode 3 --- not a memory reference; never referenced */ 957}; 958 959static const prefix_entry i386_prefixtab[] = { 960#define ADDR_PREFIX_OPCODE 0x67 961 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing 962 * (How is this useful?) */ 963#define WORD_PREFIX_OPCODE 0x66 964 { "data16", 0x66 }, /* operand size prefix */ 965 { "lock", 0xf0 }, /* bus lock prefix */ 966 { "wait", 0x9b }, /* wait for coprocessor */ 967 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */ 968 { "es", 0x26 }, { "fs", 0x64 }, 969 { "gs", 0x65 }, { "ss", 0x36 }, 970/* REPE & REPNE used to detect rep/repne with a non-string instruction */ 971#define REPNE 0xf2 972#define REPE 0xf3 973 { "rep", 0xf3 }, /* repeat string instructions */ 974 { "repe", 0xf3 }, { "repz", 0xf3 }, 975 { "repne", 0xf2 }, { "repnz", 0xf2 } 976}; 977 978static const prefix_entry *const i386_prefixtab_end 979 = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]); 980 981/* end of i386-opcode.h */ 982