cgen.h revision 89857
1/* Header file for targets using CGEN: Cpu tools GENerator. 2 3Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. 4 5This file is part of GDB, the GNU debugger, and the GNU Binutils. 6 7This program is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2 of the License, or 10(at your option) any later version. 11 12This program is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License along 18with this program; if not, write to the Free Software Foundation, Inc., 1959 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20 21#ifndef CGEN_H 22#define CGEN_H 23 24/* ??? This file requires bfd.h but only to get bfd_vma. 25 Seems like an awful lot to require just to get such a fundamental type. 26 Perhaps the definition of bfd_vma can be moved outside of bfd.h. 27 Or perhaps one could duplicate its definition in another file. 28 Until such time, this file conditionally compiles definitions that require 29 bfd_vma using BFD_VERSION. */ 30 31/* Enums must be defined before they can be used. 32 Allow them to be used in struct definitions, even though the enum must 33 be defined elsewhere. 34 If CGEN_ARCH isn't defined, this file is being included by something other 35 than <arch>-desc.h. */ 36 37/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S. 38 The lack of spaces in the arg list is important for non-stdc systems. 39 This file is included by <arch>-desc.h. 40 It can be included independently of <arch>-desc.h, in which case the arch 41 dependent portions will be declared as "unknown_cgen_foo". */ 42 43#ifndef CGEN_SYM 44#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) 45#endif 46 47/* This file contains the static (unchanging) pieces and as much other stuff 48 as we can reasonably put here. It's generally cleaner to put stuff here 49 rather than having it machine generated if possible. */ 50 51/* The assembler syntax is made up of expressions (duh...). 52 At the lowest level the values are mnemonics, register names, numbers, etc. 53 Above that are subexpressions, if any (an example might be the 54 "effective address" in m68k cpus). Subexpressions are wip. 55 At the second highest level are the insns themselves. Above that are 56 pseudo-insns, synthetic insns, and macros, if any. */ 57 58/* Lots of cpu's have a fixed insn size, or one which rarely changes, 59 and it's generally easier to handle these by treating the insn as an 60 integer type, rather than an array of characters. So we allow targets 61 to control this. When an integer type the value is in host byte order, 62 when an array of characters the value is in target byte order. */ 63 64typedef unsigned int CGEN_INSN_INT; 65#if CGEN_INT_INSN_P 66typedef CGEN_INSN_INT CGEN_INSN_BYTES; 67typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; 68#else 69typedef unsigned char *CGEN_INSN_BYTES; 70typedef unsigned char *CGEN_INSN_BYTES_PTR; 71#endif 72 73#ifdef __GNUC__ 74#define CGEN_INLINE __inline__ 75#else 76#define CGEN_INLINE 77#endif 78 79enum cgen_endian 80{ 81 CGEN_ENDIAN_UNKNOWN, 82 CGEN_ENDIAN_LITTLE, 83 CGEN_ENDIAN_BIG 84}; 85 86/* Forward decl. */ 87 88typedef struct cgen_insn CGEN_INSN; 89 90/* Opaque pointer version for use by external world. */ 91 92typedef struct cgen_cpu_desc *CGEN_CPU_DESC; 93 94/* Attributes. 95 Attributes are used to describe various random things associated with 96 an object (ifield, hardware, operand, insn, whatever) and are specified 97 as name/value pairs. 98 Integer attributes computed at compile time are currently all that's 99 supported, though adding string attributes and run-time computation is 100 straightforward. Integer attribute values are always host int's 101 (signed or unsigned). For portability, this means 32 bits. 102 Integer attributes are further categorized as boolean, bitset, integer, 103 and enum types. Boolean attributes appear frequently enough that they're 104 recorded in one host int. This limits the maximum number of boolean 105 attributes to 32, though that's a *lot* of attributes. */ 106 107/* Type of attribute values. */ 108 109typedef int CGEN_ATTR_VALUE_TYPE; 110 111/* Struct to record attribute information. */ 112 113typedef struct 114{ 115 /* Boolean attributes. */ 116 unsigned int bool; 117 /* Non-boolean integer attributes. */ 118 CGEN_ATTR_VALUE_TYPE nonbool[1]; 119} CGEN_ATTR; 120 121/* Define a structure member for attributes with N non-boolean entries. 122 There is no maximum number of non-boolean attributes. 123 There is a maximum of 32 boolean attributes (since they are all recorded 124 in one host int). */ 125 126#define CGEN_ATTR_TYPE(n) \ 127struct { unsigned int bool; \ 128 CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } 129 130/* Return the boolean attributes. */ 131 132#define CGEN_ATTR_BOOLS(a) ((a)->bool) 133 134/* Non-boolean attribute numbers are offset by this much. */ 135 136#define CGEN_ATTR_NBOOL_OFFSET 32 137 138/* Given a boolean attribute number, return its mask. */ 139 140#define CGEN_ATTR_MASK(attr) (1 << (attr)) 141 142/* Return the value of boolean attribute ATTR in ATTRS. */ 143 144#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) 145 146/* Return value of attribute ATTR in ATTR_TABLE for OBJ. 147 OBJ is a pointer to the entity that has the attributes 148 (??? not used at present but is reserved for future purposes - eventually 149 the goal is to allow recording attributes in source form and computing 150 them lazily at runtime, not sure of the details yet). */ 151 152#define CGEN_ATTR_VALUE(obj, attr_table, attr) \ 153((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ 154 ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ 155 : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET])) 156 157/* Attribute name/value tables. 158 These are used to assist parsing of descriptions at run-time. */ 159 160typedef struct 161{ 162 const char * name; 163 CGEN_ATTR_VALUE_TYPE value; 164} CGEN_ATTR_ENTRY; 165 166/* For each domain (ifld,hw,operand,insn), list of attributes. */ 167 168typedef struct 169{ 170 const char * name; 171 const CGEN_ATTR_ENTRY * dfault; 172 const CGEN_ATTR_ENTRY * vals; 173} CGEN_ATTR_TABLE; 174 175/* Instruction set variants. */ 176 177typedef struct { 178 const char *name; 179 180 /* Default instruction size (in bits). 181 This is used by the assembler when it encounters an unknown insn. */ 182 unsigned int default_insn_bitsize; 183 184 /* Base instruction size (in bits). 185 For non-LIW cpus this is generally the length of the smallest insn. 186 For LIW cpus its wip (work-in-progress). For the m32r its 32. */ 187 unsigned int base_insn_bitsize; 188 189 /* Minimum/maximum instruction size (in bits). */ 190 unsigned int min_insn_bitsize; 191 unsigned int max_insn_bitsize; 192} CGEN_ISA; 193 194/* Machine variants. */ 195 196typedef struct { 197 const char *name; 198 /* The argument to bfd_arch_info->scan. */ 199 const char *bfd_name; 200 /* one of enum mach_attr */ 201 int num; 202 /* parameter from mach->cpu */ 203 unsigned int insn_chunk_bitsize; 204} CGEN_MACH; 205 206/* Parse result (also extraction result). 207 208 The result of parsing an insn is stored here. 209 To generate the actual insn, this is passed to the insert handler. 210 When printing an insn, the result of extraction is stored here. 211 To print the insn, this is passed to the print handler. 212 213 It is machine generated so we don't define it here, 214 but we do need a forward decl for the handler fns. 215 216 There is one member for each possible field in the insn. 217 The type depends on the field. 218 Also recorded here is the computed length of the insn for architectures 219 where it varies. 220*/ 221 222typedef struct cgen_fields CGEN_FIELDS; 223 224/* Total length of the insn, as recorded in the `fields' struct. */ 225/* ??? The field insert handler has lots of opportunities for optimization 226 if it ever gets inlined. On architectures where insns all have the same 227 size, may wish to detect that and make this macro a constant - to allow 228 further optimizations. */ 229 230#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) 231 232/* Extraction support for variable length insn sets. */ 233 234/* When disassembling we don't know the number of bytes to read at the start. 235 So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest 236 are read when needed. This struct controls this. It is basically the 237 disassemble_info stuff, except that we provide a cache for values already 238 read (since bytes can typically be read several times to fetch multiple 239 operands that may be in them), and that extraction of fields is needed 240 in contexts other than disassembly. */ 241 242typedef struct { 243 /* A pointer to the disassemble_info struct. 244 We don't require dis-asm.h so we use PTR for the type here. 245 If NULL, BYTES is full of valid data (VALID == -1). */ 246 PTR dis_info; 247 /* Points to a working buffer of sufficient size. */ 248 unsigned char *insn_bytes; 249 /* Mask of bytes that are valid in INSN_BYTES. */ 250 unsigned int valid; 251} CGEN_EXTRACT_INFO; 252 253/* Associated with each insn or expression is a set of "handlers" for 254 performing operations like parsing, printing, etc. These require a bfd_vma 255 value to be passed around but we don't want all applications to need bfd.h. 256 So this stuff is only provided if bfd.h has been included. */ 257 258/* Parse handler. 259 CD is a cpu table descriptor. 260 INSN is a pointer to a struct describing the insn being parsed. 261 STRP is a pointer to a pointer to the text being parsed. 262 FIELDS is a pointer to a cgen_fields struct in which the results are placed. 263 If the expression is successfully parsed, *STRP is updated. 264 If not it is left alone. 265 The result is NULL if success or an error message. */ 266typedef const char * (cgen_parse_fn) 267 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, 268 const char **strp_, CGEN_FIELDS *fields_)); 269 270/* Insert handler. 271 CD is a cpu table descriptor. 272 INSN is a pointer to a struct describing the insn being parsed. 273 FIELDS is a pointer to a cgen_fields struct from which the values 274 are fetched. 275 INSNP is a pointer to a buffer in which to place the insn. 276 PC is the pc value of the insn. 277 The result is an error message or NULL if success. */ 278 279#ifdef BFD_VERSION 280typedef const char * (cgen_insert_fn) 281 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, 282 CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, 283 bfd_vma pc_)); 284#else 285typedef const char * (cgen_insert_fn) (); 286#endif 287 288/* Extract handler. 289 CD is a cpu table descriptor. 290 INSN is a pointer to a struct describing the insn being parsed. 291 The second argument is a pointer to a struct controlling extraction 292 (only used for variable length insns). 293 EX_INFO is a pointer to a struct for controlling reading of further 294 bytes for the insn. 295 BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). 296 FIELDS is a pointer to a cgen_fields struct in which the results are placed. 297 PC is the pc value of the insn. 298 The result is the length of the insn in bits or zero if not recognized. */ 299 300#ifdef BFD_VERSION 301typedef int (cgen_extract_fn) 302 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, 303 CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, 304 CGEN_FIELDS *fields_, bfd_vma pc_)); 305#else 306typedef int (cgen_extract_fn) (); 307#endif 308 309/* Print handler. 310 CD is a cpu table descriptor. 311 INFO is a pointer to the disassembly info. 312 Eg: disassemble_info. It's defined as `PTR' so this file can be included 313 without dis-asm.h. 314 INSN is a pointer to a struct describing the insn being printed. 315 FIELDS is a pointer to a cgen_fields struct. 316 PC is the pc value of the insn. 317 LEN is the length of the insn, in bits. */ 318 319#ifdef BFD_VERSION 320typedef void (cgen_print_fn) 321 PARAMS ((CGEN_CPU_DESC, PTR info_, const CGEN_INSN *insn_, 322 CGEN_FIELDS *fields_, bfd_vma pc_, int len_)); 323#else 324typedef void (cgen_print_fn) (); 325#endif 326 327/* Parse/insert/extract/print handlers. 328 329 Indices into the handler tables. 330 We could use pointers here instead, but 90% of them are generally identical 331 and that's a lot of redundant data. Making these unsigned char indices 332 into tables of pointers saves a bit of space. 333 Using indices also keeps assembler code out of the disassembler and 334 vice versa. */ 335 336struct cgen_opcode_handler 337{ 338 unsigned char parse, insert, extract, print; 339}; 340 341/* Assembler interface. 342 343 The interface to the assembler is intended to be clean in the sense that 344 libopcodes.a is a standalone entity and could be used with any assembler. 345 Not that one would necessarily want to do that but rather that it helps 346 keep a clean interface. The interface will obviously be slanted towards 347 GAS, but at least it's a start. 348 ??? Note that one possible user of the assembler besides GAS is GDB. 349 350 Parsing is controlled by the assembler which calls 351 CGEN_SYM (assemble_insn). If it can parse and build the entire insn 352 it doesn't call back to the assembler. If it needs/wants to call back 353 to the assembler, cgen_parse_operand_fn is called which can either 354 355 - return a number to be inserted in the insn 356 - return a "register" value to be inserted 357 (the register might not be a register per pe) 358 - queue the argument and return a marker saying the expression has been 359 queued (eg: a fix-up) 360 - return an error message indicating the expression wasn't recognizable 361 362 The result is an error message or NULL for success. 363 The parsed value is stored in the bfd_vma *. */ 364 365/* Values for indicating what the caller wants. */ 366 367enum cgen_parse_operand_type 368{ 369 CGEN_PARSE_OPERAND_INIT, 370 CGEN_PARSE_OPERAND_INTEGER, 371 CGEN_PARSE_OPERAND_ADDRESS 372}; 373 374/* Values for indicating what was parsed. */ 375 376enum cgen_parse_operand_result 377{ 378 CGEN_PARSE_OPERAND_RESULT_NUMBER, 379 CGEN_PARSE_OPERAND_RESULT_REGISTER, 380 CGEN_PARSE_OPERAND_RESULT_QUEUED, 381 CGEN_PARSE_OPERAND_RESULT_ERROR 382}; 383 384#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ 385typedef const char * (cgen_parse_operand_fn) 386 PARAMS ((CGEN_CPU_DESC, 387 enum cgen_parse_operand_type, const char **, int, int, 388 enum cgen_parse_operand_result *, bfd_vma *)); 389#else 390typedef const char * (cgen_parse_operand_fn) (); 391#endif 392 393/* Set the cgen_parse_operand_fn callback. */ 394 395extern void cgen_set_parse_operand_fn 396 PARAMS ((CGEN_CPU_DESC, cgen_parse_operand_fn)); 397 398/* Called before trying to match a table entry with the insn. */ 399 400extern void cgen_init_parse_operand PARAMS ((CGEN_CPU_DESC)); 401 402/* Operand values (keywords, integers, symbols, etc.) */ 403 404/* Types of assembler elements. */ 405 406enum cgen_asm_type 407{ 408 CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX 409}; 410 411#ifndef CGEN_ARCH 412enum cgen_hw_type { CGEN_HW_MAX }; 413#endif 414 415/* List of hardware elements. */ 416 417typedef struct 418{ 419 char *name; 420 enum cgen_hw_type type; 421 /* There is currently no example where both index specs and value specs 422 are required, so for now both are clumped under "asm_data". */ 423 enum cgen_asm_type asm_type; 424 PTR asm_data; 425#ifndef CGEN_HW_NBOOL_ATTRS 426#define CGEN_HW_NBOOL_ATTRS 1 427#endif 428 CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; 429#define CGEN_HW_ATTRS(hw) (&(hw)->attrs) 430} CGEN_HW_ENTRY; 431 432/* Return value of attribute ATTR in HW. */ 433 434#define CGEN_HW_ATTR_VALUE(hw, attr) \ 435CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) 436 437/* Table of hardware elements for selected mach, computed at runtime. 438 enum cgen_hw_type is an index into this table (specifically `entries'). */ 439 440typedef struct { 441 /* Pointer to null terminated table of all compiled in entries. */ 442 const CGEN_HW_ENTRY *init_entries; 443 unsigned int entry_size; /* since the attribute member is variable sized */ 444 /* Array of all entries, initial and run-time added. */ 445 const CGEN_HW_ENTRY **entries; 446 /* Number of elements in `entries'. */ 447 unsigned int num_entries; 448 /* For now, xrealloc is called each time a new entry is added at runtime. 449 ??? May wish to keep track of some slop to reduce the number of calls to 450 xrealloc, except that there's unlikely to be many and not expected to be 451 in speed critical code. */ 452} CGEN_HW_TABLE; 453 454extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name 455 PARAMS ((CGEN_CPU_DESC, const char *)); 456extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num 457 PARAMS ((CGEN_CPU_DESC, unsigned int)); 458 459/* This struct is used to describe things like register names, etc. */ 460 461typedef struct cgen_keyword_entry 462{ 463 /* Name (as in register name). */ 464 char * name; 465 466 /* Value (as in register number). 467 The value cannot be -1 as that is used to indicate "not found". 468 IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ 469 int value; 470 471 /* Attributes. 472 This should, but technically needn't, appear last. It is a variable sized 473 array in that one architecture may have 1 nonbool attribute and another 474 may have more. Having this last means the non-architecture specific code 475 needn't care. The goal is to eventually record 476 attributes in their raw form, evaluate them at run-time, and cache the 477 values, so this worry will go away anyway. */ 478 /* ??? Moving this last should be done by treating keywords like insn lists 479 and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ 480 /* FIXME: Not used yet. */ 481#ifndef CGEN_KEYWORD_NBOOL_ATTRS 482#define CGEN_KEYWORD_NBOOL_ATTRS 1 483#endif 484 CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; 485 486 /* ??? Putting these here means compiled in entries can't be const. 487 Not a really big deal, but something to consider. */ 488 /* Next name hash table entry. */ 489 struct cgen_keyword_entry *next_name; 490 /* Next value hash table entry. */ 491 struct cgen_keyword_entry *next_value; 492} CGEN_KEYWORD_ENTRY; 493 494/* Top level struct for describing a set of related keywords 495 (e.g. register names). 496 497 This struct supports run-time entry of new values, and hashed lookups. */ 498 499typedef struct cgen_keyword 500{ 501 /* Pointer to initial [compiled in] values. */ 502 CGEN_KEYWORD_ENTRY *init_entries; 503 504 /* Number of entries in `init_entries'. */ 505 unsigned int num_init_entries; 506 507 /* Hash table used for name lookup. */ 508 CGEN_KEYWORD_ENTRY **name_hash_table; 509 510 /* Hash table used for value lookup. */ 511 CGEN_KEYWORD_ENTRY **value_hash_table; 512 513 /* Number of entries in the hash_tables. */ 514 unsigned int hash_table_size; 515 516 /* Pointer to null keyword "" entry if present. */ 517 const CGEN_KEYWORD_ENTRY *null_entry; 518 519 /* String containing non-alphanumeric characters used 520 in keywords. 521 At present, the highest number of entries used is 1. */ 522 char nonalpha_chars[8]; 523} CGEN_KEYWORD; 524 525/* Structure used for searching. */ 526 527typedef struct 528{ 529 /* Table being searched. */ 530 const CGEN_KEYWORD *table; 531 532 /* Specification of what is being searched for. */ 533 const char *spec; 534 535 /* Current index in hash table. */ 536 unsigned int current_hash; 537 538 /* Current element in current hash chain. */ 539 CGEN_KEYWORD_ENTRY *current_entry; 540} CGEN_KEYWORD_SEARCH; 541 542/* Lookup a keyword from its name. */ 543 544const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name 545 PARAMS ((CGEN_KEYWORD *, const char *)); 546 547/* Lookup a keyword from its value. */ 548 549const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value 550 PARAMS ((CGEN_KEYWORD *, int)); 551 552/* Add a keyword. */ 553 554void cgen_keyword_add PARAMS ((CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *)); 555 556/* Keyword searching. 557 This can be used to retrieve every keyword, or a subset. */ 558 559CGEN_KEYWORD_SEARCH cgen_keyword_search_init 560 PARAMS ((CGEN_KEYWORD *, const char *)); 561const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next 562 PARAMS ((CGEN_KEYWORD_SEARCH *)); 563 564/* Operand value support routines. */ 565 566extern const char *cgen_parse_keyword 567 PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); 568#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ 569extern const char *cgen_parse_signed_integer 570 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); 571extern const char *cgen_parse_unsigned_integer 572 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); 573extern const char *cgen_parse_address 574 PARAMS ((CGEN_CPU_DESC, const char **, int, int, 575 enum cgen_parse_operand_result *, bfd_vma *)); 576extern const char *cgen_validate_signed_integer 577 PARAMS ((long, long, long)); 578extern const char *cgen_validate_unsigned_integer 579 PARAMS ((unsigned long, unsigned long, unsigned long)); 580#endif 581 582/* Operand modes. */ 583 584/* ??? This duplicates the values in arch.h. Revisit. 585 These however need the CGEN_ prefix [as does everything in this file]. */ 586/* ??? Targets may need to add their own modes so we may wish to move this 587 to <arch>-opc.h, or add a hook. */ 588 589enum cgen_mode { 590 CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ 591 CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, 592 CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, 593 CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, 594 CGEN_MODE_TARGET_MAX, 595 CGEN_MODE_INT, CGEN_MODE_UINT, 596 CGEN_MODE_MAX 597}; 598 599/* FIXME: Until simulator is updated. */ 600 601#define CGEN_MODE_VM CGEN_MODE_VOID 602 603/* Operands. */ 604 605#ifndef CGEN_ARCH 606enum cgen_operand_type { CGEN_OPERAND_MAX }; 607#endif 608 609/* "nil" indicator for the operand instance table */ 610#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX 611 612/* A tree of these structs represents the multi-ifield 613 structure of an operand's hw-index value, if it exists. */ 614 615struct cgen_ifld; 616 617typedef struct cgen_maybe_multi_ifield 618{ 619 int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); 620 n: indexed by array of more cgen_maybe_multi_ifields. */ 621 union 622 { 623 struct cgen_maybe_multi_ifield * multi; 624 struct cgen_ifld * leaf; 625 } val; 626} 627CGEN_MAYBE_MULTI_IFLD; 628 629/* This struct defines each entry in the operand table. */ 630 631typedef struct 632{ 633 /* Name as it appears in the syntax string. */ 634 char *name; 635 636 /* Operand type. */ 637 enum cgen_operand_type type; 638 639 /* The hardware element associated with this operand. */ 640 enum cgen_hw_type hw_type; 641 642 /* FIXME: We don't yet record ifield definitions, which we should. 643 When we do it might make sense to delete start/length (since they will 644 be duplicated in the ifield's definition) and replace them with a 645 pointer to the ifield entry. */ 646 647 /* Bit position. 648 This is just a hint, and may be unused in more complex operands. 649 May be unused for a modifier. */ 650 unsigned char start; 651 652 /* The number of bits in the operand. 653 This is just a hint, and may be unused in more complex operands. 654 May be unused for a modifier. */ 655 unsigned char length; 656 657 /* The (possibly-multi) ifield used as an index for this operand, if it 658 is indexed by a field at all. This substitutes / extends the start and 659 length fields above, but unsure at this time whether they are used 660 anywhere. */ 661 CGEN_MAYBE_MULTI_IFLD index_fields; 662#if 0 /* ??? Interesting idea but relocs tend to get too complicated, 663 and ABI dependent, for simple table lookups to work. */ 664 /* Ideally this would be the internal (external?) reloc type. */ 665 int reloc_type; 666#endif 667 668 /* Attributes. 669 This should, but technically needn't, appear last. It is a variable sized 670 array in that one architecture may have 1 nonbool attribute and another 671 may have more. Having this last means the non-architecture specific code 672 needn't care, now or tomorrow. The goal is to eventually record 673 attributes in their raw form, evaluate them at run-time, and cache the 674 values, so this worry will go away anyway. */ 675#ifndef CGEN_OPERAND_NBOOL_ATTRS 676#define CGEN_OPERAND_NBOOL_ATTRS 1 677#endif 678 CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; 679#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) 680} CGEN_OPERAND; 681 682/* Return value of attribute ATTR in OPERAND. */ 683 684#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ 685CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) 686 687/* Table of operands for selected mach/isa, computed at runtime. 688 enum cgen_operand_type is an index into this table (specifically 689 `entries'). */ 690 691typedef struct { 692 /* Pointer to null terminated table of all compiled in entries. */ 693 const CGEN_OPERAND *init_entries; 694 unsigned int entry_size; /* since the attribute member is variable sized */ 695 /* Array of all entries, initial and run-time added. */ 696 const CGEN_OPERAND **entries; 697 /* Number of elements in `entries'. */ 698 unsigned int num_entries; 699 /* For now, xrealloc is called each time a new entry is added at runtime. 700 ??? May wish to keep track of some slop to reduce the number of calls to 701 xrealloc, except that there's unlikely to be many and not expected to be 702 in speed critical code. */ 703} CGEN_OPERAND_TABLE; 704 705extern const CGEN_OPERAND * cgen_operand_lookup_by_name 706 PARAMS ((CGEN_CPU_DESC, const char *)); 707extern const CGEN_OPERAND * cgen_operand_lookup_by_num 708 PARAMS ((CGEN_CPU_DESC, int)); 709 710/* Instruction operand instances. 711 712 For each instruction, a list of the hardware elements that are read and 713 written are recorded. */ 714 715/* The type of the instance. */ 716 717enum cgen_opinst_type { 718 /* End of table marker. */ 719 CGEN_OPINST_END = 0, 720 CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT 721}; 722 723typedef struct 724{ 725 /* Input or output indicator. */ 726 enum cgen_opinst_type type; 727 728 /* Name of operand. */ 729 const char *name; 730 731 /* The hardware element referenced. */ 732 enum cgen_hw_type hw_type; 733 734 /* The mode in which the operand is being used. */ 735 enum cgen_mode mode; 736 737 /* The operand table entry CGEN_OPERAND_NIL if there is none 738 (i.e. an explicit hardware reference). */ 739 enum cgen_operand_type op_type; 740 741 /* If `operand' is "nil", the index (e.g. into array of registers). */ 742 int index; 743 744 /* Attributes. 745 ??? This perhaps should be a real attribute struct but there's 746 no current need, so we save a bit of space and just have a set of 747 flags. The interface is such that this can easily be made attributes 748 should it prove useful. */ 749 unsigned int attrs; 750#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) 751/* Return value of attribute ATTR in OPINST. */ 752#define CGEN_OPINST_ATTR(opinst, attr) \ 753((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) 754/* Operand is conditionally referenced (read/written). */ 755#define CGEN_OPINST_COND_REF 1 756} CGEN_OPINST; 757 758/* Syntax string. 759 760 Each insn format and subexpression has one of these. 761 762 The syntax "string" consists of characters (n > 0 && n < 128), and operand 763 values (n >= 128), and is terminated by 0. Operand values are 128 + index 764 into the operand table. The operand table doesn't exist in C, per se, as 765 the data is recorded in the parse/insert/extract/print switch statements. */ 766 767/* This should be at least as large as necessary for any target. */ 768#define CGEN_MAX_SYNTAX_ELEMENTS 48 769 770/* A target may know its own precise maximum. Assert that it falls below 771 the above limit. */ 772#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 773#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS 774#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" 775#endif 776#endif 777 778typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; 779 780typedef struct 781{ 782 CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; 783} CGEN_SYNTAX; 784 785#define CGEN_SYNTAX_STRING(syn) (syn->syntax) 786#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) 787#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c) 788#define CGEN_SYNTAX_FIELD(c) ((c) - 128) 789#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) 790 791/* ??? I can't currently think of any case where the mnemonic doesn't come 792 first [and if one ever doesn't building the hash tables will be tricky]. 793 However, we treat mnemonics as just another operand of the instruction. 794 A value of 1 means "this is where the mnemonic appears". 1 isn't 795 special other than it's a non-printable ASCII char. */ 796 797#define CGEN_SYNTAX_MNEMONIC 1 798#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) 799 800/* Instruction fields. 801 802 ??? We currently don't allow adding fields at run-time. 803 Easy to fix when needed. */ 804 805typedef struct cgen_ifld { 806 /* Enum of ifield. */ 807 int num; 808#define CGEN_IFLD_NUM(f) ((f)->num) 809 810 /* Name of the field, distinguishes it from all other fields. */ 811 const char *name; 812#define CGEN_IFLD_NAME(f) ((f)->name) 813 814 /* Default offset, in bits, from the start of the insn to the word 815 containing the field. */ 816 int word_offset; 817#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) 818 819 /* Default length of the word containing the field. */ 820 int word_size; 821#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) 822 823 /* Default starting bit number. 824 Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ 825 int start; 826#define CGEN_IFLD_START(f) ((f)->start) 827 828 /* Length of the field, in bits. */ 829 int length; 830#define CGEN_IFLD_LENGTH(f) ((f)->length) 831 832#ifndef CGEN_IFLD_NBOOL_ATTRS 833#define CGEN_IFLD_NBOOL_ATTRS 1 834#endif 835 CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; 836#define CGEN_IFLD_ATTRS(f) (&(f)->attrs) 837} CGEN_IFLD; 838 839/* Return value of attribute ATTR in IFLD. */ 840#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ 841CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) 842 843/* Instruction data. */ 844 845/* Instruction formats. 846 847 Instructions are grouped by format. Associated with an instruction is its 848 format. Each insn's opcode table entry contains a format table entry. 849 ??? There is usually very few formats compared with the number of insns, 850 so one can reduce the size of the opcode table by recording the format table 851 as a separate entity. Given that we currently don't, format table entries 852 are also distinguished by their operands. This increases the size of the 853 table, but reduces the number of tables. It's all minutiae anyway so it 854 doesn't really matter [at this point in time]. 855 856 ??? Support for variable length ISA's is wip. */ 857 858/* Accompanying each iformat description is a list of its fields. */ 859 860typedef struct { 861 const CGEN_IFLD *ifld; 862#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) 863} CGEN_IFMT_IFLD; 864 865/* This should be at least as large as necessary for any target. */ 866#define CGEN_MAX_IFMT_OPERANDS 16 867 868/* A target may know its own precise maximum. Assert that it falls below 869 the above limit. */ 870#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS 871#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS 872#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS" 873#endif 874#endif 875 876 877typedef struct 878{ 879 /* Length that MASK and VALUE have been calculated to 880 [VALUE is recorded elsewhere]. 881 Normally it is base_insn_bitsize. On [V]LIW architectures where the base 882 insn size may be larger than the size of an insn, this field is less than 883 base_insn_bitsize. */ 884 unsigned char mask_length; 885#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) 886 887 /* Total length of instruction, in bits. */ 888 unsigned char length; 889#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) 890 891 /* Mask to apply to the first MASK_LENGTH bits. 892 Each insn's value is stored with the insn. 893 The first step in recognizing an insn for disassembly is 894 (opcode & mask) == value. */ 895 CGEN_INSN_INT mask; 896#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) 897 898 /* Instruction fields. 899 +1 for trailing NULL. */ 900 CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; 901#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) 902} CGEN_IFMT; 903 904/* Instruction values. */ 905 906typedef struct 907{ 908 /* The opcode portion of the base insn. */ 909 CGEN_INSN_INT base_value; 910 911#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS 912 /* Extra opcode values beyond base_value. */ 913 unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; 914#endif 915} CGEN_IVALUE; 916 917/* Instruction opcode table. 918 This contains the syntax and format data of an instruction. */ 919 920/* ??? Some ports already have an opcode table yet still need to use the rest 921 of what cgen_insn has. Plus keeping the opcode data with the operand 922 instance data can create a pretty big file. So we keep them separately. 923 Not sure this is a good idea in the long run. */ 924 925typedef struct 926{ 927 /* Indices into parse/insert/extract/print handler tables. */ 928 struct cgen_opcode_handler handlers; 929#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) 930 931 /* Syntax string. */ 932 CGEN_SYNTAX syntax; 933#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) 934 935 /* Format entry. */ 936 const CGEN_IFMT *format; 937#define CGEN_OPCODE_FORMAT(opc) ((opc)->format) 938#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) 939#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) 940#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) 941 942 /* Instruction opcode value. */ 943 CGEN_IVALUE value; 944#define CGEN_OPCODE_VALUE(opc) (& (opc)->value) 945#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) 946#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) 947} CGEN_OPCODE; 948 949/* Instruction attributes. 950 This is made a published type as applications can cache a pointer to 951 the attributes for speed. */ 952 953#ifndef CGEN_INSN_NBOOL_ATTRS 954#define CGEN_INSN_NBOOL_ATTRS 1 955#endif 956typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; 957 958/* Enum of architecture independent attributes. */ 959 960#ifndef CGEN_ARCH 961/* ??? Numbers here are recorded in two places. */ 962typedef enum cgen_insn_attr { 963 CGEN_INSN_ALIAS = 0 964} CGEN_INSN_ATTR; 965#endif 966 967/* This struct defines each entry in the instruction table. */ 968 969typedef struct 970{ 971 /* Each real instruction is enumerated. */ 972 /* ??? This may go away in time. */ 973 int num; 974#define CGEN_INSN_NUM(insn) ((insn)->base->num) 975 976 /* Name of entry (that distinguishes it from all other entries). */ 977 /* ??? If mnemonics have operands, try to print full mnemonic. */ 978 const char *name; 979#define CGEN_INSN_NAME(insn) ((insn)->base->name) 980 981 /* Mnemonic. This is used when parsing and printing the insn. 982 In the case of insns that have operands on the mnemonics, this is 983 only the constant part. E.g. for conditional execution of an `add' insn, 984 where the full mnemonic is addeq, addne, etc., and the condition is 985 treated as an operand, this is only "add". */ 986 const char *mnemonic; 987#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) 988 989 /* Total length of instruction, in bits. */ 990 int bitsize; 991#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) 992 993#if 0 /* ??? Disabled for now as there is a problem with embedded newlines 994 and the table is already pretty big. Should perhaps be moved 995 to a file of its own. */ 996 /* Semantics, as RTL. */ 997 /* ??? Plain text or bytecodes? */ 998 /* ??? Note that the operand instance table could be computed at run-time 999 if we parse this and cache the results. Something to eventually do. */ 1000 const char *rtx; 1001#define CGEN_INSN_RTX(insn) ((insn)->base->rtx) 1002#endif 1003 1004 /* Attributes. 1005 This must appear last. It is a variable sized array in that one 1006 architecture may have 1 nonbool attribute and another may have more. 1007 Having this last means the non-architecture specific code needn't 1008 care. The goal is to eventually record attributes in their raw form, 1009 evaluate them at run-time, and cache the values, so this worry will go 1010 away anyway. */ 1011 CGEN_INSN_ATTR_TYPE attrs; 1012#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) 1013/* Return value of attribute ATTR in INSN. */ 1014#define CGEN_INSN_ATTR_VALUE(insn, attr) \ 1015CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) 1016} CGEN_IBASE; 1017 1018/* Return non-zero if INSN is the "invalid" insn marker. */ 1019 1020#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) 1021 1022/* Main struct contain instruction information. 1023 BASE is always present, the rest is present only if asked for. */ 1024 1025struct cgen_insn 1026{ 1027 /* ??? May be of use to put a type indicator here. 1028 Then this struct could different info for different classes of insns. */ 1029 /* ??? A speedup can be had by moving `base' into this struct. 1030 Maybe later. */ 1031 const CGEN_IBASE *base; 1032 const CGEN_OPCODE *opcode; 1033 const CGEN_OPINST *opinst; 1034 1035 /* Regex to disambiguate overloaded opcodes */ 1036 void *rx; 1037#define CGEN_INSN_RX(insn) ((insn)->rx) 1038#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) 1039}; 1040 1041/* Instruction lists. 1042 This is used for adding new entries and for creating the hash lists. */ 1043 1044typedef struct cgen_insn_list 1045{ 1046 struct cgen_insn_list *next; 1047 const CGEN_INSN *insn; 1048} CGEN_INSN_LIST; 1049 1050/* Table of instructions. */ 1051 1052typedef struct 1053{ 1054 const CGEN_INSN *init_entries; 1055 unsigned int entry_size; /* since the attribute member is variable sized */ 1056 unsigned int num_init_entries; 1057 CGEN_INSN_LIST *new_entries; 1058} CGEN_INSN_TABLE; 1059 1060/* Return number of instructions. This includes any added at run-time. */ 1061 1062extern int cgen_insn_count PARAMS ((CGEN_CPU_DESC)); 1063extern int cgen_macro_insn_count PARAMS ((CGEN_CPU_DESC)); 1064 1065/* Macros to access the other insn elements not recorded in CGEN_IBASE. */ 1066 1067/* Fetch INSN's operand instance table. */ 1068/* ??? Doesn't handle insns added at runtime. */ 1069#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) 1070 1071/* Return INSN's opcode table entry. */ 1072#define CGEN_INSN_OPCODE(insn) ((insn)->opcode) 1073 1074/* Return INSN's handler data. */ 1075#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) 1076 1077/* Return INSN's syntax. */ 1078#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) 1079 1080/* Return size of base mask in bits. */ 1081#define CGEN_INSN_MASK_BITSIZE(insn) \ 1082 CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) 1083 1084/* Return mask of base part of INSN. */ 1085#define CGEN_INSN_BASE_MASK(insn) \ 1086 CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) 1087 1088/* Return value of base part of INSN. */ 1089#define CGEN_INSN_BASE_VALUE(insn) \ 1090 CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) 1091 1092/* Standard way to test whether INSN is supported by MACH. 1093 MACH is one of enum mach_attr. 1094 The "|1" is because the base mach is always selected. */ 1095#define CGEN_INSN_MACH_HAS_P(insn, mach) \ 1096((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) 1097 1098/* Macro instructions. 1099 Macro insns aren't real insns, they map to one or more real insns. 1100 E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or 1101 some such. 1102 1103 Macro insns can expand to nothing (e.g. a nop that is optimized away). 1104 This is useful in multi-insn macros that build a constant in a register. 1105 Of course this isn't the default behaviour and must be explicitly enabled. 1106 1107 Assembly of macro-insns is relatively straightforward. Disassembly isn't. 1108 However, disassembly of at least some kinds of macro insns is important 1109 in order that the disassembled code preserve the readability of the original 1110 insn. What is attempted here is to disassemble all "simple" macro-insns, 1111 where "simple" is currently defined to mean "expands to one real insn". 1112 1113 Simple macro-insns are handled specially. They are emitted as ALIAS's 1114 of real insns. This simplifies their handling since there's usually more 1115 of them than any other kind of macro-insn, and proper disassembly of them 1116 falls out for free. */ 1117 1118/* For each macro-insn there may be multiple expansion possibilities, 1119 depending on the arguments. This structure is accessed via the `data' 1120 member of CGEN_INSN. */ 1121 1122typedef struct cgen_minsn_expansion { 1123 /* Function to do the expansion. 1124 If the expansion fails (e.g. "no match") NULL is returned. 1125 Space for the expansion is obtained with malloc. 1126 It is up to the caller to free it. */ 1127 const char * (* fn) PARAMS ((const struct cgen_minsn_expansion *, 1128 const char *, const char **, int *, 1129 CGEN_OPERAND **)); 1130#define CGEN_MIEXPN_FN(ex) ((ex)->fn) 1131 1132 /* Instruction(s) the macro expands to. 1133 The format of STR is defined by FN. 1134 It is typically the assembly code of the real insn, but it could also be 1135 the original Scheme expression or a tokenized form of it (with FN being 1136 an appropriate interpreter). */ 1137 const char * str; 1138#define CGEN_MIEXPN_STR(ex) ((ex)->str) 1139} CGEN_MINSN_EXPANSION; 1140 1141/* Normal expander. 1142 When supported, this function will convert the input string to another 1143 string and the parser will be invoked recursively. The output string 1144 may contain further macro invocations. */ 1145 1146extern const char * cgen_expand_macro_insn 1147 PARAMS ((CGEN_CPU_DESC, const struct cgen_minsn_expansion *, 1148 const char *, const char **, int *, CGEN_OPERAND **)); 1149 1150/* The assembler insn table is hashed based on some function of the mnemonic 1151 (the actually hashing done is up to the target, but we provide a few 1152 examples like the first letter or a function of the entire mnemonic). */ 1153 1154extern CGEN_INSN_LIST * cgen_asm_lookup_insn 1155 PARAMS ((CGEN_CPU_DESC, const char *)); 1156#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) 1157#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) 1158 1159/* The disassembler insn table is hashed based on some function of machine 1160 instruction (the actually hashing done is up to the target). */ 1161 1162extern CGEN_INSN_LIST * cgen_dis_lookup_insn 1163 PARAMS ((CGEN_CPU_DESC, const char *, CGEN_INSN_INT)); 1164/* FIXME: delete these two */ 1165#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) 1166#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) 1167 1168/* The CPU description. 1169 A copy of this is created when the cpu table is "opened". 1170 All global state information is recorded here. 1171 Access macros are provided for "public" members. */ 1172 1173typedef struct cgen_cpu_desc 1174{ 1175 /* Bitmap of selected machine(s) (a la BFD machine number). */ 1176 int machs; 1177 1178 /* Bitmap of selected isa(s). 1179 ??? Simultaneous multiple isas might not make sense, but it's not (yet) 1180 precluded. */ 1181 int isas; 1182 1183 /* Current endian. */ 1184 enum cgen_endian endian; 1185#define CGEN_CPU_ENDIAN(cd) ((cd)->endian) 1186 1187 /* Current insn endian. */ 1188 enum cgen_endian insn_endian; 1189#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) 1190 1191 /* Word size (in bits). */ 1192 /* ??? Or maybe maximum word size - might we ever need to allow a cpu table 1193 to be opened for both sparc32/sparc64? 1194 ??? Another alternative is to create a table of selected machs and 1195 lazily fetch the data from there. */ 1196 unsigned int word_bitsize; 1197 1198 /* Instruction chunk size (in bits), for purposes of endianness 1199 conversion. */ 1200 unsigned int insn_chunk_bitsize; 1201 1202 /* Indicator if sizes are unknown. 1203 This is used by default_insn_bitsize,base_insn_bitsize if there is a 1204 difference between the selected isa's. */ 1205#define CGEN_SIZE_UNKNOWN 65535 1206 1207 /* Default instruction size (in bits). 1208 This is used by the assembler when it encounters an unknown insn. */ 1209 unsigned int default_insn_bitsize; 1210 1211 /* Base instruction size (in bits). 1212 For non-LIW cpus this is generally the length of the smallest insn. 1213 For LIW cpus its wip (work-in-progress). For the m32r its 32. */ 1214 unsigned int base_insn_bitsize; 1215 1216 /* Minimum/maximum instruction size (in bits). */ 1217 unsigned int min_insn_bitsize; 1218 unsigned int max_insn_bitsize; 1219 1220 /* Instruction set variants. */ 1221 const CGEN_ISA *isa_table; 1222 1223 /* Machine variants. */ 1224 const CGEN_MACH *mach_table; 1225 1226 /* Hardware elements. */ 1227 CGEN_HW_TABLE hw_table; 1228 1229 /* Instruction fields. */ 1230 const CGEN_IFLD *ifld_table; 1231 1232 /* Operands. */ 1233 CGEN_OPERAND_TABLE operand_table; 1234 1235 /* Main instruction table. */ 1236 CGEN_INSN_TABLE insn_table; 1237#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) 1238 1239 /* Macro instructions are defined separately and are combined with real 1240 insns during hash table computation. */ 1241 CGEN_INSN_TABLE macro_insn_table; 1242 1243 /* Copy of CGEN_INT_INSN_P. */ 1244 int int_insn_p; 1245 1246 /* Called to rebuild the tables after something has changed. */ 1247 void (*rebuild_tables) PARAMS ((CGEN_CPU_DESC)); 1248 1249 /* Operand parser callback. */ 1250 cgen_parse_operand_fn * parse_operand_fn; 1251 1252 /* Parse/insert/extract/print cover fns for operands. */ 1253 const char * (*parse_operand) 1254 PARAMS ((CGEN_CPU_DESC, int opindex_, const char **, 1255 CGEN_FIELDS *fields_)); 1256#ifdef BFD_VERSION 1257 const char * (*insert_operand) 1258 PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, 1259 CGEN_INSN_BYTES_PTR, bfd_vma pc_)); 1260 int (*extract_operand) 1261 PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 1262 CGEN_FIELDS *fields_, bfd_vma pc_)); 1263 void (*print_operand) 1264 PARAMS ((CGEN_CPU_DESC, int opindex_, PTR info_, CGEN_FIELDS * fields_, 1265 void const *attrs_, bfd_vma pc_, int length_)); 1266#else 1267 const char * (*insert_operand) (); 1268 int (*extract_operand) (); 1269 void (*print_operand) (); 1270#endif 1271#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) 1272#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) 1273#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) 1274#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) 1275 1276 /* Size of CGEN_FIELDS struct. */ 1277 unsigned int sizeof_fields; 1278#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) 1279 1280 /* Set the bitsize field. */ 1281 void (*set_fields_bitsize) PARAMS ((CGEN_FIELDS *fields_, int size_)); 1282#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) 1283 1284 /* CGEN_FIELDS accessors. */ 1285 int (*get_int_operand) 1286 PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); 1287 void (*set_int_operand) 1288 PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_)); 1289#ifdef BFD_VERSION 1290 bfd_vma (*get_vma_operand) 1291 PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); 1292 void (*set_vma_operand) 1293 PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_)); 1294#else 1295 long (*get_vma_operand) (); 1296 void (*set_vma_operand) (); 1297#endif 1298#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) 1299#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) 1300#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) 1301#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) 1302 1303 /* Instruction parse/insert/extract/print handlers. */ 1304 /* FIXME: make these types uppercase. */ 1305 cgen_parse_fn * const *parse_handlers; 1306 cgen_insert_fn * const *insert_handlers; 1307 cgen_extract_fn * const *extract_handlers; 1308 cgen_print_fn * const *print_handlers; 1309#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) 1310#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) 1311#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) 1312#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) 1313 1314 /* Return non-zero if insn should be added to hash table. */ 1315 int (* asm_hash_p) PARAMS ((const CGEN_INSN *)); 1316 1317 /* Assembler hash function. */ 1318 unsigned int (* asm_hash) PARAMS ((const char *)); 1319 1320 /* Number of entries in assembler hash table. */ 1321 unsigned int asm_hash_size; 1322 1323 /* Return non-zero if insn should be added to hash table. */ 1324 int (* dis_hash_p) PARAMS ((const CGEN_INSN *)); 1325 1326 /* Disassembler hash function. */ 1327 unsigned int (* dis_hash) PARAMS ((const char *, CGEN_INSN_INT)); 1328 1329 /* Number of entries in disassembler hash table. */ 1330 unsigned int dis_hash_size; 1331 1332 /* Assembler instruction hash table. */ 1333 CGEN_INSN_LIST **asm_hash_table; 1334 CGEN_INSN_LIST *asm_hash_table_entries; 1335 1336 /* Disassembler instruction hash table. */ 1337 CGEN_INSN_LIST **dis_hash_table; 1338 CGEN_INSN_LIST *dis_hash_table_entries; 1339 1340 /* This field could be turned into a bitfield if room for other flags is needed. */ 1341 unsigned int signed_overflow_ok_p; 1342 1343} CGEN_CPU_TABLE; 1344 1345/* wip */ 1346#ifndef CGEN_WORD_ENDIAN 1347#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) 1348#endif 1349#ifndef CGEN_INSN_WORD_ENDIAN 1350#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) 1351#endif 1352 1353/* Prototypes of major functions. */ 1354/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. 1355 Not the init fns though, as that would drag in things that mightn't be 1356 used and might not even exist. */ 1357 1358/* Argument types to cpu_open. */ 1359 1360enum cgen_cpu_open_arg { 1361 CGEN_CPU_OPEN_END, 1362 /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ 1363 CGEN_CPU_OPEN_ISAS, 1364 /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ 1365 CGEN_CPU_OPEN_MACHS, 1366 /* Select machine, arg is mach's bfd name. 1367 Multiple machines can be specified by repeated use. */ 1368 CGEN_CPU_OPEN_BFDMACH, 1369 /* Select endian, arg is CGEN_ENDIAN_*. */ 1370 CGEN_CPU_OPEN_ENDIAN 1371}; 1372 1373/* Open a cpu descriptor table for use. 1374 ??? We only support ISO C stdargs here, not K&R. 1375 Laziness, plus experiment to see if anything requires K&R - eventually 1376 K&R will no longer be supported - e.g. GDB is currently trying this. */ 1377 1378extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); 1379 1380/* Cover fn to handle simple case. */ 1381 1382extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) PARAMS ((const char *mach_name_, 1383 enum cgen_endian endian_)); 1384 1385/* Close it. */ 1386 1387extern void CGEN_SYM (cpu_close) PARAMS ((CGEN_CPU_DESC)); 1388 1389/* Initialize the opcode table for use. 1390 Called by init_asm/init_dis. */ 1391 1392extern void CGEN_SYM (init_opcode_table) PARAMS ((CGEN_CPU_DESC cd_)); 1393 1394/* build the insn selection regex. 1395 called by init_opcode_table */ 1396 1397extern char * CGEN_SYM(build_insn_regex) PARAMS ((CGEN_INSN *insn_)); 1398 1399/* Initialize the ibld table for use. 1400 Called by init_asm/init_dis. */ 1401 1402extern void CGEN_SYM (init_ibld_table) PARAMS ((CGEN_CPU_DESC cd_)); 1403 1404/* Initialize an cpu table for assembler or disassembler use. 1405 These must be called immediately after cpu_open. */ 1406 1407extern void CGEN_SYM (init_asm) PARAMS ((CGEN_CPU_DESC)); 1408extern void CGEN_SYM (init_dis) PARAMS ((CGEN_CPU_DESC)); 1409 1410/* Initialize the operand instance table for use. */ 1411 1412extern void CGEN_SYM (init_opinst_table) PARAMS ((CGEN_CPU_DESC cd_)); 1413 1414/* Assemble an instruction. */ 1415 1416extern const CGEN_INSN * CGEN_SYM (assemble_insn) 1417 PARAMS ((CGEN_CPU_DESC, const char *, CGEN_FIELDS *, 1418 CGEN_INSN_BYTES_PTR, char **)); 1419 1420extern const CGEN_KEYWORD CGEN_SYM (operand_mach); 1421extern int CGEN_SYM (get_mach) PARAMS ((const char *)); 1422 1423/* Operand index computation. */ 1424extern const CGEN_INSN * cgen_lookup_insn 1425 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN * insn_, 1426 CGEN_INSN_INT int_value_, unsigned char *bytes_value_, 1427 int length_, CGEN_FIELDS *fields_, int alias_p_)); 1428extern void cgen_get_insn_operands 1429 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN * insn_, 1430 const CGEN_FIELDS *fields_, int *indices_)); 1431extern const CGEN_INSN * cgen_lookup_get_insn_operands 1432 PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, 1433 CGEN_INSN_INT int_value_, unsigned char *bytes_value_, 1434 int length_, int *indices_, CGEN_FIELDS *fields_)); 1435 1436/* Cover fns to bfd_get/set. */ 1437 1438extern CGEN_INSN_INT cgen_get_insn_value 1439 PARAMS ((CGEN_CPU_DESC, unsigned char *, int)); 1440extern void cgen_put_insn_value 1441 PARAMS ((CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT)); 1442 1443/* Read in a cpu description file. 1444 ??? For future concerns, including adding instructions to the assembler/ 1445 disassembler at run-time. */ 1446 1447extern const char * cgen_read_cpu_file 1448 PARAMS ((CGEN_CPU_DESC, const char * filename_)); 1449 1450/* Allow signed overflow of instruction fields. */ 1451extern void cgen_set_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); 1452 1453/* Generate an error message if a signed field in an instruction overflows. */ 1454extern void cgen_clear_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); 1455 1456/* Will an error message be generated if a signed field in an instruction overflows ? */ 1457extern unsigned int cgen_signed_overflow_ok_p PARAMS ((CGEN_CPU_DESC)); 1458 1459#endif /* CGEN_H */ 1460