c-sh.texi revision 94536
1@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001 2@c Free Software Foundation, Inc. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@page 6@node SH-Dependent 7@chapter Hitachi SH Dependent Features 8 9@cindex SH support 10@menu 11* SH Options:: Options 12* SH Syntax:: Syntax 13* SH Floating Point:: Floating Point 14* SH Directives:: SH Machine Directives 15* SH Opcodes:: Opcodes 16@end menu 17 18@node SH Options 19@section Options 20 21@cindex SH options 22@cindex options, SH 23@code{@value{AS}} has following command-line options for the Hitachi 24SH family. 25 26@table @code 27@kindex -little 28@kindex -big 29@kindex -relax 30@kindex -small 31@kindex -dsp 32 33@item -little 34Generate little endian code. 35 36@item -big 37Generate big endian code. 38 39@item -relax 40Alter jump instructions for long displacements. 41 42@item -small 43Align sections to 4 byte boundaries, not 16. 44 45@item -dsp 46Enable sh-dsp insns, and disable sh3e / sh4 insns. 47 48@end table 49 50@node SH Syntax 51@section Syntax 52 53@menu 54* SH-Chars:: Special Characters 55* SH-Regs:: Register Names 56* SH-Addressing:: Addressing Modes 57@end menu 58 59@node SH-Chars 60@subsection Special Characters 61 62@cindex line comment character, SH 63@cindex SH line comment character 64@samp{!} is the line comment character. 65 66@cindex line separator, SH 67@cindex statement separator, SH 68@cindex SH line separator 69You can use @samp{;} instead of a newline to separate statements. 70 71@cindex symbol names, @samp{$} in 72@cindex @code{$} in symbol names 73Since @samp{$} has no special meaning, you may use it in symbol names. 74 75@node SH-Regs 76@subsection Register Names 77 78@cindex SH registers 79@cindex registers, SH 80You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2}, 81@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8}, 82@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14}, 83and @samp{r15} to refer to the SH registers. 84 85The SH also has these control registers: 86 87@table @code 88@item pr 89procedure register (holds return address) 90 91@item pc 92program counter 93 94@item mach 95@itemx macl 96high and low multiply accumulator registers 97 98@item sr 99status register 100 101@item gbr 102global base register 103 104@item vbr 105vector base register (for interrupt vectors) 106@end table 107 108@node SH-Addressing 109@subsection Addressing Modes 110 111@cindex addressing modes, SH 112@cindex SH addressing modes 113@code{@value{AS}} understands the following addressing modes for the SH. 114@code{R@var{n}} in the following refers to any of the numbered 115registers, but @emph{not} the control registers. 116 117@table @code 118@item R@var{n} 119Register direct 120 121@item @@R@var{n} 122Register indirect 123 124@item @@-R@var{n} 125Register indirect with pre-decrement 126 127@item @@R@var{n}+ 128Register indirect with post-increment 129 130@item @@(@var{disp}, R@var{n}) 131Register indirect with displacement 132 133@item @@(R0, R@var{n}) 134Register indexed 135 136@item @@(@var{disp}, GBR) 137@code{GBR} offset 138 139@item @@(R0, GBR) 140GBR indexed 141 142@item @var{addr} 143@itemx @@(@var{disp}, PC) 144PC relative address (for branch or for addressing memory). The 145@code{@value{AS}} implementation allows you to use the simpler form 146@var{addr} anywhere a PC relative address is called for; the alternate 147form is supported for compatibility with other assemblers. 148 149@item #@var{imm} 150Immediate data 151@end table 152 153@node SH Floating Point 154@section Floating Point 155 156@cindex floating point, SH (@sc{ieee}) 157@cindex SH floating point (@sc{ieee}) 158The SH family has no hardware floating point, but the @code{.float} 159directive generates @sc{ieee} floating-point numbers for compatibility 160with other development tools. 161 162@node SH Directives 163@section SH Machine Directives 164 165@cindex SH machine directives 166@cindex machine directives, SH 167@cindex @code{uaword} directive, SH 168@cindex @code{ualong} directive, SH 169 170@table @code 171@item uaword 172@itemx ualong 173@code{@value{AS}} will issue a warning when a misaligned @code{.word} or 174@code{.long} directive is used. You may use @code{.uaword} or 175@code{.ualong} to indicate that the value is intentionally misaligned. 176@end table 177 178@node SH Opcodes 179@section Opcodes 180 181@cindex SH opcode summary 182@cindex opcode summary, SH 183@cindex mnemonics, SH 184@cindex instruction summary, SH 185For detailed information on the SH machine instruction set, see 186@cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.). 187 188@code{@value{AS}} implements all the standard SH opcodes. No additional 189pseudo-instructions are needed on this family. Note, however, that 190because @code{@value{AS}} supports a simpler form of PC-relative 191addressing, you may simply write (for example) 192 193@example 194mov.l bar,r0 195@end example 196 197@noindent 198where other assemblers might require an explicit displacement to 199@code{bar} from the program counter: 200 201@example 202mov.l @@(@var{disp}, PC) 203@end example 204 205@ifset SMALL 206@c this table, due to the multi-col faking and hardcoded order, looks silly 207@c except in smallbook. See comments below "@set SMALL" near top of this file. 208 209Here is a summary of SH opcodes: 210 211@page 212@smallexample 213@i{Legend:} 214Rn @r{a numbered register} 215Rm @r{another numbered register} 216#imm @r{immediate data} 217disp @r{displacement} 218disp8 @r{8-bit displacement} 219disp12 @r{12-bit displacement} 220 221add #imm,Rn lds.l @@Rn+,PR 222add Rm,Rn mac.w @@Rm+,@@Rn+ 223addc Rm,Rn mov #imm,Rn 224addv Rm,Rn mov Rm,Rn 225and #imm,R0 mov.b Rm,@@(R0,Rn) 226and Rm,Rn mov.b Rm,@@-Rn 227and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn 228bf disp8 mov.b @@(disp,Rm),R0 229bra disp12 mov.b @@(disp,GBR),R0 230bsr disp12 mov.b @@(R0,Rm),Rn 231bt disp8 mov.b @@Rm+,Rn 232clrmac mov.b @@Rm,Rn 233clrt mov.b R0,@@(disp,Rm) 234cmp/eq #imm,R0 mov.b R0,@@(disp,GBR) 235cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn) 236cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn) 237cmp/gt Rm,Rn mov.l Rm,@@-Rn 238cmp/hi Rm,Rn mov.l Rm,@@Rn 239cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm 240cmp/pl Rn mov.l @@(disp,GBR),R0 241cmp/pz Rn mov.l @@(disp,PC),Rn 242cmp/str Rm,Rn mov.l @@(R0,Rm),Rn 243div0s Rm,Rn mov.l @@Rm+,Rn 244div0u mov.l @@Rm,Rn 245div1 Rm,Rn mov.l R0,@@(disp,GBR) 246exts.b Rm,Rn mov.w Rm,@@(R0,Rn) 247exts.w Rm,Rn mov.w Rm,@@-Rn 248extu.b Rm,Rn mov.w Rm,@@Rn 249extu.w Rm,Rn mov.w @@(disp,Rm),R0 250jmp @@Rn mov.w @@(disp,GBR),R0 251jsr @@Rn mov.w @@(disp,PC),Rn 252ldc Rn,GBR mov.w @@(R0,Rm),Rn 253ldc Rn,SR mov.w @@Rm+,Rn 254ldc Rn,VBR mov.w @@Rm,Rn 255ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm) 256ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR) 257ldc.l @@Rn+,VBR mova @@(disp,PC),R0 258lds Rn,MACH movt Rn 259lds Rn,MACL muls Rm,Rn 260lds Rn,PR mulu Rm,Rn 261lds.l @@Rn+,MACH neg Rm,Rn 262lds.l @@Rn+,MACL negc Rm,Rn 263@page 264nop stc VBR,Rn 265not Rm,Rn stc.l GBR,@@-Rn 266or #imm,R0 stc.l SR,@@-Rn 267or Rm,Rn stc.l VBR,@@-Rn 268or.b #imm,@@(R0,GBR) sts MACH,Rn 269rotcl Rn sts MACL,Rn 270rotcr Rn sts PR,Rn 271rotl Rn sts.l MACH,@@-Rn 272rotr Rn sts.l MACL,@@-Rn 273rte sts.l PR,@@-Rn 274rts sub Rm,Rn 275sett subc Rm,Rn 276shal Rn subv Rm,Rn 277shar Rn swap.b Rm,Rn 278shll Rn swap.w Rm,Rn 279shll16 Rn tas.b @@Rn 280shll2 Rn trapa #imm 281shll8 Rn tst #imm,R0 282shlr Rn tst Rm,Rn 283shlr16 Rn tst.b #imm,@@(R0,GBR) 284shlr2 Rn xor #imm,R0 285shlr8 Rn xor Rm,Rn 286sleep xor.b #imm,@@(R0,GBR) 287stc GBR,Rn xtrct Rm,Rn 288stc SR,Rn 289@end smallexample 290@end ifset 291 292@ifset Hitachi-all 293@ifclear GENERIC 294@raisesections 295@end ifclear 296@end ifset 297 298