c-sh.texi revision 38889
1@c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@page 5@node SH-Dependent 6@chapter Hitachi SH Dependent Features 7 8@cindex SH support 9@menu 10* SH Options:: Options 11* SH Syntax:: Syntax 12* SH Floating Point:: Floating Point 13* SH Directives:: SH Machine Directives 14* SH Opcodes:: Opcodes 15@end menu 16 17@node SH Options 18@section Options 19 20@cindex SH options (none) 21@cindex options, SH (none) 22@code{@value{AS}} has no additional command-line options for the Hitachi 23SH family. 24 25@node SH Syntax 26@section Syntax 27 28@menu 29* SH-Chars:: Special Characters 30* SH-Regs:: Register Names 31* SH-Addressing:: Addressing Modes 32@end menu 33 34@node SH-Chars 35@subsection Special Characters 36 37@cindex line comment character, SH 38@cindex SH line comment character 39@samp{!} is the line comment character. 40 41@cindex line separator, SH 42@cindex statement separator, SH 43@cindex SH line separator 44You can use @samp{;} instead of a newline to separate statements. 45 46@cindex symbol names, @samp{$} in 47@cindex @code{$} in symbol names 48Since @samp{$} has no special meaning, you may use it in symbol names. 49 50@node SH-Regs 51@subsection Register Names 52 53@cindex SH registers 54@cindex registers, SH 55You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2}, 56@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8}, 57@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14}, 58and @samp{r15} to refer to the SH registers. 59 60The SH also has these control registers: 61 62@table @code 63@item pr 64procedure register (holds return address) 65 66@item pc 67program counter 68 69@item mach 70@itemx macl 71high and low multiply accumulator registers 72 73@item sr 74status register 75 76@item gbr 77global base register 78 79@item vbr 80vector base register (for interrupt vectors) 81@end table 82 83@node SH-Addressing 84@subsection Addressing Modes 85 86@cindex addressing modes, SH 87@cindex SH addressing modes 88@code{@value{AS}} understands the following addressing modes for the SH. 89@code{R@var{n}} in the following refers to any of the numbered 90registers, but @emph{not} the control registers. 91 92@table @code 93@item R@var{n} 94Register direct 95 96@item @@R@var{n} 97Register indirect 98 99@item @@-R@var{n} 100Register indirect with pre-decrement 101 102@item @@R@var{n}+ 103Register indirect with post-increment 104 105@item @@(@var{disp}, R@var{n}) 106Register indirect with displacement 107 108@item @@(R0, R@var{n}) 109Register indexed 110 111@item @@(@var{disp}, GBR) 112@code{GBR} offset 113 114@item @@(R0, GBR) 115GBR indexed 116 117@item @var{addr} 118@itemx @@(@var{disp}, PC) 119PC relative address (for branch or for addressing memory). The 120@code{@value{AS}} implementation allows you to use the simpler form 121@var{addr} anywhere a PC relative address is called for; the alternate 122form is supported for compatibility with other assemblers. 123 124@item #@var{imm} 125Immediate data 126@end table 127 128@node SH Floating Point 129@section Floating Point 130 131@cindex floating point, SH (@sc{ieee}) 132@cindex SH floating point (@sc{ieee}) 133The SH family has no hardware floating point, but the @code{.float} 134directive generates @sc{ieee} floating-point numbers for compatibility 135with other development tools. 136 137@node SH Directives 138@section SH Machine Directives 139 140@cindex SH machine directives 141@cindex machine directives, SH 142@cindex @code{uaword} directive, SH 143@cindex @code{ualong} directive, SH 144 145@table @code 146@item uaword 147@itemx ualong 148@code{@value{AS}} will issue a warning when a misaligned @code{.word} or 149@code{.long} directive is used. You may use @code{.uaword} or 150@code{.ualong} to indicate that the value is intentionally misaligned. 151@end table 152 153@node SH Opcodes 154@section Opcodes 155 156@cindex SH opcode summary 157@cindex opcode summary, SH 158@cindex mnemonics, SH 159@cindex instruction summary, SH 160For detailed information on the SH machine instruction set, see 161@cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.). 162 163@code{@value{AS}} implements all the standard SH opcodes. No additional 164pseudo-instructions are needed on this family. Note, however, that 165because @code{@value{AS}} supports a simpler form of PC-relative 166addressing, you may simply write (for example) 167 168@example 169mov.l bar,r0 170@end example 171 172@noindent 173where other assemblers might require an explicit displacement to 174@code{bar} from the program counter: 175 176@example 177mov.l @@(@var{disp}, PC) 178@end example 179 180@ifset SMALL 181@c this table, due to the multi-col faking and hardcoded order, looks silly 182@c except in smallbook. See comments below "@set SMALL" near top of this file. 183 184Here is a summary of SH opcodes: 185 186@page 187@smallexample 188@i{Legend:} 189Rn @r{a numbered register} 190Rm @r{another numbered register} 191#imm @r{immediate data} 192disp @r{displacement} 193disp8 @r{8-bit displacement} 194disp12 @r{12-bit displacement} 195 196add #imm,Rn lds.l @@Rn+,PR 197add Rm,Rn mac.w @@Rm+,@@Rn+ 198addc Rm,Rn mov #imm,Rn 199addv Rm,Rn mov Rm,Rn 200and #imm,R0 mov.b Rm,@@(R0,Rn) 201and Rm,Rn mov.b Rm,@@-Rn 202and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn 203bf disp8 mov.b @@(disp,Rm),R0 204bra disp12 mov.b @@(disp,GBR),R0 205bsr disp12 mov.b @@(R0,Rm),Rn 206bt disp8 mov.b @@Rm+,Rn 207clrmac mov.b @@Rm,Rn 208clrt mov.b R0,@@(disp,Rm) 209cmp/eq #imm,R0 mov.b R0,@@(disp,GBR) 210cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn) 211cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn) 212cmp/gt Rm,Rn mov.l Rm,@@-Rn 213cmp/hi Rm,Rn mov.l Rm,@@Rn 214cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm 215cmp/pl Rn mov.l @@(disp,GBR),R0 216cmp/pz Rn mov.l @@(disp,PC),Rn 217cmp/str Rm,Rn mov.l @@(R0,Rm),Rn 218div0s Rm,Rn mov.l @@Rm+,Rn 219div0u mov.l @@Rm,Rn 220div1 Rm,Rn mov.l R0,@@(disp,GBR) 221exts.b Rm,Rn mov.w Rm,@@(R0,Rn) 222exts.w Rm,Rn mov.w Rm,@@-Rn 223extu.b Rm,Rn mov.w Rm,@@Rn 224extu.w Rm,Rn mov.w @@(disp,Rm),R0 225jmp @@Rn mov.w @@(disp,GBR),R0 226jsr @@Rn mov.w @@(disp,PC),Rn 227ldc Rn,GBR mov.w @@(R0,Rm),Rn 228ldc Rn,SR mov.w @@Rm+,Rn 229ldc Rn,VBR mov.w @@Rm,Rn 230ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm) 231ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR) 232ldc.l @@Rn+,VBR mova @@(disp,PC),R0 233lds Rn,MACH movt Rn 234lds Rn,MACL muls Rm,Rn 235lds Rn,PR mulu Rm,Rn 236lds.l @@Rn+,MACH neg Rm,Rn 237lds.l @@Rn+,MACL negc Rm,Rn 238@page 239nop stc VBR,Rn 240not Rm,Rn stc.l GBR,@@-Rn 241or #imm,R0 stc.l SR,@@-Rn 242or Rm,Rn stc.l VBR,@@-Rn 243or.b #imm,@@(R0,GBR) sts MACH,Rn 244rotcl Rn sts MACL,Rn 245rotcr Rn sts PR,Rn 246rotl Rn sts.l MACH,@@-Rn 247rotr Rn sts.l MACL,@@-Rn 248rte sts.l PR,@@-Rn 249rts sub Rm,Rn 250sett subc Rm,Rn 251shal Rn subv Rm,Rn 252shar Rn swap.b Rm,Rn 253shll Rn swap.w Rm,Rn 254shll16 Rn tas.b @@Rn 255shll2 Rn trapa #imm 256shll8 Rn tst #imm,R0 257shlr Rn tst Rm,Rn 258shlr16 Rn tst.b #imm,@@(R0,GBR) 259shlr2 Rn xor #imm,R0 260shlr8 Rn xor Rm,Rn 261sleep xor.b #imm,@@(R0,GBR) 262stc GBR,Rn xtrct Rm,Rn 263stc SR,Rn 264@end smallexample 265@end ifset 266 267@ifset Hitachi-all 268@ifclear GENERIC 269@raisesections 270@end ifclear 271@end ifset 272 273