c-sh.texi revision 33965
1@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@page 5@node SH-Dependent 6@chapter Hitachi SH Dependent Features 7 8@cindex SH support 9@menu 10* SH Options:: Options 11* SH Syntax:: Syntax 12* SH Floating Point:: Floating Point 13* SH Directives:: SH Machine Directives 14* SH Opcodes:: Opcodes 15@end menu 16 17@node SH Options 18@section Options 19 20@cindex SH options (none) 21@cindex options, SH (none) 22@code{@value{AS}} has no additional command-line options for the Hitachi 23SH family. 24 25@node SH Syntax 26@section Syntax 27 28@menu 29* SH-Chars:: Special Characters 30* SH-Regs:: Register Names 31* SH-Addressing:: Addressing Modes 32@end menu 33 34@node SH-Chars 35@subsection Special Characters 36 37@cindex line comment character, SH 38@cindex SH line comment character 39@samp{!} is the line comment character. 40 41@cindex line separator, SH 42@cindex statement separator, SH 43@cindex SH line separator 44You can use @samp{;} instead of a newline to separate statements. 45 46@cindex symbol names, @samp{$} in 47@cindex @code{$} in symbol names 48Since @samp{$} has no special meaning, you may use it in symbol names. 49 50@node SH-Regs 51@subsection Register Names 52 53@cindex SH registers 54@cindex registers, SH 55You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2}, 56@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8}, 57@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14}, 58and @samp{r15} to refer to the SH registers. 59 60The SH also has these control registers: 61 62@table @code 63@item pr 64procedure register (holds return address) 65 66@item pc 67program counter 68 69@item mach 70@itemx macl 71high and low multiply accumulator registers 72 73@item sr 74status register 75 76@item gbr 77global base register 78 79@item vbr 80vector base register (for interrupt vectors) 81@end table 82 83@node SH-Addressing 84@subsection Addressing Modes 85 86@cindex addressing modes, SH 87@cindex SH addressing modes 88@code{@value{AS}} understands the following addressing modes for the SH. 89@code{R@var{n}} in the following refers to any of the numbered 90registers, but @emph{not} the control registers. 91 92@table @code 93@item R@var{n} 94Register direct 95 96@item @@R@var{n} 97Register indirect 98 99@item @@-R@var{n} 100Register indirect with pre-decrement 101 102@item @@R@var{n}+ 103Register indirect with post-increment 104 105@item @@(@var{disp}, R@var{n}) 106Register indirect with displacement 107 108@item @@(R0, R@var{n}) 109Register indexed 110 111@item @@(@var{disp}, GBR) 112@code{GBR} offset 113 114@item @@(R0, GBR) 115GBR indexed 116 117@item @var{addr} 118@itemx @@(@var{disp}, PC) 119PC relative address (for branch or for addressing memory). The 120@code{@value{AS}} implementation allows you to use the simpler form 121@var{addr} anywhere a PC relative address is called for; the alternate 122form is supported for compatibility with other assemblers. 123 124@item #@var{imm} 125Immediate data 126@end table 127 128@node SH Floating Point 129@section Floating Point 130 131@cindex floating point, SH (@sc{ieee}) 132@cindex SH floating point (@sc{ieee}) 133The SH family has no hardware floating point, but the @code{.float} 134directive generates @sc{ieee} floating-point numbers for compatibility 135with other development tools. 136 137@node SH Directives 138@section SH Machine Directives 139 140@cindex SH machine directives (none) 141@cindex machine directives, SH (none) 142@cindex @code{word} directive, SH 143@cindex @code{int} directive, SH 144@code{@value{AS}} has no machine-dependent directives for the SH. 145 146@node SH Opcodes 147@section Opcodes 148 149@cindex SH opcode summary 150@cindex opcode summary, SH 151@cindex mnemonics, SH 152@cindex instruction summary, SH 153For detailed information on the SH machine instruction set, see 154@cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.). 155 156@code{@value{AS}} implements all the standard SH opcodes. No additional 157pseudo-instructions are needed on this family. Note, however, that 158because @code{@value{AS}} supports a simpler form of PC-relative 159addressing, you may simply write (for example) 160 161@example 162mov.l bar,r0 163@end example 164 165@noindent 166where other assemblers might require an explicit displacement to 167@code{bar} from the program counter: 168 169@example 170mov.l @@(@var{disp}, PC) 171@end example 172 173@ifset SMALL 174@c this table, due to the multi-col faking and hardcoded order, looks silly 175@c except in smallbook. See comments below "@set SMALL" near top of this file. 176 177Here is a summary of SH opcodes: 178 179@page 180@smallexample 181@i{Legend:} 182Rn @r{a numbered register} 183Rm @r{another numbered register} 184#imm @r{immediate data} 185disp @r{displacement} 186disp8 @r{8-bit displacement} 187disp12 @r{12-bit displacement} 188 189add #imm,Rn lds.l @@Rn+,PR 190add Rm,Rn mac.w @@Rm+,@@Rn+ 191addc Rm,Rn mov #imm,Rn 192addv Rm,Rn mov Rm,Rn 193and #imm,R0 mov.b Rm,@@(R0,Rn) 194and Rm,Rn mov.b Rm,@@-Rn 195and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn 196bf disp8 mov.b @@(disp,Rm),R0 197bra disp12 mov.b @@(disp,GBR),R0 198bsr disp12 mov.b @@(R0,Rm),Rn 199bt disp8 mov.b @@Rm+,Rn 200clrmac mov.b @@Rm,Rn 201clrt mov.b R0,@@(disp,Rm) 202cmp/eq #imm,R0 mov.b R0,@@(disp,GBR) 203cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn) 204cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn) 205cmp/gt Rm,Rn mov.l Rm,@@-Rn 206cmp/hi Rm,Rn mov.l Rm,@@Rn 207cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm 208cmp/pl Rn mov.l @@(disp,GBR),R0 209cmp/pz Rn mov.l @@(disp,PC),Rn 210cmp/str Rm,Rn mov.l @@(R0,Rm),Rn 211div0s Rm,Rn mov.l @@Rm+,Rn 212div0u mov.l @@Rm,Rn 213div1 Rm,Rn mov.l R0,@@(disp,GBR) 214exts.b Rm,Rn mov.w Rm,@@(R0,Rn) 215exts.w Rm,Rn mov.w Rm,@@-Rn 216extu.b Rm,Rn mov.w Rm,@@Rn 217extu.w Rm,Rn mov.w @@(disp,Rm),R0 218jmp @@Rn mov.w @@(disp,GBR),R0 219jsr @@Rn mov.w @@(disp,PC),Rn 220ldc Rn,GBR mov.w @@(R0,Rm),Rn 221ldc Rn,SR mov.w @@Rm+,Rn 222ldc Rn,VBR mov.w @@Rm,Rn 223ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm) 224ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR) 225ldc.l @@Rn+,VBR mova @@(disp,PC),R0 226lds Rn,MACH movt Rn 227lds Rn,MACL muls Rm,Rn 228lds Rn,PR mulu Rm,Rn 229lds.l @@Rn+,MACH neg Rm,Rn 230lds.l @@Rn+,MACL negc Rm,Rn 231@page 232nop stc VBR,Rn 233not Rm,Rn stc.l GBR,@@-Rn 234or #imm,R0 stc.l SR,@@-Rn 235or Rm,Rn stc.l VBR,@@-Rn 236or.b #imm,@@(R0,GBR) sts MACH,Rn 237rotcl Rn sts MACL,Rn 238rotcr Rn sts PR,Rn 239rotl Rn sts.l MACH,@@-Rn 240rotr Rn sts.l MACL,@@-Rn 241rte sts.l PR,@@-Rn 242rts sub Rm,Rn 243sett subc Rm,Rn 244shal Rn subv Rm,Rn 245shar Rn swap.b Rm,Rn 246shll Rn swap.w Rm,Rn 247shll16 Rn tas.b @@Rn 248shll2 Rn trapa #imm 249shll8 Rn tst #imm,R0 250shlr Rn tst Rm,Rn 251shlr16 Rn tst.b #imm,@@(R0,GBR) 252shlr2 Rn xor #imm,R0 253shlr8 Rn xor Rm,Rn 254sleep xor.b #imm,@@(R0,GBR) 255stc GBR,Rn xtrct Rm,Rn 256stc SR,Rn 257@end smallexample 258@end ifset 259 260@ifset Hitachi-all 261@ifclear GENERIC 262@raisesections 263@end ifclear 264@end ifset 265 266