c-ppc.texi revision 218822
1@c Copyright 2001, 2002, 2003, 2005, 2006 2@c Free Software Foundation, Inc. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@ifset GENERIC 6@page 7@node PPC-Dependent 8@chapter PowerPC Dependent Features 9@end ifset 10@ifclear GENERIC 11@node Machine Dependencies 12@chapter PowerPC Dependent Features 13@end ifclear 14 15@cindex PowerPC support 16@menu 17* PowerPC-Opts:: Options 18* PowerPC-Pseudo:: PowerPC Assembler Directives 19@end menu 20 21@node PowerPC-Opts 22@section Options 23 24@cindex options for PowerPC 25@cindex PowerPC options 26@cindex architectures, PowerPC 27@cindex PowerPC architectures 28The PowerPC chip family includes several successive levels, using the same 29core instruction set, but including a few additional instructions at 30each level. There are exceptions to this however. For details on what 31instructions each variant supports, please see the chip's architecture 32reference manual. 33 34The following table lists all available PowerPC options. 35 36@table @code 37@item -mpwrx | -mpwr2 38Generate code for POWER/2 (RIOS2). 39 40@item -mpwr 41Generate code for POWER (RIOS1) 42 43@item -m601 44Generate code for PowerPC 601. 45 46@item -mppc, -mppc32, -m603, -m604 47Generate code for PowerPC 603/604. 48 49@item -m403, -m405 50Generate code for PowerPC 403/405. 51 52@item -m440 53Generate code for PowerPC 440. BookE and some 405 instructions. 54 55@item -m7400, -m7410, -m7450, -m7455 56Generate code for PowerPC 7400/7410/7450/7455. 57 58@item -mppc64, -m620 59Generate code for PowerPC 620/625/630. 60 61@item -me500, -me500x2 62Generate code for Motorola e500 core complex. 63 64@item -mspe 65Generate code for Motorola SPE instructions. 66 67@item -mppc64bridge 68Generate code for PowerPC 64, including bridge insns. 69 70@item -mbooke64 71Generate code for 64-bit BookE. 72 73@item -mbooke, mbooke32 74Generate code for 32-bit BookE. 75 76@item -me300 77Generate code for PowerPC e300 family. 78 79@item -maltivec 80Generate code for processors with AltiVec instructions. 81 82@item -mpower4 83Generate code for Power4 architecture. 84 85@item -mpower5 86Generate code for Power5 architecture. 87 88@item -mpower6 89Generate code for Power6 architecture. 90 91@item -mcell 92Generate code for Cell Broadband Engine architecture. 93 94@item -mcom 95Generate code Power/PowerPC common instructions. 96 97@item -many 98Generate code for any architecture (PWR/PWRX/PPC). 99 100@item -mregnames 101Allow symbolic names for registers. 102 103@item -mno-regnames 104Do not allow symbolic names for registers. 105 106@item -mrelocatable 107Support for GCC's -mrelocatable option. 108 109@item -mrelocatable-lib 110Support for GCC's -mrelocatable-lib option. 111 112@item -memb 113Set PPC_EMB bit in ELF flags. 114 115@item -mlittle, -mlittle-endian 116Generate code for a little endian machine. 117 118@item -mbig, -mbig-endian 119Generate code for a big endian machine. 120 121@item -msolaris 122Generate code for Solaris. 123 124@item -mno-solaris 125Do not generate code for Solaris. 126@end table 127 128 129@node PowerPC-Pseudo 130@section PowerPC Assembler Directives 131 132@cindex directives for PowerPC 133@cindex PowerPC directives 134A number of assembler directives are available for PowerPC. The 135following table is far from complete. 136 137@table @code 138@item .machine "string" 139This directive allows you to change the machine for which code is 140generated. @code{"string"} may be any of the -m cpu selection options 141(without the -m) enclosed in double quotes, @code{"push"}, or 142@code{"pop"}. @code{.machine "push"} saves the currently selected 143cpu, which may be restored with @code{.machine "pop"}. 144@end table 145