c-i386.texi revision 78828
178828Sobrien@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001 278828Sobrien@c Free Software Foundation, Inc. 333965Sjdp@c This is part of the GAS manual. 433965Sjdp@c For copying conditions, see the file as.texinfo. 533965Sjdp@ifset GENERIC 633965Sjdp@page 733965Sjdp@node i386-Dependent 833965Sjdp@chapter 80386 Dependent Features 933965Sjdp@end ifset 1033965Sjdp@ifclear GENERIC 1133965Sjdp@node Machine Dependencies 1233965Sjdp@chapter 80386 Dependent Features 1333965Sjdp@end ifclear 1433965Sjdp 1533965Sjdp@cindex i386 support 1633965Sjdp@cindex i80306 support 1777298Sobrien@cindex x86-64 support 1877298Sobrien 1977298SobrienThe i386 version @code{@value{AS}} supports both the original Intel 386 2077298Sobrienarchitecture in both 16 and 32-bit mode as well as AMD x86-64 architecture 2177298Sobrienextending the Intel architecture to 64-bits. 2277298Sobrien 2333965Sjdp@menu 2433965Sjdp* i386-Options:: Options 2533965Sjdp* i386-Syntax:: AT&T Syntax versus Intel Syntax 2660484Sobrien* i386-Mnemonics:: Instruction Naming 2733965Sjdp* i386-Regs:: Register Naming 2860484Sobrien* i386-Prefixes:: Instruction Prefixes 2933965Sjdp* i386-Memory:: Memory References 3078828Sobrien* i386-Jumps:: Handling of Jump Instructions 3133965Sjdp* i386-Float:: Floating Point 3260484Sobrien* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 3333965Sjdp* i386-16bit:: Writing 16-bit Code 3477298Sobrien* i386-Arch:: Specifying an x86 CPU architecture 3560484Sobrien* i386-Bugs:: AT&T Syntax bugs 3633965Sjdp* i386-Notes:: Notes 3733965Sjdp@end menu 3833965Sjdp 3933965Sjdp@node i386-Options 4033965Sjdp@section Options 4133965Sjdp 4277298Sobrien@cindex options for i386 4377298Sobrien@cindex options for x86-64 4477298Sobrien@cindex i386 options 4577298Sobrien@cindex x86-64 options 4633965Sjdp 4777298SobrienThe i386 version of @code{@value{AS}} has a few machine 4877298Sobriendependent options: 4977298Sobrien 5077298Sobrien@table @code 5177298Sobrien@cindex @samp{--32} option, i386 5277298Sobrien@cindex @samp{--32} option, x86-64 5377298Sobrien@cindex @samp{--64} option, i386 5477298Sobrien@cindex @samp{--64} option, x86-64 5577298Sobrien@item --32 | --64 5677298SobrienSelect the word size, either 32 bits or 64 bits. Selecting 32-bit 5777298Sobrienimplies Intel i386 architecture, while 64-bit implies AMD x86-64 5877298Sobrienarchitecture. 5977298Sobrien 6077298SobrienThese options are only available with the ELF object file format, and 6177298Sobrienrequire that the necessary BFD support has been included (on a 32-bit 6277298Sobrienplatform you have to add --enable-64-bit-bfd to configure enable 64-bit 6377298Sobrienusage and use x86-64 as target platform). 6477298Sobrien@end table 6577298Sobrien 6633965Sjdp@node i386-Syntax 6733965Sjdp@section AT&T Syntax versus Intel Syntax 6833965Sjdp 6977298Sobrien@cindex i386 intel_syntax pseudo op 7077298Sobrien@cindex intel_syntax pseudo op, i386 7177298Sobrien@cindex i386 att_syntax pseudo op 7277298Sobrien@cindex att_syntax pseudo op, i386 7333965Sjdp@cindex i386 syntax compatibility 7433965Sjdp@cindex syntax compatibility, i386 7577298Sobrien@cindex x86-64 intel_syntax pseudo op 7677298Sobrien@cindex intel_syntax pseudo op, x86-64 7777298Sobrien@cindex x86-64 att_syntax pseudo op 7877298Sobrien@cindex att_syntax pseudo op, x86-64 7977298Sobrien@cindex x86-64 syntax compatibility 8077298Sobrien@cindex syntax compatibility, x86-64 8177298Sobrien 8277298Sobrien@code{@value{AS}} now supports assembly using Intel assembler syntax. 8377298Sobrien@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches 8477298Sobrienback to the usual AT&T mode for compatibility with the output of 8577298Sobrien@code{@value{GCC}}. Either of these directives may have an optional 8677298Sobrienargument, @code{prefix}, or @code{noprefix} specifying whether registers 8777298Sobrienrequire a @samp{%} prefix. AT&T System V/386 assembler syntax is quite 8833965Sjdpdifferent from Intel syntax. We mention these differences because 8960484Sobrienalmost all 80386 documents use Intel syntax. Notable differences 9033965Sjdpbetween the two syntaxes are: 9133965Sjdp 9233965Sjdp@cindex immediate operands, i386 9333965Sjdp@cindex i386 immediate operands 9433965Sjdp@cindex register operands, i386 9533965Sjdp@cindex i386 register operands 9633965Sjdp@cindex jump/call operands, i386 9733965Sjdp@cindex i386 jump/call operands 9833965Sjdp@cindex operand delimiters, i386 9977298Sobrien 10077298Sobrien@cindex immediate operands, x86-64 10177298Sobrien@cindex x86-64 immediate operands 10277298Sobrien@cindex register operands, x86-64 10377298Sobrien@cindex x86-64 register operands 10477298Sobrien@cindex jump/call operands, x86-64 10577298Sobrien@cindex x86-64 jump/call operands 10677298Sobrien@cindex operand delimiters, x86-64 10733965Sjdp@itemize @bullet 10833965Sjdp@item 10933965SjdpAT&T immediate operands are preceded by @samp{$}; Intel immediate 11033965Sjdpoperands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). 11133965SjdpAT&T register operands are preceded by @samp{%}; Intel register operands 11233965Sjdpare undelimited. AT&T absolute (as opposed to PC relative) jump/call 11333965Sjdpoperands are prefixed by @samp{*}; they are undelimited in Intel syntax. 11433965Sjdp 11533965Sjdp@cindex i386 source, destination operands 11633965Sjdp@cindex source, destination operands; i386 11777298Sobrien@cindex x86-64 source, destination operands 11877298Sobrien@cindex source, destination operands; x86-64 11933965Sjdp@item 12033965SjdpAT&T and Intel syntax use the opposite order for source and destination 12133965Sjdpoperands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The 12233965Sjdp@samp{source, dest} convention is maintained for compatibility with 12360484Sobrienprevious Unix assemblers. Note that instructions with more than one 12460484Sobriensource operand, such as the @samp{enter} instruction, do @emph{not} have 12560484Sobrienreversed order. @ref{i386-Bugs}. 12633965Sjdp 12760484Sobrien@cindex mnemonic suffixes, i386 12833965Sjdp@cindex sizes operands, i386 12933965Sjdp@cindex i386 size suffixes 13077298Sobrien@cindex mnemonic suffixes, x86-64 13177298Sobrien@cindex sizes operands, x86-64 13277298Sobrien@cindex x86-64 size suffixes 13333965Sjdp@item 13433965SjdpIn AT&T syntax the size of memory operands is determined from the last 13560484Sobriencharacter of the instruction mnemonic. Mnemonic suffixes of @samp{b}, 13677298Sobrien@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long 13777298Sobrien(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes 13877298Sobrienthis by prefixing memory operands (@emph{not} the instruction mnemonics) with 13977298Sobrien@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus, 14077298SobrienIntel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T 14177298Sobriensyntax. 14233965Sjdp 14333965Sjdp@cindex return instructions, i386 14433965Sjdp@cindex i386 jump, call, return 14577298Sobrien@cindex return instructions, x86-64 14677298Sobrien@cindex x86-64 jump, call, return 14733965Sjdp@item 14833965SjdpImmediate form long jumps and calls are 14933965Sjdp@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the 15033965SjdpIntel syntax is 15133965Sjdp@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return 15233965Sjdpinstruction 15333965Sjdpis @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is 15433965Sjdp@samp{ret far @var{stack-adjust}}. 15533965Sjdp 15633965Sjdp@cindex sections, i386 15733965Sjdp@cindex i386 sections 15877298Sobrien@cindex sections, x86-64 15977298Sobrien@cindex x86-64 sections 16033965Sjdp@item 16133965SjdpThe AT&T assembler does not provide support for multiple section 16233965Sjdpprograms. Unix style systems expect all programs to be single sections. 16333965Sjdp@end itemize 16433965Sjdp 16560484Sobrien@node i386-Mnemonics 16660484Sobrien@section Instruction Naming 16733965Sjdp 16860484Sobrien@cindex i386 instruction naming 16960484Sobrien@cindex instruction naming, i386 17077298Sobrien@cindex x86-64 instruction naming 17177298Sobrien@cindex instruction naming, x86-64 17277298Sobrien 17360484SobrienInstruction mnemonics are suffixed with one character modifiers which 17477298Sobrienspecify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} 17577298Sobrienand @samp{q} specify byte, word, long and quadruple word operands. If 17677298Sobrienno suffix is specified by an instruction then @code{@value{AS}} tries to 17777298Sobrienfill in the missing suffix based on the destination register operand 17877298Sobrien(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent 17977298Sobriento @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to 18077298Sobrien@samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix 18177298Sobrienassembler which assumes that a missing mnemonic suffix implies long 18277298Sobrienoperand size. (This incompatibility does not affect compiler output 18377298Sobriensince compilers always explicitly specify the mnemonic suffix.) 18433965Sjdp 18560484SobrienAlmost all instructions have the same names in AT&T and Intel format. 18660484SobrienThere are a few exceptions. The sign extend and zero extend 18760484Sobrieninstructions need two sizes to specify them. They need a size to 18860484Sobriensign/zero extend @emph{from} and a size to zero extend @emph{to}. This 18960484Sobrienis accomplished by using two instruction mnemonic suffixes in AT&T 19060484Sobriensyntax. Base names for sign extend and zero extend are 19160484Sobrien@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} 19260484Sobrienand @samp{movzx} in Intel syntax). The instruction mnemonic suffixes 19360484Sobrienare tacked on to this base name, the @emph{from} suffix before the 19460484Sobrien@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for 19533965Sjdp``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, 19633965Sjdpthus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), 19777298Sobrien@samp{wl} (from word to long), @samp{bq} (from byte to quadruple word), 19877298Sobrien@samp{wq} (from word to quadruple word), and @samp{lq} (from long to 19977298Sobrienquadruple word). 20033965Sjdp 20133965Sjdp@cindex conversion instructions, i386 20233965Sjdp@cindex i386 conversion instructions 20377298Sobrien@cindex conversion instructions, x86-64 20477298Sobrien@cindex x86-64 conversion instructions 20533965SjdpThe Intel-syntax conversion instructions 20633965Sjdp 20733965Sjdp@itemize @bullet 20833965Sjdp@item 20933965Sjdp@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, 21033965Sjdp 21133965Sjdp@item 21233965Sjdp@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, 21333965Sjdp 21433965Sjdp@item 21533965Sjdp@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, 21633965Sjdp 21733965Sjdp@item 21833965Sjdp@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, 21977298Sobrien 22077298Sobrien@item 22177298Sobrien@samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} 22277298Sobrien(x86-64 only), 22377298Sobrien 22477298Sobrien@item 22577298Sobrien@samp{cdo} --- sign-extend quad in @samp{%rax} to octuple in 22677298Sobrien@samp{%rdx:%rax} (x86-64 only), 22733965Sjdp@end itemize 22833965Sjdp 22933965Sjdp@noindent 23077298Sobrienare called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and 23177298Sobrien@samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these 23277298Sobrieninstructions. 23333965Sjdp 23433965Sjdp@cindex jump instructions, i386 23533965Sjdp@cindex call instructions, i386 23677298Sobrien@cindex jump instructions, x86-64 23777298Sobrien@cindex call instructions, x86-64 23833965SjdpFar call/jump instructions are @samp{lcall} and @samp{ljmp} in 23933965SjdpAT&T syntax, but are @samp{call far} and @samp{jump far} in Intel 24033965Sjdpconvention. 24133965Sjdp 24233965Sjdp@node i386-Regs 24333965Sjdp@section Register Naming 24433965Sjdp 24533965Sjdp@cindex i386 registers 24633965Sjdp@cindex registers, i386 24777298Sobrien@cindex x86-64 registers 24877298Sobrien@cindex registers, x86-64 24960484SobrienRegister operands are always prefixed with @samp{%}. The 80386 registers 25033965Sjdpconsist of 25133965Sjdp 25233965Sjdp@itemize @bullet 25333965Sjdp@item 25433965Sjdpthe 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, 25533965Sjdp@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the 25633965Sjdpframe pointer), and @samp{%esp} (the stack pointer). 25733965Sjdp 25833965Sjdp@item 25933965Sjdpthe 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, 26033965Sjdp@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. 26133965Sjdp 26233965Sjdp@item 26333965Sjdpthe 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, 26433965Sjdp@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These 26533965Sjdpare the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, 26633965Sjdp@samp{%cx}, and @samp{%dx}) 26733965Sjdp 26833965Sjdp@item 26933965Sjdpthe 6 section registers @samp{%cs} (code section), @samp{%ds} 27033965Sjdp(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, 27133965Sjdpand @samp{%gs}. 27233965Sjdp 27333965Sjdp@item 27433965Sjdpthe 3 processor control registers @samp{%cr0}, @samp{%cr2}, and 27533965Sjdp@samp{%cr3}. 27633965Sjdp 27733965Sjdp@item 27833965Sjdpthe 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, 27933965Sjdp@samp{%db3}, @samp{%db6}, and @samp{%db7}. 28033965Sjdp 28133965Sjdp@item 28233965Sjdpthe 2 test registers @samp{%tr6} and @samp{%tr7}. 28333965Sjdp 28433965Sjdp@item 28533965Sjdpthe 8 floating point register stack @samp{%st} or equivalently 28633965Sjdp@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, 28733965Sjdp@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. 28877298SobrienThese registers are overloaded by 8 MMX registers @samp{%mm0}, 28977298Sobrien@samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, 29077298Sobrien@samp{%mm6} and @samp{%mm7}. 29177298Sobrien 29277298Sobrien@item 29377298Sobrienthe 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, 29477298Sobrien@samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. 29533965Sjdp@end itemize 29633965Sjdp 29777298SobrienThe AMD x86-64 architecture extends the register set by: 29877298Sobrien 29977298Sobrien@itemize @bullet 30077298Sobrien@item 30177298Sobrienenhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the 30277298Sobrienaccumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, 30377298Sobrien@samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack 30477298Sobrienpointer) 30577298Sobrien 30677298Sobrien@item 30777298Sobrienthe 8 extended registers @samp{%r8}--@samp{%r15}. 30877298Sobrien 30977298Sobrien@item 31077298Sobrienthe 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d} 31177298Sobrien 31277298Sobrien@item 31377298Sobrienthe 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w} 31477298Sobrien 31577298Sobrien@item 31677298Sobrienthe 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b} 31777298Sobrien 31877298Sobrien@item 31977298Sobrienthe 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. 32077298Sobrien 32177298Sobrien@item 32277298Sobrienthe 8 debug registers: @samp{%db8}--@samp{%db15}. 32377298Sobrien 32477298Sobrien@item 32577298Sobrienthe 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}. 32677298Sobrien@end itemize 32777298Sobrien 32860484Sobrien@node i386-Prefixes 32960484Sobrien@section Instruction Prefixes 33033965Sjdp 33160484Sobrien@cindex i386 instruction prefixes 33260484Sobrien@cindex instruction prefixes, i386 33333965Sjdp@cindex prefixes, i386 33460484SobrienInstruction prefixes are used to modify the following instruction. They 33560484Sobrienare used to repeat string instructions, to provide section overrides, to 33660484Sobrienperform bus lock operations, and to change operand and address sizes. 33760484Sobrien(Most instructions that normally operate on 32-bit operands will use 33860484Sobrien16-bit operands if the instruction has an ``operand size'' prefix.) 33960484SobrienInstruction prefixes are best written on the same line as the instruction 34060484Sobrienthey act upon. For example, the @samp{scas} (scan string) instruction is 34160484Sobrienrepeated with: 34260484Sobrien 34333965Sjdp@smallexample 34460484Sobrien repne scas %es:(%edi),%al 34533965Sjdp@end smallexample 34633965Sjdp 34760484SobrienYou may also place prefixes on the lines immediately preceding the 34860484Sobrieninstruction, but this circumvents checks that @code{@value{AS}} does 34960484Sobrienwith prefixes, and will not work with all prefixes. 35033965Sjdp 35160484SobrienHere is a list of instruction prefixes: 35260484Sobrien 35333965Sjdp@cindex section override prefixes, i386 35433965Sjdp@itemize @bullet 35533965Sjdp@item 35633965SjdpSection override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, 35733965Sjdp@samp{fs}, @samp{gs}. These are automatically added by specifying 35833965Sjdpusing the @var{section}:@var{memory-operand} form for memory references. 35933965Sjdp 36033965Sjdp@cindex size prefixes, i386 36133965Sjdp@item 36233965SjdpOperand/Address size prefixes @samp{data16} and @samp{addr16} 36360484Sobrienchange 32-bit operands/addresses into 16-bit operands/addresses, 36460484Sobrienwhile @samp{data32} and @samp{addr32} change 16-bit ones (in a 36560484Sobrien@code{.code16} section) into 32-bit operands/addresses. These prefixes 36660484Sobrien@emph{must} appear on the same line of code as the instruction they 36760484Sobrienmodify. For example, in a 16-bit @code{.code16} section, you might 36860484Sobrienwrite: 36933965Sjdp 37060484Sobrien@smallexample 37160484Sobrien addr32 jmpl *(%ebx) 37260484Sobrien@end smallexample 37360484Sobrien 37433965Sjdp@cindex bus lock prefixes, i386 37533965Sjdp@cindex inhibiting interrupts, i386 37633965Sjdp@item 37760484SobrienThe bus lock prefix @samp{lock} inhibits interrupts during execution of 37860484Sobrienthe instruction it precedes. (This is only valid with certain 37960484Sobrieninstructions; see a 80386 manual for details). 38033965Sjdp 38133965Sjdp@cindex coprocessor wait, i386 38233965Sjdp@item 38360484SobrienThe wait for coprocessor prefix @samp{wait} waits for the coprocessor to 38460484Sobriencomplete the current instruction. This should never be needed for the 38560484Sobrien80386/80387 combination. 38633965Sjdp 38733965Sjdp@cindex repeat prefixes, i386 38833965Sjdp@item 38933965SjdpThe @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added 39060484Sobriento string instructions to make them repeat @samp{%ecx} times (@samp{%cx} 39160484Sobrientimes if the current address size is 16-bits). 39277298Sobrien@cindex REX prefixes, i386 39377298Sobrien@item 39477298SobrienThe @samp{rex} family of prefixes is used by x86-64 to encode 39577298Sobrienextensions to i386 instruction set. The @samp{rex} prefix has four 39677298Sobrienbits --- an operand size overwrite (@code{64}) used to change operand size 39777298Sobrienfrom 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 39877298Sobrienregister set. 39977298Sobrien 40077298SobrienYou may write the @samp{rex} prefixes directly. The @samp{rex64xyz} 40177298Sobrieninstruction emits @samp{rex} prefix with all the bits set. By omitting 40277298Sobrienthe @code{64}, @code{x}, @code{y} or @code{z} you may write other 40377298Sobrienprefixes as well. Normally, there is no need to write the prefixes 40477298Sobrienexplicitly, since gas will automatically generate them based on the 40577298Sobrieninstruction operands. 40633965Sjdp@end itemize 40733965Sjdp 40833965Sjdp@node i386-Memory 40933965Sjdp@section Memory References 41033965Sjdp 41133965Sjdp@cindex i386 memory references 41233965Sjdp@cindex memory references, i386 41377298Sobrien@cindex x86-64 memory references 41477298Sobrien@cindex memory references, x86-64 41533965SjdpAn Intel syntax indirect memory reference of the form 41633965Sjdp 41733965Sjdp@smallexample 41833965Sjdp@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] 41933965Sjdp@end smallexample 42033965Sjdp 42133965Sjdp@noindent 42233965Sjdpis translated into the AT&T syntax 42333965Sjdp 42433965Sjdp@smallexample 42533965Sjdp@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) 42633965Sjdp@end smallexample 42733965Sjdp 42833965Sjdp@noindent 42933965Sjdpwhere @var{base} and @var{index} are the optional 32-bit base and 43033965Sjdpindex registers, @var{disp} is the optional displacement, and 43133965Sjdp@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} 43233965Sjdpto calculate the address of the operand. If no @var{scale} is 43333965Sjdpspecified, @var{scale} is taken to be 1. @var{section} specifies the 43433965Sjdpoptional section register for the memory operand, and may override the 43533965Sjdpdefault section register (see a 80386 manual for section register 43660484Sobriendefaults). Note that section overrides in AT&T syntax @emph{must} 43733965Sjdpbe preceded by a @samp{%}. If you specify a section override which 43833965Sjdpcoincides with the default section register, @code{@value{AS}} does @emph{not} 43933965Sjdpoutput any section register override prefixes to assemble the given 44033965Sjdpinstruction. Thus, section overrides can be specified to emphasize which 44133965Sjdpsection register is used for a given memory operand. 44233965Sjdp 44333965SjdpHere are some examples of Intel and AT&T style memory references: 44433965Sjdp 44533965Sjdp@table @asis 44633965Sjdp@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} 44733965Sjdp@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is 44833965Sjdpmissing, and the default section is used (@samp{%ss} for addressing with 44933965Sjdp@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. 45033965Sjdp 45133965Sjdp@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} 45233965Sjdp@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is 45333965Sjdp@samp{foo}. All other fields are missing. The section register here 45433965Sjdpdefaults to @samp{%ds}. 45533965Sjdp 45633965Sjdp@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} 45733965SjdpThis uses the value pointed to by @samp{foo} as a memory operand. 45833965SjdpNote that @var{base} and @var{index} are both missing, but there is only 45933965Sjdp@emph{one} @samp{,}. This is a syntactic exception. 46033965Sjdp 46133965Sjdp@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} 46233965SjdpThis selects the contents of the variable @samp{foo} with section 46333965Sjdpregister @var{section} being @samp{%gs}. 46433965Sjdp@end table 46533965Sjdp 46633965SjdpAbsolute (as opposed to PC relative) call and jump operands must be 46733965Sjdpprefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} 46833965Sjdpalways chooses PC relative addressing for jump/call labels. 46933965Sjdp 47060484SobrienAny instruction that has a memory operand, but no register operand, 47177298Sobrien@emph{must} specify its size (byte, word, long, or quadruple) with an 47277298Sobrieninstruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, 47377298Sobrienrespectively). 47433965Sjdp 47577298SobrienThe x86-64 architecture adds an RIP (instruction pointer relative) 47677298Sobrienaddressing. This addressing mode is specified by using @samp{rip} as a 47777298Sobrienbase register. Only constant offsets are valid. For example: 47877298Sobrien 47977298Sobrien@table @asis 48077298Sobrien@item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} 48177298SobrienPoints to the address 1234 bytes past the end of the current 48277298Sobrieninstruction. 48377298Sobrien 48477298Sobrien@item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} 48577298SobrienPoints to the @code{symbol} in RIP relative way, this is shorter than 48677298Sobrienthe default absolute addressing. 48777298Sobrien@end table 48877298Sobrien 48977298SobrienOther addressing modes remain unchanged in x86-64 architecture, except 49077298Sobrienregisters used are 64-bit instead of 32-bit. 49177298Sobrien 49278828Sobrien@node i386-Jumps 49333965Sjdp@section Handling of Jump Instructions 49433965Sjdp 49533965Sjdp@cindex jump optimization, i386 49633965Sjdp@cindex i386 jump optimization 49777298Sobrien@cindex jump optimization, x86-64 49877298Sobrien@cindex x86-64 jump optimization 49933965SjdpJump instructions are always optimized to use the smallest possible 50033965Sjdpdisplacements. This is accomplished by using byte (8-bit) displacement 50133965Sjdpjumps whenever the target is sufficiently close. If a byte displacement 50278828Sobrienis insufficient a long displacement is used. We do not support 50360484Sobrienword (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 50460484Sobrieninstruction with the @samp{data16} instruction prefix), since the 80386 50560484Sobrieninsists upon masking @samp{%eip} to 16 bits after the word displacement 50678828Sobrienis added. (See also @pxref{i386-Arch}) 50733965Sjdp 50833965SjdpNote that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, 50933965Sjdp@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte 51033965Sjdpdisplacements, so that if you use these instructions (@code{@value{GCC}} does 51133965Sjdpnot use them) you may get an error message (and incorrect code). The AT&T 51233965Sjdp80386 assembler tries to get around this problem by expanding @samp{jcxz foo} 51333965Sjdpto 51433965Sjdp 51533965Sjdp@smallexample 51633965Sjdp jcxz cx_zero 51733965Sjdp jmp cx_nonzero 51833965Sjdpcx_zero: jmp foo 51933965Sjdpcx_nonzero: 52033965Sjdp@end smallexample 52133965Sjdp 52233965Sjdp@node i386-Float 52333965Sjdp@section Floating Point 52433965Sjdp 52533965Sjdp@cindex i386 floating point 52633965Sjdp@cindex floating point, i386 52777298Sobrien@cindex x86-64 floating point 52877298Sobrien@cindex floating point, x86-64 52933965SjdpAll 80387 floating point types except packed BCD are supported. 53033965Sjdp(BCD support may be added without much difficulty). These data 53133965Sjdptypes are 16-, 32-, and 64- bit integers, and single (32-bit), 53233965Sjdpdouble (64-bit), and extended (80-bit) precision floating point. 53360484SobrienEach supported type has an instruction mnemonic suffix and a constructor 53460484Sobrienassociated with it. Instruction mnemonic suffixes specify the operand's 53560484Sobriendata type. Constructors build these data types into memory. 53633965Sjdp 53733965Sjdp@cindex @code{float} directive, i386 53833965Sjdp@cindex @code{single} directive, i386 53933965Sjdp@cindex @code{double} directive, i386 54033965Sjdp@cindex @code{tfloat} directive, i386 54177298Sobrien@cindex @code{float} directive, x86-64 54277298Sobrien@cindex @code{single} directive, x86-64 54377298Sobrien@cindex @code{double} directive, x86-64 54477298Sobrien@cindex @code{tfloat} directive, x86-64 54533965Sjdp@itemize @bullet 54633965Sjdp@item 54733965SjdpFloating point constructors are @samp{.float} or @samp{.single}, 54833965Sjdp@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. 54960484SobrienThese correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, 55060484Sobrienand @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 55160484Sobrienonly supports this format via the @samp{fldt} (load 80-bit real to stack 55260484Sobrientop) and @samp{fstpt} (store 80-bit real and pop stack) instructions. 55333965Sjdp 55433965Sjdp@cindex @code{word} directive, i386 55533965Sjdp@cindex @code{long} directive, i386 55633965Sjdp@cindex @code{int} directive, i386 55733965Sjdp@cindex @code{quad} directive, i386 55877298Sobrien@cindex @code{word} directive, x86-64 55977298Sobrien@cindex @code{long} directive, x86-64 56077298Sobrien@cindex @code{int} directive, x86-64 56177298Sobrien@cindex @code{quad} directive, x86-64 56233965Sjdp@item 56333965SjdpInteger constructors are @samp{.word}, @samp{.long} or @samp{.int}, and 56460484Sobrien@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The 56560484Sobriencorresponding instruction mnemonic suffixes are @samp{s} (single), 56660484Sobrien@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, 56760484Sobrienthe 64-bit @samp{q} format is only present in the @samp{fildq} (load 56860484Sobrienquad integer to stack top) and @samp{fistpq} (store quad integer and pop 56960484Sobrienstack) instructions. 57033965Sjdp@end itemize 57133965Sjdp 57260484SobrienRegister to register operations should not use instruction mnemonic suffixes. 57360484Sobrien@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you 57460484Sobrienwrote @samp{fst %st, %st(1)}, since all register to register operations 57560484Sobrienuse 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, 57660484Sobrienwhich converts @samp{%st} from 80-bit to 64-bit floating point format, 57760484Sobrienthen stores the result in the 4 byte location @samp{mem}) 57833965Sjdp 57960484Sobrien@node i386-SIMD 58060484Sobrien@section Intel's MMX and AMD's 3DNow! SIMD Operations 58160484Sobrien 58260484Sobrien@cindex MMX, i386 58360484Sobrien@cindex 3DNow!, i386 58460484Sobrien@cindex SIMD, i386 58577298Sobrien@cindex MMX, x86-64 58677298Sobrien@cindex 3DNow!, x86-64 58777298Sobrien@cindex SIMD, x86-64 58860484Sobrien 58960484Sobrien@code{@value{AS}} supports Intel's MMX instruction set (SIMD 59060484Sobrieninstructions for integer data), available on Intel's Pentium MMX 59160484Sobrienprocessors and Pentium II processors, AMD's K6 and K6-2 processors, 59260484SobrienCyrix' M2 processor, and probably others. It also supports AMD's 3DNow! 59360484Sobrieninstruction set (SIMD instructions for 32-bit floating point data) 59460484Sobrienavailable on AMD's K6-2 processor and possibly others in the future. 59560484Sobrien 59660484SobrienCurrently, @code{@value{AS}} does not support Intel's floating point 59760484SobrienSIMD, Katmai (KNI). 59860484Sobrien 59960484SobrienThe eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, 60060484Sobrien@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four 60160484Sobrien16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 60260484Sobrienfloating point values. The MMX registers cannot be used at the same time 60360484Sobrienas the floating point stack. 60460484Sobrien 60560484SobrienSee Intel and AMD documentation, keeping in mind that the operand order in 60660484Sobrieninstructions is reversed from the Intel syntax. 60760484Sobrien 60833965Sjdp@node i386-16bit 60933965Sjdp@section Writing 16-bit Code 61033965Sjdp 61133965Sjdp@cindex i386 16-bit code 61233965Sjdp@cindex 16-bit code, i386 61333965Sjdp@cindex real-mode code, i386 61460484Sobrien@cindex @code{code16gcc} directive, i386 61533965Sjdp@cindex @code{code16} directive, i386 61633965Sjdp@cindex @code{code32} directive, i386 61777298Sobrien@cindex @code{code64} directive, i386 61877298Sobrien@cindex @code{code64} directive, x86-64 61977298SobrienWhile @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code 62077298Sobrienor 64-bit x86-64 code depending on the default configuration, 62160484Sobrienit also supports writing code to run in real mode or in 16-bit protected 62260484Sobrienmode code segments. To do this, put a @samp{.code16} or 62360484Sobrien@samp{.code16gcc} directive before the assembly language instructions to 62460484Sobrienbe run in 16-bit mode. You can switch @code{@value{AS}} back to writing 62560484Sobriennormal 32-bit code with the @samp{.code32} directive. 62633965Sjdp 62760484Sobrien@samp{.code16gcc} provides experimental support for generating 16-bit 62860484Sobriencode from gcc, and differs from @samp{.code16} in that @samp{call}, 62960484Sobrien@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, 63060484Sobrien@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions 63160484Sobriendefault to 32-bit size. This is so that the stack pointer is 63260484Sobrienmanipulated in the same way over function calls, allowing access to 63360484Sobrienfunction parameters at the same stack offsets as in 32-bit mode. 63460484Sobrien@samp{.code16gcc} also automatically adds address size prefixes where 63560484Sobriennecessary to use the 32-bit addressing modes that gcc generates. 63633965Sjdp 63760484SobrienThe code which @code{@value{AS}} generates in 16-bit mode will not 63860484Sobriennecessarily run on a 16-bit pre-80386 processor. To write code that 63960484Sobrienruns on such a processor, you must refrain from using @emph{any} 32-bit 64060484Sobrienconstructs which require @code{@value{AS}} to output address or operand 64160484Sobriensize prefixes. 64233965Sjdp 64360484SobrienNote that writing 16-bit code instructions by explicitly specifying a 64460484Sobrienprefix or an instruction mnemonic suffix within a 32-bit code section 64560484Sobriengenerates different machine instructions than those generated for a 64660484Sobrien16-bit code segment. In a 32-bit code section, the following code 64760484Sobriengenerates the machine opcode bytes @samp{66 6a 04}, which pushes the 64860484Sobrienvalue @samp{4} onto the stack, decrementing @samp{%esp} by 2. 64933965Sjdp 65060484Sobrien@smallexample 65160484Sobrien pushw $4 65260484Sobrien@end smallexample 65360484Sobrien 65460484SobrienThe same code in a 16-bit code section would generate the machine 65560484Sobrienopcode bytes @samp{6a 04} (ie. without the operand size prefix), which 65660484Sobrienis correct since the processor default operand size is assumed to be 16 65760484Sobrienbits in a 16-bit code section. 65860484Sobrien 65960484Sobrien@node i386-Bugs 66060484Sobrien@section AT&T Syntax bugs 66160484Sobrien 66260484SobrienThe UnixWare assembler, and probably other AT&T derived ix86 Unix 66360484Sobrienassemblers, generate floating point instructions with reversed source 66460484Sobrienand destination registers in certain cases. Unfortunately, gcc and 66560484Sobrienpossibly many other programs use this reversed syntax, so we're stuck 66660484Sobrienwith it. 66760484Sobrien 66860484SobrienFor example 66960484Sobrien 67060484Sobrien@smallexample 67160484Sobrien fsub %st,%st(3) 67260484Sobrien@end smallexample 67360484Sobrien@noindent 67460484Sobrienresults in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather 67560484Sobrienthan the expected @samp{%st(3) - %st}. This happens with all the 67660484Sobriennon-commutative arithmetic floating point operations with two register 67760484Sobrienoperands where the source register is @samp{%st} and the destination 67860484Sobrienregister is @samp{%st(i)}. 67960484Sobrien 68077298Sobrien@node i386-Arch 68177298Sobrien@section Specifying CPU Architecture 68277298Sobrien 68377298Sobrien@cindex arch directive, i386 68477298Sobrien@cindex i386 arch directive 68577298Sobrien@cindex arch directive, x86-64 68677298Sobrien@cindex x86-64 arch directive 68777298Sobrien 68877298Sobrien@code{@value{AS}} may be told to assemble for a particular CPU 68977298Sobrienarchitecture with the @code{.arch @var{cpu_type}} directive. This 69077298Sobriendirective enables a warning when gas detects an instruction that is not 69177298Sobriensupported on the CPU specified. The choices for @var{cpu_type} are: 69277298Sobrien 69377298Sobrien@multitable @columnfractions .20 .20 .20 .20 69477298Sobrien@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} 69577298Sobrien@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} 69677298Sobrien@item @samp{pentiumpro} @tab @samp{pentium4} @tab @samp{k6} @tab @samp{athlon} 69777298Sobrien@item @samp{sledgehammer} 69877298Sobrien@end multitable 69977298Sobrien 70078828SobrienApart from the warning, there are only two other effects on 70178828Sobrien@code{@value{AS}} operation; Firstly, if you specify a CPU other than 70277298Sobrien@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} 70377298Sobrienwill automatically use a two byte opcode sequence. The larger three 70477298Sobrienbyte opcode sequence is used on the 486 (and when no architecture is 70577298Sobrienspecified) because it executes faster on the 486. Note that you can 70677298Sobrienexplicitly request the two byte opcode by writing @samp{sarl %eax}. 70778828SobrienSecondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, 70878828Sobrien@emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset 70978828Sobrienconditional jumps will be promoted when necessary to a two instruction 71078828Sobriensequence consisting of a conditional jump of the opposite sense around 71178828Sobrienan unconditional jump to the target. 71277298Sobrien 71378828SobrienFollowing the CPU architecture, you may specify @samp{jumps} or 71478828Sobrien@samp{nojumps} to control automatic promotion of conditional jumps. 71578828Sobrien@samp{jumps} is the default, and enables jump promotion; All external 71678828Sobrienjumps will be of the long variety, and file-local jumps will be promoted 71778828Sobrienas necessary. (@pxref{i386-Jumps}) @samp{nojumps} leaves external 71878828Sobrienconditional jumps as byte offset jumps, and warns about file-local 71978828Sobrienconditional jumps that @code{@value{AS}} promotes. 72078828SobrienUnconditional jumps are treated as for @samp{jumps}. 72178828Sobrien 72278828SobrienFor example 72378828Sobrien 72478828Sobrien@smallexample 72578828Sobrien .arch i8086,nojumps 72678828Sobrien@end smallexample 72778828Sobrien 72833965Sjdp@node i386-Notes 72933965Sjdp@section Notes 73033965Sjdp 73133965Sjdp@cindex i386 @code{mul}, @code{imul} instructions 73233965Sjdp@cindex @code{mul} instruction, i386 73333965Sjdp@cindex @code{imul} instruction, i386 73477298Sobrien@cindex @code{mul} instruction, x86-64 73577298Sobrien@cindex @code{imul} instruction, x86-64 73633965SjdpThere is some trickery concerning the @samp{mul} and @samp{imul} 73777298Sobrieninstructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding 73833965Sjdpmultiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 73933965Sjdpfor @samp{imul}) can be output only in the one operand form. Thus, 74033965Sjdp@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; 74133965Sjdpthe expanding multiply would clobber the @samp{%edx} register, and this 74233965Sjdpwould confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the 74333965Sjdp64-bit product in @samp{%edx:%eax}. 74433965Sjdp 74533965SjdpWe have added a two operand form of @samp{imul} when the first operand 74633965Sjdpis an immediate mode expression and the second operand is a register. 74733965SjdpThis is just a shorthand, so that, multiplying @samp{%eax} by 69, for 74833965Sjdpexample, can be done with @samp{imul $69, %eax} rather than @samp{imul 74933965Sjdp$69, %eax, %eax}. 75033965Sjdp 751