c-i386.texi revision 60484
160484Sobrien@c Copyright (C) 1991, 92, 93, 94, 95, 97, 1998 Free Software Foundation, Inc. 233965Sjdp@c This is part of the GAS manual. 333965Sjdp@c For copying conditions, see the file as.texinfo. 433965Sjdp@ifset GENERIC 533965Sjdp@page 633965Sjdp@node i386-Dependent 733965Sjdp@chapter 80386 Dependent Features 833965Sjdp@end ifset 933965Sjdp@ifclear GENERIC 1033965Sjdp@node Machine Dependencies 1133965Sjdp@chapter 80386 Dependent Features 1233965Sjdp@end ifclear 1333965Sjdp 1433965Sjdp@cindex i386 support 1533965Sjdp@cindex i80306 support 1633965Sjdp@menu 1733965Sjdp* i386-Options:: Options 1833965Sjdp* i386-Syntax:: AT&T Syntax versus Intel Syntax 1960484Sobrien* i386-Mnemonics:: Instruction Naming 2033965Sjdp* i386-Regs:: Register Naming 2160484Sobrien* i386-Prefixes:: Instruction Prefixes 2233965Sjdp* i386-Memory:: Memory References 2333965Sjdp* i386-jumps:: Handling of Jump Instructions 2433965Sjdp* i386-Float:: Floating Point 2560484Sobrien* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 2633965Sjdp* i386-16bit:: Writing 16-bit Code 2760484Sobrien* i386-Bugs:: AT&T Syntax bugs 2833965Sjdp* i386-Notes:: Notes 2933965Sjdp@end menu 3033965Sjdp 3133965Sjdp@node i386-Options 3233965Sjdp@section Options 3333965Sjdp 3433965Sjdp@cindex options for i386 (none) 3533965Sjdp@cindex i386 options (none) 3633965SjdpThe 80386 has no machine dependent options. 3733965Sjdp 3833965Sjdp@node i386-Syntax 3933965Sjdp@section AT&T Syntax versus Intel Syntax 4033965Sjdp 4133965Sjdp@cindex i386 syntax compatibility 4233965Sjdp@cindex syntax compatibility, i386 4333965SjdpIn order to maintain compatibility with the output of @code{@value{GCC}}, 4433965Sjdp@code{@value{AS}} supports AT&T System V/386 assembler syntax. This is quite 4533965Sjdpdifferent from Intel syntax. We mention these differences because 4660484Sobrienalmost all 80386 documents use Intel syntax. Notable differences 4733965Sjdpbetween the two syntaxes are: 4833965Sjdp 4933965Sjdp@cindex immediate operands, i386 5033965Sjdp@cindex i386 immediate operands 5133965Sjdp@cindex register operands, i386 5233965Sjdp@cindex i386 register operands 5333965Sjdp@cindex jump/call operands, i386 5433965Sjdp@cindex i386 jump/call operands 5533965Sjdp@cindex operand delimiters, i386 5633965Sjdp@itemize @bullet 5733965Sjdp@item 5833965SjdpAT&T immediate operands are preceded by @samp{$}; Intel immediate 5933965Sjdpoperands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). 6033965SjdpAT&T register operands are preceded by @samp{%}; Intel register operands 6133965Sjdpare undelimited. AT&T absolute (as opposed to PC relative) jump/call 6233965Sjdpoperands are prefixed by @samp{*}; they are undelimited in Intel syntax. 6333965Sjdp 6433965Sjdp@cindex i386 source, destination operands 6533965Sjdp@cindex source, destination operands; i386 6633965Sjdp@item 6733965SjdpAT&T and Intel syntax use the opposite order for source and destination 6833965Sjdpoperands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The 6933965Sjdp@samp{source, dest} convention is maintained for compatibility with 7060484Sobrienprevious Unix assemblers. Note that instructions with more than one 7160484Sobriensource operand, such as the @samp{enter} instruction, do @emph{not} have 7260484Sobrienreversed order. @ref{i386-Bugs}. 7333965Sjdp 7460484Sobrien@cindex mnemonic suffixes, i386 7533965Sjdp@cindex sizes operands, i386 7633965Sjdp@cindex i386 size suffixes 7733965Sjdp@item 7833965SjdpIn AT&T syntax the size of memory operands is determined from the last 7960484Sobriencharacter of the instruction mnemonic. Mnemonic suffixes of @samp{b}, 8060484Sobrien@samp{w}, and @samp{l} specify byte (8-bit), word (16-bit), and long 8160484Sobrien(32-bit) memory references. Intel syntax accomplishes this by prefixing 8260484Sobrienmemory operands (@emph{not} the instruction mnemonics) with @samp{byte 8360484Sobrienptr}, @samp{word ptr}, and @samp{dword ptr}. Thus, Intel @samp{mov al, 8460484Sobrienbyte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax. 8533965Sjdp 8633965Sjdp@cindex return instructions, i386 8733965Sjdp@cindex i386 jump, call, return 8833965Sjdp@item 8933965SjdpImmediate form long jumps and calls are 9033965Sjdp@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the 9133965SjdpIntel syntax is 9233965Sjdp@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return 9333965Sjdpinstruction 9433965Sjdpis @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is 9533965Sjdp@samp{ret far @var{stack-adjust}}. 9633965Sjdp 9733965Sjdp@cindex sections, i386 9833965Sjdp@cindex i386 sections 9933965Sjdp@item 10033965SjdpThe AT&T assembler does not provide support for multiple section 10133965Sjdpprograms. Unix style systems expect all programs to be single sections. 10233965Sjdp@end itemize 10333965Sjdp 10460484Sobrien@node i386-Mnemonics 10560484Sobrien@section Instruction Naming 10633965Sjdp 10760484Sobrien@cindex i386 instruction naming 10860484Sobrien@cindex instruction naming, i386 10960484SobrienInstruction mnemonics are suffixed with one character modifiers which 11060484Sobrienspecify the size of operands. The letters @samp{b}, @samp{w}, and 11160484Sobrien@samp{l} specify byte, word, and long operands. If no suffix is 11260484Sobrienspecified by an instruction then @code{@value{AS}} tries to fill in the 11360484Sobrienmissing suffix based on the destination register operand (the last one 11460484Sobrienby convention). Thus, @samp{mov %ax, %bx} is equivalent to @samp{movw 11560484Sobrien%ax, %bx}; also, @samp{mov $1, %bx} is equivalent to @samp{movw $1, 11660484Sobrien%bx}. Note that this is incompatible with the AT&T Unix assembler which 11760484Sobrienassumes that a missing mnemonic suffix implies long operand size. (This 11860484Sobrienincompatibility does not affect compiler output since compilers always 11960484Sobrienexplicitly specify the mnemonic suffix.) 12033965Sjdp 12160484SobrienAlmost all instructions have the same names in AT&T and Intel format. 12260484SobrienThere are a few exceptions. The sign extend and zero extend 12360484Sobrieninstructions need two sizes to specify them. They need a size to 12460484Sobriensign/zero extend @emph{from} and a size to zero extend @emph{to}. This 12560484Sobrienis accomplished by using two instruction mnemonic suffixes in AT&T 12660484Sobriensyntax. Base names for sign extend and zero extend are 12760484Sobrien@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} 12860484Sobrienand @samp{movzx} in Intel syntax). The instruction mnemonic suffixes 12960484Sobrienare tacked on to this base name, the @emph{from} suffix before the 13060484Sobrien@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for 13133965Sjdp``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, 13233965Sjdpthus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), 13333965Sjdpand @samp{wl} (from word to long). 13433965Sjdp 13533965Sjdp@cindex conversion instructions, i386 13633965Sjdp@cindex i386 conversion instructions 13733965SjdpThe Intel-syntax conversion instructions 13833965Sjdp 13933965Sjdp@itemize @bullet 14033965Sjdp@item 14133965Sjdp@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, 14233965Sjdp 14333965Sjdp@item 14433965Sjdp@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, 14533965Sjdp 14633965Sjdp@item 14733965Sjdp@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, 14833965Sjdp 14933965Sjdp@item 15033965Sjdp@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, 15133965Sjdp@end itemize 15233965Sjdp 15333965Sjdp@noindent 15433965Sjdpare called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, and @samp{cltd} in 15533965SjdpAT&T naming. @code{@value{AS}} accepts either naming for these instructions. 15633965Sjdp 15733965Sjdp@cindex jump instructions, i386 15833965Sjdp@cindex call instructions, i386 15933965SjdpFar call/jump instructions are @samp{lcall} and @samp{ljmp} in 16033965SjdpAT&T syntax, but are @samp{call far} and @samp{jump far} in Intel 16133965Sjdpconvention. 16233965Sjdp 16333965Sjdp@node i386-Regs 16433965Sjdp@section Register Naming 16533965Sjdp 16633965Sjdp@cindex i386 registers 16733965Sjdp@cindex registers, i386 16860484SobrienRegister operands are always prefixed with @samp{%}. The 80386 registers 16933965Sjdpconsist of 17033965Sjdp 17133965Sjdp@itemize @bullet 17233965Sjdp@item 17333965Sjdpthe 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, 17433965Sjdp@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the 17533965Sjdpframe pointer), and @samp{%esp} (the stack pointer). 17633965Sjdp 17733965Sjdp@item 17833965Sjdpthe 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, 17933965Sjdp@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. 18033965Sjdp 18133965Sjdp@item 18233965Sjdpthe 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, 18333965Sjdp@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These 18433965Sjdpare the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, 18533965Sjdp@samp{%cx}, and @samp{%dx}) 18633965Sjdp 18733965Sjdp@item 18833965Sjdpthe 6 section registers @samp{%cs} (code section), @samp{%ds} 18933965Sjdp(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, 19033965Sjdpand @samp{%gs}. 19133965Sjdp 19233965Sjdp@item 19333965Sjdpthe 3 processor control registers @samp{%cr0}, @samp{%cr2}, and 19433965Sjdp@samp{%cr3}. 19533965Sjdp 19633965Sjdp@item 19733965Sjdpthe 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, 19833965Sjdp@samp{%db3}, @samp{%db6}, and @samp{%db7}. 19933965Sjdp 20033965Sjdp@item 20133965Sjdpthe 2 test registers @samp{%tr6} and @samp{%tr7}. 20233965Sjdp 20333965Sjdp@item 20433965Sjdpthe 8 floating point register stack @samp{%st} or equivalently 20533965Sjdp@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, 20633965Sjdp@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. 20733965Sjdp@end itemize 20833965Sjdp 20960484Sobrien@node i386-Prefixes 21060484Sobrien@section Instruction Prefixes 21133965Sjdp 21260484Sobrien@cindex i386 instruction prefixes 21360484Sobrien@cindex instruction prefixes, i386 21433965Sjdp@cindex prefixes, i386 21560484SobrienInstruction prefixes are used to modify the following instruction. They 21660484Sobrienare used to repeat string instructions, to provide section overrides, to 21760484Sobrienperform bus lock operations, and to change operand and address sizes. 21860484Sobrien(Most instructions that normally operate on 32-bit operands will use 21960484Sobrien16-bit operands if the instruction has an ``operand size'' prefix.) 22060484SobrienInstruction prefixes are best written on the same line as the instruction 22160484Sobrienthey act upon. For example, the @samp{scas} (scan string) instruction is 22260484Sobrienrepeated with: 22360484Sobrien 22433965Sjdp@smallexample 22560484Sobrien repne scas %es:(%edi),%al 22633965Sjdp@end smallexample 22733965Sjdp 22860484SobrienYou may also place prefixes on the lines immediately preceding the 22960484Sobrieninstruction, but this circumvents checks that @code{@value{AS}} does 23060484Sobrienwith prefixes, and will not work with all prefixes. 23133965Sjdp 23260484SobrienHere is a list of instruction prefixes: 23360484Sobrien 23433965Sjdp@cindex section override prefixes, i386 23533965Sjdp@itemize @bullet 23633965Sjdp@item 23733965SjdpSection override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, 23833965Sjdp@samp{fs}, @samp{gs}. These are automatically added by specifying 23933965Sjdpusing the @var{section}:@var{memory-operand} form for memory references. 24033965Sjdp 24133965Sjdp@cindex size prefixes, i386 24233965Sjdp@item 24333965SjdpOperand/Address size prefixes @samp{data16} and @samp{addr16} 24460484Sobrienchange 32-bit operands/addresses into 16-bit operands/addresses, 24560484Sobrienwhile @samp{data32} and @samp{addr32} change 16-bit ones (in a 24660484Sobrien@code{.code16} section) into 32-bit operands/addresses. These prefixes 24760484Sobrien@emph{must} appear on the same line of code as the instruction they 24860484Sobrienmodify. For example, in a 16-bit @code{.code16} section, you might 24960484Sobrienwrite: 25033965Sjdp 25160484Sobrien@smallexample 25260484Sobrien addr32 jmpl *(%ebx) 25360484Sobrien@end smallexample 25460484Sobrien 25533965Sjdp@cindex bus lock prefixes, i386 25633965Sjdp@cindex inhibiting interrupts, i386 25733965Sjdp@item 25860484SobrienThe bus lock prefix @samp{lock} inhibits interrupts during execution of 25960484Sobrienthe instruction it precedes. (This is only valid with certain 26060484Sobrieninstructions; see a 80386 manual for details). 26133965Sjdp 26233965Sjdp@cindex coprocessor wait, i386 26333965Sjdp@item 26460484SobrienThe wait for coprocessor prefix @samp{wait} waits for the coprocessor to 26560484Sobriencomplete the current instruction. This should never be needed for the 26660484Sobrien80386/80387 combination. 26733965Sjdp 26833965Sjdp@cindex repeat prefixes, i386 26933965Sjdp@item 27033965SjdpThe @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added 27160484Sobriento string instructions to make them repeat @samp{%ecx} times (@samp{%cx} 27260484Sobrientimes if the current address size is 16-bits). 27333965Sjdp@end itemize 27433965Sjdp 27533965Sjdp@node i386-Memory 27633965Sjdp@section Memory References 27733965Sjdp 27833965Sjdp@cindex i386 memory references 27933965Sjdp@cindex memory references, i386 28033965SjdpAn Intel syntax indirect memory reference of the form 28133965Sjdp 28233965Sjdp@smallexample 28333965Sjdp@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] 28433965Sjdp@end smallexample 28533965Sjdp 28633965Sjdp@noindent 28733965Sjdpis translated into the AT&T syntax 28833965Sjdp 28933965Sjdp@smallexample 29033965Sjdp@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) 29133965Sjdp@end smallexample 29233965Sjdp 29333965Sjdp@noindent 29433965Sjdpwhere @var{base} and @var{index} are the optional 32-bit base and 29533965Sjdpindex registers, @var{disp} is the optional displacement, and 29633965Sjdp@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} 29733965Sjdpto calculate the address of the operand. If no @var{scale} is 29833965Sjdpspecified, @var{scale} is taken to be 1. @var{section} specifies the 29933965Sjdpoptional section register for the memory operand, and may override the 30033965Sjdpdefault section register (see a 80386 manual for section register 30160484Sobriendefaults). Note that section overrides in AT&T syntax @emph{must} 30233965Sjdpbe preceded by a @samp{%}. If you specify a section override which 30333965Sjdpcoincides with the default section register, @code{@value{AS}} does @emph{not} 30433965Sjdpoutput any section register override prefixes to assemble the given 30533965Sjdpinstruction. Thus, section overrides can be specified to emphasize which 30633965Sjdpsection register is used for a given memory operand. 30733965Sjdp 30833965SjdpHere are some examples of Intel and AT&T style memory references: 30933965Sjdp 31033965Sjdp@table @asis 31133965Sjdp@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} 31233965Sjdp@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is 31333965Sjdpmissing, and the default section is used (@samp{%ss} for addressing with 31433965Sjdp@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. 31533965Sjdp 31633965Sjdp@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} 31733965Sjdp@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is 31833965Sjdp@samp{foo}. All other fields are missing. The section register here 31933965Sjdpdefaults to @samp{%ds}. 32033965Sjdp 32133965Sjdp@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} 32233965SjdpThis uses the value pointed to by @samp{foo} as a memory operand. 32333965SjdpNote that @var{base} and @var{index} are both missing, but there is only 32433965Sjdp@emph{one} @samp{,}. This is a syntactic exception. 32533965Sjdp 32633965Sjdp@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} 32733965SjdpThis selects the contents of the variable @samp{foo} with section 32833965Sjdpregister @var{section} being @samp{%gs}. 32933965Sjdp@end table 33033965Sjdp 33133965SjdpAbsolute (as opposed to PC relative) call and jump operands must be 33233965Sjdpprefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} 33333965Sjdpalways chooses PC relative addressing for jump/call labels. 33433965Sjdp 33560484SobrienAny instruction that has a memory operand, but no register operand, 33660484Sobrien@emph{must} specify its size (byte, word, or long) with an instruction 33760484Sobrienmnemonic suffix (@samp{b}, @samp{w}, or @samp{l}, respectively). 33833965Sjdp 33933965Sjdp@node i386-jumps 34033965Sjdp@section Handling of Jump Instructions 34133965Sjdp 34233965Sjdp@cindex jump optimization, i386 34333965Sjdp@cindex i386 jump optimization 34433965SjdpJump instructions are always optimized to use the smallest possible 34533965Sjdpdisplacements. This is accomplished by using byte (8-bit) displacement 34633965Sjdpjumps whenever the target is sufficiently close. If a byte displacement 34733965Sjdpis insufficient a long (32-bit) displacement is used. We do not support 34860484Sobrienword (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 34960484Sobrieninstruction with the @samp{data16} instruction prefix), since the 80386 35060484Sobrieninsists upon masking @samp{%eip} to 16 bits after the word displacement 35160484Sobrienis added. 35233965Sjdp 35333965SjdpNote that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, 35433965Sjdp@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte 35533965Sjdpdisplacements, so that if you use these instructions (@code{@value{GCC}} does 35633965Sjdpnot use them) you may get an error message (and incorrect code). The AT&T 35733965Sjdp80386 assembler tries to get around this problem by expanding @samp{jcxz foo} 35833965Sjdpto 35933965Sjdp 36033965Sjdp@smallexample 36133965Sjdp jcxz cx_zero 36233965Sjdp jmp cx_nonzero 36333965Sjdpcx_zero: jmp foo 36433965Sjdpcx_nonzero: 36533965Sjdp@end smallexample 36633965Sjdp 36733965Sjdp@node i386-Float 36833965Sjdp@section Floating Point 36933965Sjdp 37033965Sjdp@cindex i386 floating point 37133965Sjdp@cindex floating point, i386 37233965SjdpAll 80387 floating point types except packed BCD are supported. 37333965Sjdp(BCD support may be added without much difficulty). These data 37433965Sjdptypes are 16-, 32-, and 64- bit integers, and single (32-bit), 37533965Sjdpdouble (64-bit), and extended (80-bit) precision floating point. 37660484SobrienEach supported type has an instruction mnemonic suffix and a constructor 37760484Sobrienassociated with it. Instruction mnemonic suffixes specify the operand's 37860484Sobriendata type. Constructors build these data types into memory. 37933965Sjdp 38033965Sjdp@cindex @code{float} directive, i386 38133965Sjdp@cindex @code{single} directive, i386 38233965Sjdp@cindex @code{double} directive, i386 38333965Sjdp@cindex @code{tfloat} directive, i386 38433965Sjdp@itemize @bullet 38533965Sjdp@item 38633965SjdpFloating point constructors are @samp{.float} or @samp{.single}, 38733965Sjdp@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. 38860484SobrienThese correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, 38960484Sobrienand @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 39060484Sobrienonly supports this format via the @samp{fldt} (load 80-bit real to stack 39160484Sobrientop) and @samp{fstpt} (store 80-bit real and pop stack) instructions. 39233965Sjdp 39333965Sjdp@cindex @code{word} directive, i386 39433965Sjdp@cindex @code{long} directive, i386 39533965Sjdp@cindex @code{int} directive, i386 39633965Sjdp@cindex @code{quad} directive, i386 39733965Sjdp@item 39833965SjdpInteger constructors are @samp{.word}, @samp{.long} or @samp{.int}, and 39960484Sobrien@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The 40060484Sobriencorresponding instruction mnemonic suffixes are @samp{s} (single), 40160484Sobrien@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, 40260484Sobrienthe 64-bit @samp{q} format is only present in the @samp{fildq} (load 40360484Sobrienquad integer to stack top) and @samp{fistpq} (store quad integer and pop 40460484Sobrienstack) instructions. 40533965Sjdp@end itemize 40633965Sjdp 40760484SobrienRegister to register operations should not use instruction mnemonic suffixes. 40860484Sobrien@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you 40960484Sobrienwrote @samp{fst %st, %st(1)}, since all register to register operations 41060484Sobrienuse 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, 41160484Sobrienwhich converts @samp{%st} from 80-bit to 64-bit floating point format, 41260484Sobrienthen stores the result in the 4 byte location @samp{mem}) 41333965Sjdp 41460484Sobrien@node i386-SIMD 41560484Sobrien@section Intel's MMX and AMD's 3DNow! SIMD Operations 41660484Sobrien 41760484Sobrien@cindex MMX, i386 41860484Sobrien@cindex 3DNow!, i386 41960484Sobrien@cindex SIMD, i386 42060484Sobrien 42160484Sobrien@code{@value{AS}} supports Intel's MMX instruction set (SIMD 42260484Sobrieninstructions for integer data), available on Intel's Pentium MMX 42360484Sobrienprocessors and Pentium II processors, AMD's K6 and K6-2 processors, 42460484SobrienCyrix' M2 processor, and probably others. It also supports AMD's 3DNow! 42560484Sobrieninstruction set (SIMD instructions for 32-bit floating point data) 42660484Sobrienavailable on AMD's K6-2 processor and possibly others in the future. 42760484Sobrien 42860484SobrienCurrently, @code{@value{AS}} does not support Intel's floating point 42960484SobrienSIMD, Katmai (KNI). 43060484Sobrien 43160484SobrienThe eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, 43260484Sobrien@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four 43360484Sobrien16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 43460484Sobrienfloating point values. The MMX registers cannot be used at the same time 43560484Sobrienas the floating point stack. 43660484Sobrien 43760484SobrienSee Intel and AMD documentation, keeping in mind that the operand order in 43860484Sobrieninstructions is reversed from the Intel syntax. 43960484Sobrien 44033965Sjdp@node i386-16bit 44133965Sjdp@section Writing 16-bit Code 44233965Sjdp 44333965Sjdp@cindex i386 16-bit code 44433965Sjdp@cindex 16-bit code, i386 44533965Sjdp@cindex real-mode code, i386 44660484Sobrien@cindex @code{code16gcc} directive, i386 44733965Sjdp@cindex @code{code16} directive, i386 44833965Sjdp@cindex @code{code32} directive, i386 44960484SobrienWhile @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code, 45060484Sobrienit also supports writing code to run in real mode or in 16-bit protected 45160484Sobrienmode code segments. To do this, put a @samp{.code16} or 45260484Sobrien@samp{.code16gcc} directive before the assembly language instructions to 45360484Sobrienbe run in 16-bit mode. You can switch @code{@value{AS}} back to writing 45460484Sobriennormal 32-bit code with the @samp{.code32} directive. 45533965Sjdp 45660484Sobrien@samp{.code16gcc} provides experimental support for generating 16-bit 45760484Sobriencode from gcc, and differs from @samp{.code16} in that @samp{call}, 45860484Sobrien@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, 45960484Sobrien@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions 46060484Sobriendefault to 32-bit size. This is so that the stack pointer is 46160484Sobrienmanipulated in the same way over function calls, allowing access to 46260484Sobrienfunction parameters at the same stack offsets as in 32-bit mode. 46360484Sobrien@samp{.code16gcc} also automatically adds address size prefixes where 46460484Sobriennecessary to use the 32-bit addressing modes that gcc generates. 46533965Sjdp 46660484SobrienThe code which @code{@value{AS}} generates in 16-bit mode will not 46760484Sobriennecessarily run on a 16-bit pre-80386 processor. To write code that 46860484Sobrienruns on such a processor, you must refrain from using @emph{any} 32-bit 46960484Sobrienconstructs which require @code{@value{AS}} to output address or operand 47060484Sobriensize prefixes. 47133965Sjdp 47260484SobrienNote that writing 16-bit code instructions by explicitly specifying a 47360484Sobrienprefix or an instruction mnemonic suffix within a 32-bit code section 47460484Sobriengenerates different machine instructions than those generated for a 47560484Sobrien16-bit code segment. In a 32-bit code section, the following code 47660484Sobriengenerates the machine opcode bytes @samp{66 6a 04}, which pushes the 47760484Sobrienvalue @samp{4} onto the stack, decrementing @samp{%esp} by 2. 47833965Sjdp 47960484Sobrien@smallexample 48060484Sobrien pushw $4 48160484Sobrien@end smallexample 48260484Sobrien 48360484SobrienThe same code in a 16-bit code section would generate the machine 48460484Sobrienopcode bytes @samp{6a 04} (ie. without the operand size prefix), which 48560484Sobrienis correct since the processor default operand size is assumed to be 16 48660484Sobrienbits in a 16-bit code section. 48760484Sobrien 48860484Sobrien@node i386-Bugs 48960484Sobrien@section AT&T Syntax bugs 49060484Sobrien 49160484SobrienThe UnixWare assembler, and probably other AT&T derived ix86 Unix 49260484Sobrienassemblers, generate floating point instructions with reversed source 49360484Sobrienand destination registers in certain cases. Unfortunately, gcc and 49460484Sobrienpossibly many other programs use this reversed syntax, so we're stuck 49560484Sobrienwith it. 49660484Sobrien 49760484SobrienFor example 49860484Sobrien 49960484Sobrien@smallexample 50060484Sobrien fsub %st,%st(3) 50160484Sobrien@end smallexample 50260484Sobrien@noindent 50360484Sobrienresults in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather 50460484Sobrienthan the expected @samp{%st(3) - %st}. This happens with all the 50560484Sobriennon-commutative arithmetic floating point operations with two register 50660484Sobrienoperands where the source register is @samp{%st} and the destination 50760484Sobrienregister is @samp{%st(i)}. 50860484Sobrien 50933965Sjdp@node i386-Notes 51033965Sjdp@section Notes 51133965Sjdp 51233965Sjdp@cindex i386 @code{mul}, @code{imul} instructions 51333965Sjdp@cindex @code{mul} instruction, i386 51433965Sjdp@cindex @code{imul} instruction, i386 51533965SjdpThere is some trickery concerning the @samp{mul} and @samp{imul} 51633965Sjdpinstructions that deserves mention. The 16-, 32-, and 64-bit expanding 51733965Sjdpmultiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 51833965Sjdpfor @samp{imul}) can be output only in the one operand form. Thus, 51933965Sjdp@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; 52033965Sjdpthe expanding multiply would clobber the @samp{%edx} register, and this 52133965Sjdpwould confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the 52233965Sjdp64-bit product in @samp{%edx:%eax}. 52333965Sjdp 52433965SjdpWe have added a two operand form of @samp{imul} when the first operand 52533965Sjdpis an immediate mode expression and the second operand is a register. 52633965SjdpThis is just a shorthand, so that, multiplying @samp{%eax} by 69, for 52733965Sjdpexample, can be done with @samp{imul $69, %eax} rather than @samp{imul 52833965Sjdp$69, %eax, %eax}. 52933965Sjdp 530