1218822Sdim@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2218822Sdim@c 2001, 2003, 2004 378828Sobrien@c Free Software Foundation, Inc. 433965Sjdp@c This is part of the GAS manual. 533965Sjdp@c For copying conditions, see the file as.texinfo. 633965Sjdp@ifset GENERIC 733965Sjdp@page 833965Sjdp@node i386-Dependent 933965Sjdp@chapter 80386 Dependent Features 1033965Sjdp@end ifset 1133965Sjdp@ifclear GENERIC 1233965Sjdp@node Machine Dependencies 1333965Sjdp@chapter 80386 Dependent Features 1433965Sjdp@end ifclear 1533965Sjdp 1633965Sjdp@cindex i386 support 1733965Sjdp@cindex i80306 support 1877298Sobrien@cindex x86-64 support 1977298Sobrien 2077298SobrienThe i386 version @code{@value{AS}} supports both the original Intel 386 2177298Sobrienarchitecture in both 16 and 32-bit mode as well as AMD x86-64 architecture 2277298Sobrienextending the Intel architecture to 64-bits. 2377298Sobrien 2433965Sjdp@menu 2533965Sjdp* i386-Options:: Options 2633965Sjdp* i386-Syntax:: AT&T Syntax versus Intel Syntax 2760484Sobrien* i386-Mnemonics:: Instruction Naming 2833965Sjdp* i386-Regs:: Register Naming 2960484Sobrien* i386-Prefixes:: Instruction Prefixes 3033965Sjdp* i386-Memory:: Memory References 3178828Sobrien* i386-Jumps:: Handling of Jump Instructions 3233965Sjdp* i386-Float:: Floating Point 3360484Sobrien* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 3433965Sjdp* i386-16bit:: Writing 16-bit Code 3577298Sobrien* i386-Arch:: Specifying an x86 CPU architecture 3660484Sobrien* i386-Bugs:: AT&T Syntax bugs 3733965Sjdp* i386-Notes:: Notes 3833965Sjdp@end menu 3933965Sjdp 4033965Sjdp@node i386-Options 4133965Sjdp@section Options 4233965Sjdp 4377298Sobrien@cindex options for i386 4477298Sobrien@cindex options for x86-64 4577298Sobrien@cindex i386 options 4677298Sobrien@cindex x86-64 options 4733965Sjdp 4877298SobrienThe i386 version of @code{@value{AS}} has a few machine 4977298Sobriendependent options: 5077298Sobrien 5177298Sobrien@table @code 5277298Sobrien@cindex @samp{--32} option, i386 5377298Sobrien@cindex @samp{--32} option, x86-64 5477298Sobrien@cindex @samp{--64} option, i386 5577298Sobrien@cindex @samp{--64} option, x86-64 5677298Sobrien@item --32 | --64 5777298SobrienSelect the word size, either 32 bits or 64 bits. Selecting 32-bit 5877298Sobrienimplies Intel i386 architecture, while 64-bit implies AMD x86-64 5977298Sobrienarchitecture. 6077298Sobrien 6177298SobrienThese options are only available with the ELF object file format, and 6277298Sobrienrequire that the necessary BFD support has been included (on a 32-bit 6377298Sobrienplatform you have to add --enable-64-bit-bfd to configure enable 64-bit 6477298Sobrienusage and use x86-64 as target platform). 65130561Sobrien 66130561Sobrien@item -n 67130561SobrienBy default, x86 GAS replaces multiple nop instructions used for 68130561Sobrienalignment within code sections with multi-byte nop instructions such 69130561Sobrienas leal 0(%esi,1),%esi. This switch disables the optimization. 70218822Sdim 71218822Sdim@cindex @samp{--divide} option, i386 72218822Sdim@item --divide 73218822SdimOn SVR4-derived platforms, the character @samp{/} is treated as a comment 74218822Sdimcharacter, which means that it cannot be used in expressions. The 75218822Sdim@samp{--divide} option turns @samp{/} into a normal character. This does 76218822Sdimnot disable @samp{/} at the beginning of a line starting a comment, or 77218822Sdimaffect using @samp{#} for starting a comment. 78218822Sdim 79218822Sdim@cindex @samp{-march=} option, i386 80218822Sdim@cindex @samp{-march=} option, x86-64 81218822Sdim@item -march=@var{CPU} 82218822SdimThis option specifies an instruction set architecture for generating 83218822Sdiminstructions. The following architectures are recognized: 84218822Sdim@code{i8086}, 85218822Sdim@code{i186}, 86218822Sdim@code{i286}, 87218822Sdim@code{i386}, 88218822Sdim@code{i486}, 89218822Sdim@code{i586}, 90218822Sdim@code{i686}, 91218822Sdim@code{pentium}, 92218822Sdim@code{pentiumpro}, 93218822Sdim@code{pentiumii}, 94218822Sdim@code{pentiumiii}, 95218822Sdim@code{pentium4}, 96218822Sdim@code{prescott}, 97218822Sdim@code{nocona}, 98218822Sdim@code{core}, 99218822Sdim@code{core2}, 100218822Sdim@code{k6}, 101218822Sdim@code{k6_2}, 102218822Sdim@code{athlon}, 103218822Sdim@code{sledgehammer}, 104218822Sdim@code{opteron}, 105218822Sdim@code{k8}, 106218822Sdim@code{generic32} and 107218822Sdim@code{generic64}. 108218822Sdim 109218822SdimThis option only affects instructions generated by the assembler. The 110218822Sdim@code{.arch} directive will take precedent. 111218822Sdim 112218822Sdim@cindex @samp{-mtune=} option, i386 113218822Sdim@cindex @samp{-mtune=} option, x86-64 114218822Sdim@item -mtune=@var{CPU} 115218822SdimThis option specifies a processor to optimize for. When used in 116218822Sdimconjunction with the @option{-march} option, only instructions 117218822Sdimof the processor specified by the @option{-march} option will be 118218822Sdimgenerated. 119218822Sdim 120218822SdimValid @var{CPU} values are identical to @option{-march=@var{CPU}}. 121218822Sdim 12277298Sobrien@end table 12377298Sobrien 12433965Sjdp@node i386-Syntax 12533965Sjdp@section AT&T Syntax versus Intel Syntax 12633965Sjdp 12777298Sobrien@cindex i386 intel_syntax pseudo op 12877298Sobrien@cindex intel_syntax pseudo op, i386 12977298Sobrien@cindex i386 att_syntax pseudo op 13077298Sobrien@cindex att_syntax pseudo op, i386 13133965Sjdp@cindex i386 syntax compatibility 13233965Sjdp@cindex syntax compatibility, i386 13377298Sobrien@cindex x86-64 intel_syntax pseudo op 13477298Sobrien@cindex intel_syntax pseudo op, x86-64 13577298Sobrien@cindex x86-64 att_syntax pseudo op 13677298Sobrien@cindex att_syntax pseudo op, x86-64 13777298Sobrien@cindex x86-64 syntax compatibility 13877298Sobrien@cindex syntax compatibility, x86-64 13977298Sobrien 14077298Sobrien@code{@value{AS}} now supports assembly using Intel assembler syntax. 14177298Sobrien@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches 14277298Sobrienback to the usual AT&T mode for compatibility with the output of 14377298Sobrien@code{@value{GCC}}. Either of these directives may have an optional 14477298Sobrienargument, @code{prefix}, or @code{noprefix} specifying whether registers 14577298Sobrienrequire a @samp{%} prefix. AT&T System V/386 assembler syntax is quite 14633965Sjdpdifferent from Intel syntax. We mention these differences because 14760484Sobrienalmost all 80386 documents use Intel syntax. Notable differences 14833965Sjdpbetween the two syntaxes are: 14933965Sjdp 15033965Sjdp@cindex immediate operands, i386 15133965Sjdp@cindex i386 immediate operands 15233965Sjdp@cindex register operands, i386 15333965Sjdp@cindex i386 register operands 15433965Sjdp@cindex jump/call operands, i386 15533965Sjdp@cindex i386 jump/call operands 15633965Sjdp@cindex operand delimiters, i386 15777298Sobrien 15877298Sobrien@cindex immediate operands, x86-64 15977298Sobrien@cindex x86-64 immediate operands 16077298Sobrien@cindex register operands, x86-64 16177298Sobrien@cindex x86-64 register operands 16277298Sobrien@cindex jump/call operands, x86-64 16377298Sobrien@cindex x86-64 jump/call operands 16477298Sobrien@cindex operand delimiters, x86-64 16533965Sjdp@itemize @bullet 16633965Sjdp@item 16733965SjdpAT&T immediate operands are preceded by @samp{$}; Intel immediate 16833965Sjdpoperands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). 16933965SjdpAT&T register operands are preceded by @samp{%}; Intel register operands 17033965Sjdpare undelimited. AT&T absolute (as opposed to PC relative) jump/call 17133965Sjdpoperands are prefixed by @samp{*}; they are undelimited in Intel syntax. 17233965Sjdp 17333965Sjdp@cindex i386 source, destination operands 17433965Sjdp@cindex source, destination operands; i386 17577298Sobrien@cindex x86-64 source, destination operands 17677298Sobrien@cindex source, destination operands; x86-64 17733965Sjdp@item 17833965SjdpAT&T and Intel syntax use the opposite order for source and destination 17933965Sjdpoperands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The 18033965Sjdp@samp{source, dest} convention is maintained for compatibility with 18160484Sobrienprevious Unix assemblers. Note that instructions with more than one 18260484Sobriensource operand, such as the @samp{enter} instruction, do @emph{not} have 18360484Sobrienreversed order. @ref{i386-Bugs}. 18433965Sjdp 18560484Sobrien@cindex mnemonic suffixes, i386 18633965Sjdp@cindex sizes operands, i386 18733965Sjdp@cindex i386 size suffixes 18877298Sobrien@cindex mnemonic suffixes, x86-64 18977298Sobrien@cindex sizes operands, x86-64 19077298Sobrien@cindex x86-64 size suffixes 19133965Sjdp@item 19233965SjdpIn AT&T syntax the size of memory operands is determined from the last 19360484Sobriencharacter of the instruction mnemonic. Mnemonic suffixes of @samp{b}, 19477298Sobrien@samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long 19577298Sobrien(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes 19677298Sobrienthis by prefixing memory operands (@emph{not} the instruction mnemonics) with 19777298Sobrien@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus, 19877298SobrienIntel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T 19977298Sobriensyntax. 20033965Sjdp 20133965Sjdp@cindex return instructions, i386 20233965Sjdp@cindex i386 jump, call, return 20377298Sobrien@cindex return instructions, x86-64 20477298Sobrien@cindex x86-64 jump, call, return 20533965Sjdp@item 20633965SjdpImmediate form long jumps and calls are 20733965Sjdp@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the 20833965SjdpIntel syntax is 20933965Sjdp@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return 21033965Sjdpinstruction 21133965Sjdpis @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is 21233965Sjdp@samp{ret far @var{stack-adjust}}. 21333965Sjdp 21433965Sjdp@cindex sections, i386 21533965Sjdp@cindex i386 sections 21677298Sobrien@cindex sections, x86-64 21777298Sobrien@cindex x86-64 sections 21833965Sjdp@item 21933965SjdpThe AT&T assembler does not provide support for multiple section 22033965Sjdpprograms. Unix style systems expect all programs to be single sections. 22133965Sjdp@end itemize 22233965Sjdp 22360484Sobrien@node i386-Mnemonics 22460484Sobrien@section Instruction Naming 22533965Sjdp 22660484Sobrien@cindex i386 instruction naming 22760484Sobrien@cindex instruction naming, i386 22877298Sobrien@cindex x86-64 instruction naming 22977298Sobrien@cindex instruction naming, x86-64 23077298Sobrien 23160484SobrienInstruction mnemonics are suffixed with one character modifiers which 23277298Sobrienspecify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} 23377298Sobrienand @samp{q} specify byte, word, long and quadruple word operands. If 23477298Sobrienno suffix is specified by an instruction then @code{@value{AS}} tries to 23577298Sobrienfill in the missing suffix based on the destination register operand 23677298Sobrien(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent 23777298Sobriento @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to 23877298Sobrien@samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix 23977298Sobrienassembler which assumes that a missing mnemonic suffix implies long 24077298Sobrienoperand size. (This incompatibility does not affect compiler output 24177298Sobriensince compilers always explicitly specify the mnemonic suffix.) 24233965Sjdp 24360484SobrienAlmost all instructions have the same names in AT&T and Intel format. 24460484SobrienThere are a few exceptions. The sign extend and zero extend 24560484Sobrieninstructions need two sizes to specify them. They need a size to 24660484Sobriensign/zero extend @emph{from} and a size to zero extend @emph{to}. This 24760484Sobrienis accomplished by using two instruction mnemonic suffixes in AT&T 24860484Sobriensyntax. Base names for sign extend and zero extend are 24960484Sobrien@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} 25060484Sobrienand @samp{movzx} in Intel syntax). The instruction mnemonic suffixes 25160484Sobrienare tacked on to this base name, the @emph{from} suffix before the 25260484Sobrien@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for 25333965Sjdp``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, 25433965Sjdpthus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), 25577298Sobrien@samp{wl} (from word to long), @samp{bq} (from byte to quadruple word), 25677298Sobrien@samp{wq} (from word to quadruple word), and @samp{lq} (from long to 25777298Sobrienquadruple word). 25833965Sjdp 25933965Sjdp@cindex conversion instructions, i386 26033965Sjdp@cindex i386 conversion instructions 26177298Sobrien@cindex conversion instructions, x86-64 26277298Sobrien@cindex x86-64 conversion instructions 26333965SjdpThe Intel-syntax conversion instructions 26433965Sjdp 26533965Sjdp@itemize @bullet 26633965Sjdp@item 26733965Sjdp@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, 26833965Sjdp 26933965Sjdp@item 27033965Sjdp@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, 27133965Sjdp 27233965Sjdp@item 27333965Sjdp@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, 27433965Sjdp 27533965Sjdp@item 27633965Sjdp@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, 27777298Sobrien 27877298Sobrien@item 27977298Sobrien@samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} 28077298Sobrien(x86-64 only), 28177298Sobrien 28277298Sobrien@item 283218822Sdim@samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in 28477298Sobrien@samp{%rdx:%rax} (x86-64 only), 28533965Sjdp@end itemize 28633965Sjdp 28733965Sjdp@noindent 28877298Sobrienare called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and 28977298Sobrien@samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these 29077298Sobrieninstructions. 29133965Sjdp 29233965Sjdp@cindex jump instructions, i386 29333965Sjdp@cindex call instructions, i386 29477298Sobrien@cindex jump instructions, x86-64 29577298Sobrien@cindex call instructions, x86-64 29633965SjdpFar call/jump instructions are @samp{lcall} and @samp{ljmp} in 29733965SjdpAT&T syntax, but are @samp{call far} and @samp{jump far} in Intel 29833965Sjdpconvention. 29933965Sjdp 30033965Sjdp@node i386-Regs 30133965Sjdp@section Register Naming 30233965Sjdp 30333965Sjdp@cindex i386 registers 30433965Sjdp@cindex registers, i386 30577298Sobrien@cindex x86-64 registers 30677298Sobrien@cindex registers, x86-64 30760484SobrienRegister operands are always prefixed with @samp{%}. The 80386 registers 30833965Sjdpconsist of 30933965Sjdp 31033965Sjdp@itemize @bullet 31133965Sjdp@item 31233965Sjdpthe 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, 31333965Sjdp@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the 31433965Sjdpframe pointer), and @samp{%esp} (the stack pointer). 31533965Sjdp 31633965Sjdp@item 31733965Sjdpthe 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, 31833965Sjdp@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. 31933965Sjdp 32033965Sjdp@item 32133965Sjdpthe 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, 32233965Sjdp@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These 32333965Sjdpare the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, 32433965Sjdp@samp{%cx}, and @samp{%dx}) 32533965Sjdp 32633965Sjdp@item 32733965Sjdpthe 6 section registers @samp{%cs} (code section), @samp{%ds} 32833965Sjdp(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, 32933965Sjdpand @samp{%gs}. 33033965Sjdp 33133965Sjdp@item 33233965Sjdpthe 3 processor control registers @samp{%cr0}, @samp{%cr2}, and 33333965Sjdp@samp{%cr3}. 33433965Sjdp 33533965Sjdp@item 33633965Sjdpthe 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, 33733965Sjdp@samp{%db3}, @samp{%db6}, and @samp{%db7}. 33833965Sjdp 33933965Sjdp@item 34033965Sjdpthe 2 test registers @samp{%tr6} and @samp{%tr7}. 34133965Sjdp 34233965Sjdp@item 34333965Sjdpthe 8 floating point register stack @samp{%st} or equivalently 34433965Sjdp@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, 34533965Sjdp@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. 34677298SobrienThese registers are overloaded by 8 MMX registers @samp{%mm0}, 34777298Sobrien@samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, 34877298Sobrien@samp{%mm6} and @samp{%mm7}. 34977298Sobrien 35077298Sobrien@item 35177298Sobrienthe 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, 35277298Sobrien@samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. 35333965Sjdp@end itemize 35433965Sjdp 35577298SobrienThe AMD x86-64 architecture extends the register set by: 35677298Sobrien 35777298Sobrien@itemize @bullet 35877298Sobrien@item 35977298Sobrienenhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the 36077298Sobrienaccumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, 36177298Sobrien@samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack 36277298Sobrienpointer) 36377298Sobrien 36477298Sobrien@item 36577298Sobrienthe 8 extended registers @samp{%r8}--@samp{%r15}. 36677298Sobrien 36777298Sobrien@item 36877298Sobrienthe 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d} 36977298Sobrien 37077298Sobrien@item 37177298Sobrienthe 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w} 37277298Sobrien 37377298Sobrien@item 37477298Sobrienthe 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b} 37577298Sobrien 37677298Sobrien@item 37777298Sobrienthe 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. 37877298Sobrien 37977298Sobrien@item 38077298Sobrienthe 8 debug registers: @samp{%db8}--@samp{%db15}. 38177298Sobrien 38277298Sobrien@item 38377298Sobrienthe 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}. 38477298Sobrien@end itemize 38577298Sobrien 38660484Sobrien@node i386-Prefixes 38760484Sobrien@section Instruction Prefixes 38833965Sjdp 38960484Sobrien@cindex i386 instruction prefixes 39060484Sobrien@cindex instruction prefixes, i386 39133965Sjdp@cindex prefixes, i386 39260484SobrienInstruction prefixes are used to modify the following instruction. They 39360484Sobrienare used to repeat string instructions, to provide section overrides, to 39460484Sobrienperform bus lock operations, and to change operand and address sizes. 39560484Sobrien(Most instructions that normally operate on 32-bit operands will use 39660484Sobrien16-bit operands if the instruction has an ``operand size'' prefix.) 39760484SobrienInstruction prefixes are best written on the same line as the instruction 39860484Sobrienthey act upon. For example, the @samp{scas} (scan string) instruction is 39960484Sobrienrepeated with: 40060484Sobrien 40133965Sjdp@smallexample 40260484Sobrien repne scas %es:(%edi),%al 40333965Sjdp@end smallexample 40433965Sjdp 40560484SobrienYou may also place prefixes on the lines immediately preceding the 40660484Sobrieninstruction, but this circumvents checks that @code{@value{AS}} does 40760484Sobrienwith prefixes, and will not work with all prefixes. 40833965Sjdp 40960484SobrienHere is a list of instruction prefixes: 41060484Sobrien 41133965Sjdp@cindex section override prefixes, i386 41233965Sjdp@itemize @bullet 41333965Sjdp@item 41433965SjdpSection override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, 41533965Sjdp@samp{fs}, @samp{gs}. These are automatically added by specifying 41633965Sjdpusing the @var{section}:@var{memory-operand} form for memory references. 41733965Sjdp 41833965Sjdp@cindex size prefixes, i386 41933965Sjdp@item 42033965SjdpOperand/Address size prefixes @samp{data16} and @samp{addr16} 42160484Sobrienchange 32-bit operands/addresses into 16-bit operands/addresses, 42260484Sobrienwhile @samp{data32} and @samp{addr32} change 16-bit ones (in a 42360484Sobrien@code{.code16} section) into 32-bit operands/addresses. These prefixes 42460484Sobrien@emph{must} appear on the same line of code as the instruction they 42560484Sobrienmodify. For example, in a 16-bit @code{.code16} section, you might 42660484Sobrienwrite: 42733965Sjdp 42860484Sobrien@smallexample 42960484Sobrien addr32 jmpl *(%ebx) 43060484Sobrien@end smallexample 43160484Sobrien 43233965Sjdp@cindex bus lock prefixes, i386 43333965Sjdp@cindex inhibiting interrupts, i386 43433965Sjdp@item 43560484SobrienThe bus lock prefix @samp{lock} inhibits interrupts during execution of 43660484Sobrienthe instruction it precedes. (This is only valid with certain 43760484Sobrieninstructions; see a 80386 manual for details). 43833965Sjdp 43933965Sjdp@cindex coprocessor wait, i386 44033965Sjdp@item 44160484SobrienThe wait for coprocessor prefix @samp{wait} waits for the coprocessor to 44260484Sobriencomplete the current instruction. This should never be needed for the 44360484Sobrien80386/80387 combination. 44433965Sjdp 44533965Sjdp@cindex repeat prefixes, i386 44633965Sjdp@item 44733965SjdpThe @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added 44860484Sobriento string instructions to make them repeat @samp{%ecx} times (@samp{%cx} 44960484Sobrientimes if the current address size is 16-bits). 45077298Sobrien@cindex REX prefixes, i386 45177298Sobrien@item 45277298SobrienThe @samp{rex} family of prefixes is used by x86-64 to encode 45377298Sobrienextensions to i386 instruction set. The @samp{rex} prefix has four 45477298Sobrienbits --- an operand size overwrite (@code{64}) used to change operand size 45577298Sobrienfrom 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 45677298Sobrienregister set. 45777298Sobrien 45877298SobrienYou may write the @samp{rex} prefixes directly. The @samp{rex64xyz} 45977298Sobrieninstruction emits @samp{rex} prefix with all the bits set. By omitting 46077298Sobrienthe @code{64}, @code{x}, @code{y} or @code{z} you may write other 46177298Sobrienprefixes as well. Normally, there is no need to write the prefixes 46277298Sobrienexplicitly, since gas will automatically generate them based on the 46377298Sobrieninstruction operands. 46433965Sjdp@end itemize 46533965Sjdp 46633965Sjdp@node i386-Memory 46733965Sjdp@section Memory References 46833965Sjdp 46933965Sjdp@cindex i386 memory references 47033965Sjdp@cindex memory references, i386 47177298Sobrien@cindex x86-64 memory references 47277298Sobrien@cindex memory references, x86-64 47333965SjdpAn Intel syntax indirect memory reference of the form 47433965Sjdp 47533965Sjdp@smallexample 47633965Sjdp@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] 47733965Sjdp@end smallexample 47833965Sjdp 47933965Sjdp@noindent 48033965Sjdpis translated into the AT&T syntax 48133965Sjdp 48233965Sjdp@smallexample 48333965Sjdp@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) 48433965Sjdp@end smallexample 48533965Sjdp 48633965Sjdp@noindent 48733965Sjdpwhere @var{base} and @var{index} are the optional 32-bit base and 48833965Sjdpindex registers, @var{disp} is the optional displacement, and 48933965Sjdp@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} 49033965Sjdpto calculate the address of the operand. If no @var{scale} is 49133965Sjdpspecified, @var{scale} is taken to be 1. @var{section} specifies the 49233965Sjdpoptional section register for the memory operand, and may override the 49333965Sjdpdefault section register (see a 80386 manual for section register 49460484Sobriendefaults). Note that section overrides in AT&T syntax @emph{must} 49533965Sjdpbe preceded by a @samp{%}. If you specify a section override which 49633965Sjdpcoincides with the default section register, @code{@value{AS}} does @emph{not} 49733965Sjdpoutput any section register override prefixes to assemble the given 49833965Sjdpinstruction. Thus, section overrides can be specified to emphasize which 49933965Sjdpsection register is used for a given memory operand. 50033965Sjdp 50133965SjdpHere are some examples of Intel and AT&T style memory references: 50233965Sjdp 50333965Sjdp@table @asis 50433965Sjdp@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} 50533965Sjdp@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is 50633965Sjdpmissing, and the default section is used (@samp{%ss} for addressing with 50733965Sjdp@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. 50833965Sjdp 50933965Sjdp@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} 51033965Sjdp@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is 51133965Sjdp@samp{foo}. All other fields are missing. The section register here 51233965Sjdpdefaults to @samp{%ds}. 51333965Sjdp 51433965Sjdp@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} 51533965SjdpThis uses the value pointed to by @samp{foo} as a memory operand. 51633965SjdpNote that @var{base} and @var{index} are both missing, but there is only 51733965Sjdp@emph{one} @samp{,}. This is a syntactic exception. 51833965Sjdp 51933965Sjdp@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} 52033965SjdpThis selects the contents of the variable @samp{foo} with section 52133965Sjdpregister @var{section} being @samp{%gs}. 52233965Sjdp@end table 52333965Sjdp 52433965SjdpAbsolute (as opposed to PC relative) call and jump operands must be 52533965Sjdpprefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} 52633965Sjdpalways chooses PC relative addressing for jump/call labels. 52733965Sjdp 52860484SobrienAny instruction that has a memory operand, but no register operand, 52977298Sobrien@emph{must} specify its size (byte, word, long, or quadruple) with an 53077298Sobrieninstruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, 53177298Sobrienrespectively). 53233965Sjdp 53377298SobrienThe x86-64 architecture adds an RIP (instruction pointer relative) 53477298Sobrienaddressing. This addressing mode is specified by using @samp{rip} as a 53577298Sobrienbase register. Only constant offsets are valid. For example: 53677298Sobrien 53777298Sobrien@table @asis 53877298Sobrien@item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} 53977298SobrienPoints to the address 1234 bytes past the end of the current 54077298Sobrieninstruction. 54177298Sobrien 54277298Sobrien@item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} 54377298SobrienPoints to the @code{symbol} in RIP relative way, this is shorter than 54477298Sobrienthe default absolute addressing. 54577298Sobrien@end table 54677298Sobrien 54777298SobrienOther addressing modes remain unchanged in x86-64 architecture, except 54877298Sobrienregisters used are 64-bit instead of 32-bit. 54977298Sobrien 55078828Sobrien@node i386-Jumps 55133965Sjdp@section Handling of Jump Instructions 55233965Sjdp 55333965Sjdp@cindex jump optimization, i386 55433965Sjdp@cindex i386 jump optimization 55577298Sobrien@cindex jump optimization, x86-64 55677298Sobrien@cindex x86-64 jump optimization 55733965SjdpJump instructions are always optimized to use the smallest possible 55833965Sjdpdisplacements. This is accomplished by using byte (8-bit) displacement 55933965Sjdpjumps whenever the target is sufficiently close. If a byte displacement 56078828Sobrienis insufficient a long displacement is used. We do not support 56160484Sobrienword (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 56260484Sobrieninstruction with the @samp{data16} instruction prefix), since the 80386 56360484Sobrieninsists upon masking @samp{%eip} to 16 bits after the word displacement 56478828Sobrienis added. (See also @pxref{i386-Arch}) 56533965Sjdp 56633965SjdpNote that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, 56733965Sjdp@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte 56833965Sjdpdisplacements, so that if you use these instructions (@code{@value{GCC}} does 56933965Sjdpnot use them) you may get an error message (and incorrect code). The AT&T 57033965Sjdp80386 assembler tries to get around this problem by expanding @samp{jcxz foo} 57133965Sjdpto 57233965Sjdp 57333965Sjdp@smallexample 57433965Sjdp jcxz cx_zero 57533965Sjdp jmp cx_nonzero 57633965Sjdpcx_zero: jmp foo 57733965Sjdpcx_nonzero: 57833965Sjdp@end smallexample 57933965Sjdp 58033965Sjdp@node i386-Float 58133965Sjdp@section Floating Point 58233965Sjdp 58333965Sjdp@cindex i386 floating point 58433965Sjdp@cindex floating point, i386 58577298Sobrien@cindex x86-64 floating point 58677298Sobrien@cindex floating point, x86-64 58733965SjdpAll 80387 floating point types except packed BCD are supported. 58833965Sjdp(BCD support may be added without much difficulty). These data 58933965Sjdptypes are 16-, 32-, and 64- bit integers, and single (32-bit), 59033965Sjdpdouble (64-bit), and extended (80-bit) precision floating point. 59160484SobrienEach supported type has an instruction mnemonic suffix and a constructor 59260484Sobrienassociated with it. Instruction mnemonic suffixes specify the operand's 59360484Sobriendata type. Constructors build these data types into memory. 59433965Sjdp 59533965Sjdp@cindex @code{float} directive, i386 59633965Sjdp@cindex @code{single} directive, i386 59733965Sjdp@cindex @code{double} directive, i386 59833965Sjdp@cindex @code{tfloat} directive, i386 59977298Sobrien@cindex @code{float} directive, x86-64 60077298Sobrien@cindex @code{single} directive, x86-64 60177298Sobrien@cindex @code{double} directive, x86-64 60277298Sobrien@cindex @code{tfloat} directive, x86-64 60333965Sjdp@itemize @bullet 60433965Sjdp@item 60533965SjdpFloating point constructors are @samp{.float} or @samp{.single}, 60633965Sjdp@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. 60760484SobrienThese correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, 60860484Sobrienand @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 60960484Sobrienonly supports this format via the @samp{fldt} (load 80-bit real to stack 61060484Sobrientop) and @samp{fstpt} (store 80-bit real and pop stack) instructions. 61133965Sjdp 61233965Sjdp@cindex @code{word} directive, i386 61333965Sjdp@cindex @code{long} directive, i386 61433965Sjdp@cindex @code{int} directive, i386 61533965Sjdp@cindex @code{quad} directive, i386 61677298Sobrien@cindex @code{word} directive, x86-64 61777298Sobrien@cindex @code{long} directive, x86-64 61877298Sobrien@cindex @code{int} directive, x86-64 61977298Sobrien@cindex @code{quad} directive, x86-64 62033965Sjdp@item 62133965SjdpInteger constructors are @samp{.word}, @samp{.long} or @samp{.int}, and 62260484Sobrien@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The 62360484Sobriencorresponding instruction mnemonic suffixes are @samp{s} (single), 62460484Sobrien@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, 62560484Sobrienthe 64-bit @samp{q} format is only present in the @samp{fildq} (load 62660484Sobrienquad integer to stack top) and @samp{fistpq} (store quad integer and pop 62760484Sobrienstack) instructions. 62833965Sjdp@end itemize 62933965Sjdp 63060484SobrienRegister to register operations should not use instruction mnemonic suffixes. 63160484Sobrien@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you 63260484Sobrienwrote @samp{fst %st, %st(1)}, since all register to register operations 63360484Sobrienuse 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, 63460484Sobrienwhich converts @samp{%st} from 80-bit to 64-bit floating point format, 63560484Sobrienthen stores the result in the 4 byte location @samp{mem}) 63633965Sjdp 63760484Sobrien@node i386-SIMD 63860484Sobrien@section Intel's MMX and AMD's 3DNow! SIMD Operations 63960484Sobrien 64060484Sobrien@cindex MMX, i386 64160484Sobrien@cindex 3DNow!, i386 64260484Sobrien@cindex SIMD, i386 64377298Sobrien@cindex MMX, x86-64 64477298Sobrien@cindex 3DNow!, x86-64 64577298Sobrien@cindex SIMD, x86-64 64660484Sobrien 64760484Sobrien@code{@value{AS}} supports Intel's MMX instruction set (SIMD 64860484Sobrieninstructions for integer data), available on Intel's Pentium MMX 64960484Sobrienprocessors and Pentium II processors, AMD's K6 and K6-2 processors, 650218822SdimCyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: 65160484Sobrieninstruction set (SIMD instructions for 32-bit floating point data) 65260484Sobrienavailable on AMD's K6-2 processor and possibly others in the future. 65360484Sobrien 65460484SobrienCurrently, @code{@value{AS}} does not support Intel's floating point 65560484SobrienSIMD, Katmai (KNI). 65660484Sobrien 65760484SobrienThe eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, 65860484Sobrien@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four 65960484Sobrien16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 66060484Sobrienfloating point values. The MMX registers cannot be used at the same time 66160484Sobrienas the floating point stack. 66260484Sobrien 66360484SobrienSee Intel and AMD documentation, keeping in mind that the operand order in 66460484Sobrieninstructions is reversed from the Intel syntax. 66560484Sobrien 66633965Sjdp@node i386-16bit 66733965Sjdp@section Writing 16-bit Code 66833965Sjdp 66933965Sjdp@cindex i386 16-bit code 67033965Sjdp@cindex 16-bit code, i386 67133965Sjdp@cindex real-mode code, i386 67260484Sobrien@cindex @code{code16gcc} directive, i386 67333965Sjdp@cindex @code{code16} directive, i386 67433965Sjdp@cindex @code{code32} directive, i386 67577298Sobrien@cindex @code{code64} directive, i386 67677298Sobrien@cindex @code{code64} directive, x86-64 67777298SobrienWhile @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code 67877298Sobrienor 64-bit x86-64 code depending on the default configuration, 67960484Sobrienit also supports writing code to run in real mode or in 16-bit protected 68060484Sobrienmode code segments. To do this, put a @samp{.code16} or 68160484Sobrien@samp{.code16gcc} directive before the assembly language instructions to 68260484Sobrienbe run in 16-bit mode. You can switch @code{@value{AS}} back to writing 68360484Sobriennormal 32-bit code with the @samp{.code32} directive. 68433965Sjdp 68560484Sobrien@samp{.code16gcc} provides experimental support for generating 16-bit 68660484Sobriencode from gcc, and differs from @samp{.code16} in that @samp{call}, 68760484Sobrien@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, 68860484Sobrien@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions 68960484Sobriendefault to 32-bit size. This is so that the stack pointer is 69060484Sobrienmanipulated in the same way over function calls, allowing access to 69160484Sobrienfunction parameters at the same stack offsets as in 32-bit mode. 69260484Sobrien@samp{.code16gcc} also automatically adds address size prefixes where 69360484Sobriennecessary to use the 32-bit addressing modes that gcc generates. 69433965Sjdp 69560484SobrienThe code which @code{@value{AS}} generates in 16-bit mode will not 69660484Sobriennecessarily run on a 16-bit pre-80386 processor. To write code that 69760484Sobrienruns on such a processor, you must refrain from using @emph{any} 32-bit 69860484Sobrienconstructs which require @code{@value{AS}} to output address or operand 69960484Sobriensize prefixes. 70033965Sjdp 70160484SobrienNote that writing 16-bit code instructions by explicitly specifying a 70260484Sobrienprefix or an instruction mnemonic suffix within a 32-bit code section 70360484Sobriengenerates different machine instructions than those generated for a 70460484Sobrien16-bit code segment. In a 32-bit code section, the following code 70560484Sobriengenerates the machine opcode bytes @samp{66 6a 04}, which pushes the 70660484Sobrienvalue @samp{4} onto the stack, decrementing @samp{%esp} by 2. 70733965Sjdp 70860484Sobrien@smallexample 70960484Sobrien pushw $4 71060484Sobrien@end smallexample 71160484Sobrien 71260484SobrienThe same code in a 16-bit code section would generate the machine 713218822Sdimopcode bytes @samp{6a 04} (i.e., without the operand size prefix), which 71460484Sobrienis correct since the processor default operand size is assumed to be 16 71560484Sobrienbits in a 16-bit code section. 71660484Sobrien 71760484Sobrien@node i386-Bugs 71860484Sobrien@section AT&T Syntax bugs 71960484Sobrien 72060484SobrienThe UnixWare assembler, and probably other AT&T derived ix86 Unix 72160484Sobrienassemblers, generate floating point instructions with reversed source 72260484Sobrienand destination registers in certain cases. Unfortunately, gcc and 72360484Sobrienpossibly many other programs use this reversed syntax, so we're stuck 72460484Sobrienwith it. 72560484Sobrien 72660484SobrienFor example 72760484Sobrien 72860484Sobrien@smallexample 72960484Sobrien fsub %st,%st(3) 73060484Sobrien@end smallexample 73160484Sobrien@noindent 73260484Sobrienresults in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather 73360484Sobrienthan the expected @samp{%st(3) - %st}. This happens with all the 73460484Sobriennon-commutative arithmetic floating point operations with two register 73560484Sobrienoperands where the source register is @samp{%st} and the destination 73660484Sobrienregister is @samp{%st(i)}. 73760484Sobrien 73877298Sobrien@node i386-Arch 73977298Sobrien@section Specifying CPU Architecture 74077298Sobrien 74177298Sobrien@cindex arch directive, i386 74277298Sobrien@cindex i386 arch directive 74377298Sobrien@cindex arch directive, x86-64 74477298Sobrien@cindex x86-64 arch directive 74577298Sobrien 74677298Sobrien@code{@value{AS}} may be told to assemble for a particular CPU 747218822Sdim(sub-)architecture with the @code{.arch @var{cpu_type}} directive. This 74877298Sobriendirective enables a warning when gas detects an instruction that is not 74977298Sobriensupported on the CPU specified. The choices for @var{cpu_type} are: 75077298Sobrien 75177298Sobrien@multitable @columnfractions .20 .20 .20 .20 75277298Sobrien@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} 75377298Sobrien@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} 754218822Sdim@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} 755218822Sdim@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} 756218822Sdim@item @samp{amdfam10} 757218822Sdim@item @samp{k6} @tab @samp{athlon} @tab @samp{sledgehammer} @tab @samp{k8} 758218822Sdim@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} 759218822Sdim@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} 760218822Sdim@item @samp{.sse4a} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.padlock} 761218822Sdim@item @samp{.pacifica} @tab @samp{.svme} @tab @samp{.abm} 76277298Sobrien@end multitable 76377298Sobrien 76478828SobrienApart from the warning, there are only two other effects on 76578828Sobrien@code{@value{AS}} operation; Firstly, if you specify a CPU other than 76677298Sobrien@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} 76777298Sobrienwill automatically use a two byte opcode sequence. The larger three 76877298Sobrienbyte opcode sequence is used on the 486 (and when no architecture is 76977298Sobrienspecified) because it executes faster on the 486. Note that you can 77077298Sobrienexplicitly request the two byte opcode by writing @samp{sarl %eax}. 77178828SobrienSecondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, 77278828Sobrien@emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset 77378828Sobrienconditional jumps will be promoted when necessary to a two instruction 77478828Sobriensequence consisting of a conditional jump of the opposite sense around 77578828Sobrienan unconditional jump to the target. 77677298Sobrien 777218822SdimFollowing the CPU architecture (but not a sub-architecture, which are those 778218822Sdimstarting with a dot), you may specify @samp{jumps} or @samp{nojumps} to 779218822Sdimcontrol automatic promotion of conditional jumps. @samp{jumps} is the 780218822Sdimdefault, and enables jump promotion; All external jumps will be of the long 781218822Sdimvariety, and file-local jumps will be promoted as necessary. 782218822Sdim(@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as 783218822Sdimbyte offset jumps, and warns about file-local conditional jumps that 784218822Sdim@code{@value{AS}} promotes. 78578828SobrienUnconditional jumps are treated as for @samp{jumps}. 78678828Sobrien 78778828SobrienFor example 78878828Sobrien 78978828Sobrien@smallexample 79078828Sobrien .arch i8086,nojumps 79178828Sobrien@end smallexample 79278828Sobrien 79333965Sjdp@node i386-Notes 79433965Sjdp@section Notes 79533965Sjdp 79633965Sjdp@cindex i386 @code{mul}, @code{imul} instructions 79733965Sjdp@cindex @code{mul} instruction, i386 79833965Sjdp@cindex @code{imul} instruction, i386 79977298Sobrien@cindex @code{mul} instruction, x86-64 80077298Sobrien@cindex @code{imul} instruction, x86-64 80133965SjdpThere is some trickery concerning the @samp{mul} and @samp{imul} 80277298Sobrieninstructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding 80333965Sjdpmultiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 80433965Sjdpfor @samp{imul}) can be output only in the one operand form. Thus, 80533965Sjdp@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; 80633965Sjdpthe expanding multiply would clobber the @samp{%edx} register, and this 80733965Sjdpwould confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the 80833965Sjdp64-bit product in @samp{%edx:%eax}. 80933965Sjdp 81033965SjdpWe have added a two operand form of @samp{imul} when the first operand 81133965Sjdpis an immediate mode expression and the second operand is a register. 81233965SjdpThis is just a shorthand, so that, multiplying @samp{%eax} by 69, for 81333965Sjdpexample, can be done with @samp{imul $69, %eax} rather than @samp{imul 81433965Sjdp$69, %eax, %eax}. 81533965Sjdp 816