1218822Sdim@c Copyright 2000, 2001, 2005 Free Software Foundation, Inc. 285815Sobrien@c This is part of the GAS manual. 385815Sobrien@c For copying conditions, see the file as.texinfo. 485815Sobrien 585815Sobrien@ifset GENERIC 685815Sobrien@page 785815Sobrien@node ARC-Dependent 885815Sobrien@chapter ARC Dependent Features 985815Sobrien@end ifset 1085815Sobrien 1185815Sobrien@ifclear GENERIC 1285815Sobrien@node Machine Dependencies 1385815Sobrien@chapter ARC Dependent Features 1485815Sobrien@end ifclear 1585815Sobrien 1685815Sobrien@set ARC_CORE_DEFAULT 6 1785815Sobrien 1885815Sobrien@cindex ARC support 1985815Sobrien@menu 2085815Sobrien* ARC Options:: Options 2185815Sobrien* ARC Syntax:: Syntax 2285815Sobrien* ARC Floating Point:: Floating Point 2385815Sobrien* ARC Directives:: ARC Machine Directives 2485815Sobrien* ARC Opcodes:: Opcodes 2585815Sobrien@end menu 2685815Sobrien 2785815Sobrien 2885815Sobrien@node ARC Options 2985815Sobrien@section Options 3085815Sobrien@cindex ARC options (none) 3185815Sobrien@cindex options for ARC (none) 3285815Sobrien 3385815Sobrien@table @code 3485815Sobrien 3585815Sobrien@cindex @code{-marc[5|6|7|8]} command line option, ARC 3685815Sobrien@item -marc[5|6|7|8] 37218822SdimThis option selects the core processor variant. Using 3885815Sobrien@code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which 3985815Sobrienis also the default. 4085815Sobrien 4185815Sobrien@table @code 4285815Sobrien 4385815Sobrien@cindex @code{arc5} arc5, ARC 4485815Sobrien@item arc5 4585815SobrienBase instruction set. 4685815Sobrien 4785815Sobrien@cindex @code{arc6} arc6, ARC 4885815Sobrien@item arc6 49218822SdimJump-and-link (jl) instruction. No requirement of an instruction between 50218822Sdimsetting flags and conditional jump. For example: 5185815Sobrien 5285815Sobrien@smallexample 5385815Sobrien mov.f r0,r1 5485815Sobrien beq foo 5585815Sobrien@end smallexample 5685815Sobrien 5785815Sobrien@cindex @code{arc7} arc7, ARC 5885815Sobrien@item arc7 5985815SobrienBreak (brk) and sleep (sleep) instructions. 6085815Sobrien 6185815Sobrien@cindex @code{arc8} arc8, ARC 6285815Sobrien@item arc8 6385815SobrienSoftware interrupt (swi) instruction. 6485815Sobrien 6585815Sobrien@end table 6685815Sobrien 6785815SobrienNote: the @code{.option} directive can to be used to select a core 6885815Sobrienvariant from within assembly code. 6985815Sobrien 7085815Sobrien@cindex @code{-EB} command line option, ARC 7185815Sobrien@item -EB 7285815SobrienThis option specifies that the output generated by the assembler should 7385815Sobrienbe marked as being encoded for a big-endian processor. 7485815Sobrien 7585815Sobrien@cindex @code{-EL} command line option, ARC 7685815Sobrien@item -EL 7785815SobrienThis option specifies that the output generated by the assembler should 7885815Sobrienbe marked as being encoded for a little-endian processor - this is the 7985815Sobriendefault. 8085815Sobrien 8185815Sobrien@end table 8285815Sobrien 8385815Sobrien 8485815Sobrien@node ARC Syntax 8585815Sobrien@section Syntax 8685815Sobrien@menu 8785815Sobrien* ARC-Chars:: Special Characters 8885815Sobrien* ARC-Regs:: Register Names 8985815Sobrien@end menu 9085815Sobrien 9185815Sobrien@node ARC-Chars 9285815Sobrien@subsection Special Characters 9385815Sobrien 9485815Sobrien@cindex ARC special characters 9585815Sobrien@cindex special characters, ARC 9685815Sobrien*TODO* 9785815Sobrien 9885815Sobrien@node ARC-Regs 9985815Sobrien@subsection Register Names 10085815Sobrien 10185815Sobrien@cindex ARC register names 10285815Sobrien@cindex register names, ARC 10385815Sobrien*TODO* 10485815Sobrien 10585815Sobrien 10685815Sobrien@node ARC Floating Point 10785815Sobrien@section Floating Point 10885815Sobrien 10985815Sobrien@cindex floating point, ARC (@sc{ieee}) 11085815Sobrien@cindex ARC floating point (@sc{ieee}) 11185815SobrienThe ARC core does not currently have hardware floating point 11285815Sobriensupport. Software floating point support is provided by @code{GCC} 11385815Sobrienand uses @sc{ieee} floating-point numbers. 11485815Sobrien 11585815Sobrien 11685815Sobrien@node ARC Directives 11785815Sobrien@section ARC Machine Directives 11885815Sobrien 11985815Sobrien@cindex machine directives, ARC 12085815Sobrien@cindex ARC machine directives 12185815SobrienThe ARC version of @code{@value{AS}} supports the following additional 12285815Sobrienmachine directives: 12385815Sobrien 12485815Sobrien@table @code 12585815Sobrien 12685815Sobrien@cindex @code{2byte} directive, ARC 12785815Sobrien@item .2byte @var{expressions} 12885815Sobrien*TODO* 12985815Sobrien 13085815Sobrien@cindex @code{3byte} directive, ARC 13185815Sobrien@item .3byte @var{expressions} 13285815Sobrien*TODO* 13385815Sobrien 13485815Sobrien@cindex @code{4byte} directive, ARC 13585815Sobrien@item .4byte @var{expressions} 13685815Sobrien*TODO* 13785815Sobrien 13885815Sobrien@cindex @code{extAuxRegister} directive, ARC 13985815Sobrien@item .extAuxRegister @var{name},@var{address},@var{mode} 140218822SdimThe ARCtangent A4 has extensible auxiliary register space. The 141218822Sdimauxiliary registers can be defined in the assembler source code by 142218822Sdimusing this directive. The first parameter is the @var{name} of the 143218822Sdimnew auxiallry register. The second parameter is the @var{address} of 144218822Sdimthe register in the auxiliary register memory map for the variant of 145218822Sdimthe ARC. The third parameter specifies the @var{mode} in which the 146218822Sdimregister can be operated is and it can be one of: 14785815Sobrien 148218822Sdim@table @code 149218822Sdim@item r (readonly) 150218822Sdim@item w (write only) 151218822Sdim@item r|w (read or write) 152218822Sdim@end table 153218822Sdim 154218822SdimFor example: 155218822Sdim 15685815Sobrien@smallexample 15785815Sobrien .extAuxRegister mulhi,0x12,w 15885815Sobrien@end smallexample 15985815Sobrien 160218822SdimThis specifies an extension auxiliary register called @emph{mulhi} 161218822Sdimwhich is at address 0x12 in the memory space and which is only 162218822Sdimwritable. 163218822Sdim 16485815Sobrien@cindex @code{extCondCode} directive, ARC 16585815Sobrien@item .extCondCode @var{suffix},@var{value} 166218822SdimThe condition codes on the ARCtangent A4 are extensible and can be 167218822Sdimspecified by means of this assembler directive. They are specified 168218822Sdimby the suffix and the value for the condition code. They can be used to 169218822Sdimspecify extra condition codes with any values. For example: 17085815Sobrien 17185815Sobrien@smallexample 17285815Sobrien .extCondCode is_busy,0x14 173218822Sdim 174218822Sdim add.is_busy r1,r2,r3 175218822Sdim bis_busy _main 17685815Sobrien@end smallexample 17785815Sobrien 17885815Sobrien@cindex @code{extCoreRegister} directive, ARC 17985815Sobrien@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut} 180218822SdimSpecifies an extension core register @var{name} for the application. 181218822SdimThis allows a register @var{name} with a valid @var{regnum} between 0 182218822Sdimand 60, with the following as valid values for @var{mode} 18385815Sobrien 184218822Sdim@table @samp 185218822Sdim@item @emph{r} (readonly) 186218822Sdim@item @emph{w} (write only) 187218822Sdim@item @emph{r|w} (read or write) 188218822Sdim@end table 189218822Sdim 190218822Sdim 191218822SdimThe other parameter gives a description of the register having a 192218822Sdim@var{shortcut} in the pipeline. The valid values are: 193218822Sdim 194218822Sdim@table @code 195218822Sdim@item can_shortcut 196218822Sdim@item cannot_shortcut 197218822Sdim@end table 198218822Sdim 199218822SdimFor example: 200218822Sdim 20185815Sobrien@smallexample 20285815Sobrien .extCoreRegister mlo,57,r,can_shortcut 20385815Sobrien@end smallexample 20485815Sobrien 205218822SdimThis defines an extension core register mlo with the value 57 which 206218822Sdimcan shortcut the pipeline. 207218822Sdim 20885815Sobrien@cindex @code{extInstruction} directive, ARC 20985815Sobrien@item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass} 210218822SdimThe ARCtangent A4 allows the user to specify extension instructions. 211218822SdimThe extension instructions are not macros. The assembler creates 212218822Sdimencodings for use of these instructions according to the specification 213218822Sdimby the user. The parameters are: 21485815Sobrien 215218822Sdim@table @bullet 216218822Sdim@item @var{name} 217218822SdimName of the extension instruction 218218822Sdim 219218822Sdim@item @var{opcode} 220218822SdimOpcode to be used. (Bits 27:31 in the encoding). Valid values 221218822Sdim0x10-0x1f or 0x03 222218822Sdim 223218822Sdim@item @var{subopcode} 224218822SdimSubopcode to be used. Valid values are from 0x09-0x3f. However the 225218822Sdimcorrect value also depends on @var{syntaxclass} 226218822Sdim 227218822Sdim@item @var{suffixclass} 228218822SdimDetermines the kinds of suffixes to be allowed. Valid values are 229218822Sdim@code{SUFFIX_NONE}, @code{SUFFIX_COND}, 230218822Sdim@code{SUFFIX_FLAG} which indicates the absence or presence of 231218822Sdimconditional suffixes and flag setting by the extension instruction. 232218822SdimIt is also possible to specify that an instruction sets the flags and 233218822Sdimis condtional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}. 234218822Sdim 235218822Sdim@item @var{syntaxclass} 236218822SdimDetermines the syntax class for the instruction. It can have the 237218822Sdimfollowing values: 238218822Sdim 239218822Sdim@table @code 240218822Sdim@item @code{SYNTAX_2OP}: 241218822Sdim2 Operand Instruction 242218822Sdim@item @code{SYNTAX_3OP}: 243218822Sdim3 Operand Instruction 244218822Sdim@end table 245218822Sdim 246218822SdimIn addition there could be modifiers for the syntax class as described 247218822Sdimbelow: 248218822Sdim 249218822Sdim@itemize @minus 250218822SdimSyntax Class Modifiers are: 251218822Sdim 252218822Sdim@item @code{OP1_MUST_BE_IMM}: 253218822SdimModifies syntax class SYNTAX_3OP, specifying that the first operand 254218822Sdimof a three-operand instruction must be an immediate (i.e., the result 255218822Sdimis discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with 256218822SdimSYNTAX_3OP as given in the example below. This could usually be used 257218822Sdimto set the flags using specific instructions and not retain results. 258218822Sdim 259218822Sdim@item @code{OP1_IMM_IMPLIED}: 260218822SdimModifies syntax class SYNTAX_20P, it specifies that there is an 261218822Sdimimplied immediate destination operand which does not appear in the 262218822Sdimsyntax. For example, if the source code contains an instruction like: 263218822Sdim 26485815Sobrien@smallexample 265218822Sdiminst r1,r2 26685815Sobrien@end smallexample 26785815Sobrien 268218822Sdimit really means that the first argument is an implied immediate (that 269218822Sdimis, the result is discarded). This is the same as though the source 270218822Sdimcode were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it 271218822Sdimwith SYNTAX_20P. 272218822Sdim 273218822Sdim@end itemize 274218822Sdim@end table 275218822Sdim 276218822SdimFor example, defining 64-bit multiplier with immediate operands: 277218822Sdim 278218822Sdim@smallexample 279218822Sdim.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , 280218822Sdim SYNTAX_3OP|OP1_MUST_BE_IMM 281218822Sdim@end smallexample 282218822Sdim 283218822SdimThe above specifies an extension instruction called mp64 which has 3 operands, 284218822Sdimsets the flags, can be used with a condition code, for which the 285218822Sdimfirst operand is an immediate. (Equivalent to discarding the result 286218822Sdimof the operation). 287218822Sdim 288218822Sdim@smallexample 289218822Sdim .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED 290218822Sdim@end smallexample 291218822Sdim 292218822SdimThis describes a 2 operand instruction with an implicit first 293218822Sdimimmediate operand. The result of this operation would be discarded. 294218822Sdim 29585815Sobrien@cindex @code{half} directive, ARC 29685815Sobrien@item .half @var{expressions} 29785815Sobrien*TODO* 29885815Sobrien 29985815Sobrien@cindex @code{long} directive, ARC 30085815Sobrien@item .long @var{expressions} 30185815Sobrien*TODO* 30285815Sobrien 30385815Sobrien@cindex @code{option} directive, ARC 30485815Sobrien@item .option @var{arc|arc5|arc6|arc7|arc8} 30585815SobrienThe @code{.option} directive must be followed by the desired core 30685815Sobrienversion. Again @code{arc} is an alias for 30785815Sobrien@code{arc@value{ARC_CORE_DEFAULT}}. 30885815Sobrien 30985815SobrienNote: the @code{.option} directive overrides the command line option 31085815Sobrien@code{-marc}; a warning is emitted when the version is not consistent 31185815Sobrienbetween the two - even for the implicit default core version 31285815Sobrien(arc@value{ARC_CORE_DEFAULT}). 31385815Sobrien 31485815Sobrien@cindex @code{short} directive, ARC 31585815Sobrien@item .short @var{expressions} 31685815Sobrien*TODO* 31785815Sobrien 31885815Sobrien@cindex @code{word} directive, ARC 31985815Sobrien@item .word @var{expressions} 32085815Sobrien*TODO* 32185815Sobrien 32285815Sobrien@end table 32385815Sobrien 32485815Sobrien 32585815Sobrien@node ARC Opcodes 32685815Sobrien@section Opcodes 32785815Sobrien 32885815Sobrien@cindex ARC opcodes 32985815Sobrien@cindex opcodes for ARC 33085815Sobrien 33185815SobrienFor information on the ARC instruction set, see @cite{ARC Programmers 332218822SdimReference Manual}, ARC International (www.arc.com) 333218822Sdim 334