pci_lpc.c revision 268972 
1/*-
2 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
3 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_lpc.c 268972 2014-07-22 03:14:37Z jhb $
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/pci_lpc.c 268972 2014-07-22 03:14:37Z jhb $");
32
33#include <sys/types.h>
34#include <machine/vmm.h>
35#include <machine/vmm_dev.h>
36
37#include <stdio.h>
38#include <stdlib.h>
39#include <string.h>
40
41#include <vmmapi.h>
42
43#include "acpi.h"
44#include "inout.h"
45#include "pci_emul.h"
46#include "pci_irq.h"
47#include "pci_lpc.h"
48#include "uart_emul.h"
49
50#define	IO_ICU1		0x20
51#define	IO_ICU2		0xA0
52
53SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
54SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
55
56#define	ELCR_PORT	0x4d0
57SYSRES_IO(ELCR_PORT, 2);
58
59#define	IO_TIMER1_PORT	0x40
60
61#define	NMISC_PORT	0x61
62SYSRES_IO(NMISC_PORT, 1);
63
64static struct pci_devinst *lpc_bridge;
65
66#define	LPC_UART_NUM	2
67static struct lpc_uart_softc {
68	struct uart_softc *uart_softc;
69	const char *opts;
70	int	iobase;
71	int	irq;
72	int	enabled;
73} lpc_uart_softc[LPC_UART_NUM];
74
75static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" };
76
77/*
78 * LPC device configuration is in the following form:
79 * <lpc_device_name>[,<options>]
80 * For e.g. "com1,stdio"
81 */
82int
83lpc_device_parse(const char *opts)
84{
85	int unit, error;
86	char *str, *cpy, *lpcdev;
87
88	error = -1;
89	str = cpy = strdup(opts);
90	lpcdev = strsep(&str, ",");
91	if (lpcdev != NULL) {
92		for (unit = 0; unit < LPC_UART_NUM; unit++) {
93			if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
94				lpc_uart_softc[unit].opts = str;
95				error = 0;
96				goto done;
97			}
98		}
99	}
100
101done:
102	if (error)
103		free(cpy);
104
105	return (error);
106}
107
108static void
109lpc_uart_intr_assert(void *arg)
110{
111	struct lpc_uart_softc *sc = arg;
112
113	assert(sc->irq >= 0);
114
115	vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq);
116}
117
118static void
119lpc_uart_intr_deassert(void *arg)
120{
121	/*
122	 * The COM devices on the LPC bus generate edge triggered interrupts,
123	 * so nothing more to do here.
124	 */
125}
126
127static int
128lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
129		    uint32_t *eax, void *arg)
130{
131	int offset;
132	struct lpc_uart_softc *sc = arg;
133
134	offset = port - sc->iobase;
135
136	switch (bytes) {
137	case 1:
138		if (in)
139			*eax = uart_read(sc->uart_softc, offset);
140		else
141			uart_write(sc->uart_softc, offset, *eax);
142		break;
143	case 2:
144		if (in) {
145			*eax = uart_read(sc->uart_softc, offset);
146			*eax |= uart_read(sc->uart_softc, offset + 1) << 8;
147		} else {
148			uart_write(sc->uart_softc, offset, *eax);
149			uart_write(sc->uart_softc, offset + 1, *eax >> 8);
150		}
151		break;
152	default:
153		return (-1);
154	}
155
156	return (0);
157}
158
159static int
160lpc_init(void)
161{
162	struct lpc_uart_softc *sc;
163	struct inout_port iop;
164	const char *name;
165	int unit, error;
166
167	/* COM1 and COM2 */
168	for (unit = 0; unit < LPC_UART_NUM; unit++) {
169		sc = &lpc_uart_softc[unit];
170		name = lpc_uart_names[unit];
171
172		if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
173			fprintf(stderr, "Unable to allocate resources for "
174			    "LPC device %s\n", name);
175			return (-1);
176		}
177		pci_irq_reserve(sc->irq);
178
179		sc->uart_softc = uart_init(lpc_uart_intr_assert,
180				    lpc_uart_intr_deassert, sc);
181
182		if (uart_set_backend(sc->uart_softc, sc->opts) != 0) {
183			fprintf(stderr, "Unable to initialize backend '%s' "
184			    "for LPC device %s\n", sc->opts, name);
185			return (-1);
186		}
187
188		bzero(&iop, sizeof(struct inout_port));
189		iop.name = name;
190		iop.port = sc->iobase;
191		iop.size = UART_IO_BAR_SIZE;
192		iop.flags = IOPORT_F_INOUT;
193		iop.handler = lpc_uart_io_handler;
194		iop.arg = sc;
195
196		error = register_inout(&iop);
197		assert(error == 0);
198		sc->enabled = 1;
199	}
200
201	return (0);
202}
203
204static void
205pci_lpc_write_dsdt(struct pci_devinst *pi)
206{
207	struct lpc_dsdt **ldpp, *ldp;
208
209	dsdt_line("");
210	dsdt_line("Device (ISA)");
211	dsdt_line("{");
212	dsdt_line("  Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
213	dsdt_line("  OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");
214	dsdt_line("  Field (LPCR, AnyAcc, NoLock, Preserve)");
215	dsdt_line("  {");
216	dsdt_line("    Offset (0x60),");
217	dsdt_line("    PIRA,   8,");
218	dsdt_line("    PIRB,   8,");
219	dsdt_line("    PIRC,   8,");
220	dsdt_line("    PIRD,   8,");
221	dsdt_line("    Offset (0x68),");
222	dsdt_line("    PIRE,   8,");
223	dsdt_line("    PIRF,   8,");
224	dsdt_line("    PIRG,   8,");
225	dsdt_line("    PIRH,   8");
226	dsdt_line("  }");
227	dsdt_line("");
228
229	dsdt_indent(1);
230	SET_FOREACH(ldpp, lpc_dsdt_set) {
231		ldp = *ldpp;
232		ldp->handler();
233	}
234
235	dsdt_line("");
236	dsdt_line("Device (PIC)");
237	dsdt_line("{");
238	dsdt_line("  Name (_HID, EisaId (\"PNP0000\"))");
239	dsdt_line("  Name (_CRS, ResourceTemplate ()");
240	dsdt_line("  {");
241	dsdt_indent(2);
242	dsdt_fixed_ioport(IO_ICU1, 2);
243	dsdt_fixed_ioport(IO_ICU2, 2);
244	dsdt_fixed_irq(2);
245	dsdt_unindent(2);
246	dsdt_line("  })");
247	dsdt_line("}");
248
249	dsdt_line("");
250	dsdt_line("Device (TIMR)");
251	dsdt_line("{");
252	dsdt_line("  Name (_HID, EisaId (\"PNP0100\"))");
253	dsdt_line("  Name (_CRS, ResourceTemplate ()");
254	dsdt_line("  {");
255	dsdt_indent(2);
256	dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
257	dsdt_fixed_irq(0);
258	dsdt_unindent(2);
259	dsdt_line("  })");
260	dsdt_line("}");
261	dsdt_unindent(1);
262
263	dsdt_line("}");
264}
265
266static void
267pci_lpc_sysres_dsdt(void)
268{
269	struct lpc_sysres **lspp, *lsp;
270
271	dsdt_line("");
272	dsdt_line("Device (SIO)");
273	dsdt_line("{");
274	dsdt_line("  Name (_HID, EisaId (\"PNP0C02\"))");
275	dsdt_line("  Name (_CRS, ResourceTemplate ()");
276	dsdt_line("  {");
277
278	dsdt_indent(2);
279	SET_FOREACH(lspp, lpc_sysres_set) {
280		lsp = *lspp;
281		switch (lsp->type) {
282		case LPC_SYSRES_IO:
283			dsdt_fixed_ioport(lsp->base, lsp->length);
284			break;
285		case LPC_SYSRES_MEM:
286			dsdt_fixed_mem32(lsp->base, lsp->length);
287			break;
288		}
289	}
290	dsdt_unindent(2);
291
292	dsdt_line("  })");
293	dsdt_line("}");
294}
295LPC_DSDT(pci_lpc_sysres_dsdt);
296
297static void
298pci_lpc_uart_dsdt(void)
299{
300	struct lpc_uart_softc *sc;
301	int unit;
302
303	for (unit = 0; unit < LPC_UART_NUM; unit++) {
304		sc = &lpc_uart_softc[unit];
305		if (!sc->enabled)
306			continue;
307		dsdt_line("");
308		dsdt_line("Device (%s)", lpc_uart_names[unit]);
309		dsdt_line("{");
310		dsdt_line("  Name (_HID, EisaId (\"PNP0501\"))");
311		dsdt_line("  Name (_UID, %d)", unit + 1);
312		dsdt_line("  Name (_CRS, ResourceTemplate ()");
313		dsdt_line("  {");
314		dsdt_indent(2);
315		dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE);
316		dsdt_fixed_irq(sc->irq);
317		dsdt_unindent(2);
318		dsdt_line("  })");
319		dsdt_line("}");
320	}
321}
322LPC_DSDT(pci_lpc_uart_dsdt);
323
324static int
325pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
326		  int coff, int bytes, uint32_t val)
327{
328	int pirq_pin;
329
330	if (bytes == 1) {
331		pirq_pin = 0;
332		if (coff >= 0x60 && coff <= 0x63)
333			pirq_pin = coff - 0x60 + 1;
334		if (coff >= 0x68 && coff <= 0x6b)
335			pirq_pin = coff - 0x68 + 5;
336		if (pirq_pin != 0) {
337			pirq_write(ctx, pirq_pin, val);
338			pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
339			return (0);
340		}
341	}
342	return (-1);
343}
344
345static void
346pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
347	       int baridx, uint64_t offset, int size, uint64_t value)
348{
349}
350
351static uint64_t
352pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
353	      int baridx, uint64_t offset, int size)
354{
355	return (0);
356}
357
358#define	LPC_DEV		0x7000
359#define	LPC_VENDOR	0x8086
360
361static int
362pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
363{
364
365	/*
366	 * Do not allow more than one LPC bridge to be configured.
367	 */
368	if (lpc_bridge != NULL) {
369		fprintf(stderr, "Only one LPC bridge is allowed.\n");
370		return (-1);
371	}
372
373	/*
374	 * Enforce that the LPC can only be configured on bus 0. This
375	 * simplifies the ACPI DSDT because it can provide a decode for
376	 * all legacy i/o ports behind bus 0.
377	 */
378	if (pi->pi_bus != 0) {
379		fprintf(stderr, "LPC bridge can be present only on bus 0.\n");
380		return (-1);
381	}
382
383	if (lpc_init() != 0)
384		return (-1);
385
386	/* initialize config space */
387	pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
388	pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
389	pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
390	pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
391
392	lpc_bridge = pi;
393
394	return (0);
395}
396
397char *
398lpc_pirq_name(int pin)
399{
400	char *name;
401
402	if (lpc_bridge == NULL)
403		return (NULL);
404	asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1);
405	return (name);
406}
407
408void
409lpc_pirq_routed(void)
410{
411	int pin;
412
413	if (lpc_bridge == NULL)
414		return;
415
416 	for (pin = 0; pin < 4; pin++)
417		pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));
418	for (pin = 0; pin < 4; pin++)
419		pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));
420}
421
422struct pci_devemu pci_de_lpc = {
423	.pe_emu =	"lpc",
424	.pe_init =	pci_lpc_init,
425	.pe_write_dsdt = pci_lpc_write_dsdt,
426	.pe_cfgwrite =	pci_lpc_cfgwrite,
427	.pe_barwrite =	pci_lpc_write,
428	.pe_barread =	pci_lpc_read
429};
430PCI_EMUL_SET(pci_de_lpc);
431