pci_emul.h revision 267393
1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.h 267393 2014-06-12 13:13:15Z jhb $ 27 */ 28 29#ifndef _PCI_EMUL_H_ 30#define _PCI_EMUL_H_ 31 32#include <sys/types.h> 33#include <sys/queue.h> 34#include <sys/kernel.h> 35#include <sys/_pthreadtypes.h> 36 37#include <dev/pci/pcireg.h> 38 39#include <assert.h> 40 41#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 42#define PCIY_RESERVED 0x00 43 44struct vmctx; 45struct pci_devinst; 46struct memory_region; 47 48struct pci_devemu { 49 char *pe_emu; /* Name of device emulation */ 50 51 /* instance creation */ 52 int (*pe_init)(struct vmctx *, struct pci_devinst *, 53 char *opts); 54 55 /* ACPI DSDT enumeration */ 56 void (*pe_write_dsdt)(struct pci_devinst *); 57 58 /* config space read/write callbacks */ 59 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu, 60 struct pci_devinst *pi, int offset, 61 int bytes, uint32_t val); 62 int (*pe_cfgread)(struct vmctx *ctx, int vcpu, 63 struct pci_devinst *pi, int offset, 64 int bytes, uint32_t *retval); 65 66 /* BAR read/write callbacks */ 67 void (*pe_barwrite)(struct vmctx *ctx, int vcpu, 68 struct pci_devinst *pi, int baridx, 69 uint64_t offset, int size, uint64_t value); 70 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, 71 struct pci_devinst *pi, int baridx, 72 uint64_t offset, int size); 73}; 74#define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 75 76enum pcibar_type { 77 PCIBAR_NONE, 78 PCIBAR_IO, 79 PCIBAR_MEM32, 80 PCIBAR_MEM64, 81 PCIBAR_MEMHI64 82}; 83 84struct pcibar { 85 enum pcibar_type type; /* io or memory */ 86 uint64_t size; 87 uint64_t addr; 88}; 89 90#define PI_NAMESZ 40 91 92struct msix_table_entry { 93 uint64_t addr; 94 uint32_t msg_data; 95 uint32_t vector_control; 96} __packed; 97 98/* 99 * In case the structure is modified to hold extra information, use a define 100 * for the size that should be emulated. 101 */ 102#define MSIX_TABLE_ENTRY_SIZE 16 103#define MAX_MSIX_TABLE_ENTRIES 2048 104#define PBA_TABLE_ENTRY_SIZE 8 105 106enum lintr_stat { 107 IDLE, 108 ASSERTED, 109 PENDING 110}; 111 112struct pci_devinst { 113 struct pci_devemu *pi_d; 114 struct vmctx *pi_vmctx; 115 uint8_t pi_bus, pi_slot, pi_func; 116 char pi_name[PI_NAMESZ]; 117 int pi_bar_getsize; 118 119 struct { 120 int8_t pin; 121 enum lintr_stat state; 122 int ioapic_irq; 123 pthread_mutex_t lock; 124 } pi_lintr; 125 126 struct { 127 int enabled; 128 uint64_t addr; 129 uint64_t msg_data; 130 int maxmsgnum; 131 } pi_msi; 132 133 struct { 134 int enabled; 135 int table_bar; 136 int pba_bar; 137 size_t table_offset; 138 int table_count; 139 size_t pba_offset; 140 size_t pba_size; 141 int function_mask; 142 struct msix_table_entry *table; /* allocated at runtime */ 143 } pi_msix; 144 145 void *pi_arg; /* devemu-private data */ 146 147 u_char pi_cfgdata[PCI_REGMAX + 1]; 148 struct pcibar pi_bar[PCI_BARMAX + 1]; 149}; 150 151struct msicap { 152 uint8_t capid; 153 uint8_t nextptr; 154 uint16_t msgctrl; 155 uint32_t addrlo; 156 uint32_t addrhi; 157 uint16_t msgdata; 158} __packed; 159 160struct msixcap { 161 uint8_t capid; 162 uint8_t nextptr; 163 uint16_t msgctrl; 164 uint32_t table_info; /* bar index and offset within it */ 165 uint32_t pba_info; /* bar index and offset within it */ 166} __packed; 167 168struct pciecap { 169 uint8_t capid; 170 uint8_t nextptr; 171 uint16_t pcie_capabilities; 172 173 uint32_t dev_capabilities; /* all devices */ 174 uint16_t dev_control; 175 uint16_t dev_status; 176 177 uint32_t link_capabilities; /* devices with links */ 178 uint16_t link_control; 179 uint16_t link_status; 180 181 uint32_t slot_capabilities; /* ports with slots */ 182 uint16_t slot_control; 183 uint16_t slot_status; 184 185 uint16_t root_control; /* root ports */ 186 uint16_t root_capabilities; 187 uint32_t root_status; 188 189 uint32_t dev_capabilities2; /* all devices */ 190 uint16_t dev_control2; 191 uint16_t dev_status2; 192 193 uint32_t link_capabilities2; /* devices with links */ 194 uint16_t link_control2; 195 uint16_t link_status2; 196 197 uint32_t slot_capabilities2; /* ports with slots */ 198 uint16_t slot_control2; 199 uint16_t slot_status2; 200} __packed; 201 202typedef void (*pci_lintr_cb)(int slot, int pin, int ioapic_irq, void *arg); 203 204int init_pci(struct vmctx *ctx); 205void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 206 int bytes, uint32_t val); 207void msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 208 int bytes, uint32_t val); 209void pci_callback(void); 210int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 211 enum pcibar_type type, uint64_t size); 212int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, 213 uint64_t hostbase, enum pcibar_type type, uint64_t size); 214int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 215int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 216void pci_generate_msi(struct pci_devinst *pi, int msgnum); 217void pci_generate_msix(struct pci_devinst *pi, int msgnum); 218void pci_lintr_assert(struct pci_devinst *pi); 219void pci_lintr_deassert(struct pci_devinst *pi); 220int pci_lintr_request(struct pci_devinst *pi); 221int pci_msi_enabled(struct pci_devinst *pi); 222int pci_msix_enabled(struct pci_devinst *pi); 223int pci_msix_table_bar(struct pci_devinst *pi); 224int pci_msix_pba_bar(struct pci_devinst *pi); 225int pci_msi_msgnum(struct pci_devinst *pi); 226int pci_parse_slot(char *opt); 227void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 228int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 229int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 230 uint64_t value); 231uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 232int pci_count_lintr(void); 233void pci_walk_lintr(pci_lintr_cb cb, void *arg); 234void pci_write_dsdt(void); 235 236static __inline void 237pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 238{ 239 assert(offset <= PCI_REGMAX); 240 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 241} 242 243static __inline void 244pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 245{ 246 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 247 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 248} 249 250static __inline void 251pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 252{ 253 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 254 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 255} 256 257static __inline uint8_t 258pci_get_cfgdata8(struct pci_devinst *pi, int offset) 259{ 260 assert(offset <= PCI_REGMAX); 261 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 262} 263 264static __inline uint16_t 265pci_get_cfgdata16(struct pci_devinst *pi, int offset) 266{ 267 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 268 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 269} 270 271static __inline uint32_t 272pci_get_cfgdata32(struct pci_devinst *pi, int offset) 273{ 274 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 275 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 276} 277 278#endif /* _PCI_EMUL_H_ */ 279