pci_emul.c revision 262350
1/*- 2 * Copyright (c) 2011 NetApp, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.c 262350 2014-02-23 00:46:05Z jhb $ 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/pci_emul.c 262350 2014-02-23 00:46:05Z jhb $"); 31 32#include <sys/param.h> 33#include <sys/linker_set.h> 34#include <sys/errno.h> 35 36#include <ctype.h> 37#include <stdio.h> 38#include <stdlib.h> 39#include <string.h> 40#include <strings.h> 41#include <assert.h> 42#include <stdbool.h> 43 44#include <machine/vmm.h> 45#include <vmmapi.h> 46 47#include "acpi.h" 48#include "bhyverun.h" 49#include "inout.h" 50#include "legacy_irq.h" 51#include "mem.h" 52#include "pci_emul.h" 53#include "pci_lpc.h" 54 55#define CONF1_ADDR_PORT 0x0cf8 56#define CONF1_DATA_PORT 0x0cfc 57 58#define CONF1_ENABLE 0x80000000ul 59 60#define CFGWRITE(pi,off,val,b) \ 61do { \ 62 if ((b) == 1) { \ 63 pci_set_cfgdata8((pi),(off),(val)); \ 64 } else if ((b) == 2) { \ 65 pci_set_cfgdata16((pi),(off),(val)); \ 66 } else { \ 67 pci_set_cfgdata32((pi),(off),(val)); \ 68 } \ 69} while (0) 70 71#define MAXSLOTS (PCI_SLOTMAX + 1) 72#define MAXFUNCS (PCI_FUNCMAX + 1) 73 74static struct slotinfo { 75 char *si_name; 76 char *si_param; 77 struct pci_devinst *si_devi; 78 int si_legacy; 79} pci_slotinfo[MAXSLOTS][MAXFUNCS]; 80 81SET_DECLARE(pci_devemu_set, struct pci_devemu); 82 83static uint64_t pci_emul_iobase; 84static uint64_t pci_emul_membase32; 85static uint64_t pci_emul_membase64; 86 87#define PCI_EMUL_IOBASE 0x2000 88#define PCI_EMUL_IOLIMIT 0x10000 89 90#define PCI_EMUL_MEMLIMIT32 0xE0000000 /* 3.5GB */ 91 92#define PCI_EMUL_MEMBASE64 0xD000000000UL 93#define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 94 95static struct pci_devemu *pci_emul_finddev(char *name); 96 97static int pci_emul_devices; 98static struct mem_range pci_mem_hole; 99 100/* 101 * I/O access 102 */ 103 104/* 105 * Slot options are in the form: 106 * 107 * <slot>[:<func>],<emul>[,<config>] 108 * 109 * slot is 0..31 110 * func is 0..7 111 * emul is a string describing the type of PCI device e.g. virtio-net 112 * config is an optional string, depending on the device, that can be 113 * used for configuration. 114 * Examples are: 115 * 1,virtio-net,tap0 116 * 3:0,dummy 117 */ 118static void 119pci_parse_slot_usage(char *aopt) 120{ 121 122 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 123} 124 125int 126pci_parse_slot(char *opt, int legacy) 127{ 128 char *slot, *func, *emul, *config; 129 char *str, *cpy; 130 int error, snum, fnum; 131 132 error = -1; 133 str = cpy = strdup(opt); 134 135 slot = strsep(&str, ","); 136 func = NULL; 137 if (strchr(slot, ':') != NULL) { 138 func = cpy; 139 (void) strsep(&func, ":"); 140 } 141 142 emul = strsep(&str, ","); 143 config = str; 144 145 if (emul == NULL) { 146 pci_parse_slot_usage(opt); 147 goto done; 148 } 149 150 snum = atoi(slot); 151 fnum = func ? atoi(func) : 0; 152 153 if (snum < 0 || snum >= MAXSLOTS || fnum < 0 || fnum >= MAXFUNCS) { 154 pci_parse_slot_usage(opt); 155 goto done; 156 } 157 158 if (pci_slotinfo[snum][fnum].si_name != NULL) { 159 fprintf(stderr, "pci slot %d:%d already occupied!\n", 160 snum, fnum); 161 goto done; 162 } 163 164 if (pci_emul_finddev(emul) == NULL) { 165 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 166 snum, fnum, emul); 167 goto done; 168 } 169 170 error = 0; 171 pci_slotinfo[snum][fnum].si_name = emul; 172 pci_slotinfo[snum][fnum].si_param = config; 173 pci_slotinfo[snum][fnum].si_legacy = legacy; 174 175done: 176 if (error) 177 free(cpy); 178 179 return (error); 180} 181 182static int 183pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 184{ 185 186 if (offset < pi->pi_msix.pba_offset) 187 return (0); 188 189 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 190 return (0); 191 } 192 193 return (1); 194} 195 196int 197pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 198 uint64_t value) 199{ 200 int msix_entry_offset; 201 int tab_index; 202 char *dest; 203 204 /* support only 4 or 8 byte writes */ 205 if (size != 4 && size != 8) 206 return (-1); 207 208 /* 209 * Return if table index is beyond what device supports 210 */ 211 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 212 if (tab_index >= pi->pi_msix.table_count) 213 return (-1); 214 215 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 216 217 /* support only aligned writes */ 218 if ((msix_entry_offset % size) != 0) 219 return (-1); 220 221 dest = (char *)(pi->pi_msix.table + tab_index); 222 dest += msix_entry_offset; 223 224 if (size == 4) 225 *((uint32_t *)dest) = value; 226 else 227 *((uint64_t *)dest) = value; 228 229 return (0); 230} 231 232uint64_t 233pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 234{ 235 char *dest; 236 int msix_entry_offset; 237 int tab_index; 238 uint64_t retval = ~0; 239 240 /* 241 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 242 * table but we also allow 1 byte access to accomodate reads from 243 * ddb. 244 */ 245 if (size != 1 && size != 4 && size != 8) 246 return (retval); 247 248 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 249 250 /* support only aligned reads */ 251 if ((msix_entry_offset % size) != 0) { 252 return (retval); 253 } 254 255 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 256 257 if (tab_index < pi->pi_msix.table_count) { 258 /* valid MSI-X Table access */ 259 dest = (char *)(pi->pi_msix.table + tab_index); 260 dest += msix_entry_offset; 261 262 if (size == 1) 263 retval = *((uint8_t *)dest); 264 else if (size == 4) 265 retval = *((uint32_t *)dest); 266 else 267 retval = *((uint64_t *)dest); 268 } else if (pci_valid_pba_offset(pi, offset)) { 269 /* return 0 for PBA access */ 270 retval = 0; 271 } 272 273 return (retval); 274} 275 276int 277pci_msix_table_bar(struct pci_devinst *pi) 278{ 279 280 if (pi->pi_msix.table != NULL) 281 return (pi->pi_msix.table_bar); 282 else 283 return (-1); 284} 285 286int 287pci_msix_pba_bar(struct pci_devinst *pi) 288{ 289 290 if (pi->pi_msix.table != NULL) 291 return (pi->pi_msix.pba_bar); 292 else 293 return (-1); 294} 295 296static int 297pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 298 uint32_t *eax, void *arg) 299{ 300 struct pci_devinst *pdi = arg; 301 struct pci_devemu *pe = pdi->pi_d; 302 uint64_t offset; 303 int i; 304 305 for (i = 0; i <= PCI_BARMAX; i++) { 306 if (pdi->pi_bar[i].type == PCIBAR_IO && 307 port >= pdi->pi_bar[i].addr && 308 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 309 offset = port - pdi->pi_bar[i].addr; 310 if (in) 311 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 312 offset, bytes); 313 else 314 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 315 bytes, *eax); 316 return (0); 317 } 318 } 319 return (-1); 320} 321 322static int 323pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 324 int size, uint64_t *val, void *arg1, long arg2) 325{ 326 struct pci_devinst *pdi = arg1; 327 struct pci_devemu *pe = pdi->pi_d; 328 uint64_t offset; 329 int bidx = (int) arg2; 330 331 assert(bidx <= PCI_BARMAX); 332 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 333 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 334 assert(addr >= pdi->pi_bar[bidx].addr && 335 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 336 337 offset = addr - pdi->pi_bar[bidx].addr; 338 339 if (dir == MEM_F_WRITE) 340 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, size, *val); 341 else 342 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, offset, size); 343 344 return (0); 345} 346 347 348static int 349pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 350 uint64_t *addr) 351{ 352 uint64_t base; 353 354 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 355 356 base = roundup2(*baseptr, size); 357 358 if (base + size <= limit) { 359 *addr = base; 360 *baseptr = base + size; 361 return (0); 362 } else 363 return (-1); 364} 365 366int 367pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 368 uint64_t size) 369{ 370 371 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 372} 373 374/* 375 * Register (or unregister) the MMIO or I/O region associated with the BAR 376 * register 'idx' of an emulated pci device. 377 */ 378static void 379modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 380{ 381 int error; 382 struct inout_port iop; 383 struct mem_range mr; 384 385 switch (pi->pi_bar[idx].type) { 386 case PCIBAR_IO: 387 bzero(&iop, sizeof(struct inout_port)); 388 iop.name = pi->pi_name; 389 iop.port = pi->pi_bar[idx].addr; 390 iop.size = pi->pi_bar[idx].size; 391 if (registration) { 392 iop.flags = IOPORT_F_INOUT; 393 iop.handler = pci_emul_io_handler; 394 iop.arg = pi; 395 error = register_inout(&iop); 396 } else 397 error = unregister_inout(&iop); 398 break; 399 case PCIBAR_MEM32: 400 case PCIBAR_MEM64: 401 bzero(&mr, sizeof(struct mem_range)); 402 mr.name = pi->pi_name; 403 mr.base = pi->pi_bar[idx].addr; 404 mr.size = pi->pi_bar[idx].size; 405 if (registration) { 406 mr.flags = MEM_F_RW; 407 mr.handler = pci_emul_mem_handler; 408 mr.arg1 = pi; 409 mr.arg2 = idx; 410 error = register_mem(&mr); 411 } else 412 error = unregister_mem(&mr); 413 break; 414 default: 415 error = EINVAL; 416 break; 417 } 418 assert(error == 0); 419} 420 421static void 422unregister_bar(struct pci_devinst *pi, int idx) 423{ 424 425 modify_bar_registration(pi, idx, 0); 426} 427 428static void 429register_bar(struct pci_devinst *pi, int idx) 430{ 431 432 modify_bar_registration(pi, idx, 1); 433} 434 435/* Are we decoding i/o port accesses for the emulated pci device? */ 436static int 437porten(struct pci_devinst *pi) 438{ 439 uint16_t cmd; 440 441 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 442 443 return (cmd & PCIM_CMD_PORTEN); 444} 445 446/* Are we decoding memory accesses for the emulated pci device? */ 447static int 448memen(struct pci_devinst *pi) 449{ 450 uint16_t cmd; 451 452 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 453 454 return (cmd & PCIM_CMD_MEMEN); 455} 456 457/* 458 * Update the MMIO or I/O address that is decoded by the BAR register. 459 * 460 * If the pci device has enabled the address space decoding then intercept 461 * the address range decoded by the BAR register. 462 */ 463static void 464update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 465{ 466 int decode; 467 468 if (pi->pi_bar[idx].type == PCIBAR_IO) 469 decode = porten(pi); 470 else 471 decode = memen(pi); 472 473 if (decode) 474 unregister_bar(pi, idx); 475 476 switch (type) { 477 case PCIBAR_IO: 478 case PCIBAR_MEM32: 479 pi->pi_bar[idx].addr = addr; 480 break; 481 case PCIBAR_MEM64: 482 pi->pi_bar[idx].addr &= ~0xffffffffUL; 483 pi->pi_bar[idx].addr |= addr; 484 break; 485 case PCIBAR_MEMHI64: 486 pi->pi_bar[idx].addr &= 0xffffffff; 487 pi->pi_bar[idx].addr |= addr; 488 break; 489 default: 490 assert(0); 491 } 492 493 if (decode) 494 register_bar(pi, idx); 495} 496 497int 498pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 499 enum pcibar_type type, uint64_t size) 500{ 501 int error; 502 uint64_t *baseptr, limit, addr, mask, lobits, bar; 503 504 assert(idx >= 0 && idx <= PCI_BARMAX); 505 506 if ((size & (size - 1)) != 0) 507 size = 1UL << flsl(size); /* round up to a power of 2 */ 508 509 /* Enforce minimum BAR sizes required by the PCI standard */ 510 if (type == PCIBAR_IO) { 511 if (size < 4) 512 size = 4; 513 } else { 514 if (size < 16) 515 size = 16; 516 } 517 518 switch (type) { 519 case PCIBAR_NONE: 520 baseptr = NULL; 521 addr = mask = lobits = 0; 522 break; 523 case PCIBAR_IO: 524 if (hostbase && 525 pci_slotinfo[pdi->pi_slot][pdi->pi_func].si_legacy) { 526 assert(hostbase < PCI_EMUL_IOBASE); 527 baseptr = &hostbase; 528 } else { 529 baseptr = &pci_emul_iobase; 530 } 531 limit = PCI_EMUL_IOLIMIT; 532 mask = PCIM_BAR_IO_BASE; 533 lobits = PCIM_BAR_IO_SPACE; 534 break; 535 case PCIBAR_MEM64: 536 /* 537 * XXX 538 * Some drivers do not work well if the 64-bit BAR is allocated 539 * above 4GB. Allow for this by allocating small requests under 540 * 4GB unless then allocation size is larger than some arbitrary 541 * number (32MB currently). 542 */ 543 if (size > 32 * 1024 * 1024) { 544 /* 545 * XXX special case for device requiring peer-peer DMA 546 */ 547 if (size == 0x100000000UL) 548 baseptr = &hostbase; 549 else 550 baseptr = &pci_emul_membase64; 551 limit = PCI_EMUL_MEMLIMIT64; 552 mask = PCIM_BAR_MEM_BASE; 553 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 554 PCIM_BAR_MEM_PREFETCH; 555 break; 556 } else { 557 baseptr = &pci_emul_membase32; 558 limit = PCI_EMUL_MEMLIMIT32; 559 mask = PCIM_BAR_MEM_BASE; 560 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 561 } 562 break; 563 case PCIBAR_MEM32: 564 baseptr = &pci_emul_membase32; 565 limit = PCI_EMUL_MEMLIMIT32; 566 mask = PCIM_BAR_MEM_BASE; 567 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 568 break; 569 default: 570 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 571 assert(0); 572 } 573 574 if (baseptr != NULL) { 575 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 576 if (error != 0) 577 return (error); 578 } 579 580 pdi->pi_bar[idx].type = type; 581 pdi->pi_bar[idx].addr = addr; 582 pdi->pi_bar[idx].size = size; 583 584 /* Initialize the BAR register in config space */ 585 bar = (addr & mask) | lobits; 586 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 587 588 if (type == PCIBAR_MEM64) { 589 assert(idx + 1 <= PCI_BARMAX); 590 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 591 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 592 } 593 594 register_bar(pdi, idx); 595 596 return (0); 597} 598 599#define CAP_START_OFFSET 0x40 600static int 601pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 602{ 603 int i, capoff, capid, reallen; 604 uint16_t sts; 605 606 static u_char endofcap[4] = { 607 PCIY_RESERVED, 0, 0, 0 608 }; 609 610 assert(caplen > 0 && capdata[0] != PCIY_RESERVED); 611 612 reallen = roundup2(caplen, 4); /* dword aligned */ 613 614 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 615 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 616 capoff = CAP_START_OFFSET; 617 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 618 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 619 } else { 620 capoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR); 621 while (1) { 622 assert((capoff & 0x3) == 0); 623 capid = pci_get_cfgdata8(pi, capoff); 624 if (capid == PCIY_RESERVED) 625 break; 626 capoff = pci_get_cfgdata8(pi, capoff + 1); 627 } 628 } 629 630 /* Check if we have enough space */ 631 if (capoff + reallen + sizeof(endofcap) > PCI_REGMAX + 1) 632 return (-1); 633 634 /* Copy the capability */ 635 for (i = 0; i < caplen; i++) 636 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 637 638 /* Set the next capability pointer */ 639 pci_set_cfgdata8(pi, capoff + 1, capoff + reallen); 640 641 /* Copy of the reserved capability which serves as the end marker */ 642 for (i = 0; i < sizeof(endofcap); i++) 643 pci_set_cfgdata8(pi, capoff + reallen + i, endofcap[i]); 644 645 return (0); 646} 647 648static struct pci_devemu * 649pci_emul_finddev(char *name) 650{ 651 struct pci_devemu **pdpp, *pdp; 652 653 SET_FOREACH(pdpp, pci_devemu_set) { 654 pdp = *pdpp; 655 if (!strcmp(pdp->pe_emu, name)) { 656 return (pdp); 657 } 658 } 659 660 return (NULL); 661} 662 663static int 664pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int slot, int func, 665 char *params) 666{ 667 struct pci_devinst *pdi; 668 int err; 669 670 pdi = malloc(sizeof(struct pci_devinst)); 671 bzero(pdi, sizeof(*pdi)); 672 673 pdi->pi_vmctx = ctx; 674 pdi->pi_bus = 0; 675 pdi->pi_slot = slot; 676 pdi->pi_func = func; 677 pdi->pi_lintr_pin = -1; 678 pdi->pi_d = pde; 679 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 680 681 /* Disable legacy interrupts */ 682 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 683 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 684 685 pci_set_cfgdata8(pdi, PCIR_COMMAND, 686 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 687 688 err = (*pde->pe_init)(ctx, pdi, params); 689 if (err != 0) { 690 free(pdi); 691 } else { 692 pci_emul_devices++; 693 pci_slotinfo[slot][func].si_devi = pdi; 694 } 695 696 return (err); 697} 698 699void 700pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 701{ 702 int mmc; 703 704 CTASSERT(sizeof(struct msicap) == 14); 705 706 /* Number of msi messages must be a power of 2 between 1 and 32 */ 707 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 708 mmc = ffs(msgnum) - 1; 709 710 bzero(msicap, sizeof(struct msicap)); 711 msicap->capid = PCIY_MSI; 712 msicap->nextptr = nextptr; 713 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 714} 715 716int 717pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 718{ 719 struct msicap msicap; 720 721 pci_populate_msicap(&msicap, msgnum, 0); 722 723 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 724} 725 726static void 727pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 728 uint32_t msix_tab_size, int nextptr) 729{ 730 CTASSERT(sizeof(struct msixcap) == 12); 731 732 assert(msix_tab_size % 4096 == 0); 733 734 bzero(msixcap, sizeof(struct msixcap)); 735 msixcap->capid = PCIY_MSIX; 736 msixcap->nextptr = nextptr; 737 738 /* 739 * Message Control Register, all fields set to 740 * zero except for the Table Size. 741 * Note: Table size N is encoded as N-1 742 */ 743 msixcap->msgctrl = msgnum - 1; 744 745 /* 746 * MSI-X BAR setup: 747 * - MSI-X table start at offset 0 748 * - PBA table starts at a 4K aligned offset after the MSI-X table 749 */ 750 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 751 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 752} 753 754static void 755pci_msix_table_init(struct pci_devinst *pi, int table_entries) 756{ 757 int i, table_size; 758 759 assert(table_entries > 0); 760 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 761 762 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 763 pi->pi_msix.table = malloc(table_size); 764 bzero(pi->pi_msix.table, table_size); 765 766 /* set mask bit of vector control register */ 767 for (i = 0; i < table_entries; i++) 768 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 769} 770 771int 772pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 773{ 774 uint16_t pba_index; 775 uint32_t tab_size; 776 struct msixcap msixcap; 777 778 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 779 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 780 781 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 782 783 /* Align table size to nearest 4K */ 784 tab_size = roundup2(tab_size, 4096); 785 786 pi->pi_msix.table_bar = barnum; 787 pi->pi_msix.pba_bar = barnum; 788 pi->pi_msix.table_offset = 0; 789 pi->pi_msix.table_count = msgnum; 790 pi->pi_msix.pba_offset = tab_size; 791 792 /* calculate the MMIO size required for MSI-X PBA */ 793 pba_index = (msgnum - 1) / (PBA_TABLE_ENTRY_SIZE * 8); 794 pi->pi_msix.pba_size = (pba_index + 1) * PBA_TABLE_ENTRY_SIZE; 795 796 pci_msix_table_init(pi, msgnum); 797 798 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size, 0); 799 800 /* allocate memory for MSI-X Table and PBA */ 801 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 802 tab_size + pi->pi_msix.pba_size); 803 804 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 805 sizeof(msixcap))); 806} 807 808void 809msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 810 int bytes, uint32_t val) 811{ 812 uint16_t msgctrl, rwmask; 813 int off, table_bar; 814 815 off = offset - capoff; 816 table_bar = pi->pi_msix.table_bar; 817 /* Message Control Register */ 818 if (off == 2 && bytes == 2) { 819 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 820 msgctrl = pci_get_cfgdata16(pi, offset); 821 msgctrl &= ~rwmask; 822 msgctrl |= val & rwmask; 823 val = msgctrl; 824 825 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 826 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 827 } 828 829 CFGWRITE(pi, offset, val, bytes); 830} 831 832void 833msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 834 int bytes, uint32_t val) 835{ 836 uint16_t msgctrl, rwmask, msgdata, mme; 837 uint32_t addrlo; 838 839 /* 840 * If guest is writing to the message control register make sure 841 * we do not overwrite read-only fields. 842 */ 843 if ((offset - capoff) == 2 && bytes == 2) { 844 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 845 msgctrl = pci_get_cfgdata16(pi, offset); 846 msgctrl &= ~rwmask; 847 msgctrl |= val & rwmask; 848 val = msgctrl; 849 850 addrlo = pci_get_cfgdata32(pi, capoff + 4); 851 if (msgctrl & PCIM_MSICTRL_64BIT) 852 msgdata = pci_get_cfgdata16(pi, capoff + 12); 853 else 854 msgdata = pci_get_cfgdata16(pi, capoff + 8); 855 856 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 857 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 858 if (pi->pi_msi.enabled) { 859 pi->pi_msi.addr = addrlo; 860 pi->pi_msi.msg_data = msgdata; 861 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 862 } else { 863 pi->pi_msi.maxmsgnum = 0; 864 } 865 } 866 867 CFGWRITE(pi, offset, val, bytes); 868} 869 870void 871pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 872 int bytes, uint32_t val) 873{ 874 875 /* XXX don't write to the readonly parts */ 876 CFGWRITE(pi, offset, val, bytes); 877} 878 879#define PCIECAP_VERSION 0x2 880int 881pci_emul_add_pciecap(struct pci_devinst *pi, int type) 882{ 883 int err; 884 struct pciecap pciecap; 885 886 CTASSERT(sizeof(struct pciecap) == 60); 887 888 if (type != PCIEM_TYPE_ROOT_PORT) 889 return (-1); 890 891 bzero(&pciecap, sizeof(pciecap)); 892 893 pciecap.capid = PCIY_EXPRESS; 894 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; 895 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 896 pciecap.link_status = 0x11; /* gen1, x1 */ 897 898 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 899 return (err); 900} 901 902/* 903 * This function assumes that 'coff' is in the capabilities region of the 904 * config space. 905 */ 906static void 907pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 908{ 909 int capid; 910 uint8_t capoff, nextoff; 911 912 /* Do not allow un-aligned writes */ 913 if ((offset & (bytes - 1)) != 0) 914 return; 915 916 /* Find the capability that we want to update */ 917 capoff = CAP_START_OFFSET; 918 while (1) { 919 capid = pci_get_cfgdata8(pi, capoff); 920 if (capid == PCIY_RESERVED) 921 break; 922 923 nextoff = pci_get_cfgdata8(pi, capoff + 1); 924 if (offset >= capoff && offset < nextoff) 925 break; 926 927 capoff = nextoff; 928 } 929 assert(offset >= capoff); 930 931 /* 932 * Capability ID and Next Capability Pointer are readonly. 933 * However, some o/s's do 4-byte writes that include these. 934 * For this case, trim the write back to 2 bytes and adjust 935 * the data. 936 */ 937 if (offset == capoff || offset == capoff + 1) { 938 if (offset == capoff && bytes == 4) { 939 bytes = 2; 940 offset += 2; 941 val >>= 16; 942 } else 943 return; 944 } 945 946 switch (capid) { 947 case PCIY_MSI: 948 msicap_cfgwrite(pi, capoff, offset, bytes, val); 949 break; 950 case PCIY_MSIX: 951 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 952 break; 953 case PCIY_EXPRESS: 954 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 955 break; 956 default: 957 break; 958 } 959} 960 961static int 962pci_emul_iscap(struct pci_devinst *pi, int offset) 963{ 964 int found; 965 uint16_t sts; 966 uint8_t capid, lastoff; 967 968 found = 0; 969 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 970 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 971 lastoff = pci_get_cfgdata8(pi, PCIR_CAP_PTR); 972 while (1) { 973 assert((lastoff & 0x3) == 0); 974 capid = pci_get_cfgdata8(pi, lastoff); 975 if (capid == PCIY_RESERVED) 976 break; 977 lastoff = pci_get_cfgdata8(pi, lastoff + 1); 978 } 979 if (offset >= CAP_START_OFFSET && offset <= lastoff) 980 found = 1; 981 } 982 return (found); 983} 984 985static int 986pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 987 int size, uint64_t *val, void *arg1, long arg2) 988{ 989 /* 990 * Ignore writes; return 0xff's for reads. The mem read code 991 * will take care of truncating to the correct size. 992 */ 993 if (dir == MEM_F_READ) { 994 *val = 0xffffffffffffffff; 995 } 996 997 return (0); 998} 999 1000int 1001init_pci(struct vmctx *ctx) 1002{ 1003 struct pci_devemu *pde; 1004 struct slotinfo *si; 1005 size_t lowmem; 1006 int slot, func; 1007 int error; 1008 1009 pci_emul_iobase = PCI_EMUL_IOBASE; 1010 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1011 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1012 1013 for (slot = 0; slot < MAXSLOTS; slot++) { 1014 for (func = 0; func < MAXFUNCS; func++) { 1015 si = &pci_slotinfo[slot][func]; 1016 if (si->si_name != NULL) { 1017 pde = pci_emul_finddev(si->si_name); 1018 assert(pde != NULL); 1019 error = pci_emul_init(ctx, pde, slot, func, 1020 si->si_param); 1021 if (error) 1022 return (error); 1023 } 1024 } 1025 } 1026 1027 /* 1028 * The guest physical memory map looks like the following: 1029 * [0, lowmem) guest system memory 1030 * [lowmem, lowmem_limit) memory hole (may be absent) 1031 * [lowmem_limit, 4GB) PCI hole (32-bit BAR allocation) 1032 * [4GB, 4GB + highmem) 1033 * 1034 * Accesses to memory addresses that are not allocated to system 1035 * memory or PCI devices return 0xff's. 1036 */ 1037 error = vm_get_memory_seg(ctx, 0, &lowmem, NULL); 1038 assert(error == 0); 1039 1040 memset(&pci_mem_hole, 0, sizeof(struct mem_range)); 1041 pci_mem_hole.name = "PCI hole"; 1042 pci_mem_hole.flags = MEM_F_RW; 1043 pci_mem_hole.base = lowmem; 1044 pci_mem_hole.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1045 pci_mem_hole.handler = pci_emul_fallback_handler; 1046 1047 error = register_mem_fallback(&pci_mem_hole); 1048 assert(error == 0); 1049 1050 return (0); 1051} 1052 1053void 1054pci_write_dsdt(void) 1055{ 1056 struct pci_devinst *pi; 1057 int slot, func; 1058 1059 dsdt_indent(1); 1060 dsdt_line("Scope (_SB)"); 1061 dsdt_line("{"); 1062 dsdt_line(" Device (PCI0)"); 1063 dsdt_line(" {"); 1064 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1065 dsdt_line(" Name (_ADR, Zero)"); 1066 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1067 dsdt_line(" {"); 1068 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1069 "MaxFixed, PosDecode,"); 1070 dsdt_line(" 0x0000, // Granularity"); 1071 dsdt_line(" 0x0000, // Range Minimum"); 1072 dsdt_line(" 0x00FF, // Range Maximum"); 1073 dsdt_line(" 0x0000, // Translation Offset"); 1074 dsdt_line(" 0x0100, // Length"); 1075 dsdt_line(" ,, )"); 1076 dsdt_indent(3); 1077 dsdt_fixed_ioport(0xCF8, 8); 1078 dsdt_unindent(3); 1079 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1080 "PosDecode, EntireRange,"); 1081 dsdt_line(" 0x0000, // Granularity"); 1082 dsdt_line(" 0x0000, // Range Minimum"); 1083 dsdt_line(" 0x0CF7, // Range Maximum"); 1084 dsdt_line(" 0x0000, // Translation Offset"); 1085 dsdt_line(" 0x0CF8, // Length"); 1086 dsdt_line(" ,, , TypeStatic)"); 1087 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1088 "PosDecode, EntireRange,"); 1089 dsdt_line(" 0x0000, // Granularity"); 1090 dsdt_line(" 0x0D00, // Range Minimum"); 1091 dsdt_line(" 0xFFFF, // Range Maximum"); 1092 dsdt_line(" 0x0000, // Translation Offset"); 1093 dsdt_line(" 0xF300, // Length"); 1094 dsdt_line(" ,, , TypeStatic)"); 1095 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1096 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1097 dsdt_line(" 0x00000000, // Granularity"); 1098 dsdt_line(" 0x%08lX, // Range Minimum\n", 1099 pci_mem_hole.base); 1100 dsdt_line(" 0x%08X, // Range Maximum\n", 1101 PCI_EMUL_MEMLIMIT32 - 1); 1102 dsdt_line(" 0x00000000, // Translation Offset"); 1103 dsdt_line(" 0x%08lX, // Length\n", 1104 PCI_EMUL_MEMLIMIT32 - pci_mem_hole.base); 1105 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1106 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1107 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1108 dsdt_line(" 0x0000000000000000, // Granularity"); 1109 dsdt_line(" 0x%016lX, // Range Minimum\n", 1110 PCI_EMUL_MEMBASE64); 1111 dsdt_line(" 0x%016lX, // Range Maximum\n", 1112 PCI_EMUL_MEMLIMIT64 - 1); 1113 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1114 dsdt_line(" 0x%016lX, // Length\n", 1115 PCI_EMUL_MEMLIMIT64 - PCI_EMUL_MEMBASE64); 1116 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1117 dsdt_line(" })"); 1118 1119 dsdt_indent(2); 1120 for (slot = 0; slot < MAXSLOTS; slot++) { 1121 for (func = 0; func < MAXFUNCS; func++) { 1122 pi = pci_slotinfo[slot][func].si_devi; 1123 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1124 pi->pi_d->pe_write_dsdt(pi); 1125 } 1126 } 1127 dsdt_unindent(2); 1128 1129 dsdt_line(" }"); 1130 dsdt_line("}"); 1131 dsdt_unindent(1); 1132} 1133 1134int 1135pci_msi_enabled(struct pci_devinst *pi) 1136{ 1137 return (pi->pi_msi.enabled); 1138} 1139 1140int 1141pci_msi_maxmsgnum(struct pci_devinst *pi) 1142{ 1143 if (pi->pi_msi.enabled) 1144 return (pi->pi_msi.maxmsgnum); 1145 else 1146 return (0); 1147} 1148 1149int 1150pci_msix_enabled(struct pci_devinst *pi) 1151{ 1152 1153 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1154} 1155 1156void 1157pci_generate_msix(struct pci_devinst *pi, int index) 1158{ 1159 struct msix_table_entry *mte; 1160 1161 if (!pci_msix_enabled(pi)) 1162 return; 1163 1164 if (pi->pi_msix.function_mask) 1165 return; 1166 1167 if (index >= pi->pi_msix.table_count) 1168 return; 1169 1170 mte = &pi->pi_msix.table[index]; 1171 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1172 /* XXX Set PBA bit if interrupt is disabled */ 1173 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1174 } 1175} 1176 1177void 1178pci_generate_msi(struct pci_devinst *pi, int index) 1179{ 1180 1181 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1182 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1183 pi->pi_msi.msg_data + index); 1184 } 1185} 1186 1187int 1188pci_is_legacy(struct pci_devinst *pi) 1189{ 1190 1191 return (pci_slotinfo[pi->pi_slot][pi->pi_func].si_legacy); 1192} 1193 1194int 1195pci_lintr_request(struct pci_devinst *pi, int req) 1196{ 1197 int irq; 1198 1199 irq = legacy_irq_alloc(req); 1200 if (irq < 0) 1201 return (-1); 1202 1203 pi->pi_lintr_pin = irq; 1204 pci_set_cfgdata8(pi, PCIR_INTLINE, irq); 1205 pci_set_cfgdata8(pi, PCIR_INTPIN, 1); 1206 return (0); 1207} 1208 1209void 1210pci_lintr_assert(struct pci_devinst *pi) 1211{ 1212 1213 assert(pi->pi_lintr_pin >= 0); 1214 1215 if (pi->pi_lintr_state == 0) { 1216 pi->pi_lintr_state = 1; 1217 vm_ioapic_assert_irq(pi->pi_vmctx, pi->pi_lintr_pin); 1218 } 1219} 1220 1221void 1222pci_lintr_deassert(struct pci_devinst *pi) 1223{ 1224 1225 assert(pi->pi_lintr_pin >= 0); 1226 1227 if (pi->pi_lintr_state == 1) { 1228 pi->pi_lintr_state = 0; 1229 vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr_pin); 1230 } 1231} 1232 1233/* 1234 * Return 1 if the emulated device in 'slot' is a multi-function device. 1235 * Return 0 otherwise. 1236 */ 1237static int 1238pci_emul_is_mfdev(int slot) 1239{ 1240 int f, numfuncs; 1241 1242 numfuncs = 0; 1243 for (f = 0; f < MAXFUNCS; f++) { 1244 if (pci_slotinfo[slot][f].si_devi != NULL) { 1245 numfuncs++; 1246 } 1247 } 1248 return (numfuncs > 1); 1249} 1250 1251/* 1252 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1253 * whether or not is a multi-function being emulated in the pci 'slot'. 1254 */ 1255static void 1256pci_emul_hdrtype_fixup(int slot, int off, int bytes, uint32_t *rv) 1257{ 1258 int mfdev; 1259 1260 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1261 mfdev = pci_emul_is_mfdev(slot); 1262 switch (bytes) { 1263 case 1: 1264 case 2: 1265 *rv &= ~PCIM_MFDEV; 1266 if (mfdev) { 1267 *rv |= PCIM_MFDEV; 1268 } 1269 break; 1270 case 4: 1271 *rv &= ~(PCIM_MFDEV << 16); 1272 if (mfdev) { 1273 *rv |= (PCIM_MFDEV << 16); 1274 } 1275 break; 1276 } 1277 } 1278} 1279 1280static int cfgbus, cfgslot, cfgfunc, cfgoff; 1281 1282static int 1283pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1284 uint32_t *eax, void *arg) 1285{ 1286 uint32_t x; 1287 1288 if (bytes != 4) { 1289 if (in) 1290 *eax = (bytes == 2) ? 0xffff : 0xff; 1291 return (0); 1292 } 1293 1294 if (in) { 1295 x = (cfgbus << 16) | 1296 (cfgslot << 11) | 1297 (cfgfunc << 8) | 1298 cfgoff; 1299 *eax = x | CONF1_ENABLE; 1300 } else { 1301 x = *eax; 1302 cfgoff = x & PCI_REGMAX; 1303 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1304 cfgslot = (x >> 11) & PCI_SLOTMAX; 1305 cfgbus = (x >> 16) & PCI_BUSMAX; 1306 } 1307 1308 return (0); 1309} 1310INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1311 1312static uint32_t 1313bits_changed(uint32_t old, uint32_t new, uint32_t mask) 1314{ 1315 1316 return ((old ^ new) & mask); 1317} 1318 1319static void 1320pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes) 1321{ 1322 int i; 1323 uint16_t old; 1324 1325 /* 1326 * The command register is at an offset of 4 bytes and thus the 1327 * guest could write 1, 2 or 4 bytes starting at this offset. 1328 */ 1329 1330 old = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1331 CFGWRITE(pi, PCIR_COMMAND, new, bytes); /* update config */ 1332 new = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */ 1333 1334 /* 1335 * If the MMIO or I/O address space decoding has changed then 1336 * register/unregister all BARs that decode that address space. 1337 */ 1338 for (i = 0; i <= PCI_BARMAX; i++) { 1339 switch (pi->pi_bar[i].type) { 1340 case PCIBAR_NONE: 1341 case PCIBAR_MEMHI64: 1342 break; 1343 case PCIBAR_IO: 1344 /* I/O address space decoding changed? */ 1345 if (bits_changed(old, new, PCIM_CMD_PORTEN)) { 1346 if (porten(pi)) 1347 register_bar(pi, i); 1348 else 1349 unregister_bar(pi, i); 1350 } 1351 break; 1352 case PCIBAR_MEM32: 1353 case PCIBAR_MEM64: 1354 /* MMIO address space decoding changed? */ 1355 if (bits_changed(old, new, PCIM_CMD_MEMEN)) { 1356 if (memen(pi)) 1357 register_bar(pi, i); 1358 else 1359 unregister_bar(pi, i); 1360 } 1361 break; 1362 default: 1363 assert(0); 1364 } 1365 } 1366} 1367 1368static int 1369pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1370 uint32_t *eax, void *arg) 1371{ 1372 struct pci_devinst *pi; 1373 struct pci_devemu *pe; 1374 int coff, idx, needcfg; 1375 uint64_t addr, bar, mask; 1376 1377 assert(bytes == 1 || bytes == 2 || bytes == 4); 1378 1379 if (cfgbus == 0) 1380 pi = pci_slotinfo[cfgslot][cfgfunc].si_devi; 1381 else 1382 pi = NULL; 1383 1384 coff = cfgoff + (port - CONF1_DATA_PORT); 1385 1386#if 0 1387 printf("pcicfg-%s from 0x%0x of %d bytes (%d/%d/%d)\n\r", 1388 in ? "read" : "write", coff, bytes, cfgbus, cfgslot, cfgfunc); 1389#endif 1390 1391 /* 1392 * Just return if there is no device at this cfgslot:cfgfunc or 1393 * if the guest is doing an un-aligned access 1394 */ 1395 if (pi == NULL || (coff & (bytes - 1)) != 0) { 1396 if (in) 1397 *eax = 0xffffffff; 1398 return (0); 1399 } 1400 1401 pe = pi->pi_d; 1402 1403 /* 1404 * Config read 1405 */ 1406 if (in) { 1407 /* Let the device emulation override the default handler */ 1408 if (pe->pe_cfgread != NULL) { 1409 needcfg = pe->pe_cfgread(ctx, vcpu, pi, 1410 coff, bytes, eax); 1411 } else { 1412 needcfg = 1; 1413 } 1414 1415 if (needcfg) { 1416 if (bytes == 1) 1417 *eax = pci_get_cfgdata8(pi, coff); 1418 else if (bytes == 2) 1419 *eax = pci_get_cfgdata16(pi, coff); 1420 else 1421 *eax = pci_get_cfgdata32(pi, coff); 1422 } 1423 1424 pci_emul_hdrtype_fixup(cfgslot, coff, bytes, eax); 1425 } else { 1426 /* Let the device emulation override the default handler */ 1427 if (pe->pe_cfgwrite != NULL && 1428 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1429 return (0); 1430 1431 /* 1432 * Special handling for write to BAR registers 1433 */ 1434 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1435 /* 1436 * Ignore writes to BAR registers that are not 1437 * 4-byte aligned. 1438 */ 1439 if (bytes != 4 || (coff & 0x3) != 0) 1440 return (0); 1441 idx = (coff - PCIR_BAR(0)) / 4; 1442 mask = ~(pi->pi_bar[idx].size - 1); 1443 switch (pi->pi_bar[idx].type) { 1444 case PCIBAR_NONE: 1445 pi->pi_bar[idx].addr = bar = 0; 1446 break; 1447 case PCIBAR_IO: 1448 addr = *eax & mask; 1449 addr &= 0xffff; 1450 bar = addr | PCIM_BAR_IO_SPACE; 1451 /* 1452 * Register the new BAR value for interception 1453 */ 1454 if (addr != pi->pi_bar[idx].addr) { 1455 update_bar_address(pi, addr, idx, 1456 PCIBAR_IO); 1457 } 1458 break; 1459 case PCIBAR_MEM32: 1460 addr = bar = *eax & mask; 1461 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1462 if (addr != pi->pi_bar[idx].addr) { 1463 update_bar_address(pi, addr, idx, 1464 PCIBAR_MEM32); 1465 } 1466 break; 1467 case PCIBAR_MEM64: 1468 addr = bar = *eax & mask; 1469 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1470 PCIM_BAR_MEM_PREFETCH; 1471 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1472 update_bar_address(pi, addr, idx, 1473 PCIBAR_MEM64); 1474 } 1475 break; 1476 case PCIBAR_MEMHI64: 1477 mask = ~(pi->pi_bar[idx - 1].size - 1); 1478 addr = ((uint64_t)*eax << 32) & mask; 1479 bar = addr >> 32; 1480 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1481 update_bar_address(pi, addr, idx - 1, 1482 PCIBAR_MEMHI64); 1483 } 1484 break; 1485 default: 1486 assert(0); 1487 } 1488 pci_set_cfgdata32(pi, coff, bar); 1489 1490 } else if (pci_emul_iscap(pi, coff)) { 1491 pci_emul_capwrite(pi, coff, bytes, *eax); 1492 } else if (coff == PCIR_COMMAND) { 1493 pci_emul_cmdwrite(pi, *eax, bytes); 1494 } else { 1495 CFGWRITE(pi, coff, *eax, bytes); 1496 } 1497 } 1498 1499 return (0); 1500} 1501 1502INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1503INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1504INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1505INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1506 1507/* 1508 * I/O ports to configure PCI IRQ routing. We ignore all writes to it. 1509 */ 1510static int 1511pci_irq_port_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1512 uint32_t *eax, void *arg) 1513{ 1514 assert(in == 0); 1515 return (0); 1516} 1517INOUT_PORT(pci_irq, 0xC00, IOPORT_F_OUT, pci_irq_port_handler); 1518INOUT_PORT(pci_irq, 0xC01, IOPORT_F_OUT, pci_irq_port_handler); 1519SYSRES_IO(0xC00, 2); 1520 1521#define PCI_EMUL_TEST 1522#ifdef PCI_EMUL_TEST 1523/* 1524 * Define a dummy test device 1525 */ 1526#define DIOSZ 20 1527#define DMEMSZ 4096 1528struct pci_emul_dsoftc { 1529 uint8_t ioregs[DIOSZ]; 1530 uint8_t memregs[DMEMSZ]; 1531}; 1532 1533#define PCI_EMUL_MSI_MSGS 4 1534#define PCI_EMUL_MSIX_MSGS 16 1535 1536static int 1537pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1538{ 1539 int error; 1540 struct pci_emul_dsoftc *sc; 1541 1542 sc = malloc(sizeof(struct pci_emul_dsoftc)); 1543 memset(sc, 0, sizeof(struct pci_emul_dsoftc)); 1544 1545 pi->pi_arg = sc; 1546 1547 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1548 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1549 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1550 1551 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1552 assert(error == 0); 1553 1554 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1555 assert(error == 0); 1556 1557 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 1558 assert(error == 0); 1559 1560 return (0); 1561} 1562 1563static void 1564pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1565 uint64_t offset, int size, uint64_t value) 1566{ 1567 int i; 1568 struct pci_emul_dsoftc *sc = pi->pi_arg; 1569 1570 if (baridx == 0) { 1571 if (offset + size > DIOSZ) { 1572 printf("diow: iow too large, offset %ld size %d\n", 1573 offset, size); 1574 return; 1575 } 1576 1577 if (size == 1) { 1578 sc->ioregs[offset] = value & 0xff; 1579 } else if (size == 2) { 1580 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 1581 } else if (size == 4) { 1582 *(uint32_t *)&sc->ioregs[offset] = value; 1583 } else { 1584 printf("diow: iow unknown size %d\n", size); 1585 } 1586 1587 /* 1588 * Special magic value to generate an interrupt 1589 */ 1590 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 1591 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 1592 1593 if (value == 0xabcdef) { 1594 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 1595 pci_generate_msi(pi, i); 1596 } 1597 } 1598 1599 if (baridx == 1) { 1600 if (offset + size > DMEMSZ) { 1601 printf("diow: memw too large, offset %ld size %d\n", 1602 offset, size); 1603 return; 1604 } 1605 1606 if (size == 1) { 1607 sc->memregs[offset] = value; 1608 } else if (size == 2) { 1609 *(uint16_t *)&sc->memregs[offset] = value; 1610 } else if (size == 4) { 1611 *(uint32_t *)&sc->memregs[offset] = value; 1612 } else if (size == 8) { 1613 *(uint64_t *)&sc->memregs[offset] = value; 1614 } else { 1615 printf("diow: memw unknown size %d\n", size); 1616 } 1617 1618 /* 1619 * magic interrupt ?? 1620 */ 1621 } 1622 1623 if (baridx > 1) { 1624 printf("diow: unknown bar idx %d\n", baridx); 1625 } 1626} 1627 1628static uint64_t 1629pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 1630 uint64_t offset, int size) 1631{ 1632 struct pci_emul_dsoftc *sc = pi->pi_arg; 1633 uint32_t value; 1634 1635 if (baridx == 0) { 1636 if (offset + size > DIOSZ) { 1637 printf("dior: ior too large, offset %ld size %d\n", 1638 offset, size); 1639 return (0); 1640 } 1641 1642 if (size == 1) { 1643 value = sc->ioregs[offset]; 1644 } else if (size == 2) { 1645 value = *(uint16_t *) &sc->ioregs[offset]; 1646 } else if (size == 4) { 1647 value = *(uint32_t *) &sc->ioregs[offset]; 1648 } else { 1649 printf("dior: ior unknown size %d\n", size); 1650 } 1651 } 1652 1653 if (baridx == 1) { 1654 if (offset + size > DMEMSZ) { 1655 printf("dior: memr too large, offset %ld size %d\n", 1656 offset, size); 1657 return (0); 1658 } 1659 1660 if (size == 1) { 1661 value = sc->memregs[offset]; 1662 } else if (size == 2) { 1663 value = *(uint16_t *) &sc->memregs[offset]; 1664 } else if (size == 4) { 1665 value = *(uint32_t *) &sc->memregs[offset]; 1666 } else if (size == 8) { 1667 value = *(uint64_t *) &sc->memregs[offset]; 1668 } else { 1669 printf("dior: ior unknown size %d\n", size); 1670 } 1671 } 1672 1673 1674 if (baridx > 1) { 1675 printf("dior: unknown bar idx %d\n", baridx); 1676 return (0); 1677 } 1678 1679 return (value); 1680} 1681 1682struct pci_devemu pci_dummy = { 1683 .pe_emu = "dummy", 1684 .pe_init = pci_emul_dinit, 1685 .pe_barwrite = pci_emul_diow, 1686 .pe_barread = pci_emul_dior 1687}; 1688PCI_EMUL_SET(pci_dummy); 1689 1690#endif /* PCI_EMUL_TEST */ 1691