mptbl.c revision 261088 
1/*-
2 * Copyright (c) 2012 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/usr.sbin/bhyve/mptbl.c 261088 2014-01-23 20:21:39Z jhb $
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/mptbl.c 261088 2014-01-23 20:21:39Z jhb $");
31
32#include <sys/types.h>
33#include <sys/errno.h>
34#include <x86/mptable.h>
35
36#include <stdio.h>
37#include <string.h>
38
39#include "bhyverun.h"
40#include "mptbl.h"
41
42#define MPTABLE_BASE		0xF0000
43
44/* floating pointer length + maximum length of configuration table */
45#define	MPTABLE_MAX_LENGTH	(65536 + 16)
46
47#define LAPIC_PADDR		0xFEE00000
48#define LAPIC_VERSION 		16
49
50#define IOAPIC_PADDR		0xFEC00000
51#define IOAPIC_VERSION		0x11
52
53#define MP_SPECREV		4
54#define MPFP_SIG		"_MP_"
55
56/* Configuration header defines */
57#define MPCH_SIG		"PCMP"
58#define MPCH_OEMID		"BHyVe   "
59#define MPCH_OEMID_LEN          8
60#define MPCH_PRODID             "Hypervisor  "
61#define MPCH_PRODID_LEN         12
62
63/* Processor entry defines */
64#define MPEP_SIG_FAMILY		6	/* XXX bhyve should supply this */
65#define MPEP_SIG_MODEL		26
66#define MPEP_SIG_STEPPING	5
67#define MPEP_SIG		\
68	((MPEP_SIG_FAMILY << 8) | \
69	 (MPEP_SIG_MODEL << 4)	| \
70	 (MPEP_SIG_STEPPING))
71
72#define MPEP_FEATURES           (0xBFEBFBFF) /* XXX Intel i7 */
73
74/* Number of i/o intr entries */
75#define	MPEII_MAX_IRQ		24
76
77/* Bus entry defines */
78#define MPE_NUM_BUSES		2
79#define MPE_BUSNAME_LEN		6
80#define MPE_BUSNAME_ISA		"ISA   "
81#define MPE_BUSNAME_PCI		"PCI   "
82
83static void *oem_tbl_start;
84static int oem_tbl_size;
85
86static uint8_t
87mpt_compute_checksum(void *base, size_t len)
88{
89	uint8_t	*bytes;
90	uint8_t	sum;
91
92	for(bytes = base, sum = 0; len > 0; len--) {
93		sum += *bytes++;
94	}
95
96	return (256 - sum);
97}
98
99static void
100mpt_build_mpfp(mpfps_t mpfp, vm_paddr_t gpa)
101{
102
103	memset(mpfp, 0, sizeof(*mpfp));
104	memcpy(mpfp->signature, MPFP_SIG, 4);
105	mpfp->pap = gpa + sizeof(*mpfp);
106	mpfp->length = 1;
107	mpfp->spec_rev = MP_SPECREV;
108	mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(*mpfp));
109}
110
111static void
112mpt_build_mpch(mpcth_t mpch)
113{
114
115	memset(mpch, 0, sizeof(*mpch));
116	memcpy(mpch->signature, MPCH_SIG, 4);
117	mpch->spec_rev = MP_SPECREV;
118	memcpy(mpch->oem_id, MPCH_OEMID, MPCH_OEMID_LEN);
119	memcpy(mpch->product_id, MPCH_PRODID, MPCH_PRODID_LEN);
120	mpch->apic_address = LAPIC_PADDR;
121}
122
123static void
124mpt_build_proc_entries(proc_entry_ptr mpep, int ncpu)
125{
126	int i;
127
128	for (i = 0; i < ncpu; i++) {
129		memset(mpep, 0, sizeof(*mpep));
130		mpep->type = MPCT_ENTRY_PROCESSOR;
131		mpep->apic_id = i; // XXX
132		mpep->apic_version = LAPIC_VERSION;
133		mpep->cpu_flags = PROCENTRY_FLAG_EN;
134		if (i == 0)
135			mpep->cpu_flags |= PROCENTRY_FLAG_BP;
136		mpep->cpu_signature = MPEP_SIG;
137		mpep->feature_flags = MPEP_FEATURES;
138		mpep++;
139	}
140}
141
142static void
143mpt_build_bus_entries(bus_entry_ptr mpeb)
144{
145
146	memset(mpeb, 0, sizeof(*mpeb));
147	mpeb->type = MPCT_ENTRY_BUS;
148	mpeb->bus_id = 0;
149	memcpy(mpeb->bus_type, MPE_BUSNAME_PCI, MPE_BUSNAME_LEN);
150	mpeb++;
151
152	memset(mpeb, 0, sizeof(*mpeb));
153	mpeb->type = MPCT_ENTRY_BUS;
154	mpeb->bus_id = 1;
155	memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN);
156}
157
158static void
159mpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id)
160{
161
162	memset(mpei, 0, sizeof(*mpei));
163	mpei->type = MPCT_ENTRY_IOAPIC;
164	mpei->apic_id = id;
165	mpei->apic_version = IOAPIC_VERSION;
166	mpei->apic_flags = IOAPICENTRY_FLAG_EN;
167	mpei->apic_address = IOAPIC_PADDR;
168}
169
170static void
171mpt_build_ioint_entries(int_entry_ptr mpie, int num_pins, int id)
172{
173	int pin;
174
175	/*
176	 * The following config is taken from kernel mptable.c
177	 * mptable_parse_default_config_ints(...), for now
178	 * just use the default config, tweek later if needed.
179	 */
180
181	/* Run through all 16 pins. */
182	for (pin = 0; pin < num_pins; pin++) {
183		memset(mpie, 0, sizeof(*mpie));
184		mpie->type = MPCT_ENTRY_INT;
185		mpie->src_bus_id = 1;
186		mpie->dst_apic_id = id;
187
188		/*
189		 * All default configs route IRQs from bus 0 to the first 16
190		 * pins of the first I/O APIC with an APIC ID of 2.
191		 */
192		mpie->dst_apic_int = pin;
193		switch (pin) {
194		case 0:
195			/* Pin 0 is an ExtINT pin. */
196			mpie->int_type = INTENTRY_TYPE_EXTINT;
197			break;
198		case 2:
199			/* IRQ 0 is routed to pin 2. */
200			mpie->int_type = INTENTRY_TYPE_INT;
201			mpie->src_bus_irq = 0;
202			break;
203		case 5:
204		case 10:
205		case 11:
206			/*
207			 * PCI Irqs set to level triggered.
208			 */
209			mpie->int_flags = INTENTRY_FLAGS_TRIGGER_LEVEL;
210			mpie->src_bus_id = 0;
211			/* fall through.. */
212		default:
213			/* All other pins are identity mapped. */
214			mpie->int_type = INTENTRY_TYPE_INT;
215			mpie->src_bus_irq = pin;
216			break;
217		}
218		mpie++;
219	}
220
221}
222
223void
224mptable_add_oemtbl(void *tbl, int tblsz)
225{
226
227	oem_tbl_start = tbl;
228	oem_tbl_size = tblsz;
229}
230
231int
232mptable_build(struct vmctx *ctx, int ncpu)
233{
234	mpcth_t			mpch;
235	bus_entry_ptr		mpeb;
236	io_apic_entry_ptr	mpei;
237	proc_entry_ptr		mpep;
238	mpfps_t			mpfp;
239	int_entry_ptr		mpie;
240	char 			*curraddr;
241	char 			*startaddr;
242
243	startaddr = paddr_guest2host(ctx, MPTABLE_BASE, MPTABLE_MAX_LENGTH);
244	if (startaddr == NULL) {
245		printf("mptable requires mapped mem\n");
246		return (ENOMEM);
247	}
248
249	curraddr = startaddr;
250	mpfp = (mpfps_t)curraddr;
251	mpt_build_mpfp(mpfp, MPTABLE_BASE);
252	curraddr += sizeof(*mpfp);
253
254	mpch = (mpcth_t)curraddr;
255	mpt_build_mpch(mpch);
256	curraddr += sizeof(*mpch);
257
258	mpep = (proc_entry_ptr)curraddr;
259	mpt_build_proc_entries(mpep, ncpu);
260	curraddr += sizeof(*mpep) * ncpu;
261	mpch->entry_count += ncpu;
262
263	mpeb = (bus_entry_ptr) curraddr;
264	mpt_build_bus_entries(mpeb);
265	curraddr += sizeof(*mpeb) * MPE_NUM_BUSES;
266	mpch->entry_count += MPE_NUM_BUSES;
267
268	mpei = (io_apic_entry_ptr)curraddr;
269	mpt_build_ioapic_entries(mpei, 0);
270	curraddr += sizeof(*mpei);
271	mpch->entry_count++;
272
273	mpie = (int_entry_ptr) curraddr;
274	mpt_build_ioint_entries(mpie, MPEII_MAX_IRQ, 0);
275	curraddr += sizeof(*mpie) * MPEII_MAX_IRQ;
276	mpch->entry_count += MPEII_MAX_IRQ;
277
278	if (oem_tbl_start) {
279		mpch->oem_table_pointer = curraddr - startaddr + MPTABLE_BASE;
280		mpch->oem_table_size = oem_tbl_size;
281		memcpy(curraddr, oem_tbl_start, oem_tbl_size);
282	}
283
284	mpch->base_table_length = curraddr - (char *)mpch;
285	mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length);
286
287	return (0);
288}
289