1185743Ssam/*- 2185743Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185743Ssam * All rights reserved. 4185743Ssam * 5185743Ssam * Redistribution and use in source and binary forms, with or without 6185743Ssam * modification, are permitted provided that the following conditions 7185743Ssam * are met: 8185743Ssam * 1. Redistributions of source code must retain the above copyright 9185743Ssam * notice, this list of conditions and the following disclaimer, 10185743Ssam * without modification. 11185743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12185743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13185743Ssam * redistribution must be conditioned upon including a substantially 14185743Ssam * similar Disclaimer requirement for further binary redistribution. 15185743Ssam * 16185743Ssam * NO WARRANTY 17185743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18185743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19185743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20185743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21185743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22185743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23185743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24185743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25185743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26185743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27185743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28185743Ssam * 29185743Ssam * $FreeBSD$ 30185743Ssam */ 31185743Ssam#include "diag.h" 32185743Ssam 33185743Ssam#include "ah.h" 34185743Ssam#include "ah_internal.h" 35185743Ssam#include "ar5416/ar5416reg.h" 36185743Ssam#include "ar5416/ar5416phy.h" 37185743Ssam 38185743Ssam#include "dumpregs.h" 39185743Ssam 40185743Ssam#define N(a) (sizeof(a) / sizeof(a[0])) 41185743Ssam 42237830Sadrian#define MAC5416 SREV(13,8), SREV(0xffff,0xffff) /* XXX */ 43185743Ssam 44185743Ssamstatic struct dumpreg ar5416regs[] = { 45189701Ssam DEFBASIC(AR_CR, "CR"), 46189701Ssam DEFBASIC(AR_RXDP, "RXDP"), 47189701Ssam DEFBASIC(AR_CFG, "CFG"), 48189701Ssam DEFBASIC(AR_MIRT, "MIRT"), 49189701Ssam DEFBASIC(AR_TIMT, "TIMT"), 50189701Ssam DEFBASIC(AR_CST, "CST"), 51189701Ssam DEFBASIC(AR_IER, "IER"), 52189701Ssam DEFBASIC(AR_TXCFG, "TXCFG"), 53189712Ssam DEFBASICfmt(AR_RXCFG, "RXCFG", 54189712Ssam "\20\6JUMBO_ENA\7JUMBO_WRAP\10SLEEP_DEBUG"), 55189701Ssam DEFBASIC(AR_MIBC, "MIBC"), 56189701Ssam DEFBASIC(AR_TOPS, "TOPS"), 57189701Ssam DEFBASIC(AR_RXNPTO, "RXNPTO"), 58189701Ssam DEFBASIC(AR_TXNPTO, "TXNPTO"), 59189701Ssam DEFBASIC(AR_RPGTO, "RPGTO"), 60189701Ssam DEFBASIC(AR_RPCNT, "RPCNT"), 61189701Ssam DEFBASIC(AR_MACMISC, "MACMISC"), 62189701Ssam DEFBASIC(AR_SPC_0, "SPC_0"), 63189701Ssam DEFBASIC(AR_SPC_1, "SPC_1"), 64189701Ssam DEFBASIC(AR_GTXTO, "GTXTO"), 65189701Ssam DEFBASIC(AR_GTTM, "GTTM"), 66185743Ssam 67189712Ssam DEFINTfmt(AR_ISR, "ISR", 68189712Ssam "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC" 69189712Ssam "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM" 70189712Ssam "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS" 71189712Ssam "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"), 72189701Ssam DEFINT(AR_ISR_S0, "ISR_S0"), 73189701Ssam DEFINT(AR_ISR_S1, "ISR_S1"), 74189712Ssam DEFINTfmt(AR_ISR_S2, "ISR_S2", 75189712Ssam "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO" 76189712Ssam "\30CABTO\31DTIM"), 77189701Ssam DEFINT(AR_ISR_S3, "ISR_S3"), 78189701Ssam DEFINT(AR_ISR_S4, "ISR_S4"), 79234015Sadrian DEFINT(AR_ISR_S5, "ISR_S5"), 80189712Ssam DEFINTfmt(AR_IMR, "IMR", 81189712Ssam "\20\1RXOK\2RXDESC\3RXERR\4RXNOPKT\5RXEOL\6RXORN\7TXOK\10TXDESC" 82189712Ssam "\11TXERR\12TXNOPKT\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM" 83189712Ssam "\21SWBA\22BRSSI\23BMISS\24HIUERR\25BNR\26RXCHIRP\27RXDOPPL\30BCNMISS" 84189712Ssam "\31TIM\32GPIO\33QCBROVF\34QCBRURN\35QTRIG"), 85189701Ssam DEFINT(AR_IMR_S0, "IMR_S0"), 86189701Ssam DEFINT(AR_IMR_S1, "IMR_S1"), 87189712Ssam DEFINTfmt(AR_IMR_S2, "IMR_S2", 88189712Ssam "\20\21MCABT\22SSERR\23DPERR\24TIM\25CABEND\26DTIMSYNC\27BCNTO" 89189712Ssam "\30CABTO\31DTIM"), 90189701Ssam DEFINT(AR_IMR_S3, "IMR_S3"), 91189701Ssam DEFINT(AR_IMR_S4, "IMR_S4"), 92185743Ssam /* NB: don't read the RAC so we don't affect operation */ 93189701Ssam DEFVOID(AR_ISR_RAC, "ISR_RAC"), 94189701Ssam DEFINT(AR_ISR_S0_S, "ISR_S0_S"), 95189701Ssam DEFINT(AR_ISR_S1_S, "ISR_S1_S"), 96189701Ssam DEFINT(AR_ISR_S2_S, "ISR_S2_S"), 97189701Ssam DEFINT(AR_ISR_S3_S, "ISR_S3_S"), 98189701Ssam DEFINT(AR_ISR_S4_S, "ISR_S4_S"), 99234015Sadrian DEFINT(AR_ISR_S5_S, "ISR_S5_S"), 100185743Ssam 101189701Ssam DEFBASIC(AR_DMADBG_0, "DMADBG0"), 102189701Ssam DEFBASIC(AR_DMADBG_1, "DMADBG1"), 103189701Ssam DEFBASIC(AR_DMADBG_2, "DMADBG2"), 104189701Ssam DEFBASIC(AR_DMADBG_3, "DMADBG3"), 105189701Ssam DEFBASIC(AR_DMADBG_4, "DMADBG4"), 106189701Ssam DEFBASIC(AR_DMADBG_5, "DMADBG5"), 107189701Ssam DEFBASIC(AR_DMADBG_6, "DMADBG6"), 108189701Ssam DEFBASIC(AR_DMADBG_7, "DMADBG7"), 109185743Ssam 110189701Ssam DEFBASIC(AR_DCM_A, "DCM_A"), 111189701Ssam DEFBASIC(AR_DCM_D, "DCM_D"), 112189701Ssam DEFBASIC(AR_DCCFG, "DCCFG"), 113189701Ssam DEFBASIC(AR_CCFG, "CCFG"), 114189701Ssam DEFBASIC(AR_CCUCFG, "CCUCFG"), 115189701Ssam DEFBASIC(AR_CPC_0, "CPC0"), 116189701Ssam DEFBASIC(AR_CPC_1, "CPC1"), 117189701Ssam DEFBASIC(AR_CPC_2, "CPC2"), 118189701Ssam DEFBASIC(AR_CPC_3, "CPC3"), 119189701Ssam DEFBASIC(AR_CPCOVF, "CPCOVF"), 120185743Ssam 121189701Ssam DEFQCU(AR_Q0_TXDP, "Q0_TXDP"), 122189701Ssam DEFQCU(AR_Q1_TXDP, "Q1_TXDP"), 123189701Ssam DEFQCU(AR_Q2_TXDP, "Q2_TXDP"), 124189701Ssam DEFQCU(AR_Q3_TXDP, "Q3_TXDP"), 125189701Ssam DEFQCU(AR_Q4_TXDP, "Q4_TXDP"), 126189701Ssam DEFQCU(AR_Q5_TXDP, "Q5_TXDP"), 127189701Ssam DEFQCU(AR_Q6_TXDP, "Q6_TXDP"), 128189701Ssam DEFQCU(AR_Q7_TXDP, "Q7_TXDP"), 129189701Ssam DEFQCU(AR_Q8_TXDP, "Q8_TXDP"), 130189701Ssam DEFQCU(AR_Q9_TXDP, "Q9_TXDP"), 131185743Ssam 132189701Ssam DEFQCU(AR_Q_TXE, "Q_TXE"), 133189701Ssam DEFQCU(AR_Q_TXD, "Q_TXD"), 134185743Ssam 135189701Ssam DEFQCU(AR_Q0_CBRCFG, "Q0_CBR"), 136189701Ssam DEFQCU(AR_Q1_CBRCFG, "Q1_CBR"), 137189701Ssam DEFQCU(AR_Q2_CBRCFG, "Q2_CBR"), 138189701Ssam DEFQCU(AR_Q3_CBRCFG, "Q3_CBR"), 139189701Ssam DEFQCU(AR_Q4_CBRCFG, "Q4_CBR"), 140189701Ssam DEFQCU(AR_Q5_CBRCFG, "Q5_CBR"), 141189701Ssam DEFQCU(AR_Q6_CBRCFG, "Q6_CBR"), 142189701Ssam DEFQCU(AR_Q7_CBRCFG, "Q7_CBR"), 143189701Ssam DEFQCU(AR_Q8_CBRCFG, "Q8_CBR"), 144189701Ssam DEFQCU(AR_Q9_CBRCFG, "Q9_CBR"), 145185743Ssam 146189701Ssam DEFQCU(AR_Q0_RDYTIMECFG, "Q0_RDYT"), 147189701Ssam DEFQCU(AR_Q1_RDYTIMECFG, "Q1_RDYT"), 148189701Ssam DEFQCU(AR_Q2_RDYTIMECFG, "Q2_RDYT"), 149189701Ssam DEFQCU(AR_Q3_RDYTIMECFG, "Q3_RDYT"), 150189701Ssam DEFQCU(AR_Q4_RDYTIMECFG, "Q4_RDYT"), 151189701Ssam DEFQCU(AR_Q5_RDYTIMECFG, "Q5_RDYT"), 152189701Ssam DEFQCU(AR_Q6_RDYTIMECFG, "Q6_RDYT"), 153189701Ssam DEFQCU(AR_Q7_RDYTIMECFG, "Q7_RDYT"), 154189701Ssam DEFQCU(AR_Q8_RDYTIMECFG, "Q8_RDYT"), 155189701Ssam DEFQCU(AR_Q9_RDYTIMECFG, "Q9_RDYT"), 156185743Ssam 157189701Ssam DEFQCU(AR_Q_ONESHOTARM_SC, "Q_ONESHOTARM_SC"), 158189701Ssam DEFQCU(AR_Q_ONESHOTARM_CC, "Q_ONESHOTARM_CC"), 159185743Ssam 160189701Ssam DEFQCU(AR_Q0_MISC, "Q0_MISC"), 161189701Ssam DEFQCU(AR_Q1_MISC, "Q1_MISC"), 162189701Ssam DEFQCU(AR_Q2_MISC, "Q2_MISC"), 163189701Ssam DEFQCU(AR_Q3_MISC, "Q3_MISC"), 164189701Ssam DEFQCU(AR_Q4_MISC, "Q4_MISC"), 165189701Ssam DEFQCU(AR_Q5_MISC, "Q5_MISC"), 166189701Ssam DEFQCU(AR_Q6_MISC, "Q6_MISC"), 167189701Ssam DEFQCU(AR_Q7_MISC, "Q7_MISC"), 168189701Ssam DEFQCU(AR_Q8_MISC, "Q8_MISC"), 169189701Ssam DEFQCU(AR_Q9_MISC, "Q9_MISC"), 170185743Ssam 171189701Ssam DEFQCU(AR_Q0_STS, "Q0_STS"), 172189701Ssam DEFQCU(AR_Q1_STS, "Q1_STS"), 173189701Ssam DEFQCU(AR_Q2_STS, "Q2_STS"), 174189701Ssam DEFQCU(AR_Q3_STS, "Q3_STS"), 175189701Ssam DEFQCU(AR_Q4_STS, "Q4_STS"), 176189701Ssam DEFQCU(AR_Q5_STS, "Q5_STS"), 177189701Ssam DEFQCU(AR_Q6_STS, "Q6_STS"), 178189701Ssam DEFQCU(AR_Q7_STS, "Q7_STS"), 179189701Ssam DEFQCU(AR_Q8_STS, "Q8_STS"), 180189701Ssam DEFQCU(AR_Q9_STS, "Q9_STS"), 181185743Ssam 182189701Ssam DEFQCU(AR_Q_RDYTIMESHDN, "Q_RDYTIMSHD"), 183185743Ssam 184189701Ssam DEFQCU(AR_Q_CBBS, "Q_CBBS"), 185189701Ssam DEFQCU(AR_Q_CBBA, "Q_CBBA"), 186189701Ssam DEFQCU(AR_Q_CBC, "Q_CBC"), 187185743Ssam 188189701Ssam DEFDCU(AR_D0_QCUMASK, "D0_MASK"), 189189701Ssam DEFDCU(AR_D1_QCUMASK, "D1_MASK"), 190189701Ssam DEFDCU(AR_D2_QCUMASK, "D2_MASK"), 191189701Ssam DEFDCU(AR_D3_QCUMASK, "D3_MASK"), 192189701Ssam DEFDCU(AR_D4_QCUMASK, "D4_MASK"), 193189701Ssam DEFDCU(AR_D5_QCUMASK, "D5_MASK"), 194189701Ssam DEFDCU(AR_D6_QCUMASK, "D6_MASK"), 195189701Ssam DEFDCU(AR_D7_QCUMASK, "D7_MASK"), 196189701Ssam DEFDCU(AR_D8_QCUMASK, "D8_MASK"), 197189701Ssam DEFDCU(AR_D9_QCUMASK, "D9_MASK"), 198185743Ssam 199189701Ssam DEFDCU(AR_D0_LCL_IFS, "D0_IFS"), 200189701Ssam DEFDCU(AR_D1_LCL_IFS, "D1_IFS"), 201189701Ssam DEFDCU(AR_D2_LCL_IFS, "D2_IFS"), 202189701Ssam DEFDCU(AR_D3_LCL_IFS, "D3_IFS"), 203189701Ssam DEFDCU(AR_D4_LCL_IFS, "D4_IFS"), 204189701Ssam DEFDCU(AR_D5_LCL_IFS, "D5_IFS"), 205189701Ssam DEFDCU(AR_D6_LCL_IFS, "D6_IFS"), 206189701Ssam DEFDCU(AR_D7_LCL_IFS, "D7_IFS"), 207189701Ssam DEFDCU(AR_D8_LCL_IFS, "D8_IFS"), 208189701Ssam DEFDCU(AR_D9_LCL_IFS, "D9_IFS"), 209185743Ssam 210189701Ssam DEFDCU(AR_D0_RETRY_LIMIT, "D0_RTRY"), 211189701Ssam DEFDCU(AR_D1_RETRY_LIMIT, "D1_RTRY"), 212189701Ssam DEFDCU(AR_D2_RETRY_LIMIT, "D2_RTRY"), 213189701Ssam DEFDCU(AR_D3_RETRY_LIMIT, "D3_RTRY"), 214189701Ssam DEFDCU(AR_D4_RETRY_LIMIT, "D4_RTRY"), 215189701Ssam DEFDCU(AR_D5_RETRY_LIMIT, "D5_RTRY"), 216189701Ssam DEFDCU(AR_D6_RETRY_LIMIT, "D6_RTRY"), 217189701Ssam DEFDCU(AR_D7_RETRY_LIMIT, "D7_RTRY"), 218189701Ssam DEFDCU(AR_D8_RETRY_LIMIT, "D8_RTRY"), 219189701Ssam DEFDCU(AR_D9_RETRY_LIMIT, "D9_RTRY"), 220185743Ssam 221189701Ssam DEFDCU(AR_D0_CHNTIME, "D0_CHNT"), 222189701Ssam DEFDCU(AR_D1_CHNTIME, "D1_CHNT"), 223189701Ssam DEFDCU(AR_D2_CHNTIME, "D2_CHNT"), 224189701Ssam DEFDCU(AR_D3_CHNTIME, "D3_CHNT"), 225189701Ssam DEFDCU(AR_D4_CHNTIME, "D4_CHNT"), 226189701Ssam DEFDCU(AR_D5_CHNTIME, "D5_CHNT"), 227189701Ssam DEFDCU(AR_D6_CHNTIME, "D6_CHNT"), 228189701Ssam DEFDCU(AR_D7_CHNTIME, "D7_CHNT"), 229189701Ssam DEFDCU(AR_D8_CHNTIME, "D8_CHNT"), 230189701Ssam DEFDCU(AR_D9_CHNTIME, "D9_CHNT"), 231185743Ssam 232189701Ssam DEFDCU(AR_D0_MISC, "D0_MISC"), 233189701Ssam DEFDCU(AR_D1_MISC, "D1_MISC"), 234189701Ssam DEFDCU(AR_D2_MISC, "D2_MISC"), 235189701Ssam DEFDCU(AR_D3_MISC, "D3_MISC"), 236189701Ssam DEFDCU(AR_D4_MISC, "D4_MISC"), 237189701Ssam DEFDCU(AR_D5_MISC, "D5_MISC"), 238189701Ssam DEFDCU(AR_D6_MISC, "D6_MISC"), 239189701Ssam DEFDCU(AR_D7_MISC, "D7_MISC"), 240189701Ssam DEFDCU(AR_D8_MISC, "D8_MISC"), 241189701Ssam DEFDCU(AR_D9_MISC, "D9_MISC"), 242185743Ssam 243189701Ssam _DEFREG(AR_D_SEQNUM, "D_SEQ", DUMP_BASIC | DUMP_DCU), 244189701Ssam DEFBASIC(AR_D_GBL_IFS_SIFS, "D_SIFS"), 245189701Ssam DEFBASIC(AR_D_GBL_IFS_SLOT, "D_SLOT"), 246189701Ssam DEFBASIC(AR_D_GBL_IFS_EIFS, "D_EIFS"), 247189701Ssam DEFBASIC(AR_D_GBL_IFS_MISC, "D_MISC"), 248189701Ssam DEFBASIC(AR_D_FPCTL, "D_FPCTL"), 249189701Ssam DEFBASIC(AR_D_TXPSE, "D_TXPSE"), 250189701Ssam DEFVOID(AR_D_TXBLK_CMD, "D_CMD"), 251185743Ssam#if 0 252189701Ssam DEFVOID(AR_D_TXBLK_DATA, "D_DATA"), 253185743Ssam#endif 254189701Ssam DEFVOID(AR_D_TXBLK_CLR, "D_CLR"), 255189701Ssam DEFVOID(AR_D_TXBLK_SET, "D_SET"), 256185743Ssam 257189701Ssam DEFBASIC(AR_MAC_LED, "MAC_LED"), 258189712Ssam DEFBASICfmt(AR_RC, "RC", 259189712Ssam "\20\1AHB\2APB\11HOSTIF"), 260189701Ssam DEFBASIC(AR_SCR, "SCR"), 261189701Ssam DEFBASIC(AR_INTPEND, "INTPEND"), 262189701Ssam DEFBASIC(AR_SFR, "SFR"), 263189701Ssam DEFBASIC(AR_PCICFG, "PCICFG"), 264189701Ssam DEFBASIC(AR_SREV, "SREV"), 265185743Ssam 266189701Ssam DEFBASIC(AR_AHB_MODE, "AHBMODE"), 267189701Ssam DEFBASIC(AR_PCIE_PM_CTRL, "PCIEPMC"), 268189701Ssam DEFBASIC(AR5416_PCIE_SERDES,"SERDES"), 269189701Ssam DEFBASIC(AR5416_PCIE_SERDES2, "SERDES2"), 270185743Ssam 271189701Ssam DEFVOID(AR_INTR_SYNC_CAUSE_CLR, "INTR_SYNC_CAUSE_CLR"), 272189701Ssam DEFVOID(AR_INTR_SYNC_CAUSE, "INTR_SYNC_CAUSE"), 273189701Ssam DEFVOID(AR_INTR_SYNC_ENABLE,"INTR_SYNC_ENABLE"), 274189701Ssam DEFBASIC(AR_INTR_ASYNC_MASK,"IASYNCM"), 275189701Ssam DEFBASIC(AR_INTR_SYNC_MASK, "ISYNCM"), 276189701Ssam DEFVOID(AR_INTR_ASYNC_CAUSE,"INTR_ASYNC_CAUSE"), 277189701Ssam DEFVOID(AR_INTR_ASYNC_ENABLE,"INTR_ASYNC_ENABLE"), 278185743Ssam 279189712Ssam DEFBASICfmt(AR_RTC_RC, "RTC_RC", 280189712Ssam "\20\1MAC_WARM\2MAC_COLD"), 281189701Ssam DEFBASIC(AR_RTC_PLL_CONTROL,"RTC_PLL"), 282189701Ssam DEFVOID(AR_RTC_RESET, "RTC_RESET"), 283189712Ssam DEFVOIDfmt(AR_RTC_STATUS, "RTC_STATUS", 284189712Ssam "\20\1SHUTDOWN\2ON\3SLEEP\4WAKEUP\5COLDRESET\6PLLCHANGE"), 285189701Ssam DEFVOID(AR_RTC_SLEEP_CLK, "RTC_SLEEP_CLK"), 286189712Ssam DEFVOIDfmt(AR_RTC_FORCE_WAKE,"RTC_FORCE_WAKE", 287189712Ssam "\20\1EN\2WAKE_ON_INT"), 288189701Ssam DEFVOID(AR_RTC_INTR_CAUSE, "RTC_INTR_CAUSE"), 289189701Ssam DEFVOID(AR_RTC_INTR_MASK, "RTC_INTR_MASK"), 290185743Ssam 291189701Ssam DEFBASIC(AR_GPIO_IN_OUT, "GPIOIO"), 292189701Ssam DEFBASIC(AR_GPIO_OE_OUT, "GPIOOE"), 293189701Ssam DEFBASIC(AR_GPIO_INTR_POL, "GPIOPOL"), 294189701Ssam DEFBASIC(AR_GPIO_INPUT_EN_VAL, "GPIOIEV"), 295189701Ssam DEFBASIC(AR_GPIO_INPUT_MUX1, "GPIMUX1"), 296189701Ssam DEFBASIC(AR_GPIO_INPUT_MUX2, "GPIMUX2"), 297189701Ssam DEFBASIC(AR_GPIO_OUTPUT_MUX1, "GPOMUX1"), 298189701Ssam DEFBASIC(AR_GPIO_OUTPUT_MUX2, "GPOMUX2"), 299189701Ssam DEFBASIC(AR_GPIO_OUTPUT_MUX3, "GPOMUX3"), 300189701Ssam DEFBASIC(AR_OBS, "OBS"), 301189701Ssam DEFVOID(AR_EEPROM_ADDR, "EEADDR"), 302189701Ssam DEFVOID(AR_EEPROM_DATA, "EEDATA"), 303189701Ssam DEFVOID(AR_EEPROM_CMD, "EECMD"), 304189701Ssam DEFVOID(AR_EEPROM_STS, "EESTS"), 305189701Ssam DEFVOID(AR_EEPROM_CFG, "EECFG"), 306189701Ssam DEFBASIC(AR_STA_ID0, "STA_ID0"), 307189712Ssam DEFBASICfmt(AR_STA_ID1, "STA_ID1", 308189712Ssam "\20\21AP\22ADHOC\23PWR_SAV\24KSRCHDIS\25PCF\26USE_DEFANT" 309189712Ssam "\27UPD_DEFANT\30RTS_USE_DEF\31ACKCTS_6MB\32BASE_RATE_11B" 310189712Ssam "\33USE_DA_SG\34CRPT_MIC_ENABLE\35KSRCH_MODE\36PRE_SEQNUM" 311189712Ssam "\37CBCIV_ENDIAN\40MCAST_KSRC"), 312189701Ssam DEFBASIC(AR_BSS_ID0, "BSS_ID0"), 313189701Ssam DEFBASIC(AR_BSS_ID1, "BSS_ID1"), 314189701Ssam DEFBASIC(AR_SLOT_TIME, "SLOTTIME"), 315189701Ssam DEFBASIC(AR_TIME_OUT, "TIME_OUT"), 316189701Ssam DEFBASIC(AR_RSSI_THR, "RSSI_THR"), 317189701Ssam DEFBASIC(AR_USEC, "USEC"), 318189701Ssam DEFBASIC(AR_BEACON, "BEACON"), 319189701Ssam DEFBASIC(AR_CFP_PERIOD, "CFP_PER"), 320189701Ssam DEFBASIC(AR_TIMER0, "TIMER0"), 321189701Ssam DEFBASIC(AR_TIMER1, "TIMER1"), 322189701Ssam DEFBASIC(AR_TIMER2, "TIMER2"), 323189701Ssam DEFBASIC(AR_TIMER3, "TIMER3"), 324189701Ssam DEFBASIC(AR_CFP_DUR, "CFP_DUR"), 325189701Ssam DEFBASIC(AR_RX_FILTER, "RXFILTER"), 326189701Ssam DEFBASIC(AR_MCAST_FIL0, "MCAST_0"), 327189701Ssam DEFBASIC(AR_MCAST_FIL1, "MCAST_1"), 328189712Ssam DEFBASICfmt(AR_DIAG_SW, "DIAG_SW", 329189712Ssam "\20\1CACHE_ACK\2ACK_DIS\3CTS_DIS\4ENCRYPT_DIS\5DECRYPT_DIS\6RX_DIS" 330189712Ssam "\7CORR_FCS\10CHAN_INFO\11EN_SCRAMSD\22FRAME_NV0\25RX_CLR_HI" 331189712Ssam "\26IGNORE_CS\27CHAN_IDLE\30PHEAR_ME"), 332189701Ssam DEFBASIC(AR_TSF_L32, "TSF_L32"), 333189701Ssam DEFBASIC(AR_TSF_U32, "TSF_U32"), 334189701Ssam DEFBASIC(AR_TST_ADDAC, "TST_ADAC"), 335189701Ssam DEFBASIC(AR_DEF_ANTENNA, "DEF_ANT"), 336189701Ssam DEFBASIC(AR_QOS_MASK, "QOS_MASK"), 337189701Ssam DEFBASIC(AR_SEQ_MASK, "SEQ_MASK"), 338189701Ssam DEFBASIC(AR_OBSERV_2, "OBSERV2"), 339189701Ssam DEFBASIC(AR_OBSERV_1, "OBSERV1"), 340185743Ssam 341189701Ssam DEFBASIC(AR_LAST_TSTP, "LAST_TST"), 342189701Ssam DEFBASIC(AR_NAV, "NAV"), 343189701Ssam DEFBASIC(AR_RTS_OK, "RTS_OK"), 344189701Ssam DEFBASIC(AR_RTS_FAIL, "RTS_FAIL"), 345189701Ssam DEFBASIC(AR_ACK_FAIL, "ACK_FAIL"), 346189701Ssam DEFBASIC(AR_FCS_FAIL, "FCS_FAIL"), 347189701Ssam DEFBASIC(AR_BEACON_CNT, "BEAC_CNT"), 348185743Ssam 349189701Ssam DEFBASIC(AR_SLEEP1, "SLEEP1"), 350189701Ssam DEFBASIC(AR_SLEEP2, "SLEEP2"), 351189701Ssam DEFBASIC(AR_SLEEP3, "SLEEP3"), 352189701Ssam DEFBASIC(AR_BSSMSKL, "BSSMSKL"), 353189701Ssam DEFBASIC(AR_BSSMSKU, "BSSMSKU"), 354189701Ssam DEFBASIC(AR_TPC, "TPC"), 355189701Ssam DEFBASIC(AR_TFCNT, "TFCNT"), 356189701Ssam DEFBASIC(AR_RFCNT, "RFCNT"), 357189701Ssam DEFBASIC(AR_RCCNT, "RCCNT"), 358189701Ssam DEFBASIC(AR_CCCNT, "CCCNT"), 359189701Ssam DEFBASIC(AR_QUIET1, "QUIET1"), 360189701Ssam DEFBASIC(AR_QUIET2, "QUIET2"), 361189701Ssam DEFBASIC(AR_TSF_PARM, "TSF_PARM"), 362189701Ssam DEFBASIC(AR_NOACK, "NOACK"), 363189701Ssam DEFBASIC(AR_PHY_ERR, "PHY_ERR"), 364189701Ssam DEFBASIC(AR_QOS_CONTROL, "QOS_CTRL"), 365189701Ssam DEFBASIC(AR_QOS_SELECT, "QOS_SEL"), 366189701Ssam DEFBASIC(AR_MISC_MODE, "MISCMODE"), 367189701Ssam DEFBASIC(AR_FILTOFDM, "FILTOFDM"), 368189701Ssam DEFBASIC(AR_FILTCCK, "FILTCCK"), 369189701Ssam DEFBASIC(AR_PHYCNT1, "PHYCNT1"), 370189701Ssam DEFBASIC(AR_PHYCNTMASK1, "PHYCMSK1"), 371189701Ssam DEFBASIC(AR_PHYCNT2, "PHYCNT2"), 372189701Ssam DEFBASIC(AR_PHYCNTMASK2, "PHYCMSK2"), 373185743Ssam 374189701Ssam DEFBASIC(AR_TXOP_X, "TXOPX"), 375189701Ssam DEFBASIC(AR_NEXT_TBTT, "NXTTBTT"), 376189701Ssam DEFBASIC(AR_NEXT_DBA, "NXTDBA"), 377189701Ssam DEFBASIC(AR_NEXT_SWBA, "NXTSWBA"), 378189701Ssam DEFBASIC(AR_NEXT_CFP, "NXTCFP"), 379189701Ssam DEFBASIC(AR_NEXT_HCF, "NXTHCF"), 380189701Ssam DEFBASIC(AR_NEXT_DTIM, "NXTDTIM"), 381189701Ssam DEFBASIC(AR_NEXT_QUIET, "NXTQUIET"), 382189701Ssam DEFBASIC(AR_NEXT_NDP, "NXTNDP"), 383189701Ssam DEFBASIC(AR5416_BEACON_PERIOD, "BCNPER"), 384189701Ssam DEFBASIC(AR_DBA_PERIOD, "DBAPER"), 385189701Ssam DEFBASIC(AR_SWBA_PERIOD, "SWBAPER"), 386189701Ssam DEFBASIC(AR_TIM_PERIOD, "TIMPER"), 387189701Ssam DEFBASIC(AR_DTIM_PERIOD, "DTIMPER"), 388189701Ssam DEFBASIC(AR_QUIET_PERIOD, "QUIETPER"), 389189701Ssam DEFBASIC(AR_NDP_PERIOD, "NDPPER"), 390189701Ssam DEFBASIC(AR_TIMER_MODE, "TIMERMOD"), 391189701Ssam DEFBASIC(AR_2040_MODE, "2040MODE"), 392189701Ssam DEFBASIC(AR_PCU_TXBUF_CTRL, "PCUTXBUF"), 393189701Ssam DEFBASIC(AR_SLP32_MODE, "SLP32MOD"), 394189701Ssam DEFBASIC(AR_SLP32_WAKE, "SLP32WAK"), 395189701Ssam DEFBASIC(AR_SLP32_INC, "SLP32INC"), 396189701Ssam DEFBASIC(AR_SLP_CNT, "SLPCNT"), 397189701Ssam DEFBASIC(AR_SLP_MIB_CTRL, "SLPMIB"), 398189701Ssam DEFBASIC(AR_EXTRCCNT, "EXTRCCNT"), 399206848Srpaulo DEFBASIC(AR_PHY_TURBO, "PHYTURBO"), 400189701Ssam 401189712Ssam DEFVOID(AR_PHY_ADC_SERIAL_CTL, "PHY_ADC_SERIAL_CTL"), 402189712Ssam 403185743Ssam /* XXX { AR_RATE_DURATION(0), AR_RATE_DURATION(0x20) }, */ 404185743Ssam}; 405185743Ssam 406185743Ssamstatic __constructor void 407185743Ssamar5416_ctor(void) 408185743Ssam{ 409185743Ssam register_regs(ar5416regs, N(ar5416regs), MAC5416, PHYANY); 410185743Ssam register_keycache(128, MAC5416, PHYANY); 411185743Ssam 412185743Ssam register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5416, PHYANY); 413185743Ssam register_range(0x9900, 0x997c, DUMP_BASEBAND, MAC5416, PHYANY); 414185743Ssam register_range(0x99a4, 0x99a4, DUMP_BASEBAND, MAC5416, PHYANY); 415185743Ssam register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5416, PHYANY); 416185743Ssam register_range(0xa180, 0xa238, DUMP_BASEBAND, MAC5416, PHYANY); 417185743Ssam register_range(0xa258, 0xa26c, DUMP_BASEBAND, MAC5416, PHYANY); 418185743Ssam register_range(0xa3c8, 0xa3d4, DUMP_BASEBAND, MAC5416, PHYANY); 419185743Ssam register_range(0xa864, 0xa864, DUMP_BASEBAND, MAC5416, PHYANY); 420185743Ssam register_range(0xa9bc, 0xa9bc, DUMP_BASEBAND, MAC5416, PHYANY); 421185743Ssam register_range(0xb864, 0xb864, DUMP_BASEBAND, MAC5416, PHYANY); 422185743Ssam register_range(0xb9bc, 0xb9bc, DUMP_BASEBAND, MAC5416, PHYANY); 423185743Ssam} 424