sbus.c revision 109623
1/*- 2 * Copyright (c) 1998 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Kranenburg. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/* 37 * Copyright (c) 1992, 1993 38 * The Regents of the University of California. All rights reserved. 39 * 40 * This software was developed by the Computer Systems Engineering group 41 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 42 * contributed to Berkeley. 43 * 44 * All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the University of 47 * California, Lawrence Berkeley Laboratory. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 3. All advertising materials mentioning features or use of this software 58 * must display the following acknowledgement: 59 * This product includes software developed by the University of 60 * California, Berkeley and its contributors. 61 * 4. Neither the name of the University nor the names of its contributors 62 * may be used to endorse or promote products derived from this software 63 * without specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 66 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 69 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 70 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 71 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 72 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 73 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 74 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 75 * SUCH DAMAGE. 76 */ 77/* 78 * Copyright (c) 1999 Eduardo Horvath 79 * Copyright (c) 2002 by Thomas Moestl <tmm@FreeBSD.org>. 80 * All rights reserved. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 88 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 89 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 91 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 94 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 95 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 96 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 97 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 98 * SUCH DAMAGE. 99 * 100 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 101 * from: NetBSD: sbus.c,v 1.46 2001/10/07 20:30:41 eeh Exp 102 * 103 * $FreeBSD: head/sys/sparc64/sbus/sbus.c 109623 2003-01-21 08:56:16Z alfred $ 104 */ 105 106/* 107 * Sbus support. 108 */ 109#include <sys/param.h> 110#include <sys/systm.h> 111#include <sys/bus.h> 112#include <sys/kernel.h> 113#include <sys/malloc.h> 114#include <sys/pcpu.h> 115#include <sys/reboot.h> 116 117#include <ofw/openfirm.h> 118 119#include <machine/bus.h> 120#include <machine/iommureg.h> 121#include <machine/bus_common.h> 122#include <machine/frame.h> 123#include <machine/intr_machdep.h> 124#include <machine/nexusvar.h> 125#include <machine/ofw_upa.h> 126#include <machine/resource.h> 127 128#include <sys/rman.h> 129 130#include <machine/iommuvar.h> 131 132#include <sparc64/sbus/ofw_sbus.h> 133#include <sparc64/sbus/sbusreg.h> 134#include <sparc64/sbus/sbusvar.h> 135 136 137#ifdef DEBUG 138#define SDB_DVMA 0x1 139#define SDB_INTR 0x2 140int sbus_debug = 0; 141#define DPRINTF(l, s) do { if (sbus_debug & l) printf s; } while (0) 142#else 143#define DPRINTF(l, s) 144#endif 145 146struct sbus_devinfo { 147 int sdi_burstsz; 148 char *sdi_compat; 149 char *sdi_name; /* PROM name */ 150 phandle_t sdi_node; /* PROM node */ 151 int sdi_slot; 152 char *sdi_type; /* PROM name */ 153 154 struct resource_list sdi_rl; 155}; 156 157/* Range descriptor, allocated for each sc_range. */ 158struct sbus_rd { 159 bus_addr_t rd_poffset; 160 bus_addr_t rd_pend; 161 int rd_slot; 162 bus_addr_t rd_coffset; 163 bus_addr_t rd_cend; 164 struct rman rd_rman; 165 bus_space_handle_t rd_bushandle; 166 struct resource *rd_res; 167}; 168 169struct sbus_softc { 170 bus_space_tag_t sc_bustag; 171 bus_space_handle_t sc_bushandle; 172 bus_dma_tag_t sc_dmatag; 173 bus_dma_tag_t sc_cdmatag; 174 bus_space_tag_t sc_cbustag; 175 int sc_clockfreq; /* clock frequency (in Hz) */ 176 struct upa_regs *sc_reg; 177 int sc_nreg; 178 int sc_nrange; 179 struct sbus_rd *sc_rd; 180 int sc_burst; /* burst transfer sizes supported */ 181 int *sc_intr_compat;/* `intr' property to sbus compat */ 182 183 struct resource *sc_sysio_res; 184 int sc_ign; /* Interrupt group number for this sysio */ 185 struct iommu_state sc_is; /* IOMMU state, see iommureg.h */ 186 187 struct resource *sc_ot_ires; 188 void *sc_ot_ihand; 189 struct resource *sc_pf_ires; 190 void *sc_pf_ihand; 191}; 192 193struct sbus_clr { 194 struct sbus_softc *scl_sc; 195 bus_addr_t scl_clr; /* clear register */ 196 driver_intr_t *scl_handler; /* handler to call */ 197 void *scl_arg; /* argument for the handler */ 198 void *scl_cookie; /* interrupt cookie of parent bus */ 199}; 200 201#define SYSIO_READ8(sc, off) \ 202 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 203#define SYSIO_WRITE8(sc, off, v) \ 204 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 205 206static int sbus_probe(device_t dev); 207static int sbus_print_child(device_t dev, device_t child); 208static void sbus_probe_nomatch(device_t dev, device_t child); 209static int sbus_read_ivar(device_t, device_t, int, u_long *); 210static struct resource_list *sbus_get_resource_list(device_t dev, 211 device_t child); 212static int sbus_setup_intr(device_t, device_t, struct resource *, int, 213 driver_intr_t *, void *, void **); 214static int sbus_teardown_intr(device_t, device_t, struct resource *, void *); 215static struct resource *sbus_alloc_resource(device_t, device_t, int, int *, 216 u_long, u_long, u_long, u_int); 217static int sbus_activate_resource(device_t, device_t, int, int, 218 struct resource *); 219static int sbus_deactivate_resource(device_t, device_t, int, int, 220 struct resource *); 221static int sbus_release_resource(device_t, device_t, int, int, 222 struct resource *); 223 224static struct sbus_devinfo * sbus_setup_dinfo(struct sbus_softc *sc, 225 phandle_t node, char *name); 226static void sbus_destroy_dinfo(struct sbus_devinfo *dinfo); 227static void sbus_intr_stub(void *); 228static bus_space_tag_t sbus_alloc_bustag(struct sbus_softc *); 229static void sbus_overtemp(void *); 230static void sbus_pwrfail(void *); 231 232/* 233 * DVMA routines 234 */ 235static int sbus_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 236 bus_dmamap_t *); 237static int sbus_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 238static int sbus_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, void *, 239 bus_size_t, bus_dmamap_callback_t *, void *, int); 240static int sbus_dmamap_load_mbuf(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 241 struct mbuf *, bus_dmamap_callback2_t *, void *, int); 242static int sbus_dmamap_load_uio(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 243 struct uio *, bus_dmamap_callback2_t *, void *, int); 244static void sbus_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 245static void sbus_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 246 bus_dmasync_op_t); 247static int sbus_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 248 bus_dmamap_t *); 249static void sbus_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 250 bus_dmamap_t); 251 252static device_method_t sbus_methods[] = { 253 /* Device interface */ 254 DEVMETHOD(device_probe, sbus_probe), 255 DEVMETHOD(device_attach, bus_generic_attach), 256 257 /* Bus interface */ 258 DEVMETHOD(bus_print_child, sbus_print_child), 259 DEVMETHOD(bus_probe_nomatch, sbus_probe_nomatch), 260 DEVMETHOD(bus_read_ivar, sbus_read_ivar), 261 DEVMETHOD(bus_setup_intr, sbus_setup_intr), 262 DEVMETHOD(bus_teardown_intr, sbus_teardown_intr), 263 DEVMETHOD(bus_alloc_resource, sbus_alloc_resource), 264 DEVMETHOD(bus_activate_resource, sbus_activate_resource), 265 DEVMETHOD(bus_deactivate_resource, sbus_deactivate_resource), 266 DEVMETHOD(bus_release_resource, sbus_release_resource), 267 DEVMETHOD(bus_get_resource_list, sbus_get_resource_list), 268 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 269 270 { 0, 0 } 271}; 272 273static driver_t sbus_driver = { 274 "sbus", 275 sbus_methods, 276 sizeof(struct sbus_softc), 277}; 278 279static devclass_t sbus_devclass; 280 281DRIVER_MODULE(sbus, nexus, sbus_driver, sbus_devclass, 0, 0); 282 283#define OFW_SBUS_TYPE "sbus" 284#define OFW_SBUS_NAME "sbus" 285 286static int 287sbus_probe(device_t dev) 288{ 289 struct sbus_softc *sc = device_get_softc(dev); 290 struct sbus_devinfo *sdi; 291 struct sbus_ranges *range; 292 struct resource *res; 293 device_t cdev; 294 bus_addr_t phys; 295 bus_size_t size; 296 char *name, *cname, *t; 297 phandle_t child, node = nexus_get_node(dev); 298 u_int64_t mr; 299 int intr, clock, rid, vec, i; 300 301 t = nexus_get_device_type(dev); 302 if (((t == NULL || strcmp(t, OFW_SBUS_TYPE) != 0)) && 303 strcmp(nexus_get_name(dev), OFW_SBUS_NAME) != 0) 304 return (ENXIO); 305 device_set_desc(dev, "U2S UPA-SBus bridge"); 306 307 if ((sc->sc_nreg = OF_getprop_alloc(node, "reg", sizeof(*sc->sc_reg), 308 (void **)&sc->sc_reg)) == -1) { 309 panic("sbus_probe: error getting reg property"); 310 } 311 if (sc->sc_nreg < 1) 312 panic("sbus_probe: bogus properties"); 313 phys = UPA_REG_PHYS(&sc->sc_reg[0]); 314 size = UPA_REG_SIZE(&sc->sc_reg[0]); 315 rid = 0; 316 sc->sc_sysio_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys, 317 phys + size - 1, size, RF_ACTIVE); 318 if (sc->sc_sysio_res == NULL || 319 rman_get_start(sc->sc_sysio_res) != phys) 320 panic("sbus_probe: can't allocate device memory"); 321 sc->sc_bustag = rman_get_bustag(sc->sc_sysio_res); 322 sc->sc_bushandle = rman_get_bushandle(sc->sc_sysio_res); 323 324 if (OF_getprop(node, "interrupts", &intr, sizeof(intr)) == -1) 325 panic("sbus_probe: cannot get IGN"); 326 sc->sc_ign = intr & INTMAP_IGN_MASK; /* Find interrupt group no */ 327 sc->sc_cbustag = sbus_alloc_bustag(sc); 328 329 /* 330 * Record clock frequency for synchronous SCSI. 331 * IS THIS THE CORRECT DEFAULT?? 332 */ 333 if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) == -1) 334 clock = 25000000; 335 sc->sc_clockfreq = clock; 336 clock /= 1000; 337 device_printf(dev, "clock %d.%03d MHz\n", clock / 1000, clock % 1000); 338 339 sc->sc_dmatag = nexus_get_dmatag(dev); 340 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 341 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_cdmatag) != 0) 342 panic("bus_dma_tag_create failed"); 343 /* Customize the tag */ 344 sc->sc_cdmatag->dt_cookie = sc; 345 sc->sc_cdmatag->dt_dmamap_create = sbus_dmamap_create; 346 sc->sc_cdmatag->dt_dmamap_destroy = sbus_dmamap_destroy; 347 sc->sc_cdmatag->dt_dmamap_load = sbus_dmamap_load; 348 sc->sc_cdmatag->dt_dmamap_load_mbuf = sbus_dmamap_load_mbuf; 349 sc->sc_cdmatag->dt_dmamap_load_uio = sbus_dmamap_load_uio; 350 sc->sc_cdmatag->dt_dmamap_unload = sbus_dmamap_unload; 351 sc->sc_cdmatag->dt_dmamap_sync = sbus_dmamap_sync; 352 sc->sc_cdmatag->dt_dmamem_alloc = sbus_dmamem_alloc; 353 sc->sc_cdmatag->dt_dmamem_free = sbus_dmamem_free; 354 /* XXX: register as root dma tag (kluge). */ 355 sparc64_root_dma_tag = sc->sc_cdmatag; 356 357 /* 358 * Collect address translations from the OBP. 359 */ 360 if ((sc->sc_nrange = OF_getprop_alloc(node, "ranges", 361 sizeof(*range), (void **)&range)) == -1) { 362 panic("%s: error getting ranges property", 363 device_get_name(dev)); 364 } 365 sc->sc_rd = (struct sbus_rd *)malloc(sizeof(*sc->sc_rd) * sc->sc_nrange, 366 M_DEVBUF, M_NOWAIT); 367 if (sc->sc_rd == NULL) 368 panic("sbus_probe: could not allocate rmans"); 369 /* 370 * Preallocate all space that the SBus bridge decodes, so that nothing 371 * else gets in the way; set up rmans etc. 372 */ 373 for (i = 0; i < sc->sc_nrange; i++) { 374 phys = range[i].poffset | ((bus_addr_t)range[i].pspace << 32); 375 size = range[i].size; 376 sc->sc_rd[i].rd_slot = range[i].cspace; 377 sc->sc_rd[i].rd_coffset = range[i].coffset; 378 sc->sc_rd[i].rd_cend = sc->sc_rd[i].rd_coffset + size; 379 rid = 0; 380 if ((res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys, 381 phys + size - 1, size, RF_ACTIVE)) == NULL) 382 panic("sbus_probe: could not allocate decoded range"); 383 sc->sc_rd[i].rd_bushandle = rman_get_bushandle(res); 384 sc->sc_rd[i].rd_rman.rm_type = RMAN_ARRAY; 385 sc->sc_rd[i].rd_rman.rm_descr = "SBus Device Memory"; 386 if (rman_init(&sc->sc_rd[i].rd_rman) != 0 || 387 rman_manage_region(&sc->sc_rd[i].rd_rman, 0, size) != 0) 388 panic("sbus_probe: failed to set up memory rman"); 389 sc->sc_rd[i].rd_poffset = phys; 390 sc->sc_rd[i].rd_pend = phys + size; 391 sc->sc_rd[i].rd_res = res; 392 } 393 free(range, M_OFWPROP); 394 395 /* 396 * Get the SBus burst transfer size if burst transfers are supported. 397 * XXX: is the default correct? 398 */ 399 if (OF_getprop(node, "burst-sizes", &sc->sc_burst, 400 sizeof(sc->sc_burst)) == -1 || sc->sc_burst == 0) 401 sc->sc_burst = SBUS_BURST_DEF; 402 403 /* initalise the IOMMU */ 404 405 /* punch in our copies */ 406 sc->sc_is.is_bustag = sc->sc_bustag; 407 sc->sc_is.is_bushandle = sc->sc_bushandle; 408 sc->sc_is.is_iommu = SBR_IOMMU; 409 sc->sc_is.is_dtag = SBR_IOMMU_TLB_TAG_DIAG; 410 sc->sc_is.is_ddram = SBR_IOMMU_TLB_DATA_DIAG; 411 sc->sc_is.is_dqueue = SBR_IOMMU_QUEUE_DIAG; 412 sc->sc_is.is_dva = SBR_IOMMU_SVADIAG; 413 sc->sc_is.is_dtcmp = 0; 414 sc->sc_is.is_sb[0] = SBR_STRBUF; 415 sc->sc_is.is_sb[1] = NULL; 416 417 /* give us a nice name.. */ 418 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 419 if (name == 0) 420 panic("sbus_probe: couldn't malloc iommu name"); 421 snprintf(name, 32, "%s dvma", device_get_name(dev)); 422 423 /* 424 * Note: the SBus IOMMU ignores the high bits of an address, so a NULL 425 * DMA pointer will be translated by the first page of the IOTSB. 426 * To detect bugs we'll allocate and ignore the first entry. 427 */ 428 iommu_init(name, &sc->sc_is, 2, -1, 1); 429 430 /* Enable the over-temperature and power-fail intrrupts. */ 431 rid = 0; 432 mr = SYSIO_READ8(sc, SBR_THERM_INT_MAP); 433 vec = INTVEC(mr); 434 if ((sc->sc_ot_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec, 435 vec, 1, RF_ACTIVE)) == NULL) 436 panic("sbus_probe: failed to get temperature interrupt"); 437 bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_FAST, 438 sbus_overtemp, sc, &sc->sc_ot_ihand); 439 SYSIO_WRITE8(sc, SBR_THERM_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid))); 440 rid = 0; 441 mr = SYSIO_READ8(sc, SBR_POWER_INT_MAP); 442 vec = INTVEC(mr); 443 if ((sc->sc_pf_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec, 444 vec, 1, RF_ACTIVE)) == NULL) 445 panic("sbus_probe: failed to get power fail interrupt"); 446 bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_FAST, 447 sbus_pwrfail, sc, &sc->sc_pf_ihand); 448 SYSIO_WRITE8(sc, SBR_POWER_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid))); 449 450 /* Initialize the counter-timer. */ 451 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, SBR_TC0); 452 453 /* 454 * Loop through ROM children, fixing any relative addresses 455 * and then configuring each device. 456 * `specials' is an array of device names that are treated 457 * specially: 458 */ 459 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 460 if ((OF_getprop_alloc(child, "name", 1, (void **)&cname)) == -1) 461 continue; 462 463 if ((sdi = sbus_setup_dinfo(sc, child, cname)) == NULL) { 464 device_printf(dev, "<%s>: incomplete\n", cname); 465 free(cname, M_OFWPROP); 466 continue; 467 } 468 if ((cdev = device_add_child(dev, NULL, -1)) == NULL) 469 panic("sbus_probe: device_add_child failed"); 470 device_set_ivars(cdev, sdi); 471 } 472 return (0); 473} 474 475static struct sbus_devinfo * 476sbus_setup_dinfo(struct sbus_softc *sc, phandle_t node, char *name) 477{ 478 struct sbus_devinfo *sdi; 479 struct sbus_regs *reg; 480 u_int32_t base, iv, *intr; 481 int i, nreg, nintr, slot, rslot; 482 483 sdi = malloc(sizeof(*sdi), M_DEVBUF, M_ZERO); 484 if (sdi == NULL) 485 return (NULL); 486 resource_list_init(&sdi->sdi_rl); 487 sdi->sdi_name = name; 488 sdi->sdi_node = node; 489 OF_getprop_alloc(node, "compat", 1, (void **)&sdi->sdi_compat); 490 OF_getprop_alloc(node, "device_type", 1, (void **)&sdi->sdi_type); 491 slot = -1; 492 nreg = OF_getprop_alloc(node, "reg", sizeof(*reg), (void **)®); 493 if (nreg == -1) { 494 if (sdi->sdi_type == NULL || 495 strcmp(sdi->sdi_type, "hierarchical") != 0) { 496 sbus_destroy_dinfo(sdi); 497 return (NULL); 498 } 499 } else { 500 for (i = 0; i < nreg; i++) { 501 base = reg[i].sbr_offset; 502 if (SBUS_ABS(base)) { 503 rslot = SBUS_ABS_TO_SLOT(base); 504 base = SBUS_ABS_TO_OFFSET(base); 505 } else 506 rslot = reg[i].sbr_slot; 507 if (slot != -1 && slot != rslot) 508 panic("sbus_setup_dinfo: multiple slots"); 509 slot = rslot; 510 511 resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY, i, 512 base, base + reg[i].sbr_size, reg[i].sbr_size); 513 } 514 free(reg, M_OFWPROP); 515 } 516 sdi->sdi_slot = slot; 517 518 /* 519 * The `interrupts' property contains the Sbus interrupt level. 520 */ 521 nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intr), (void **)&intr); 522 if (nintr != -1) { 523 for (i = 0; i < nintr; i++) { 524 iv = intr[i]; 525 /* 526 * Sbus card devices need the slot number encoded into 527 * the vector as this is generally not done. 528 */ 529 if ((iv & INTMAP_OBIO_MASK) == 0) 530 iv |= slot << 3; 531 /* Set the ign as appropriate. */ 532 iv |= sc->sc_ign; 533 resource_list_add(&sdi->sdi_rl, SYS_RES_IRQ, i, 534 iv, iv, 1); 535 } 536 free(intr, M_OFWPROP); 537 } 538 if (OF_getprop(node, "burst-sizes", &sdi->sdi_burstsz, 539 sizeof(sdi->sdi_burstsz)) == -1) 540 sdi->sdi_burstsz = sc->sc_burst; 541 else 542 sdi->sdi_burstsz &= sc->sc_burst; 543 544 return (sdi); 545} 546 547/* Free everything except sdi_name, which is handled separately. */ 548static void 549sbus_destroy_dinfo(struct sbus_devinfo *dinfo) 550{ 551 552 resource_list_free(&dinfo->sdi_rl); 553 if (dinfo->sdi_compat != NULL) 554 free(dinfo->sdi_compat, M_OFWPROP); 555 if (dinfo->sdi_type != NULL) 556 free(dinfo->sdi_type, M_OFWPROP); 557 free(dinfo, M_DEVBUF); 558} 559 560static int 561sbus_print_child(device_t dev, device_t child) 562{ 563 struct sbus_devinfo *dinfo; 564 struct resource_list *rl; 565 int rv; 566 567 dinfo = device_get_ivars(child); 568 rl = &dinfo->sdi_rl; 569 rv = bus_print_child_header(dev, child); 570 rv += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 571 rv += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 572 rv += bus_print_child_footer(dev, child); 573 return (rv); 574} 575 576static void 577sbus_probe_nomatch(device_t dev, device_t child) 578{ 579 char *name; 580 char *type; 581 582 if (BUS_READ_IVAR(dev, child, SBUS_IVAR_NAME, 583 (uintptr_t *)&name) != 0 || 584 BUS_READ_IVAR(dev, child, SBUS_IVAR_DEVICE_TYPE, 585 (uintptr_t *)&type) != 0) 586 return; 587 588 if (type == NULL) 589 type = "(unknown)"; 590 device_printf(dev, "<%s>, type %s (no driver attached)\n", 591 name, type); 592} 593 594static int 595sbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 596{ 597 struct sbus_softc *sc = device_get_softc(dev); 598 struct sbus_devinfo *dinfo; 599 600 if ((dinfo = device_get_ivars(child)) == NULL) 601 return (ENOENT); 602 switch (which) { 603 case SBUS_IVAR_BURSTSZ: 604 *result = dinfo->sdi_burstsz; 605 break; 606 case SBUS_IVAR_CLOCKFREQ: 607 *result = sc->sc_clockfreq; 608 break; 609 case SBUS_IVAR_COMPAT: 610 *result = (uintptr_t)dinfo->sdi_compat; 611 break; 612 case SBUS_IVAR_NAME: 613 *result = (uintptr_t)dinfo->sdi_name; 614 break; 615 case SBUS_IVAR_NODE: 616 *result = dinfo->sdi_node; 617 break; 618 case SBUS_IVAR_SLOT: 619 *result = dinfo->sdi_slot; 620 break; 621 case SBUS_IVAR_DEVICE_TYPE: 622 *result = (uintptr_t)dinfo->sdi_type; 623 break; 624 default: 625 return (ENOENT); 626 } 627 return 0; 628} 629 630static struct resource_list * 631sbus_get_resource_list(device_t dev, device_t child) 632{ 633 struct sbus_devinfo *sdi; 634 635 sdi = device_get_ivars(child); 636 return (&sdi->sdi_rl); 637} 638 639/* Write to the correct clr register, and call the actual handler. */ 640static void 641sbus_intr_stub(void *arg) 642{ 643 struct sbus_clr *scl; 644 645 scl = (struct sbus_clr *)arg; 646 scl->scl_handler(scl->scl_arg); 647 SYSIO_WRITE8(scl->scl_sc, scl->scl_clr, 0); 648} 649 650static int 651sbus_setup_intr(device_t dev, device_t child, 652 struct resource *ires, int flags, driver_intr_t *intr, void *arg, 653 void **cookiep) 654{ 655 struct sbus_softc *sc; 656 struct sbus_clr *scl; 657 bus_addr_t intrmapptr, intrclrptr, intrptr; 658 u_int64_t intrmap; 659 u_int32_t inr, slot; 660 int error, i; 661 long vec = rman_get_start(ires); 662 663 sc = (struct sbus_softc *)device_get_softc(dev); 664 scl = (struct sbus_clr *)malloc(sizeof(*scl), M_DEVBUF, M_NOWAIT); 665 if (scl == NULL) 666 return (NULL); 667 intrptr = intrmapptr = intrclrptr = 0; 668 intrmap = 0; 669 inr = INTVEC(vec); 670 if ((inr & INTMAP_OBIO_MASK) == 0) { 671 /* 672 * We're in an SBUS slot, register the map and clear 673 * intr registers. 674 */ 675 slot = INTSLOT(vec); 676 intrmapptr = SBR_SLOT0_INT_MAP + slot * 8; 677 intrclrptr = SBR_SLOT0_INT_CLR + 678 (slot * 8 * 8) + (INTPRI(vec) * 8); 679 /* Enable the interrupt, insert IGN. */ 680 intrmap = inr | sc->sc_ign; 681 } else { 682 intrptr = SBR_SCSI_INT_MAP; 683 /* Insert IGN */ 684 inr |= sc->sc_ign; 685 for (i = 0; intrptr <= SBR_RESERVED_INT_MAP && 686 INTVEC(intrmap = SYSIO_READ8(sc, intrptr)) != 687 INTVEC(inr); intrptr += 8, i++) 688 ; 689 if (INTVEC(intrmap) == INTVEC(inr)) { 690 /* Register the map and clear intr registers */ 691 intrmapptr = intrptr; 692 intrclrptr = SBR_SCSI_INT_CLR + i * 8; 693 /* Enable the interrupt */ 694 } else 695 panic("sbus_setup_intr: IRQ not found!"); 696 } 697 698 scl->scl_sc = sc; 699 scl->scl_arg = arg; 700 scl->scl_handler = intr; 701 scl->scl_clr = intrclrptr; 702 /* Disable the interrupt while we fiddle with it */ 703 SYSIO_WRITE8(sc, intrmapptr, intrmap); 704 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 705 sbus_intr_stub, scl, cookiep); 706 if (error != 0) { 707 free(scl, M_DEVBUF); 708 return (error); 709 } 710 scl->scl_cookie = *cookiep; 711 *cookiep = scl; 712 713 /* 714 * Clear the interrupt, it might have been triggered before it was 715 * set up. 716 */ 717 SYSIO_WRITE8(sc, intrclrptr, 0); 718 /* 719 * Enable the interrupt and program the target module now we have the 720 * handler installed. 721 */ 722 SYSIO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(intrmap, PCPU_GET(mid))); 723 return (error); 724} 725 726static int 727sbus_teardown_intr(device_t dev, device_t child, 728 struct resource *vec, void *cookie) 729{ 730 struct sbus_clr *scl; 731 int error; 732 733 scl = (struct sbus_clr *)cookie; 734 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 735 scl->scl_cookie); 736 /* 737 * Don't disable the interrupt for now, so that stray interupts get 738 * detected... 739 */ 740 if (error != 0) 741 free(scl, M_DEVBUF); 742 return (error); 743} 744 745/* 746 * There is no need to handle pass-throughs here; there are no bridges to 747 * SBuses. 748 */ 749static struct resource * 750sbus_alloc_resource(device_t bus, device_t child, int type, int *rid, 751 u_long start, u_long end, u_long count, u_int flags) 752{ 753 struct sbus_softc *sc; 754 struct sbus_devinfo *sdi; 755 struct rman *rm; 756 struct resource *rv; 757 struct resource_list *rl; 758 struct resource_list_entry *rle; 759 bus_space_handle_t bh; 760 bus_addr_t toffs; 761 bus_size_t tend; 762 int i; 763 int isdefault = (start == 0UL && end == ~0UL); 764 int needactivate = flags & RF_ACTIVE; 765 766 sc = (struct sbus_softc *)device_get_softc(bus); 767 sdi = device_get_ivars(child); 768 rl = &sdi->sdi_rl; 769 rle = resource_list_find(rl, type, *rid); 770 if (rle == NULL) 771 return (NULL); 772 if (rle->res != NULL) 773 panic("sbus_alloc_resource: resource entry is busy"); 774 if (isdefault) { 775 start = rle->start; 776 count = ulmax(count, rle->count); 777 end = ulmax(rle->end, start + count - 1); 778 } 779 switch (type) { 780 case SYS_RES_IRQ: 781 rv = BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 782 rid, start, end, count, flags); 783 if (rv == NULL) 784 return (NULL); 785 break; 786 case SYS_RES_MEMORY: 787 rm = NULL; 788 bh = toffs = tend = 0; 789 for (i = 0; i < sc->sc_nrange; i++) { 790 if (sc->sc_rd[i].rd_slot != sdi->sdi_slot || 791 start < sc->sc_rd[i].rd_coffset || 792 start > sc->sc_rd[i].rd_cend) 793 continue; 794 /* Disallow cross-range allocations. */ 795 if (end > sc->sc_rd[i].rd_cend) 796 return (NULL); 797 /* We've found the connection to the parent bus */ 798 toffs = start - sc->sc_rd[i].rd_coffset; 799 tend = end - sc->sc_rd[i].rd_coffset; 800 rm = &sc->sc_rd[i].rd_rman; 801 bh = sc->sc_rd[i].rd_bushandle; 802 } 803 if (toffs == NULL) 804 return (NULL); 805 flags &= ~RF_ACTIVE; 806 rv = rman_reserve_resource(rm, toffs, tend, count, flags, 807 child); 808 if (rv == NULL) 809 return (NULL); 810 rman_set_bustag(rv, sc->sc_cbustag); 811 rman_set_bushandle(rv, bh + rman_get_start(rv)); 812 if (needactivate) { 813 if (bus_activate_resource(child, type, *rid, rv)) { 814 rman_release_resource(rv); 815 return (NULL); 816 } 817 } 818 break; 819 default: 820 return (NULL); 821 } 822 rle->res = rv; 823 return (rv); 824} 825 826static int 827sbus_activate_resource(device_t bus, device_t child, int type, int rid, 828 struct resource *r) 829{ 830 831 if (type == SYS_RES_IRQ) { 832 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), 833 child, type, rid, r)); 834 } 835 return (rman_activate_resource(r)); 836} 837 838static int 839sbus_deactivate_resource(device_t bus, device_t child, int type, int rid, 840 struct resource *r) 841{ 842 843 if (type == SYS_RES_IRQ) { 844 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), 845 child, type, rid, r)); 846 } 847 return (rman_deactivate_resource(r)); 848} 849 850static int 851sbus_release_resource(device_t bus, device_t child, int type, int rid, 852 struct resource *r) 853{ 854 struct sbus_devinfo *sdi; 855 struct resource_list_entry *rle; 856 int error = 0; 857 858 if (type == SYS_RES_IRQ) 859 error = BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 860 type, rid, r); 861 else { 862 if ((rman_get_flags(r) & RF_ACTIVE) != 0) 863 error = bus_deactivate_resource(child, type, rid, r); 864 if (error != 0) 865 return (error); 866 error = rman_release_resource(r); 867 } 868 if (error != 0) 869 return (error); 870 sdi = device_get_ivars(child); 871 rle = resource_list_find(&sdi->sdi_rl, type, rid); 872 if (rle == NULL) 873 panic("sbus_release_resource: can't find resource"); 874 if (rle->res == NULL) 875 panic("sbus_release_resource: resource entry is not busy"); 876 rle->res = NULL; 877 return (0); 878} 879 880/* 881 * Handle an overtemp situation. 882 * 883 * SPARCs have temperature sensors which generate interrupts 884 * if the machine's temperature exceeds a certain threshold. 885 * This handles the interrupt and powers off the machine. 886 * The same needs to be done to PCI controller drivers. 887 */ 888static void 889sbus_overtemp(void *arg) 890{ 891 892 printf("DANGER: OVER TEMPERATURE detected\nShutting down NOW.\n"); 893 shutdown_nice(RB_POWEROFF); 894} 895 896/* Try to shut down in time in case of power failure. */ 897static void 898sbus_pwrfail(void *arg) 899{ 900 901 printf("Power failure detected\nShutting down NOW.\n"); 902 shutdown_nice(0); 903} 904 905static bus_space_tag_t 906sbus_alloc_bustag(struct sbus_softc *sc) 907{ 908 bus_space_tag_t sbt; 909 910 sbt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 911 M_NOWAIT | M_ZERO); 912 if (sbt == NULL) 913 panic("sbus_alloc_bustag: out of memory"); 914 915 bzero(sbt, sizeof *sbt); 916 sbt->bst_cookie = sc; 917 sbt->bst_parent = sc->sc_bustag; 918 sbt->bst_type = SBUS_BUS_SPACE; 919 return (sbt); 920} 921 922static int 923sbus_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 924 bus_dmamap_t *mapp) 925{ 926 struct sbus_softc *sc = (struct sbus_softc *)pdmat->dt_cookie; 927 928 return (iommu_dvmamap_create(pdmat, ddmat, &sc->sc_is, flags, mapp)); 929 930} 931 932static int 933sbus_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 934{ 935 struct sbus_softc *sc = (struct sbus_softc *)pdmat->dt_cookie; 936 937 return (iommu_dvmamap_destroy(pdmat, ddmat, &sc->sc_is, map)); 938} 939 940static int 941sbus_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 942 void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 943 void *callback_arg, int flags) 944{ 945 struct sbus_softc *sc = (struct sbus_softc *)pdmat->dt_cookie; 946 947 return (iommu_dvmamap_load(pdmat, ddmat, &sc->sc_is, map, buf, buflen, 948 callback, callback_arg, flags)); 949} 950 951static int 952sbus_dmamap_load_mbuf(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 953 bus_dmamap_t map, struct mbuf *m, bus_dmamap_callback2_t *callback, 954 void *callback_arg, int flags) 955{ 956 struct sbus_softc *sc = (struct sbus_softc *)pdmat->dt_cookie; 957 958 return (iommu_dvmamap_load_mbuf(pdmat, ddmat, &sc->sc_is, map, m, 959 callback, callback_arg, flags)); 960} 961 962static int 963sbus_dmamap_load_uio(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, 964 bus_dmamap_t map, struct uio *uio, bus_dmamap_callback2_t *callback, 965 void *callback_arg, int flags) 966{ 967 struct sbus_softc *sc = (struct sbus_softc *)pdmat->dt_cookie; 968 969 return (iommu_dvmamap_load_uio(pdmat, ddmat, &sc->sc_is, map, uio, 970 callback, callback_arg, flags)); 971} 972 973static void 974sbus_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 975{ 976 struct sbus_softc *sc = (struct sbus_softc *)pdmat->dt_cookie; 977 978 iommu_dvmamap_unload(pdmat, ddmat, &sc->sc_is, map); 979} 980 981static void 982sbus_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 983 bus_dmasync_op_t op) 984{ 985 struct sbus_softc *sc = (struct sbus_softc *)pdmat->dt_cookie; 986 987 iommu_dvmamap_sync(pdmat, ddmat, &sc->sc_is, map, op); 988} 989 990static int 991sbus_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 992 int flags, bus_dmamap_t *mapp) 993{ 994 struct sbus_softc *sc = (struct sbus_softc *)pdmat->dt_cookie; 995 996 return (iommu_dvmamem_alloc(pdmat, ddmat, &sc->sc_is, vaddr, flags, 997 mapp)); 998} 999 1000static void 1001sbus_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 1002 bus_dmamap_t map) 1003{ 1004 struct sbus_softc *sc = (struct sbus_softc *)pdmat->dt_cookie; 1005 1006 iommu_dvmamem_free(pdmat, ddmat, &sc->sc_is, vaddr, map); 1007} 1008