1139825Simp/*- 286231Stmm * Copyright (c) 1999, 2000 Matthew R. Green 3117119Stmm * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4167308Smarius * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 586231Stmm * All rights reserved. 686231Stmm * 786231Stmm * Redistribution and use in source and binary forms, with or without 886231Stmm * modification, are permitted provided that the following conditions 986231Stmm * are met: 1086231Stmm * 1. Redistributions of source code must retain the above copyright 1186231Stmm * notice, this list of conditions and the following disclaimer. 1286231Stmm * 2. Redistributions in binary form must reproduce the above copyright 1386231Stmm * notice, this list of conditions and the following disclaimer in the 1486231Stmm * documentation and/or other materials provided with the distribution. 1586231Stmm * 3. The name of the author may not be used to endorse or promote products 1686231Stmm * derived from this software without specific prior written permission. 1786231Stmm * 1886231Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1986231Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2086231Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2186231Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2286231Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 2386231Stmm * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2486231Stmm * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 2586231Stmm * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2686231Stmm * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2786231Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2886231Stmm * SUCH DAMAGE. 2986231Stmm * 3090617Stmm * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 3186231Stmm */ 3286231Stmm 33152696Smarius#include <sys/cdefs.h> 34152696Smarius__FBSDID("$FreeBSD: stable/10/sys/sparc64/pci/psycho.c 318273 2017-05-14 14:04:32Z marius $"); 35152696Smarius 3686231Stmm/* 37153052Smarius * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38153052Smarius * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 3986231Stmm */ 4086231Stmm 41117119Stmm#include "opt_ofw_pci.h" 4286231Stmm#include "opt_psycho.h" 4386231Stmm 4486231Stmm#include <sys/param.h> 4586231Stmm#include <sys/systm.h> 4686231Stmm#include <sys/bus.h> 47174117Smarius#include <sys/endian.h> 48131949Smarcel#include <sys/kdb.h> 4986231Stmm#include <sys/kernel.h> 50170851Smarius#include <sys/lock.h> 51167308Smarius#include <sys/malloc.h> 52130068Sphk#include <sys/module.h> 53170851Smarius#include <sys/mutex.h> 54107477Stmm#include <sys/pcpu.h> 55153055Smarius#include <sys/reboot.h> 56171730Smarius#include <sys/rman.h> 57247600Smarius#include <sys/sysctl.h> 5886231Stmm 59133589Smarius#include <dev/ofw/ofw_bus.h> 60119338Simp#include <dev/ofw/openfirm.h> 6186231Stmm 6286231Stmm#include <machine/bus.h> 63167308Smarius#include <machine/bus_common.h> 64116541Stmm#include <machine/bus_private.h> 6586231Stmm#include <machine/iommureg.h> 66167308Smarius#include <machine/iommuvar.h> 6786231Stmm#include <machine/resource.h> 68152698Smarius#include <machine/ver.h> 6986231Stmm 70165886Smarius#include <dev/pci/pcireg.h> 71119291Simp#include <dev/pci/pcivar.h> 7286231Stmm 7386231Stmm#include <sparc64/pci/ofw_pci.h> 7486231Stmm#include <sparc64/pci/psychoreg.h> 7586231Stmm#include <sparc64/pci/psychovar.h> 7686231Stmm 7786231Stmm#include "pcib_if.h" 7886231Stmm 79152696Smariusstatic const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 80152696Smarius const char *); 81167308Smariusstatic const struct psycho_desc *psycho_get_desc(device_t); 82172066Smariusstatic void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 83247620Smarius driver_filter_t, driver_intr_t); 84172066Smariusstatic int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 8590617Stmm bus_addr_t *, u_long *); 86220039Smariusstatic void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 87220039Smarius bus_dmasync_op_t op); 88172066Smariusstatic void psycho_intr_enable(void *); 89172066Smariusstatic void psycho_intr_disable(void *); 90178443Smariusstatic void psycho_intr_assign(void *); 91178443Smariusstatic void psycho_intr_clear(void *); 9286231Stmm 9386231Stmm/* Interrupt handlers */ 94167308Smariusstatic driver_filter_t psycho_ue; 95167308Smariusstatic driver_filter_t psycho_ce; 96167308Smariusstatic driver_filter_t psycho_pci_bus; 97247600Smariusstatic driver_filter_t psycho_powerdebug; 98247620Smariusstatic driver_intr_t psycho_powerdown; 99247620Smariusstatic driver_intr_t psycho_overtemp; 10086231Stmm#ifdef PSYCHO_MAP_WAKEUP 101167308Smariusstatic driver_filter_t psycho_wakeup; 10286231Stmm#endif 10386231Stmm 10486231Stmm/* IOMMU support */ 105152698Smariusstatic void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 10686231Stmm 10786231Stmm/* 108152696Smarius * Methods 10986231Stmm */ 110117119Stmmstatic device_probe_t psycho_probe; 111117119Stmmstatic device_attach_t psycho_attach; 112117119Stmmstatic bus_setup_intr_t psycho_setup_intr; 113117119Stmmstatic bus_alloc_resource_t psycho_alloc_resource; 114117119Stmmstatic pcib_maxslots_t psycho_maxslots; 115117119Stmmstatic pcib_read_config_t psycho_read_config; 116117119Stmmstatic pcib_write_config_t psycho_write_config; 117117119Stmmstatic pcib_route_interrupt_t psycho_route_interrupt; 118220039Smariusstatic ofw_pci_setup_device_t psycho_setup_device; 11986231Stmm 12086231Stmmstatic device_method_t psycho_methods[] = { 12186231Stmm /* Device interface */ 12286231Stmm DEVMETHOD(device_probe, psycho_probe), 12386231Stmm DEVMETHOD(device_attach, psycho_attach), 124154870Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 125154870Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 126154870Smarius DEVMETHOD(device_resume, bus_generic_resume), 12786231Stmm 12886231Stmm /* Bus interface */ 129292789Smarius DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar), 130152696Smarius DEVMETHOD(bus_setup_intr, psycho_setup_intr), 131220039Smarius DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 13286231Stmm DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 133292789Smarius DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource), 134225931Smarius DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 135292789Smarius DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource), 136225931Smarius DEVMETHOD(bus_release_resource, bus_generic_release_resource), 137292789Smarius DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag), 13886231Stmm 13986231Stmm /* pcib interface */ 14086231Stmm DEVMETHOD(pcib_maxslots, psycho_maxslots), 14186231Stmm DEVMETHOD(pcib_read_config, psycho_read_config), 14286231Stmm DEVMETHOD(pcib_write_config, psycho_write_config), 14386231Stmm DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 14486231Stmm 145133589Smarius /* ofw_bus interface */ 146292789Smarius DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node), 147133589Smarius 148220039Smarius /* ofw_pci interface */ 149220039Smarius DEVMETHOD(ofw_pci_setup_device, psycho_setup_device), 150220039Smarius 151227843Smarius DEVMETHOD_END 15286231Stmm}; 15386231Stmm 15486231Stmmstatic devclass_t psycho_devclass; 15586231Stmm 156174117SmariusDEFINE_CLASS_0(pcib, psycho_driver, psycho_methods, 157174117Smarius sizeof(struct psycho_softc)); 158247600SmariusEARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, NULL, NULL, 159215349Smarius BUS_PASS_BUS); 16086231Stmm 161247600Smariusstatic SYSCTL_NODE(_hw, OID_AUTO, psycho, CTLFLAG_RD, 0, "psycho parameters"); 162247600Smarius 163247600Smariusstatic u_int psycho_powerfail = 1; 164247600SmariusTUNABLE_INT("hw.psycho.powerfail", &psycho_powerfail); 165247600SmariusSYSCTL_UINT(_hw_psycho, OID_AUTO, powerfail, CTLFLAG_RDTUN, &psycho_powerfail, 166247600Smarius 0, "powerfail action (0: none, 1: shutdown (default), 2: debugger)"); 167247600Smarius 168170930Smariusstatic SLIST_HEAD(, psycho_softc) psycho_softcs = 169105274Stmm SLIST_HEAD_INITIALIZER(psycho_softcs); 17086231Stmm 171172066Smariusstatic const struct intr_controller psycho_ic = { 172172066Smarius psycho_intr_enable, 173172066Smarius psycho_intr_disable, 174178443Smarius psycho_intr_assign, 175178443Smarius psycho_intr_clear 17686231Stmm}; 17786231Stmm 178172066Smariusstruct psycho_icarg { 179172066Smarius struct psycho_softc *pica_sc; 180172066Smarius bus_addr_t pica_map; 181172066Smarius bus_addr_t pica_clr; 182172066Smarius}; 183172066Smarius 184206018Smarius#define PSYCHO_READ8(sc, off) \ 185170851Smarius bus_read_8((sc)->sc_mem_res, (off)) 186206018Smarius#define PSYCHO_WRITE8(sc, off, v) \ 187170851Smarius bus_write_8((sc)->sc_mem_res, (off), (v)) 188206018Smarius#define PCICTL_READ8(sc, off) \ 18990617Stmm PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 190206018Smarius#define PCICTL_WRITE8(sc, off, v) \ 19190617Stmm PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 19290617Stmm 19386231Stmm/* 194152696Smarius * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 19586231Stmm * single PCI bus and does not have a streaming buffer. It often has an APB 19686231Stmm * (advanced PCI bridge) connected to it, which was designed specifically for 197247914Sgavin * the IIi. The APB lets the IIi handle two independent PCI buses, and 198152696Smarius * appears as two "Simba"'s underneath the Sabre. 19986231Stmm * 200153052Smarius * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 201153052Smarius * basically the same as Sabre but without an APB underneath it. 202153052Smarius * 203201199Smarius * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA 204201199Smarius * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 205152696Smarius * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 206152696Smarius * will usually find a "Psycho+" since I don't think the original "Psycho" 20788371Stmm * ever shipped, and if it did it would be in the U30. 20886231Stmm * 209152696Smarius * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 21086231Stmm * both part of the same IC, they only have a single register space. As such, 21186231Stmm * they need to be configured together, even though the autoconfiguration will 21286231Stmm * attach them separately. 21386231Stmm * 214152696Smarius * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 21586231Stmm * as pci1 and pci2, although they have been implemented with other PCI bus 21686231Stmm * numbers on some machines. 21786231Stmm * 218152696Smarius * On UltraII machines, there can be any number of "Psycho+" ICs, each 21988371Stmm * providing two PCI buses. 22086231Stmm */ 221166901Spiso 222105283Stmmstruct psycho_desc { 223152696Smarius const char *pd_string; 224152696Smarius int pd_mode; 225152696Smarius const char *pd_name; 226105283Stmm}; 227105283Stmm 228242625Sdimstatic const struct psycho_desc psycho_compats[] = { 229105283Stmm { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 230153052Smarius { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 231153052Smarius { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 232105283Stmm { NULL, 0, NULL } 233105283Stmm}; 234105283Stmm 235242625Sdimstatic const struct psycho_desc psycho_models[] = { 236105283Stmm { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 237105283Stmm { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 238105283Stmm { NULL, 0, NULL } 239105283Stmm}; 240105283Stmm 241152696Smariusstatic const struct psycho_desc * 242152696Smariuspsycho_find_desc(const struct psycho_desc *table, const char *string) 243105283Stmm{ 244152696Smarius const struct psycho_desc *desc; 245105283Stmm 246167308Smarius if (string == NULL) 247167308Smarius return (NULL); 248167308Smarius for (desc = table; desc->pd_string != NULL; desc++) 249105283Stmm if (strcmp(desc->pd_string, string) == 0) 250105283Stmm return (desc); 251105283Stmm return (NULL); 252105283Stmm} 253105283Stmm 254152696Smariusstatic const struct psycho_desc * 255167308Smariuspsycho_get_desc(device_t dev) 256105283Stmm{ 257152696Smarius const struct psycho_desc *rv; 258105283Stmm 259167308Smarius rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 260167308Smarius if (rv == NULL) 261201199Smarius rv = psycho_find_desc(psycho_compats, 262201199Smarius ofw_bus_get_compat(dev)); 263105283Stmm return (rv); 264105283Stmm} 265105283Stmm 26686231Stmmstatic int 26786231Stmmpsycho_probe(device_t dev) 26886231Stmm{ 269152696Smarius const char *dtype; 27086231Stmm 271167308Smarius dtype = ofw_bus_get_type(dev); 272197164Smarius if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 273167308Smarius psycho_get_desc(dev) != NULL) { 27486231Stmm device_set_desc(dev, "U2P UPA-PCI bridge"); 27586231Stmm return (0); 27686231Stmm } 27786231Stmm return (ENXIO); 27886231Stmm} 27986231Stmm 28086231Stmmstatic int 28186231Stmmpsycho_attach(device_t dev) 28286231Stmm{ 283172066Smarius struct psycho_icarg *pica; 284165886Smarius struct psycho_softc *asc, *sc, *osc; 285152696Smarius const struct psycho_desc *desc; 286172066Smarius bus_addr_t intrclr, intrmap; 287292789Smarius bus_dma_tag_t dmat; 288165886Smarius uint64_t csr, dr; 289220039Smarius phandle_t node; 290292789Smarius uint32_t dvmabase, prop; 291190109Smarius u_int rerun, ver; 292201199Smarius int i, j; 29386231Stmm 294167308Smarius node = ofw_bus_get_node(dev); 29586231Stmm sc = device_get_softc(dev); 296167308Smarius desc = psycho_get_desc(dev); 29786231Stmm 29886231Stmm sc->sc_dev = dev; 299105283Stmm sc->sc_mode = desc->pd_mode; 30086231Stmm 30186231Stmm /* 302152696Smarius * The Psycho gets three register banks: 30386231Stmm * (0) per-PBM configuration and status registers 30486231Stmm * (1) per-PBM PCI configuration space, containing only the 30586231Stmm * PBM 256-byte PCI header 306152696Smarius * (2) the shared Psycho configuration registers 30786231Stmm */ 30886231Stmm if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 309190109Smarius i = 2; 310167308Smarius sc->sc_pcictl = 311167308Smarius bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 312167308Smarius bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 313115417Stmm switch (sc->sc_pcictl) { 314115417Stmm case PSR_PCICTL0: 315115417Stmm sc->sc_half = 0; 316115417Stmm break; 317115417Stmm case PSR_PCICTL1: 318115417Stmm sc->sc_half = 1; 319115417Stmm break; 320115417Stmm default: 321152696Smarius panic("%s: bogus PCI control register location", 322152696Smarius __func__); 323182020Smarius /* NOTREACHED */ 324115417Stmm } 32586231Stmm } else { 326190109Smarius i = 0; 327115417Stmm sc->sc_pcictl = PSR_PCICTL0; 328115417Stmm sc->sc_half = 0; 32986231Stmm } 330190109Smarius sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 331167308Smarius (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 332167308Smarius RF_ACTIVE); 333167308Smarius if (sc->sc_mem_res == NULL) 334167308Smarius panic("%s: could not allocate registers", __func__); 33586231Stmm 33686231Stmm /* 337190109Smarius * Match other Psychos that are already configured against 338178840Smarius * the base physical address. This will be the same for a 33986231Stmm * pair of devices that share register space. 34086231Stmm */ 341165886Smarius osc = NULL; 342105274Stmm SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 343167308Smarius if (rman_get_start(asc->sc_mem_res) == 344167308Smarius rman_get_start(sc->sc_mem_res)) { 345152696Smarius /* Found partner. */ 346105274Stmm osc = asc; 347105274Stmm break; 348105274Stmm } 34986231Stmm } 350170851Smarius if (osc == NULL) { 351170851Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 352170851Smarius M_NOWAIT | M_ZERO); 353170851Smarius if (sc->sc_mtx == NULL) 354170851Smarius panic("%s: could not malloc mutex", __func__); 355170851Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 356170851Smarius } else { 357190109Smarius if (sc->sc_mode != PSYCHO_MODE_PSYCHO) 358190109Smarius panic("%s: no partner expected", __func__); 359170851Smarius if (mtx_initialized(osc->sc_mtx) == 0) 360170851Smarius panic("%s: mutex not initialized", __func__); 361170851Smarius sc->sc_mtx = osc->sc_mtx; 362170851Smarius } 363292789Smarius SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 36486231Stmm 36590617Stmm csr = PSYCHO_READ8(sc, PSR_CS); 366165886Smarius ver = PSYCHO_GCSR_VERS(csr); 367172066Smarius sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 36890617Stmm if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 369172066Smarius sc->sc_ign = PSYCHO_GCSR_IGN(csr); 370182110Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 371182110Smarius prop = 33000000; 37290617Stmm 373182110Smarius device_printf(dev, 374182110Smarius "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n", 375165886Smarius desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 376182110Smarius 'A' + sc->sc_half, prop / 1000 / 1000); 37790617Stmm 378165886Smarius /* Set up the PCI control and PCI diagnostic registers. */ 379165886Smarius 38090617Stmm csr = PCICTL_READ8(sc, PCR_CS); 381165886Smarius csr &= ~PCICTL_ARB_PARK; 382220039Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 383165886Smarius csr |= PCICTL_ARB_PARK; 384165886Smarius 385165886Smarius /* Workarounds for version specific bugs. */ 386165886Smarius dr = PCICTL_READ8(sc, PCR_DIAG); 387165886Smarius switch (ver) { 388165886Smarius case 0: 389165886Smarius dr |= DIAG_RTRY_DIS; 390165886Smarius dr &= ~DIAG_DWSYNC_DIS; 391190109Smarius rerun = 0; 392165886Smarius break; 393165886Smarius case 1: 394165886Smarius csr &= ~PCICTL_ARB_PARK; 395165886Smarius dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 396190109Smarius rerun = 0; 397165886Smarius break; 398165886Smarius default: 399165886Smarius dr |= DIAG_DWSYNC_DIS; 400165886Smarius dr &= ~DIAG_RTRY_DIS; 401190109Smarius rerun = 1; 402165886Smarius break; 403165886Smarius } 404165886Smarius 405183152Smarius csr |= PCICTL_ERRINTEN | PCICTL_ARB_4; 406165886Smarius csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 407165886Smarius#ifdef PSYCHO_DEBUG 408165886Smarius device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 409165886Smarius (unsigned long long)PCICTL_READ8(sc, PCR_CS), 410165886Smarius (unsigned long long)csr); 411165886Smarius#endif 41290617Stmm PCICTL_WRITE8(sc, PCR_CS, csr); 41386231Stmm 414165886Smarius dr &= ~DIAG_ISYNC_DIS; 415165886Smarius#ifdef PSYCHO_DEBUG 416165886Smarius device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 417165886Smarius (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 418165886Smarius (unsigned long long)dr); 419165886Smarius#endif 420165886Smarius PCICTL_WRITE8(sc, PCR_DIAG, dr); 421165886Smarius 422108800Stmm if (sc->sc_mode == PSYCHO_MODE_SABRE) { 423128625Stmm /* Use the PROM preset for now. */ 424108800Stmm csr = PCICTL_READ8(sc, PCR_TAS); 425108800Stmm if (csr == 0) 426153052Smarius panic("%s: Hummingbird/Sabre TAS not initialized.", 427153052Smarius __func__); 428152698Smarius dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 429108800Stmm } else 430152698Smarius dvmabase = -1; 431108800Stmm 43286231Stmm /* 433172066Smarius * If we're a Hummingbird/Sabre or the first of a pair of Psychos 434172066Smarius * to arrive here, do the interrupt setup and start up the IOMMU. 435153055Smarius */ 43686231Stmm if (osc == NULL) { 43786231Stmm /* 438172066Smarius * Hunt through all the interrupt mapping regs and register 439172066Smarius * our interrupt controller for the corresponding interrupt 440190109Smarius * vectors. We do this early in order to be able to catch 441190109Smarius * stray interrupts. 442172066Smarius */ 443201199Smarius for (i = 0; i <= PSYCHO_MAX_INO; i++) { 444201199Smarius if (psycho_find_intrmap(sc, i, &intrmap, &intrclr, 445172066Smarius NULL) == 0) 446172066Smarius continue; 447172066Smarius pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 448172066Smarius if (pica == NULL) 449172066Smarius panic("%s: could not allocate interrupt " 450172066Smarius "controller argument", __func__); 451172066Smarius pica->pica_sc = sc; 452172066Smarius pica->pica_map = intrmap; 453172066Smarius pica->pica_clr = intrclr; 454172066Smarius#ifdef PSYCHO_DEBUG 455172066Smarius /* 456172066Smarius * Enable all interrupts and clear all interrupt 457178840Smarius * states. This aids the debugging of interrupt 458172066Smarius * routing problems. 459172066Smarius */ 460172066Smarius device_printf(dev, 461172066Smarius "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 462201199Smarius i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 463201199Smarius (u_long)intrmap, (u_long)PSYCHO_READ8(sc, 464201199Smarius intrmap), (u_long)intrclr); 465201199Smarius PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i)); 466206018Smarius PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE); 467172066Smarius PSYCHO_WRITE8(sc, intrmap, 468201199Smarius INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i), 469172066Smarius PCPU_GET(mid))); 470172066Smarius#endif 471201199Smarius j = intr_controller_register(INTMAP_VEC(sc->sc_ign, 472201199Smarius i), &psycho_ic, pica); 473201199Smarius if (j != 0) 474190109Smarius device_printf(dev, "could not register " 475190109Smarius "interrupt controller for INO %d (%d)\n", 476201199Smarius i, j); 477172066Smarius } 478172066Smarius 479190109Smarius if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 480178840Smarius sparc64_counter_init(device_get_nameunit(dev), 481178840Smarius rman_get_bustag(sc->sc_mem_res), 482170851Smarius rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 48390617Stmm 48486231Stmm /* 485165886Smarius * Set up IOMMU and PCI configuration if we're the first 486190109Smarius * of a pair of Psychos to arrive here or a Hummingbird 487190109Smarius * or Sabre. 48886231Stmm * 48986231Stmm * We should calculate a TSB size based on amount of RAM 490108470Sschweikh * and number of bus controllers and number and type of 49186231Stmm * child devices. 49286231Stmm * 49386231Stmm * For the moment, 32KB should be more than enough. 49486231Stmm */ 495220147Smarius sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT | 496220147Smarius M_ZERO); 49790617Stmm if (sc->sc_is == NULL) 498220147Smarius panic("%s: could not malloc IOMMU state", __func__); 499201395Smarius sc->sc_is->is_flags = IOMMU_PRESERVE_PROM; 500220039Smarius if (sc->sc_mode == PSYCHO_MODE_SABRE) { 501220147Smarius sc->sc_dma_methods = 502220147Smarius malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF, 503220147Smarius M_NOWAIT); 504220147Smarius if (sc->sc_dma_methods == NULL) 505220147Smarius panic("%s: could not malloc DMA methods", 506220147Smarius __func__); 507220147Smarius memcpy(sc->sc_dma_methods, &iommu_dma_methods, 508220147Smarius sizeof(*sc->sc_dma_methods)); 509220147Smarius sc->sc_dma_methods->dm_dmamap_sync = 510220039Smarius sabre_dmamap_sync; 511171730Smarius sc->sc_is->is_pmaxaddr = 512171730Smarius IOMMU_MAXADDR(SABRE_IOMMU_BITS); 513220147Smarius } else { 514220147Smarius sc->sc_dma_methods = &iommu_dma_methods; 515171730Smarius sc->sc_is->is_pmaxaddr = 516171730Smarius IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 517220147Smarius } 518190109Smarius sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0; 519152696Smarius if (OF_getproplen(node, "no-streaming-cache") < 0) 52090617Stmm sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 521190109Smarius sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0; 522152698Smarius psycho_iommu_init(sc, 3, dvmabase); 52386231Stmm } else { 524153052Smarius /* Just copy IOMMU state, config tag and address. */ 525220147Smarius sc->sc_dma_methods = &iommu_dma_methods; 52686231Stmm sc->sc_is = osc->sc_is; 527152696Smarius if (OF_getproplen(node, "no-streaming-cache") < 0) 52890617Stmm sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 52990617Stmm iommu_reset(sc->sc_is); 53086231Stmm } 53186231Stmm 532292789Smarius /* Create our DMA tag. */ 533171730Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 534171730Smarius sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 535292789Smarius 0xff, 0xffffffff, 0, NULL, NULL, &dmat) != 0) 536225931Smarius panic("%s: could not create PCI DMA tag", __func__); 537292789Smarius dmat->dt_cookie = sc->sc_is; 538292789Smarius dmat->dt_mt = sc->sc_dma_methods; 539116213Stmm 540292789Smarius if (ofw_pci_attach_common(dev, dmat, PSYCHO_IO_SIZE, 541292789Smarius PSYCHO_MEM_SIZE) != 0) 542292789Smarius panic("%s: ofw_pci_attach_common() failed", __func__); 54398148Stmm 544183152Smarius /* Clear any pending PCI error bits. */ 545292789Smarius PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 546292789Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_ops.sc_pci_secbus, 547183152Smarius PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2); 548183152Smarius PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS)); 549183152Smarius PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS)); 550165886Smarius 551183152Smarius if (osc == NULL) { 552183152Smarius /* 553183152Smarius * Establish handlers for interesting interrupts... 554183152Smarius * 555183152Smarius * XXX We need to remember these and remove this to support 556183152Smarius * hotplug on the UPA/FHC bus. 557183152Smarius * 558183152Smarius * XXX Not all controllers have these, but installing them 559183152Smarius * is better than trying to sort through this mess. 560183152Smarius */ 561247620Smarius psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 562247620Smarius psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 563247600Smarius switch (psycho_powerfail) { 564247600Smarius case 0: 565247600Smarius break; 566247600Smarius case 2: 567247600Smarius psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, 568247620Smarius psycho_powerdebug, NULL); 569247600Smarius break; 570247600Smarius default: 571247620Smarius psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 572247600Smarius psycho_powerdown); 573247600Smarius break; 574247600Smarius } 575183152Smarius if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 576183152Smarius /* 577183152Smarius * Hummingbirds/Sabres do not have the following two 578183152Smarius * interrupts. 579183152Smarius */ 580183152Smarius 581183152Smarius /* 582183152Smarius * The spare hardware interrupt is used for the 583183152Smarius * over-temperature interrupt. 584183152Smarius */ 585247620Smarius psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, NULL, 586247600Smarius psycho_overtemp); 587183152Smarius#ifdef PSYCHO_MAP_WAKEUP 588183152Smarius /* 589183152Smarius * psycho_wakeup() doesn't do anything useful right 590183152Smarius * now. 591183152Smarius */ 592183152Smarius psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 593247620Smarius psycho_wakeup, NULL); 594183152Smarius#endif /* PSYCHO_MAP_WAKEUP */ 595183152Smarius } 596183152Smarius } 597165886Smarius /* 598183152Smarius * Register a PCI bus error interrupt handler according to which 599183152Smarius * half this is. Hummingbird/Sabre don't have a PCI bus B error 600183152Smarius * interrupt but they are also only used for PCI bus A. 601183152Smarius */ 602183152Smarius psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 603247620Smarius PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 604183152Smarius 605183152Smarius /* 606165886Smarius * Set the latency timer register as this isn't always done by the 607165886Smarius * firmware. 608165886Smarius */ 609292789Smarius PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 610182020Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 611165886Smarius 612201199Smarius for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t)) 613292789Smarius le16enc(&sc->sc_pci_hpbcfg[i], 614292789Smarius bus_space_read_2(sc->sc_ops.sc_pci_cfgt, 615292789Smarius sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], 616292789Smarius PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, PCS_DEVICE, 617201199Smarius PCS_FUNC, i))); 618201199Smarius for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t)) 619292789Smarius sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_ops.sc_pci_cfgt, 620292789Smarius sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 621292789Smarius sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i)); 622174117Smarius 623152698Smarius /* 624153052Smarius * On E250 the interrupt map entry for the EBus bridge is wrong, 625153052Smarius * causing incorrect interrupts to be assigned to some devices on 626178840Smarius * the EBus. Work around it by changing our copy of the interrupt 627178840Smarius * map mask to perform a full comparison of the INO. That way 628153052Smarius * the interrupt map entry for the EBus bridge won't match at all 629153052Smarius * and the INOs specified in the "interrupts" properties of the 630153052Smarius * EBus devices will be used directly instead. 631152698Smarius */ 632152698Smarius if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 633292789Smarius sc->sc_ops.sc_pci_iinfo.opi_imapmsk != NULL) 634292789Smarius *(ofw_pci_intr_t *)(&sc->sc_ops.sc_pci_iinfo.opi_imapmsk[ 635292789Smarius sc->sc_ops.sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 636117119Stmm 637178279Smarius device_add_child(dev, "pci", -1); 63886231Stmm return (bus_generic_attach(dev)); 63986231Stmm} 64086231Stmm 64186231Stmmstatic void 642172066Smariuspsycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 643247620Smarius driver_filter_t filt, driver_intr_t intr) 64486231Stmm{ 645172066Smarius u_long vec; 646170851Smarius int rid; 64786231Stmm 648153055Smarius rid = index; 649201199Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 650201199Smarius SYS_RES_IRQ, &rid, RF_ACTIVE); 651190109Smarius if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) { 652190109Smarius /* 653190109Smarius * These interrupts aren't mandatory and not available 654190109Smarius * with all controllers (not even Psychos). 655190109Smarius */ 656190109Smarius return; 657190109Smarius } 658170851Smarius if (sc->sc_irq_res[index] == NULL || 659201199Smarius INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != 660201199Smarius sc->sc_ign || 661172066Smarius INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 662172066Smarius intr_vectors[vec].iv_ic != &psycho_ic || 663190109Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 664247620Smarius INTR_TYPE_MISC | INTR_BRIDGE, filt, intr, sc, 665190109Smarius &sc->sc_ihand[index]) != 0) 666170851Smarius panic("%s: failed to set up interrupt %d", __func__, index); 66786231Stmm} 66886231Stmm 66986231Stmmstatic int 670201199Smariuspsycho_find_intrmap(struct psycho_softc *sc, u_int ino, 671201199Smarius bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 67286231Stmm{ 673172066Smarius bus_addr_t intrclr, intrmap; 674172066Smarius uint64_t diag; 67586231Stmm int found; 67686231Stmm 677172066Smarius /* 678172066Smarius * XXX we only compare INOs rather than INRs since the firmware may 679172066Smarius * not provide the IGN and the IGN is constant for all devices on 680172066Smarius * that PCI controller. 681172066Smarius * This could cause problems for the FFB/external interrupt which 682172066Smarius * has a full vector that can be set arbitrarily. 683172066Smarius */ 684172066Smarius 685172066Smarius if (ino > PSYCHO_MAX_INO) { 686172066Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 687172066Smarius ino); 688172066Smarius return (0); 689172066Smarius } 690172066Smarius 69186231Stmm found = 0; 692172066Smarius /* Hunt through OBIO first. */ 69390617Stmm diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 69490617Stmm for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 695172066Smarius intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 696167308Smarius diag >>= 2) { 697172066Smarius if (sc->sc_mode == PSYCHO_MODE_SABRE && 698172066Smarius (intrmap == PSR_TIMER0_INT_MAP || 699172066Smarius intrmap == PSR_TIMER1_INT_MAP || 700172066Smarius intrmap == PSR_PCIBERR_INT_MAP || 701172066Smarius intrmap == PSR_PWRMGT_INT_MAP)) 702172066Smarius continue; 703172066Smarius if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 70486231Stmm diag &= 2; 70586231Stmm found = 1; 70686231Stmm break; 70786231Stmm } 70886231Stmm } 70986231Stmm 71086231Stmm if (!found) { 71190617Stmm diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 712153052Smarius /* Now do PCI interrupts. */ 71390617Stmm for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 714167308Smarius intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 715167308Smarius diag >>= 8) { 716107476Stmm if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 717107476Stmm (intrmap == PSR_PCIA2_INT_MAP || 718172066Smarius intrmap == PSR_PCIA3_INT_MAP)) 719107476Stmm continue; 720172066Smarius if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 72190617Stmm intrclr += 8 * (ino & 3); 72286231Stmm diag = (diag >> ((ino & 3) * 2)) & 2; 72386231Stmm found = 1; 72486231Stmm break; 72586231Stmm } 72686231Stmm } 72786231Stmm } 72886231Stmm if (intrmapptr != NULL) 72986231Stmm *intrmapptr = intrmap; 73086231Stmm if (intrclrptr != NULL) 73186231Stmm *intrclrptr = intrclr; 73286231Stmm if (intrdiagptr != NULL) 73386231Stmm *intrdiagptr = diag; 73486231Stmm return (found); 73586231Stmm} 73686231Stmm 73786231Stmm/* 738152696Smarius * Interrupt handlers 73986231Stmm */ 740166901Spisostatic int 74186231Stmmpsycho_ue(void *arg) 74286231Stmm{ 743152696Smarius struct psycho_softc *sc = arg; 744152696Smarius uint64_t afar, afsr; 74586231Stmm 74690617Stmm afar = PSYCHO_READ8(sc, PSR_UE_AFA); 74790617Stmm afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 74893053Stmm /* 74993053Stmm * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 75093053Stmm * the AFAR to be set to the physical address of the TTE entry that 751178840Smarius * was invalid/write protected. Call into the IOMMU code to have 752165886Smarius * them decoded to virtual I/O addresses. 75393053Stmm */ 75493053Stmm if ((afsr & UEAFSR_P_DTE) != 0) 75593053Stmm iommu_decode_fault(sc->sc_is, afar); 756108800Stmm panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 757206020Smarius device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr); 758166901Spiso return (FILTER_HANDLED); 75986231Stmm} 76086231Stmm 761166901Spisostatic int 76286231Stmmpsycho_ce(void *arg) 76386231Stmm{ 764152696Smarius struct psycho_softc *sc = arg; 765152696Smarius uint64_t afar, afsr; 76686231Stmm 767170851Smarius mtx_lock_spin(sc->sc_mtx); 76890617Stmm afar = PSYCHO_READ8(sc, PSR_CE_AFA); 76990617Stmm afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 770117119Stmm device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 771117119Stmm "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 772119737Stmm /* Clear the error bits that we caught. */ 773183152Smarius PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr); 774170851Smarius mtx_unlock_spin(sc->sc_mtx); 775166901Spiso return (FILTER_HANDLED); 77686231Stmm} 77786231Stmm 778166901Spisostatic int 779153055Smariuspsycho_pci_bus(void *arg) 78086231Stmm{ 781152696Smarius struct psycho_softc *sc = arg; 782152696Smarius uint64_t afar, afsr; 78386231Stmm 784153055Smarius afar = PCICTL_READ8(sc, PCR_AFA); 785153055Smarius afsr = PCICTL_READ8(sc, PCR_AFS); 786153055Smarius panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 787206020Smarius device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 788153055Smarius (u_long)afsr); 789166901Spiso return (FILTER_HANDLED); 79086231Stmm} 79186231Stmm 792166901Spisostatic int 793247600Smariuspsycho_powerdebug(void *arg __unused) 79486231Stmm{ 79592212Sjake 796174898Srwatson kdb_enter(KDB_WHY_POWERFAIL, "powerfail"); 797247600Smarius return (FILTER_HANDLED); 798247600Smarius} 799247600Smarius 800247620Smariusstatic void 801247600Smariuspsycho_powerdown(void *arg __unused) 802247600Smarius{ 803172066Smarius static int shutdown; 804172066Smarius 805172066Smarius /* As the interrupt is cleared we may be called multiple times. */ 806172066Smarius if (shutdown != 0) 807247620Smarius return; 808172066Smarius shutdown++; 80986231Stmm printf("Power Failure Detected: Shutting down NOW.\n"); 810247600Smarius shutdown_nice(RB_POWEROFF); 81186231Stmm} 81286231Stmm 813247620Smariusstatic void 814247600Smariuspsycho_overtemp(void *arg __unused) 815153055Smarius{ 816172066Smarius static int shutdown; 817153055Smarius 818172066Smarius /* As the interrupt is cleared we may be called multiple times. */ 819172066Smarius if (shutdown != 0) 820247620Smarius return; 821172066Smarius shutdown++; 822153055Smarius printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 823153055Smarius shutdown_nice(RB_POWEROFF); 824153055Smarius} 825153055Smarius 82686231Stmm#ifdef PSYCHO_MAP_WAKEUP 827166901Spisostatic int 82886231Stmmpsycho_wakeup(void *arg) 82986231Stmm{ 830152696Smarius struct psycho_softc *sc = arg; 83186231Stmm 832201199Smarius /* We don't really have a framework to deal with this properly. */ 833117119Stmm device_printf(sc->sc_dev, "power management wakeup\n"); 834166901Spiso return (FILTER_HANDLED); 83586231Stmm} 83686231Stmm#endif /* PSYCHO_MAP_WAKEUP */ 83786231Stmm 838152696Smariusstatic void 839152698Smariuspsycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 84086231Stmm{ 84190617Stmm struct iommu_state *is = sc->sc_is; 84286231Stmm 843152696Smarius /* Punch in our copies. */ 844170851Smarius is->is_bustag = rman_get_bustag(sc->sc_mem_res); 845170851Smarius is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 84690617Stmm is->is_iommu = PSR_IOMMU; 84790617Stmm is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 84890617Stmm is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 84990617Stmm is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 85090617Stmm is->is_dva = PSR_IOMMU_SVADIAG; 85190617Stmm is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 85286231Stmm 853178840Smarius iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0); 85486231Stmm} 85586231Stmm 85686231Stmmstatic int 85786231Stmmpsycho_maxslots(device_t dev) 85886231Stmm{ 85986231Stmm 860117119Stmm /* XXX: is this correct? */ 861117119Stmm return (PCI_SLOTMAX); 86286231Stmm} 86386231Stmm 864152696Smariusstatic uint32_t 86586231Stmmpsycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 866152696Smarius int width) 86786231Stmm{ 86886231Stmm struct psycho_softc *sc; 86986231Stmm 870152696Smarius sc = device_get_softc(dev); 871174117Smarius /* 872174117Smarius * The Hummingbird and Sabre bridges are picky in that they 873174117Smarius * only allow their config space to be accessed using the 874174117Smarius * "native" width of the respective register being accessed 875174117Smarius * and return semi-random other content of their config space 876178840Smarius * otherwise. Given that the PCI specs don't say anything 877174117Smarius * about such a (unusual) limitation and lots of stuff expects 878174117Smarius * to be able to access the contents of the config space at 879178840Smarius * any width we allow just that. We do this by using a copy 880174117Smarius * of the header of the bridge (the rest is all zero anyway) 881174117Smarius * read during attach (expect for PCIR_STATUS) in order to 882174117Smarius * simplify things. 883174117Smarius * The Psycho bridges contain a dupe of their header at 0x80 884174117Smarius * which we nullify that way also. 885174117Smarius */ 886292789Smarius if (bus == sc->sc_ops.sc_pci_secbus && slot == PCS_DEVICE && 887174117Smarius func == PCS_FUNC) { 888292789Smarius if (reg % width != 0) 889174117Smarius return (-1); 890174117Smarius 891174134Smarius if (reg >= sizeof(sc->sc_pci_hpbcfg)) 892174117Smarius return (0); 893174117Smarius 894174117Smarius if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 895174117Smarius reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 896174117Smarius le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], 897292789Smarius bus_space_read_2(sc->sc_ops.sc_pci_cfgt, 898292789Smarius sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], 899292789Smarius PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, 900174117Smarius PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 901174117Smarius 902174117Smarius switch (width) { 903174117Smarius case 1: 904174117Smarius return (sc->sc_pci_hpbcfg[reg]); 905174117Smarius case 2: 906174117Smarius return (le16dec(&sc->sc_pci_hpbcfg[reg])); 907174117Smarius case 4: 908174117Smarius return (le32dec(&sc->sc_pci_hpbcfg[reg])); 909174117Smarius } 910174117Smarius } 911174117Smarius 912292789Smarius return (ofw_pci_read_config_common(dev, PCI_REGMAX, 913292789Smarius PSYCHO_CONF_OFF(bus, slot, func, reg), bus, slot, func, reg, 914292789Smarius width)); 91586231Stmm} 91686231Stmm 91786231Stmmstatic void 918201199Smariuspsycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, 919201199Smarius u_int reg, uint32_t val, int width) 92086231Stmm{ 92186231Stmm 922292789Smarius ofw_pci_write_config_common(dev, PCI_REGMAX, PSYCHO_CONF_OFF(bus, 923292789Smarius slot, func, reg), bus, slot, func, reg, val, width); 92486231Stmm} 92586231Stmm 92686231Stmmstatic int 927117119Stmmpsycho_route_interrupt(device_t bridge, device_t dev, int pin) 92886231Stmm{ 929152696Smarius struct psycho_softc *sc; 930117119Stmm bus_addr_t intrmap; 931292789Smarius ofw_pci_intr_t mintr; 93286231Stmm 933292789Smarius mintr = ofw_pci_route_interrupt_common(bridge, dev, pin); 934292789Smarius if (PCI_INTERRUPT_VALID(mintr)) 935117119Stmm return (mintr); 93686231Stmm /* 937117119Stmm * If this is outside of the range for an intpin, it's likely a full 938152696Smarius * INO, and no mapping is required at all; this happens on the U30, 939178840Smarius * where there's no interrupt map at the Psycho node. Fortunately, 940117119Stmm * there seem to be no INOs in the intpin range on this boxen, so 941117119Stmm * this easy heuristics will do. 942117119Stmm */ 943117119Stmm if (pin > 4) 944117119Stmm return (pin); 945117119Stmm /* 946318273Smarius * Guess the INO; we always assume that this is a non-OBIO device, 947318273Smarius * and that pin is a "real" intpin number. Determine the mapping 948318273Smarius * register to be used by the slot number. 949318273Smarius * We only need to do this on E450s and U30s, though; here, the 950318273Smarius * slot numbers for bus A are one-based, while those for bus B 951318273Smarius * seemingly have an offset of 2 (hence the factor of 3 below). 952117119Stmm */ 953318273Smarius sc = device_get_softc(bridge); 954117119Stmm intrmap = PSR_PCIA0_INT_MAP + 955117119Stmm 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 956117119Stmm mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 957201199Smarius device_printf(bridge, 958201199Smarius "guessing interrupt %d for device %d.%d pin %d\n", 959117119Stmm (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 960117119Stmm return (mintr); 96186231Stmm} 96286231Stmm 963220039Smariusstatic void 964220039Smariussabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 965170387Spiso{ 966220039Smarius struct iommu_state *is = dt->dt_cookie; 967170387Spiso 968220039Smarius if ((map->dm_flags & DMF_LOADED) == 0) 969220039Smarius return; 970220039Smarius 971220039Smarius if ((op & BUS_DMASYNC_POSTREAD) != 0) 972220039Smarius (void)bus_space_read_8(is->is_bustag, is->is_bushandle, 973220039Smarius PSR_DMA_WRITE_SYNC); 974220039Smarius 975220039Smarius if ((op & BUS_DMASYNC_PREWRITE) != 0) 976220039Smarius membar(Sync); 977170387Spiso} 978170387Spiso 979170387Spisostatic void 980172066Smariuspsycho_intr_enable(void *arg) 98186231Stmm{ 982172066Smarius struct intr_vector *iv = arg; 983172066Smarius struct psycho_icarg *pica = iv->iv_icarg; 98486231Stmm 985172066Smarius PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 986172066Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 98786231Stmm} 98886231Stmm 989172066Smariusstatic void 990172066Smariuspsycho_intr_disable(void *arg) 991172066Smarius{ 992172066Smarius struct intr_vector *iv = arg; 993172066Smarius struct psycho_icarg *pica = iv->iv_icarg; 994172066Smarius 995172066Smarius PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 996172066Smarius} 997172066Smarius 998172066Smariusstatic void 999178443Smariuspsycho_intr_assign(void *arg) 1000172066Smarius{ 1001172066Smarius struct intr_vector *iv = arg; 1002172066Smarius struct psycho_icarg *pica = iv->iv_icarg; 1003172066Smarius 1004178443Smarius PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID( 1005178443Smarius PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid)); 1006178443Smarius} 1007178443Smarius 1008178443Smariusstatic void 1009178443Smariuspsycho_intr_clear(void *arg) 1010178443Smarius{ 1011178443Smarius struct intr_vector *iv = arg; 1012178443Smarius struct psycho_icarg *pica = iv->iv_icarg; 1013178443Smarius 1014206018Smarius PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE); 1015172066Smarius} 1016172066Smarius 101786231Stmmstatic int 1018152696Smariuspsycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1019167308Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1020166901Spiso void **cookiep) 102186231Stmm{ 102286231Stmm struct psycho_softc *sc; 1023172066Smarius u_long vec; 102486231Stmm 1025152696Smarius sc = device_get_softc(dev); 102686231Stmm /* 1027172066Smarius * Make sure the vector is fully specified and we registered 1028172066Smarius * our interrupt controller for it. 102986231Stmm */ 1030165886Smarius vec = rman_get_start(ires); 1031172066Smarius if (INTIGN(vec) != sc->sc_ign || 1032172066Smarius intr_vectors[vec].iv_ic != &psycho_ic) { 1033172066Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1034165886Smarius return (EINVAL); 103586231Stmm } 1036172066Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1037172066Smarius arg, cookiep)); 103886231Stmm} 103986231Stmm 104086231Stmmstatic struct resource * 104186231Stmmpsycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 104286231Stmm u_long start, u_long end, u_long count, u_int flags) 104386231Stmm{ 104486231Stmm struct psycho_softc *sc; 104586231Stmm 1046292789Smarius if (type == SYS_RES_IRQ) { 1047292789Smarius sc = device_get_softc(bus); 1048172066Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 104986231Stmm } 1050292789Smarius return (ofw_pci_alloc_resource(bus, child, type, rid, start, end, 1051292789Smarius count, flags)); 105286231Stmm} 105386231Stmm 1054220039Smariusstatic void 1055220039Smariuspsycho_setup_device(device_t bus, device_t child) 1056220039Smarius{ 1057220039Smarius struct psycho_softc *sc; 1058220039Smarius uint32_t rev; 1059220039Smarius 1060220039Smarius sc = device_get_softc(bus); 1061220039Smarius /* 1062220039Smarius * Revision 0 EBus bridges have a bug which prevents them from 1063220039Smarius * working when bus parking is enabled. 1064220039Smarius */ 1065220039Smarius if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 || 1066220039Smarius strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) && 1067220039Smarius OF_getprop(ofw_bus_get_node(child), "revision-id", &rev, 1068220039Smarius sizeof(rev)) > 0 && rev == 0) 1069220039Smarius PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) & 1070220039Smarius ~PCICTL_ARB_PARK); 1071220039Smarius} 1072