1/*- 2 * Copyright (c) 2001 Jake Burkholder. 3 * Copyright (c) 2008, 2010 Marius Strobl <marius@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#ifndef _MACHINE_TLB_H_ 31#define _MACHINE_TLB_H_ 32 33#define TLB_DIRECT_ADDRESS_BITS (43) 34#define TLB_DIRECT_PAGE_BITS (PAGE_SHIFT_4M) 35 36#define TLB_DIRECT_ADDRESS_MASK ((1UL << TLB_DIRECT_ADDRESS_BITS) - 1) 37#define TLB_DIRECT_PAGE_MASK ((1UL << TLB_DIRECT_PAGE_BITS) - 1) 38 39#define TLB_PHYS_TO_DIRECT(pa) \ 40 ((pa) | VM_MIN_DIRECT_ADDRESS) 41#define TLB_DIRECT_TO_PHYS(va) \ 42 ((va) & TLB_DIRECT_ADDRESS_MASK) 43#define TLB_DIRECT_TO_TTE_MASK \ 44 (TD_V | TD_4M | (TLB_DIRECT_ADDRESS_MASK - TLB_DIRECT_PAGE_MASK)) 45 46#define TLB_DAR_SLOT_SHIFT (3) 47#define TLB_DAR_TLB_SHIFT (16) 48#define TLB_DAR_SLOT(tlb, slot) \ 49 ((tlb) << TLB_DAR_TLB_SHIFT | (slot) << TLB_DAR_SLOT_SHIFT) 50#define TLB_DAR_T16 (0) /* US-III{,i,+}, IV{,+} */ 51#define TLB_DAR_T32 (0) /* US-I, II{,e,i} */ 52#define TLB_DAR_DT512_0 (2) /* US-III{,i,+}, IV{,+} */ 53#define TLB_DAR_DT512_1 (3) /* US-III{,i,+}, IV{,+} */ 54#define TLB_DAR_IT128 (2) /* US-III{,i,+}, IV */ 55#define TLB_DAR_IT512 (2) /* US-IV+ */ 56#define TLB_DAR_FTLB (0) /* SPARC64 V, VI, VII, VIIIfx */ 57#define TLB_DAR_STLB (2) /* SPARC64 V, VI, VII, VIIIfx */ 58 59#define TAR_VPN_SHIFT (13) 60#define TAR_CTX_MASK ((1 << TAR_VPN_SHIFT) - 1) 61 62#define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK) 63#define TLB_TAR_CTX(ctx) ((ctx) & TAR_CTX_MASK) 64 65#define TLB_CXR_CTX_BITS (13) 66#define TLB_CXR_CTX_MASK \ 67 (((1UL << TLB_CXR_CTX_BITS) - 1) << TLB_CXR_CTX_SHIFT) 68#define TLB_CXR_CTX_SHIFT (0) 69#define TLB_CXR_PGSZ_BITS (3) 70#define TLB_CXR_PGSZ_MASK (~TLB_CXR_CTX_MASK) 71#define TLB_PCXR_N_IPGSZ0_SHIFT (53) /* SPARC64 VI, VII, VIIIfx */ 72#define TLB_PCXR_N_IPGSZ1_SHIFT (50) /* SPARC64 VI, VII, VIIIfx */ 73#define TLB_PCXR_N_PGSZ0_SHIFT (61) 74#define TLB_PCXR_N_PGSZ1_SHIFT (58) 75#define TLB_PCXR_N_PGSZ_I_SHIFT (55) /* US-IV+ */ 76#define TLB_PCXR_P_IPGSZ0_SHIFT (24) /* SPARC64 VI, VII, VIIIfx */ 77#define TLB_PCXR_P_IPGSZ1_SHIFT (27) /* SPARC64 VI, VII, VIIIfx */ 78#define TLB_PCXR_P_PGSZ0_SHIFT (16) 79#define TLB_PCXR_P_PGSZ1_SHIFT (19) 80/* 81 * Note that the US-IV+ documentation appears to have TLB_PCXR_P_PGSZ_I_SHIFT 82 * and TLB_PCXR_P_PGSZ0_SHIFT erroneously inverted. 83 */ 84#define TLB_PCXR_P_PGSZ_I_SHIFT (22) /* US-IV+ */ 85#define TLB_SCXR_S_PGSZ1_SHIFT (19) 86#define TLB_SCXR_S_PGSZ0_SHIFT (16) 87 88#define TLB_TAE_PGSZ_BITS (3) 89#define TLB_TAE_PGSZ0_MASK \ 90 (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ0_SHIFT) 91#define TLB_TAE_PGSZ1_MASK \ 92 (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ1_SHIFT) 93#define TLB_TAE_PGSZ0_SHIFT (16) 94#define TLB_TAE_PGSZ1_SHIFT (19) 95 96#define TLB_DEMAP_ID_SHIFT (4) 97#define TLB_DEMAP_ID_PRIMARY (0) 98#define TLB_DEMAP_ID_SECONDARY (1) 99#define TLB_DEMAP_ID_NUCLEUS (2) 100 101#define TLB_DEMAP_TYPE_SHIFT (6) 102#define TLB_DEMAP_TYPE_PAGE (0) 103#define TLB_DEMAP_TYPE_CONTEXT (1) 104#define TLB_DEMAP_TYPE_ALL (2) /* US-III and beyond only */ 105 106#define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK) 107#define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT) 108#define TLB_DEMAP_TYPE(type) ((type) << TLB_DEMAP_TYPE_SHIFT) 109 110#define TLB_DEMAP_PAGE (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE)) 111#define TLB_DEMAP_CONTEXT (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT)) 112#define TLB_DEMAP_ALL (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_ALL)) 113 114#define TLB_DEMAP_PRIMARY (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY)) 115#define TLB_DEMAP_SECONDARY (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY)) 116#define TLB_DEMAP_NUCLEUS (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS)) 117 118#define TLB_CTX_KERNEL (0) 119#define TLB_CTX_USER_MIN (1) 120#define TLB_CTX_USER_MAX (8192) 121 122#define MMU_SFSR_ASI_SHIFT (16) 123#define MMU_SFSR_FT_SHIFT (7) 124#define MMU_SFSR_E_SHIFT (6) 125#define MMU_SFSR_CT_SHIFT (4) 126#define MMU_SFSR_PR_SHIFT (3) 127#define MMU_SFSR_W_SHIFT (2) 128#define MMU_SFSR_OW_SHIFT (1) 129#define MMU_SFSR_FV_SHIFT (0) 130 131#define MMU_SFSR_ASI_SIZE (8) 132#define MMU_SFSR_FT_SIZE (6) 133#define MMU_SFSR_CT_SIZE (2) 134 135#define MMU_SFSR_GET_ASI(sfsr) \ 136 (((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1)) 137#define MMU_SFSR_GET_FT(sfsr) \ 138 (((sfsr) >> MMU_SFSR_FT_SHIFT) & ((1UL << MMU_SFSR_FT_SIZE) - 1)) 139#define MMU_SFSR_GET_CT(sfsr) \ 140 (((sfsr) >> MMU_SFSR_CT_SHIFT) & ((1UL << MMU_SFSR_CT_SIZE) - 1)) 141 142#define MMU_SFSR_E (1UL << MMU_SFSR_E_SHIFT) 143#define MMU_SFSR_PR (1UL << MMU_SFSR_PR_SHIFT) 144#define MMU_SFSR_W (1UL << MMU_SFSR_W_SHIFT) 145#define MMU_SFSR_OW (1UL << MMU_SFSR_OW_SHIFT) 146#define MMU_SFSR_FV (1UL << MMU_SFSR_FV_SHIFT) 147 148typedef void tlb_flush_nonlocked_t(void); 149typedef void tlb_flush_user_t(void); 150 151struct pmap; 152struct tlb_entry; 153 154extern int dtlb_slots; 155extern int itlb_slots; 156extern int kernel_tlb_slots; 157extern struct tlb_entry *kernel_tlbs; 158 159void tlb_context_demap(struct pmap *pm); 160void tlb_page_demap(struct pmap *pm, vm_offset_t va); 161void tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end); 162 163tlb_flush_nonlocked_t cheetah_tlb_flush_nonlocked; 164tlb_flush_user_t cheetah_tlb_flush_user; 165 166tlb_flush_nonlocked_t spitfire_tlb_flush_nonlocked; 167tlb_flush_user_t spitfire_tlb_flush_user; 168 169tlb_flush_nonlocked_t zeus_tlb_flush_nonlocked; 170tlb_flush_user_t zeus_tlb_flush_user; 171 172extern tlb_flush_nonlocked_t *tlb_flush_nonlocked; 173extern tlb_flush_user_t *tlb_flush_user; 174 175#endif /* !_MACHINE_TLB_H_ */ 176