cpu.c revision 259256
1/*- 2 * Copyright (c) 2001 Matt Thomas. 3 * Copyright (c) 2001 Tsubai Masanari. 4 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by 18 * Internet Research Institute, Inc. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33/*- 34 * Copyright (C) 2003 Benno Rice. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 51 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 52 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 53 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 54 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 55 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 * 57 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $ 58 * $FreeBSD: stable/10/sys/powerpc/powerpc/cpu.c 259256 2013-12-12 12:29:35Z andreast $ 59 */ 60 61#include <sys/param.h> 62#include <sys/systm.h> 63#include <sys/bus.h> 64#include <sys/conf.h> 65#include <sys/cpu.h> 66#include <sys/kernel.h> 67#include <sys/proc.h> 68#include <sys/sysctl.h> 69 70#include <machine/bus.h> 71#include <machine/cpu.h> 72#include <machine/hid.h> 73#include <machine/md_var.h> 74#include <machine/smp.h> 75#include <machine/spr.h> 76 77#include <dev/ofw/openfirm.h> 78 79static void cpu_6xx_setup(int cpuid, uint16_t vers); 80static void cpu_970_setup(int cpuid, uint16_t vers); 81static void cpu_booke_setup(int cpuid, uint16_t vers); 82 83int powerpc_pow_enabled; 84void (*cpu_idle_hook)(sbintime_t) = NULL; 85static void cpu_idle_60x(sbintime_t); 86static void cpu_idle_booke(sbintime_t); 87 88struct cputab { 89 const char *name; 90 uint16_t version; 91 uint16_t revfmt; 92 int features; /* Do not include PPC_FEATURE_32 or 93 * PPC_FEATURE_HAS_MMU */ 94 void (*cpu_setup)(int cpuid, uint16_t vers); 95}; 96#define REVFMT_MAJMIN 1 /* %u.%u */ 97#define REVFMT_HEX 2 /* 0x%04x */ 98#define REVFMT_DEC 3 /* %u */ 99static const struct cputab models[] = { 100 { "Motorola PowerPC 601", MPC601, REVFMT_DEC, 101 PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, cpu_6xx_setup }, 102 { "Motorola PowerPC 602", MPC602, REVFMT_DEC, 103 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 104 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN, 105 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 106 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN, 107 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 108 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN, 109 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 110 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN, 111 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 112 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN, 113 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 114 { "Motorola PowerPC 620", MPC620, REVFMT_HEX, 115 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL }, 116 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN, 117 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 118 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN, 119 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 120 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN, 121 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 122 cpu_970_setup }, 123 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN, 124 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 125 cpu_970_setup }, 126 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN, 127 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 128 cpu_970_setup }, 129 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN, 130 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 131 cpu_970_setup }, 132 { "IBM POWER4", IBMPOWER4, REVFMT_MAJMIN, 133 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL }, 134 { "IBM POWER4+", IBMPOWER4PLUS, REVFMT_MAJMIN, 135 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL }, 136 { "IBM POWER5", IBMPOWER5, REVFMT_MAJMIN, 137 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL }, 138 { "IBM POWER5+", IBMPOWER5PLUS, REVFMT_MAJMIN, 139 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL }, 140 { "IBM POWER6", IBMPOWER6, REVFMT_MAJMIN, 141 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 142 NULL }, 143 { "IBM POWER7", IBMPOWER7, REVFMT_MAJMIN, 144 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 145 NULL }, 146 { "IBM POWER7+", IBMPOWER7PLUS, REVFMT_MAJMIN, 147 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 148 NULL }, 149 { "IBM POWER8", IBMPOWER8, REVFMT_MAJMIN, 150 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 151 NULL }, 152 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN, 153 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 154 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN, 155 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 156 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN, 157 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 158 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN, 159 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 160 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN, 161 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 162 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN, 163 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 164 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN, 165 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 166 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN, 167 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 168 { "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN, 169 PPC_FEATURE_HAS_FPU, cpu_6xx_setup }, 170 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN, 171 0, cpu_booke_setup }, 172 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN, 173 0, cpu_booke_setup }, 174 { "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN, 175 0, cpu_booke_setup }, 176 { "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN, 177 0, cpu_booke_setup }, 178 { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN, 179 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 180 NULL}, 181 { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, NULL }, 182}; 183 184static void cpu_6xx_print_cacheinfo(u_int, uint16_t); 185static int cpu_feature_bit(SYSCTL_HANDLER_ARGS); 186 187static char model[64]; 188SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, ""); 189 190int cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU; 191SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLTYPE_INT | CTLFLAG_RD, 192 &cpu_features, sizeof(cpu_features), "IX", "PowerPC CPU features"); 193 194/* Provide some user-friendly aliases for bits in cpu_features */ 195SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD, 196 0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I", 197 "Floating point instructions executed in hardware"); 198SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD, 199 0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec"); 200 201void 202cpu_setup(u_int cpuid) 203{ 204 u_int pvr, maj, min; 205 uint16_t vers, rev, revfmt; 206 uint64_t cps; 207 const struct cputab *cp; 208 const char *name; 209 210 pvr = mfpvr(); 211 vers = pvr >> 16; 212 rev = pvr; 213 switch (vers) { 214 case MPC7410: 215 min = (pvr >> 0) & 0xff; 216 maj = min <= 4 ? 1 : 2; 217 break; 218 case FSL_E500v1: 219 case FSL_E500v2: 220 case FSL_E500mc: 221 case FSL_E5500: 222 maj = (pvr >> 4) & 0xf; 223 min = (pvr >> 0) & 0xf; 224 break; 225 default: 226 maj = (pvr >> 8) & 0xf; 227 min = (pvr >> 0) & 0xf; 228 } 229 230 for (cp = models; cp->version != 0; cp++) { 231 if (cp->version == vers) 232 break; 233 } 234 235 revfmt = cp->revfmt; 236 name = cp->name; 237 if (rev == MPC750 && pvr == 15) { 238 name = "Motorola MPC755"; 239 revfmt = REVFMT_HEX; 240 } 241 strncpy(model, name, sizeof(model) - 1); 242 243 printf("cpu%d: %s revision ", cpuid, name); 244 245 switch (revfmt) { 246 case REVFMT_MAJMIN: 247 printf("%u.%u", maj, min); 248 break; 249 case REVFMT_HEX: 250 printf("0x%04x", rev); 251 break; 252 case REVFMT_DEC: 253 printf("%u", rev); 254 break; 255 } 256 257 if (cpu_est_clockrate(0, &cps) == 0) 258 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100); 259 printf("\n"); 260 261 cpu_features |= cp->features; 262 printf("cpu%d: Features %b\n", cpuid, cpu_features, 263 PPC_FEATURE_BITMASK); 264 265 /* 266 * Configure CPU 267 */ 268 if (cp->cpu_setup != NULL) 269 cp->cpu_setup(cpuid, vers); 270} 271 272/* Get current clock frequency for the given cpu id. */ 273int 274cpu_est_clockrate(int cpu_id, uint64_t *cps) 275{ 276 uint16_t vers; 277 register_t msr; 278 phandle_t cpu, dev, root; 279 int res = 0; 280 char buf[8]; 281 282 vers = mfpvr() >> 16; 283 msr = mfmsr(); 284 mtmsr(msr & ~PSL_EE); 285 286 switch (vers) { 287 case MPC7450: 288 case MPC7455: 289 case MPC7457: 290 case MPC750: 291 case IBM750FX: 292 case MPC7400: 293 case MPC7410: 294 case MPC7447A: 295 case MPC7448: 296 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 297 mtspr(SPR_PMC1, 0); 298 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); 299 DELAY(1000); 300 *cps = (mfspr(SPR_PMC1) * 1000) + 4999; 301 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 302 303 mtmsr(msr); 304 return (0); 305 case IBM970: 306 case IBM970FX: 307 case IBM970MP: 308 isync(); 309 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); 310 isync(); 311 mtspr(SPR_970MMCR1, 0); 312 mtspr(SPR_970MMCRA, 0); 313 mtspr(SPR_970PMC1, 0); 314 mtspr(SPR_970MMCR0, 315 SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES)); 316 isync(); 317 DELAY(1000); 318 powerpc_sync(); 319 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); 320 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999; 321 322 mtmsr(msr); 323 return (0); 324 325 default: 326 root = OF_peer(0); 327 if (root == 0) 328 return (ENXIO); 329 330 dev = OF_child(root); 331 while (dev != 0) { 332 res = OF_getprop(dev, "name", buf, sizeof(buf)); 333 if (res > 0 && strcmp(buf, "cpus") == 0) 334 break; 335 dev = OF_peer(dev); 336 } 337 cpu = OF_child(dev); 338 while (cpu != 0) { 339 res = OF_getprop(cpu, "device_type", buf, 340 sizeof(buf)); 341 if (res > 0 && strcmp(buf, "cpu") == 0) 342 break; 343 cpu = OF_peer(cpu); 344 } 345 if (cpu == 0) 346 return (ENOENT); 347 if (OF_getprop(cpu, "ibm,extended-clock-frequency", 348 cps, sizeof(*cps)) >= 0) { 349 return (0); 350 } else if (OF_getprop(cpu, "clock-frequency", cps, 351 sizeof(cell_t)) >= 0) { 352 *cps >>= 32; 353 return (0); 354 } else { 355 return (ENOENT); 356 } 357 } 358} 359 360void 361cpu_6xx_setup(int cpuid, uint16_t vers) 362{ 363 register_t hid0, pvr; 364 const char *bitmask; 365 366 hid0 = mfspr(SPR_HID0); 367 pvr = mfpvr(); 368 369 /* 370 * Configure power-saving mode. 371 */ 372 switch (vers) { 373 case MPC603: 374 case MPC603e: 375 case MPC603ev: 376 case MPC604ev: 377 case MPC750: 378 case IBM750FX: 379 case MPC7400: 380 case MPC7410: 381 case MPC8240: 382 case MPC8245: 383 /* Select DOZE mode. */ 384 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 385 hid0 |= HID0_DOZE | HID0_DPM; 386 powerpc_pow_enabled = 1; 387 break; 388 389 case MPC7448: 390 case MPC7447A: 391 case MPC7457: 392 case MPC7455: 393 case MPC7450: 394 /* Enable the 7450 branch caches */ 395 hid0 |= HID0_SGE | HID0_BTIC; 396 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 397 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */ 398 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 399 || (pvr >> 16) == MPC7457) 400 hid0 &= ~HID0_BTIC; 401 /* Select NAP mode. */ 402 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 403 hid0 |= HID0_NAP | HID0_DPM; 404 powerpc_pow_enabled = 1; 405 break; 406 407 default: 408 /* No power-saving mode is available. */ ; 409 } 410 411 switch (vers) { 412 case IBM750FX: 413 case MPC750: 414 hid0 &= ~HID0_DBP; /* XXX correct? */ 415 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 416 break; 417 418 case MPC7400: 419 case MPC7410: 420 hid0 &= ~HID0_SPD; 421 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 422 hid0 |= HID0_EIEC; 423 break; 424 425 } 426 427 mtspr(SPR_HID0, hid0); 428 429 if (bootverbose) 430 cpu_6xx_print_cacheinfo(cpuid, vers); 431 432 switch (vers) { 433 case MPC7447A: 434 case MPC7448: 435 case MPC7450: 436 case MPC7455: 437 case MPC7457: 438 bitmask = HID0_7450_BITMASK; 439 break; 440 default: 441 bitmask = HID0_BITMASK; 442 break; 443 } 444 445 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask); 446 447 if (cpu_idle_hook == NULL) 448 cpu_idle_hook = cpu_idle_60x; 449} 450 451 452static void 453cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers) 454{ 455 register_t hid; 456 457 hid = mfspr(SPR_HID0); 458 printf("cpu%u: ", cpuid); 459 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis"); 460 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis"); 461 462 printf("cpu%u: ", cpuid); 463 if (mfspr(SPR_L2CR) & L2CR_L2E) { 464 switch (vers) { 465 case MPC7450: 466 case MPC7455: 467 case MPC7457: 468 printf("256KB L2 cache, "); 469 if (mfspr(SPR_L3CR) & L3CR_L3E) 470 printf("%cMB L3 backside cache", 471 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1'); 472 else 473 printf("L3 cache disabled"); 474 printf("\n"); 475 break; 476 case IBM750FX: 477 printf("512KB L2 cache\n"); 478 break; 479 default: 480 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) { 481 case L2SIZ_256K: 482 printf("256KB "); 483 break; 484 case L2SIZ_512K: 485 printf("512KB "); 486 break; 487 case L2SIZ_1M: 488 printf("1MB "); 489 break; 490 } 491 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT) 492 ? "through" : "back"); 493 if (mfspr(SPR_L2CR) & L2CR_L2PE) 494 printf(", with parity"); 495 printf(" backside cache\n"); 496 break; 497 } 498 } else 499 printf("L2 cache disabled\n"); 500} 501 502static void 503cpu_booke_setup(int cpuid, uint16_t vers) 504{ 505#ifdef BOOKE_E500 506 register_t hid0; 507 508 hid0 = mfspr(SPR_HID0); 509 510 /* Programe power-management mode. */ 511 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 512 hid0 |= HID0_DOZE; 513 514 mtspr(SPR_HID0, hid0); 515 516 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK); 517#endif 518 519 if (cpu_idle_hook == NULL) 520 cpu_idle_hook = cpu_idle_booke; 521} 522 523static void 524cpu_970_setup(int cpuid, uint16_t vers) 525{ 526#ifdef AIM 527 uint32_t hid0_hi, hid0_lo; 528 529 __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;" 530 : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0)); 531 532 /* Configure power-saving mode */ 533 switch (vers) { 534 case IBM970MP: 535 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM); 536 hid0_hi &= ~HID0_DOZE; 537 break; 538 default: 539 hid0_hi |= (HID0_NAP | HID0_DPM); 540 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP); 541 break; 542 } 543 powerpc_pow_enabled = 1; 544 545 __asm __volatile (" \ 546 sync; isync; \ 547 sldi %0,%0,32; or %0,%0,%1; \ 548 mtspr %2, %0; \ 549 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \ 550 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \ 551 sync; isync" 552 :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0)); 553 554 __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;" 555 : "=r" (hid0_hi) : "K" (SPR_HID0)); 556 printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK); 557#endif 558 559 cpu_idle_hook = cpu_idle_60x; 560} 561 562static int 563cpu_feature_bit(SYSCTL_HANDLER_ARGS) 564{ 565 int result; 566 567 result = (cpu_features & arg2) ? 1 : 0; 568 569 return (sysctl_handle_int(oidp, &result, 0, req)); 570} 571 572void 573cpu_idle(int busy) 574{ 575 sbintime_t sbt = -1; 576 577#ifdef INVARIANTS 578 if ((mfmsr() & PSL_EE) != PSL_EE) { 579 struct thread *td = curthread; 580 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr); 581 panic("ints disabled in idleproc!"); 582 } 583#endif 584 585 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 586 busy, curcpu); 587 588 if (cpu_idle_hook != NULL) { 589 if (!busy) { 590 critical_enter(); 591 sbt = cpu_idleclock(); 592 } 593 cpu_idle_hook(sbt); 594 if (!busy) { 595 cpu_activeclock(); 596 critical_exit(); 597 } 598 } 599 600 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 601 busy, curcpu); 602} 603 604int 605cpu_idle_wakeup(int cpu) 606{ 607 return (0); 608} 609 610static void 611cpu_idle_60x(sbintime_t sbt) 612{ 613 register_t msr; 614 uint16_t vers; 615 616 if (!powerpc_pow_enabled) 617 return; 618 619 msr = mfmsr(); 620 vers = mfpvr() >> 16; 621 622#ifdef AIM 623 switch (vers) { 624 case IBM970: 625 case IBM970FX: 626 case IBM970MP: 627 case MPC7447A: 628 case MPC7448: 629 case MPC7450: 630 case MPC7455: 631 case MPC7457: 632 __asm __volatile("\ 633 dssall; sync; mtmsr %0; isync" 634 :: "r"(msr | PSL_POW)); 635 break; 636 default: 637 powerpc_sync(); 638 mtmsr(msr | PSL_POW); 639 isync(); 640 break; 641 } 642#endif 643} 644 645static void 646cpu_idle_booke(sbintime_t sbt) 647{ 648 register_t msr; 649 650 msr = mfmsr(); 651 652#ifdef E500 653 /* Freescale E500 core RM section 6.4.1. */ 654 __asm __volatile("msync; mtmsr %0; isync" :: 655 "r" (msr | PSL_WE)); 656#endif 657} 658 659