viareg.h revision 260674 
1/*-
2 * Copyright (C) 2008 Nathan Whitehorn
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * $FreeBSD: stable/10/sys/powerpc/powermac/viareg.h 260674 2014-01-15 06:17:15Z jhibbits $
26 */
27
28#ifndef	_POWERPC_VIAREG_H_
29#define	_POWERPC_VIAREG_H_
30
31/* VIA interface registers */
32#define vBufB		0x0000	/* register B */
33#define vDirB		0x0400	/* data direction register */
34#define vDirA		0x0600	/* data direction register */
35#define vT1C		0x0800	/* Timer 1 counter Lo */
36#define vT1CH		0x0a00	/* Timer 1 counter Hi */
37#define vSR		0x1400	/* shift register */
38#define vACR		0x1600	/* aux control register */
39#define vPCR		0x1800	/* peripheral control register */
40#define vIFR		0x1a00	/* interrupt flag register */
41#define vIER		0x1c00	/* interrupt enable register */
42#define vBufA		0x1e00	/* register A */
43
44#define vPB		0x0000
45#define vPB3		0x08
46#define vPB4		0x10
47#define vPB5		0x20
48#define vSR_INT		0x04
49#define vSR_OUT		0x10
50
51#endif /* _POWERPC_VIAREG_H_ */
52