1139825Simp/*- 299663Sbenno * Copyright (C) 2002 Benno Rice. 399663Sbenno * All rights reserved. 499663Sbenno * 599663Sbenno * Redistribution and use in source and binary forms, with or without 699663Sbenno * modification, are permitted provided that the following conditions 799663Sbenno * are met: 899663Sbenno * 1. Redistributions of source code must retain the above copyright 999663Sbenno * notice, this list of conditions and the following disclaimer. 1099663Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1199663Sbenno * notice, this list of conditions and the following disclaimer in the 1299663Sbenno * documentation and/or other materials provided with the distribution. 1399663Sbenno * 1499663Sbenno * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 1599663Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1699663Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1799663Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 1899663Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 1999663Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2099663Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2199663Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2299663Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 2399663Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2499663Sbenno * 2599663Sbenno * $FreeBSD$ 2699663Sbenno */ 2799663Sbenno 2899663Sbenno#ifndef _POWERPC_POWERMAC_UNINORTHVAR_H_ 2999663Sbenno#define _POWERPC_POWERMAC_UNINORTHVAR_H_ 3099663Sbenno 31260674Sjhibbits#include <dev/ofw/ofw_bus_subr.h> 32260674Sjhibbits#include <dev/ofw/ofw_pci.h> 33230993Snwhitehorn#include <powerpc/ofw/ofw_pci.h> 3499663Sbenno 3599663Sbennostruct uninorth_softc { 36230993Snwhitehorn struct ofw_pci_softc pci_sc; 3799663Sbenno vm_offset_t sc_addr; 3899663Sbenno vm_offset_t sc_data; 39208149Snwhitehorn int sc_ver; 4099663Sbenno}; 4199663Sbenno 42103618Sgrehanstruct unin_chip_softc { 43266019Sian uint64_t sc_physaddr; 44266019Sian uint64_t sc_size; 45103618Sgrehan vm_offset_t sc_addr; 46208149Snwhitehorn struct rman sc_mem_rman; 47103618Sgrehan int sc_version; 48103618Sgrehan}; 49103618Sgrehan 50103618Sgrehan/* 51208149Snwhitehorn * Format of a unin reg property entry. 52208149Snwhitehorn */ 53208149Snwhitehornstruct unin_chip_reg { 54208149Snwhitehorn u_int32_t mr_base; 55208149Snwhitehorn u_int32_t mr_size; 56208149Snwhitehorn}; 57208149Snwhitehorn 58208149Snwhitehorn/* 59208149Snwhitehorn * Per unin device structure. 60208149Snwhitehorn */ 61208149Snwhitehornstruct unin_chip_devinfo { 62208149Snwhitehorn int udi_interrupts[6]; 63208149Snwhitehorn int udi_ninterrupts; 64208149Snwhitehorn int udi_base; 65208149Snwhitehorn struct ofw_bus_devinfo udi_obdinfo; 66208149Snwhitehorn struct resource_list udi_resources; 67208149Snwhitehorn}; 68208149Snwhitehorn 69208149Snwhitehorn/* 70103618Sgrehan * Version register 71103618Sgrehan */ 72103618Sgrehan#define UNIN_VERS 0x0 73103618Sgrehan 74103618Sgrehan/* 75103618Sgrehan * Clock-control register 76103618Sgrehan */ 77208149Snwhitehorn#define UNIN_CLOCKCNTL 0x20 78208149Snwhitehorn#define UNIN_CLOCKCNTL_GMAC 0x2 79103618Sgrehan 80208149Snwhitehorn/* 81260674Sjhibbits * Power management register 82260674Sjhibbits */ 83260674Sjhibbits#define UNIN_PWR_MGMT 0x30 84260674Sjhibbits#define UNIN_PWR_NORMAL 0x00 85260674Sjhibbits#define UNIN_PWR_IDLE2 0x01 86260674Sjhibbits#define UNIN_PWR_SLEEP 0x02 87260674Sjhibbits#define UNIN_PWR_SAVE 0x03 88260674Sjhibbits#define UNIN_PWR_MASK 0x03 89260674Sjhibbits 90260674Sjhibbits/* 91260674Sjhibbits * Hardware initialization state register 92260674Sjhibbits */ 93260674Sjhibbits#define UNIN_HWINIT_STATE 0x70 94260674Sjhibbits#define UNIN_SLEEPING 0x01 95260674Sjhibbits#define UNIN_RUNNING 0x02 96260674Sjhibbits 97260674Sjhibbits 98260674Sjhibbits/* 99208149Snwhitehorn * Toggle registers 100208149Snwhitehorn */ 101208149Snwhitehorn#define UNIN_TOGGLE_REG 0xe0 102208149Snwhitehorn#define UNIN_MPIC_RESET 0x2 103208149Snwhitehorn#define UNIN_MPIC_OUTPUT_ENABLE 0x4 104208149Snwhitehorn 105260674Sjhibbitsextern int unin_chip_sleep(device_t dev, int idle); 106260674Sjhibbitsextern int unin_chip_wake(device_t dev); 107103618Sgrehan#endif /* _POWERPC_POWERMAC_UNINORTHVAR_H_ */ 108