platform_mpc85xx.c revision 266003 
1/*-
2 * Copyright (c) 2008-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/10/sys/powerpc/mpc85xx/platform_mpc85xx.c 266003 2014-05-14 04:14:58Z ian $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/bus.h>
34#include <sys/pcpu.h>
35#include <sys/proc.h>
36#include <sys/smp.h>
37
38#include <machine/bus.h>
39#include <machine/cpu.h>
40#include <machine/hid.h>
41#include <machine/platform.h>
42#include <machine/platformvar.h>
43#include <machine/smp.h>
44#include <machine/spr.h>
45#include <machine/vmparam.h>
46
47#include <dev/fdt/fdt_common.h>
48#include <dev/ofw/ofw_bus.h>
49#include <dev/ofw/ofw_bus_subr.h>
50#include <dev/ofw/openfirm.h>
51
52#include <vm/vm.h>
53#include <vm/pmap.h>
54
55#include <powerpc/mpc85xx/mpc85xx.h>
56
57#include "platform_if.h"
58
59#ifdef SMP
60extern void *ap_pcpu;
61extern vm_paddr_t kernload;		/* Kernel physical load address */
62extern uint8_t __boot_page[];		/* Boot page body */
63extern uint32_t bp_ntlb1s;
64extern uint32_t bp_tlb1[];
65extern uint32_t bp_tlb1_end[];
66#endif
67
68extern uint32_t *bootinfo;
69vm_offset_t ccsrbar_va;
70
71static int cpu, maxcpu;
72
73static int mpc85xx_probe(platform_t);
74static int mpc85xx_attach(platform_t);
75static void mpc85xx_mem_regions(platform_t, struct mem_region **phys,
76    int *physsz, struct mem_region **avail, int *availsz);
77static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref);
78static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref);
79static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref);
80static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref);
81static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu);
82
83static void mpc85xx_reset(platform_t);
84
85static platform_method_t mpc85xx_methods[] = {
86	PLATFORMMETHOD(platform_probe,		mpc85xx_probe),
87	PLATFORMMETHOD(platform_attach,		mpc85xx_attach),
88	PLATFORMMETHOD(platform_mem_regions,	mpc85xx_mem_regions),
89	PLATFORMMETHOD(platform_timebase_freq,	mpc85xx_timebase_freq),
90
91	PLATFORMMETHOD(platform_smp_first_cpu,	mpc85xx_smp_first_cpu),
92	PLATFORMMETHOD(platform_smp_next_cpu,	mpc85xx_smp_next_cpu),
93	PLATFORMMETHOD(platform_smp_get_bsp,	mpc85xx_smp_get_bsp),
94	PLATFORMMETHOD(platform_smp_start_cpu,	mpc85xx_smp_start_cpu),
95
96	PLATFORMMETHOD(platform_reset,		mpc85xx_reset),
97
98	PLATFORMMETHOD_END
99};
100
101static platform_def_t mpc85xx_platform = {
102	"mpc85xx",
103	mpc85xx_methods,
104	0
105};
106
107PLATFORM_DEF(mpc85xx_platform);
108
109static int
110mpc85xx_probe(platform_t plat)
111{
112	u_int pvr = mfpvr() >> 16;
113
114	if ((pvr & 0xfff0) == FSL_E500v1)
115		return (BUS_PROBE_DEFAULT);
116
117	return (ENXIO);
118}
119
120static int
121mpc85xx_attach(platform_t plat)
122{
123	phandle_t cpus, child, ccsr;
124	const char *soc_name_guesses[] = {"/soc", "soc", NULL};
125	const char **name;
126	pcell_t ranges[6], acells, pacells, scells;
127	uint32_t sr;
128	uint64_t ccsrbar, ccsrsize;
129	int i, law_max, tgt;
130
131	if ((cpus = OF_finddevice("/cpus")) != -1) {
132		for (maxcpu = 0, child = OF_child(cpus); child != 0;
133		    child = OF_peer(child), maxcpu++)
134			;
135	} else
136		maxcpu = 1;
137
138	/*
139	 * Locate CCSR region. Irritatingly, there is no way to find it
140	 * unless you already know where it is. Try to infer its location
141	 * from the device tree.
142	 */
143
144	ccsr = -1;
145	for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++)
146		ccsr = OF_finddevice(*name);
147	if (ccsr == -1) {
148		char type[64];
149
150	 	/* That didn't work. Search for devices of type "soc" */
151		child = OF_child(OF_peer(0));
152		for (OF_child(child); child != 0; child = OF_peer(child)) {
153			if (OF_getprop(child, "device_type", type, sizeof(type))
154			    <= 0)
155				continue;
156
157			if (strcmp(type, "soc") == 0) {
158				ccsr = child;
159				break;
160			}
161		}
162	}
163
164	if (ccsr == -1)
165		panic("Could not locate CCSR window!");
166
167	OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells));
168	OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells));
169	OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells,
170	    sizeof(pacells));
171	OF_getprop(ccsr, "ranges", ranges, sizeof(ranges));
172	ccsrbar = ccsrsize = 0;
173	for (i = acells; i < acells + pacells; i++) {
174		ccsrbar <<= 32;
175		ccsrbar |= ranges[i];
176	}
177	for (i = acells + pacells; i < acells + pacells + scells; i++) {
178		ccsrsize <<= 32;
179		ccsrsize |= ranges[i];
180	}
181	ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
182
183	/*
184	 * Clear local access windows. Skip DRAM entries, so we don't shoot
185	 * ourselves in the foot.
186	 */
187	law_max = law_getmax();
188	for (i = 0; i < law_max; i++) {
189		sr = ccsr_read4(OCP85XX_LAWSR(i));
190		if ((sr & 0x80000000) == 0)
191			continue;
192		tgt = (sr & 0x01f00000) >> 20;
193		if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
194		    tgt == OCP85XX_TGTIF_RAM_INTL)
195			continue;
196
197		ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
198	}
199
200	return (0);
201}
202
203void
204mpc85xx_mem_regions(platform_t plat, struct mem_region **phys, int *physsz,
205    struct mem_region **avail, int *availsz)
206{
207
208	ofw_mem_regions(phys, physsz, avail, availsz);
209}
210
211static u_long
212mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref)
213{
214	u_long ticks;
215	phandle_t cpus, child;
216	pcell_t freq;
217
218	if (bootinfo != NULL) {
219		if (bootinfo[0] == 1) {
220			/* Backward compatibility. See 8-STABLE. */
221			ticks = bootinfo[3] >> 3;
222		} else {
223			/* Compatibility with Juniper's loader. */
224			ticks = bootinfo[5] >> 3;
225		}
226	} else
227		ticks = 0;
228
229	if ((cpus = OF_finddevice("/cpus")) == -1)
230		goto out;
231
232	if ((child = OF_child(cpus)) == 0)
233		goto out;
234
235	switch (OF_getproplen(child, "timebase-frequency")) {
236	case 4:
237	{
238		uint32_t tbase;
239		OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
240		ticks = tbase;
241		return (ticks);
242	}
243	case 8:
244	{
245		uint64_t tbase;
246		OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
247		ticks = tbase;
248		return (ticks);
249	}
250	default:
251		break;
252	}
253
254	freq = 0;
255	if (OF_getprop(child, "bus-frequency", (void *)&freq,
256	    sizeof(freq)) <= 0)
257		goto out;
258
259	/*
260	 * Time Base and Decrementer are updated every 8 CCB bus clocks.
261	 * HID0[SEL_TBCLK] = 0
262	 */
263	if (freq != 0)
264		ticks = freq / 8;
265
266out:
267	if (ticks <= 0)
268		panic("Unable to determine timebase frequency!");
269
270	return (ticks);
271}
272
273static int
274mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
275{
276
277	cpu = 0;
278	cpuref->cr_cpuid = cpu;
279	cpuref->cr_hwref = cpuref->cr_cpuid;
280	if (bootverbose)
281		printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
282	cpu++;
283
284	return (0);
285}
286
287static int
288mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
289{
290
291	if (cpu >= maxcpu)
292		return (ENOENT);
293
294	cpuref->cr_cpuid = cpu++;
295	cpuref->cr_hwref = cpuref->cr_cpuid;
296	if (bootverbose)
297		printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
298
299	return (0);
300}
301
302static int
303mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
304{
305
306	cpuref->cr_cpuid = mfspr(SPR_PIR);
307	cpuref->cr_hwref = cpuref->cr_cpuid;
308
309	return (0);
310}
311
312static int
313mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
314{
315#ifdef SMP
316	uint32_t *tlb1;
317	uint32_t bptr, eebpcr;
318	int i, timeout;
319
320	eebpcr = ccsr_read4(OCP85XX_EEBPCR);
321	if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) {
322		printf("SMP: CPU %d already out of hold-off state!\n",
323		    pc->pc_cpuid);
324		return (ENXIO);
325	}
326
327	ap_pcpu = pc;
328
329	i = 0;
330	tlb1 = bp_tlb1;
331	while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) {
332		mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i));
333		__asm __volatile("isync; tlbre");
334		tlb1[0] = mfspr(SPR_MAS1);
335		tlb1[1] = mfspr(SPR_MAS2);
336		tlb1[2] = mfspr(SPR_MAS3);
337		i++;
338		tlb1 += 3;
339	}
340	if (i < bp_ntlb1s)
341		bp_ntlb1s = i;
342
343	/*
344	 * Set BPTR to the physical address of the boot page
345	 */
346	bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
347	KASSERT((bptr & 0xfff) == 0,
348	    ("%s: boot page is not aligned (%#x)", __func__, bptr));
349	bptr = (bptr >> 12) | 0x80000000u;
350	ccsr_write4(OCP85XX_BPTR, bptr);
351	__asm __volatile("isync; msync");
352
353	/* Flush caches to have our changes hit DRAM. */
354	cpu_flush_dcache(__boot_page, 4096);
355
356	/*
357	 * Release AP from hold-off state
358	 */
359	eebpcr |= (1 << (pc->pc_cpuid + 24));
360	ccsr_write4(OCP85XX_EEBPCR, eebpcr);
361	__asm __volatile("isync; msync");
362
363	timeout = 500;
364	while (!pc->pc_awake && timeout--)
365		DELAY(1000);	/* wait 1ms */
366
367	/*
368	 * Disable boot page translation so that the 4K page at the default
369	 * address (= 0xfffff000) isn't permanently remapped and thus not
370	 * usable otherwise.
371	 */
372	ccsr_write4(OCP85XX_BPTR, 0);
373	__asm __volatile("isync; msync");
374
375	if (!pc->pc_awake)
376		printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
377	return ((pc->pc_awake) ? 0 : EBUSY);
378#else
379	/* No SMP support */
380	return (ENXIO);
381#endif
382}
383
384static void
385mpc85xx_reset(platform_t plat)
386{
387
388	/*
389	 * Try the dedicated reset register first.
390	 * If the SoC doesn't have one, we'll fall
391	 * back to using the debug control register.
392	 */
393	ccsr_write4(OCP85XX_RSTCR, 2);
394
395	/* Clear DBCR0, disables debug interrupts and events. */
396	mtspr(SPR_DBCR0, 0);
397	__asm __volatile("isync");
398
399	/* Enable Debug Interrupts in MSR. */
400	mtmsr(mfmsr() | PSL_DE);
401
402	/* Enable debug interrupts and issue reset. */
403	mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
404
405	printf("Reset failed...\n");
406	while (1)
407		;
408}
409
410