1236121Sraj/*-
2236121Sraj * Copyright (c) 2011-2012 Semihalf
3236121Sraj * All rights reserved.
4236121Sraj *
5236121Sraj * Redistribution and use in source and binary forms, with or without
6236121Sraj * modification, are permitted provided that the following conditions
7236121Sraj * are met:
8236121Sraj * 1. Redistributions of source code must retain the above copyright
9236121Sraj *    notice, this list of conditions and the following disclaimer.
10236121Sraj * 2. Redistributions in binary form must reproduce the above copyright
11236121Sraj *    notice, this list of conditions and the following disclaimer in the
12236121Sraj *    documentation and/or other materials provided with the distribution.
13236121Sraj *
14236121Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15236121Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16236121Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17236121Sraj * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18236121Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19236121Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20236121Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21236121Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22236121Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23236121Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24236121Sraj * SUCH DAMAGE.
25236121Sraj *
26236121Sraj * $FreeBSD: stable/10/sys/powerpc/mpc85xx/fsl_sdhc.h 321946 2017-08-02 20:27:30Z marius $
27236121Sraj */
28236121Sraj
29236121Sraj#ifndef FSL_SDHC_H_
30236121Sraj#define FSL_SDHC_H_
31236121Sraj
32236121Sraj#include <sys/cdefs.h>
33236121Sraj
34236121Sraj#include <sys/param.h>
35236121Sraj#include <sys/bus.h>
36236121Sraj#include <sys/kernel.h>
37236121Sraj#include <sys/lock.h>
38236121Sraj#include <sys/module.h>
39236121Sraj#include <sys/mutex.h>
40236121Sraj#include <sys/rman.h>
41236121Sraj#include <sys/sysctl.h>
42236121Sraj#include <sys/systm.h>
43236121Sraj#include <sys/taskqueue.h>
44236121Sraj
45236121Sraj#include <machine/bus.h>
46236121Sraj
47236121Sraj#include <dev/mmc/bridge.h>
48236121Sraj#include <dev/mmc/mmcreg.h>
49236121Sraj#include <dev/mmc/mmcbrvar.h>
50236121Sraj
51236121Sraj/*****************************************************************************
52236121Sraj * Private defines
53236121Sraj *****************************************************************************/
54236121Srajstruct slot {
55236121Sraj	uint32_t	clock;
56236121Sraj};
57236121Sraj
58236121Srajstruct fsl_sdhc_softc {
59236121Sraj	device_t		self;
60236121Sraj	device_t		child;
61236121Sraj
62236121Sraj	bus_space_handle_t	bsh;
63236121Sraj	bus_space_tag_t		bst;
64236121Sraj
65236121Sraj	struct resource		*mem_resource;
66236121Sraj	int			mem_rid;
67236121Sraj	struct resource		*irq_resource;
68236121Sraj	int			irq_rid;
69236121Sraj	void			*ihl;
70236121Sraj
71236121Sraj	bus_dma_tag_t		dma_tag;
72236121Sraj	bus_dmamap_t		dma_map;
73236121Sraj	uint32_t*		dma_mem;
74236121Sraj	bus_addr_t		dma_phys;
75236121Sraj
76236121Sraj	struct mtx		mtx;
77236121Sraj
78236121Sraj	struct task		card_detect_task;
79236121Sraj	struct callout		card_detect_callout;
80236121Sraj
81236121Sraj	struct mmc_host		mmc_host;
82236121Sraj
83236121Sraj	struct slot		slot;
84236121Sraj	uint32_t		bus_busy;
85236121Sraj	uint32_t		platform_clock;
86236121Sraj
87236121Sraj	struct mmc_request	*request;
88236121Sraj	int			data_done;
89236121Sraj	int			command_done;
90236121Sraj	int			use_dma;
91236121Sraj	uint32_t*		data_ptr;
92236121Sraj	uint32_t		data_offset;
93236121Sraj};
94236121Sraj
95236121Sraj#define FSL_SDHC_RESET_DELAY 50
96236121Sraj
97236121Sraj#define	FSL_SDHC_BASE_CLOCK_DIV		(2)
98236121Sraj#define	FSL_SDHC_MAX_DIV		(FSL_SDHC_BASE_CLOCK_DIV * 256 * 16)
99236121Sraj#define	FSL_SDHC_MIN_DIV		(FSL_SDHC_BASE_CLOCK_DIV * 2)
100236121Sraj#define	FSL_SDHC_MAX_CLOCK		(50000000)
101236121Sraj
102236121Sraj#define	FSL_SDHC_MAX_BLOCK_COUNT	(65535)
103236121Sraj#define	FSL_SDHC_MAX_BLOCK_SIZE		(4096)
104236121Sraj
105236121Sraj#define FSL_SDHC_FIFO_BUF_SIZE		(64)	/* Water-mark level. */
106236121Sraj#define FSL_SDHC_FIFO_BUF_WORDS		(FSL_SDHC_FIFO_BUF_SIZE / 4)
107236121Sraj
108236121Sraj#define FSL_SDHC_DMA_SEGMENT_SIZE	(1024)
109236121Sraj#define	FSL_SDHC_DMA_ALIGNMENT		(4)
110236121Sraj#define	FSL_SDHC_DMA_BLOCK_SIZE		FSL_SDHC_MAX_BLOCK_SIZE
111236121Sraj
112236121Sraj/*
113236121Sraj * Offsets of SD HC registers
114236121Sraj */
115236121Srajenum sdhc_reg_off {
116236121Sraj	SDHC_DSADDR	= 0x000,
117236121Sraj	SDHC_BLKATTR	= 0x004,
118236121Sraj	SDHC_CMDARG	= 0x008,
119236121Sraj	SDHC_XFERTYP	= 0x00c,
120236121Sraj	SDHC_CMDRSP0	= 0x010,
121236121Sraj	SDHC_CMDRSP1	= 0x014,
122236121Sraj	SDHC_CMDRSP2	= 0x018,
123236121Sraj	SDHC_CMDRSP3	= 0x01c,
124236121Sraj	SDHC_DATPORT	= 0x020,
125236121Sraj	SDHC_PRSSTAT	= 0x024,
126236121Sraj	SDHC_PROCTL	= 0x028,
127236121Sraj	SDHC_SYSCTL	= 0x02c,
128236121Sraj	SDHC_IRQSTAT	= 0x030,
129236121Sraj	SDHC_IRQSTATEN	= 0x034,
130236121Sraj	SDHC_IRQSIGEN	= 0x038,
131236121Sraj	SDHC_AUTOC12ERR	= 0x03c,
132236121Sraj	SDHC_HOSTCAPBLT	= 0x040,
133236121Sraj	SDHC_WML	= 0x044,
134236121Sraj	SDHC_FEVT	= 0x050,
135236121Sraj	SDHC_HOSTVER	= 0x0fc,
136236121Sraj	SDHC_DCR	= 0x40c
137236121Sraj};
138236121Sraj
139236121Srajenum sysctl_bit {
140236121Sraj	SYSCTL_INITA	= 0x08000000,
141236121Sraj	SYSCTL_RSTD	= 0x04000000,
142236121Sraj	SYSCTL_RSTC	= 0x02000000,
143236121Sraj	SYSCTL_RSTA	= 0x01000000,
144236121Sraj	SYSCTL_DTOCV	= 0x000f0000,
145236121Sraj	SYSCTL_SDCLKFS	= 0x0000ff00,
146236121Sraj	SYSCTL_DVS	= 0x000000f0,
147236121Sraj	SYSCTL_PEREN	= 0x00000004,
148236121Sraj	SYSCTL_HCKEN	= 0x00000002,
149236121Sraj	SYSCTL_IPGEN	= 0x00000001
150236121Sraj};
151236121Sraj
152236121Sraj#define HEX_LEFT_SHIFT(x)	(4 * x)
153236121Srajenum sysctl_shift {
154236121Sraj	SHIFT_DTOCV	= HEX_LEFT_SHIFT(4),
155236121Sraj	SHIFT_SDCLKFS	= HEX_LEFT_SHIFT(2),
156236121Sraj	SHIFT_DVS	= HEX_LEFT_SHIFT(1)
157236121Sraj};
158236121Sraj
159236121Srajenum proctl_bit {
160236121Sraj	PROCTL_WECRM	= 0x04000000,
161236121Sraj	PROCTL_WECINS	= 0x02000000,
162236121Sraj	PROCTL_WECINT	= 0x01000000,
163236121Sraj	PROCTL_RWCTL	= 0x00040000,
164236121Sraj	PROCTL_CREQ	= 0x00020000,
165236121Sraj	PROCTL_SABGREQ	= 0x00010000,
166236121Sraj	PROCTL_CDSS	= 0x00000080,
167236121Sraj	PROCTL_CDTL	= 0x00000040,
168236121Sraj	PROCTL_EMODE	= 0x00000030,
169236121Sraj	PROCTL_D3CD	= 0x00000008,
170236121Sraj	PROCTL_DTW	= 0x00000006
171236121Sraj};
172236121Sraj
173236121Srajenum dtw {
174236121Sraj	DTW_1	= 0x00000000,
175236121Sraj	DTW_4	= 0x00000002,
176236121Sraj	DTW_8	= 0x00000004
177236121Sraj};
178236121Sraj
179236121Srajenum prsstat_bit {
180236121Sraj	PRSSTAT_DLSL	= 0xff000000,
181236121Sraj	PRSSTAT_CLSL	= 0x00800000,
182236121Sraj	PRSSTAT_WPSPL	= 0x00080000,
183236121Sraj	PRSSTAT_CDPL	= 0x00040000,
184236121Sraj	PRSSTAT_CINS	= 0x00010000,
185236121Sraj	PRSSTAT_BREN	= 0x00000800,
186236121Sraj	PRSSTAT_BWEN	= 0x00000400,
187236121Sraj	PRSSTAT_RTA	= 0x00000200,
188236121Sraj	PRSSTAT_WTA	= 0x00000100,
189236121Sraj	PRSSTAT_SDOFF	= 0x00000080,
190236121Sraj	PRSSTAT_PEROFF	= 0x00000040,
191236121Sraj	PRSSTAT_HCKOFF	= 0x00000020,
192236121Sraj	PRSSTAT_IPGOFF	= 0x00000010,
193236121Sraj	PRSSTAT_DLA	= 0x00000004,
194236121Sraj	PRSSTAT_CDIHB	= 0x00000002,
195236121Sraj	PRSSTAT_CIHB	= 0x00000001
196236121Sraj
197236121Sraj};
198236121Sraj
199236121Srajenum irq_bits {
200236121Sraj	IRQ_DMAE	= 0x10000000,
201236121Sraj	IRQ_AC12E	= 0x01000000,
202236121Sraj	IRQ_DEBE	= 0x00400000,
203236121Sraj	IRQ_DCE		= 0x00200000,
204236121Sraj	IRQ_DTOE	= 0x00100000,
205236121Sraj	IRQ_CIE		= 0x00080000,
206236121Sraj	IRQ_CEBE	= 0x00040000,
207236121Sraj	IRQ_CCE		= 0x00020000,
208236121Sraj	IRQ_CTOE	= 0x00010000,
209236121Sraj	IRQ_CINT	= 0x00000100,
210236121Sraj	IRQ_CRM		= 0x00000080,
211236121Sraj	IRQ_CINS	= 0x00000040,
212236121Sraj	IRQ_BRR		= 0x00000020,
213236121Sraj	IRQ_BWR		= 0x00000010,
214236121Sraj	IRQ_DINT	= 0x00000008,
215236121Sraj	IRQ_BGE		= 0x00000004,
216236121Sraj	IRQ_TC		= 0x00000002,
217236121Sraj	IRQ_CC		= 0x00000001
218236121Sraj};
219236121Sraj
220236121Srajenum irq_masks {
221236121Sraj	IRQ_ERROR_DATA_MASK	= IRQ_DMAE | IRQ_DEBE | IRQ_DCE | IRQ_DTOE,
222236121Sraj	IRQ_ERROR_CMD_MASK	= IRQ_AC12E | IRQ_CIE | IRQ_CTOE | IRQ_CCE |
223236121Sraj				  IRQ_CEBE
224236121Sraj};
225236121Sraj
226236121Srajenum dcr_bits {
227236121Sraj	DCR_PRI			= 0x0000c000,
228236121Sraj	DCR_SNOOP		= 0x00000040,
229236121Sraj	DCR_AHB2MAG_BYPASS	= 0x00000020,
230236121Sraj	DCR_RD_SAFE		= 0x00000004,
231236121Sraj	DCR_RD_PFE		= 0x00000002,
232236121Sraj	DCR_RD_PF_SIZE		= 0x00000001
233236121Sraj};
234236121Sraj
235236121Sraj#define	DCR_PRI_SHIFT	(14)
236236121Sraj
237236121Srajenum xfertyp_bits {
238236121Sraj	XFERTYP_CMDINX	= 0x3f000000,
239236121Sraj	XFERTYP_CMDTYP	= 0x00c00000,
240236121Sraj	XFERTYP_DPSEL	= 0x00200000,
241236121Sraj	XFERTYP_CICEN	= 0x00100000,
242236121Sraj	XFERTYP_CCCEN	= 0x00080000,
243236121Sraj	XFERTYP_RSPTYP	= 0x00030000,
244236121Sraj	XFERTYP_MSBSEL	= 0x00000020,
245236121Sraj	XFERTYP_DTDSEL	= 0x00000010,
246236121Sraj	XFERTYP_AC12EN	= 0x00000004,
247236121Sraj	XFERTYP_BCEN	= 0x00000002,
248236121Sraj	XFERTYP_DMAEN	= 0x00000001
249236121Sraj};
250236121Sraj
251236121Sraj#define	CMDINX_SHIFT	(24)
252236121Sraj
253236121Srajenum xfertyp_cmdtyp {
254236121Sraj	CMDTYP_NORMAL	= 0x00000000,
255236121Sraj	CMDYTP_SUSPEND	= 0x00400000,
256236121Sraj	CMDTYP_RESUME	= 0x00800000,
257236121Sraj	CMDTYP_ABORT	= 0x00c00000
258236121Sraj};
259236121Sraj
260236121Srajenum xfertyp_rsptyp {
261236121Sraj	RSPTYP_NONE	= 0x00000000,
262236121Sraj	RSPTYP_136	= 0x00010000,
263236121Sraj	RSPTYP_48	= 0x00020000,
264236121Sraj	RSPTYP_48_BUSY	= 0x00030000
265236121Sraj};
266236121Sraj
267236121Srajenum blkattr_bits {
268236121Sraj	BLKATTR_BLKSZE	= 0x00001fff,
269236121Sraj	BLKATTR_BLKCNT	= 0xffff0000
270236121Sraj};
271236121Sraj#define	BLKATTR_BLOCK_COUNT(x)	(x << 16)
272236121Sraj
273236121Srajenum wml_bits {
274236121Sraj	WR_WML	= 0x00ff0000,
275236121Sraj	RD_WML	= 0x000000ff,
276236121Sraj};
277236121Sraj
278236121Srajenum sdhc_bit_mask {
279236121Sraj	MASK_CLOCK_CONTROL	= 0x0000ffff,
280236121Sraj	MASK_IRQ_ALL		= IRQ_DMAE | IRQ_AC12E | IRQ_DEBE | IRQ_DCE |
281236121Sraj				  IRQ_DTOE | IRQ_CIE | IRQ_CEBE | IRQ_CCE |
282236121Sraj				  IRQ_CTOE | IRQ_CINT | IRQ_CRM | IRQ_CINS |
283236121Sraj				  IRQ_BRR | IRQ_BWR | IRQ_DINT | IRQ_BGE |
284236121Sraj				  IRQ_TC | IRQ_CC,
285236121Sraj};
286236121Sraj
287236121Srajenum sdhc_line {
288236121Sraj	SDHC_DAT_LINE	= 0x2,
289236121Sraj	SDHC_CMD_LINE	= 0x1
290236121Sraj};
291236121Sraj
292236121Sraj#endif /* FSL_SDHC_H_ */
293