machdep_e500.c revision 236324
1236324Sraj/*- 2236324Sraj * Copyright (c) 2011-2012 Semihalf. 3236324Sraj * All rights reserved. 4236324Sraj * 5236324Sraj * Redistribution and use in source and binary forms, with or without 6236324Sraj * modification, are permitted provided that the following conditions 7236324Sraj * are met: 8236324Sraj * 1. Redistributions of source code must retain the above copyright 9236324Sraj * notice, this list of conditions and the following disclaimer. 10236324Sraj * 2. Redistributions in binary form must reproduce the above copyright 11236324Sraj * notice, this list of conditions and the following disclaimer in the 12236324Sraj * documentation and/or other materials provided with the distribution. 13236324Sraj * 14236324Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15236324Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16236324Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17236324Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18236324Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19236324Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20236324Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21236324Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22236324Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23236324Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24236324Sraj * SUCH DAMAGE. 25236324Sraj */ 26236324Sraj 27236324Sraj#include <sys/cdefs.h> 28236324Sraj__FBSDID("$FreeBSD: head/sys/powerpc/booke/machdep_e500.c 236324 2012-05-30 17:34:40Z raj $"); 29236324Sraj 30236324Sraj#include <sys/types.h> 31236324Sraj#include <sys/reboot.h> 32236324Sraj 33236324Sraj#include <machine/machdep.h> 34236324Sraj 35236324Sraj#include <dev/fdt/fdt_common.h> 36236324Sraj 37236324Sraj#include <powerpc/mpc85xx/mpc85xx.h> 38236324Sraj 39236324Srajextern void dcache_enable(void); 40236324Srajextern void dcache_inval(void); 41236324Srajextern void icache_enable(void); 42236324Srajextern void icache_inval(void); 43236324Srajextern void l2cache_enable(void); 44236324Srajextern void l2cache_inval(void); 45236324Sraj 46236324Srajvoid 47236324Srajbooke_init_tlb(vm_paddr_t fdt_immr_pa) 48236324Sraj{ 49236324Sraj 50236324Sraj /* Initialize TLB1 handling */ 51236324Sraj tlb1_init(fdt_immr_pa); 52236324Sraj} 53236324Sraj 54236324Srajvoid 55236324Srajbooke_enable_l1_cache(void) 56236324Sraj{ 57236324Sraj uint32_t csr; 58236324Sraj 59236324Sraj /* Enable D-cache if applicable */ 60236324Sraj csr = mfspr(SPR_L1CSR0); 61236324Sraj if ((csr & L1CSR0_DCE) == 0) { 62236324Sraj dcache_inval(); 63236324Sraj dcache_enable(); 64236324Sraj } 65236324Sraj 66236324Sraj csr = mfspr(SPR_L1CSR0); 67236324Sraj if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) 68236324Sraj printf("L1 D-cache %sabled\n", 69236324Sraj (csr & L1CSR0_DCE) ? "en" : "dis"); 70236324Sraj 71236324Sraj /* Enable L1 I-cache if applicable. */ 72236324Sraj csr = mfspr(SPR_L1CSR1); 73236324Sraj if ((csr & L1CSR1_ICE) == 0) { 74236324Sraj icache_inval(); 75236324Sraj icache_enable(); 76236324Sraj } 77236324Sraj 78236324Sraj csr = mfspr(SPR_L1CSR1); 79236324Sraj if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) 80236324Sraj printf("L1 I-cache %sabled\n", 81236324Sraj (csr & L1CSR1_ICE) ? "en" : "dis"); 82236324Sraj} 83236324Sraj 84236324Sraj#if 0 85236324Srajvoid 86236324Srajbooke_enable_l2_cache(void) 87236324Sraj{ 88236324Sraj uint32_t csr; 89236324Sraj 90236324Sraj /* Enable L2 cache on E500mc */ 91236324Sraj if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) || 92236324Sraj (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) { 93236324Sraj csr = mfspr(SPR_L2CSR0); 94236324Sraj if ((csr & L2CSR0_L2E) == 0) { 95236324Sraj l2cache_inval(); 96236324Sraj l2cache_enable(); 97236324Sraj } 98236324Sraj 99236324Sraj csr = mfspr(SPR_L2CSR0); 100236324Sraj if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0) 101236324Sraj printf("L2 cache %sabled\n", 102236324Sraj (csr & L2CSR0_L2E) ? "en" : "dis"); 103236324Sraj } 104236324Sraj} 105236324Sraj 106236324Srajvoid 107236324Srajbooke_enable_l3_cache(void) 108236324Sraj{ 109236324Sraj uint32_t csr, size, ver; 110236324Sraj 111236324Sraj /* Enable L3 CoreNet Platform Cache (CPC) */ 112236324Sraj ver = SVR_VER(mfspr(SPR_SVR)); 113236324Sraj if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 || 114236324Sraj ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) { 115236324Sraj csr = ccsr_read4(OCP85XX_CPC_CSR0); 116236324Sraj if ((csr & OCP85XX_CPC_CSR0_CE) == 0) { 117236324Sraj l3cache_inval(); 118236324Sraj l3cache_enable(); 119236324Sraj } 120236324Sraj 121236324Sraj csr = ccsr_read4(OCP85XX_CPC_CSR0); 122236324Sraj if ((boothowto & RB_VERBOSE) != 0 || 123236324Sraj (csr & OCP85XX_CPC_CSR0_CE) == 0) { 124236324Sraj size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0)); 125236324Sraj printf("L3 Corenet Platform Cache: %d KB %sabled\n", 126236324Sraj size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ? 127236324Sraj "dis" : "en"); 128236324Sraj } 129236324Sraj } 130236324Sraj} 131236324Sraj 132236324Srajvoid 133236324Srajbooke_disable_l2_cache(void) 134236324Sraj{ 135236324Sraj} 136236324Sraj 137236324Srajstatic void 138236324Srajl3cache_inval(void) 139236324Sraj{ 140236324Sraj 141236324Sraj /* Flash invalidate the CPC and clear all the locks */ 142236324Sraj ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI | 143236324Sraj OCP85XX_CPC_CSR0_LFC); 144236324Sraj while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI | 145236324Sraj OCP85XX_CPC_CSR0_LFC)) 146236324Sraj ; 147236324Sraj} 148236324Sraj 149236324Srajstatic void 150236324Srajl3cache_enable(void) 151236324Sraj{ 152236324Sraj 153236324Sraj ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE | 154236324Sraj OCP85XX_CPC_CSR0_PE); 155236324Sraj /* Read back to sync write */ 156236324Sraj ccsr_read4(OCP85XX_CPC_CSR0); 157236324Sraj} 158236324Sraj#endif 159